8200 lines
837 KiB
C
8200 lines
837 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_gc6_island_h__
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#define __ga102_dev_gc6_island_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PGC6 0x118fff:0x118000 /* RW--D */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK 0x00118060 /* RW-4R */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_ram" /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_ram" /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_RAM_PWR_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK 0x00118064 /* RW-4R */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASE_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK 0x00118068 /* RW-4R */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_PMU 0x0000004a /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_SEC2_PMU 0x0000004e /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE0 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE1 0x0000004e /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE2 0x0000004e /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE3 0x0000004e /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK 0x0011806c /* RW-4R */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_PMU 0x0000004a /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_SEC2_PMU 0x0000004e /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE0 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE1 0x0000004e /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE2 0x0000004e /* RW--V */
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#define NV_PGC6_BSI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE3 0x0000004e /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK 0x00118070 /* RW-4R */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_LDO_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK 0x00118100 /* RW-4R */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK 0x00118104 /* RW-4R */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK 0x00118074 /* RW-4R */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK 0x00118078 /* RW-4R */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_TRIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK 0x0011807c /* RW-4R */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP 0x0000004c /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE0 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE1 0x0000004c /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE2 0x0000004c /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE3 0x0000004c /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK 0x001183e8 /* RW-4R */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_fuseps18" /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP 0x0000004c /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gc6_bsi_fuseps18" /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE0 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE1 0x0000004c /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK 0x001183f0 /* RW-4R */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK 0x00118080 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK 0x00118084 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK 0x00118088 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK 0x0011808c /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK 0x00118090 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK 0x00118094 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK 0x00118098 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK 0x0011809c /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK 0x001180a0 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK 0x001180a4 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK 0x001180a8 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK 0x001180ac /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK 0x001180b0 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK 0x001180b4 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK 0x001180b8 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK 0x001180bc /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK 0x001183ec /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_bsi_debug" /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x0000000C /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL 0x00118000 /* RW-4R */
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#define NV_PGC6_BSI_CTRL__PRIV_LEVEL_MASK 0x00118074 /* */
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#define NV_PGC6_BSI_CTRL_MODE 1:0 /* RWIVF */
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#define NV_PGC6_BSI_CTRL_MODE_NONE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_MODE_GC5 0x00000001 /* -W--T */
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#define NV_PGC6_BSI_CTRL_MODE_GC6 0x00000002 /* -W--T */
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#define NV_PGC6_BSI_CTRL_MODE_CYA 0x00000003 /* -W--T */
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#define NV_PGC6_BSI_CTRL_CYA 2:2 /* RWIUF */
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#define NV_PGC6_BSI_CTRL_CYA_GC6 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_CYA_GC5 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_CTRL_BSI2SCI_CLKREQ 4:4 /* RWIUF */
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#define NV_PGC6_BSI_CTRL_BSI2SCI_CLKREQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_CTRL_BSI2SCI_CLKREQ_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_BSI2SCI_RXSTAT 5:5 /* RWIUF */
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#define NV_PGC6_BSI_CTRL_BSI2SCI_RXSTAT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_CTRL_BSI2SCI_RXSTAT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_RAMVALID 8:8 /* RWIUF */
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#define NV_PGC6_BSI_CTRL_RAMVALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_CTRL_RAMVALID_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_CTRL_SLCGDIS 12:12 /* RWIUF */
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#define NV_PGC6_BSI_CTRL_SLCGDIS_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_CTRL_SLCGDIS_TRUE 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_PMUTXTRIG 0x00118004 /* RW-4R */
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#define NV_PGC6_BSI_PMUTXTRIG__PRIV_LEVEL_MASK 0x00118078 /* */
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#define NV_PGC6_BSI_PMUTXTRIG_TRIG 0:0 /* RWIVF */
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#define NV_PGC6_BSI_PMUTXTRIG_TRIG_FALSE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PMUTXTRIG_TRIG_TRUE 0x00000001 /* -W--T */
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#define NV_PGC6_BSI_BOOTPHASES 0x00118008 /* RW-4R */
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#define NV_PGC6_BSI_BOOTPHASES__PRIV_LEVEL_MASK 0x00118064 /* */
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#define NV_PGC6_BSI_BOOTPHASES_GC5START 4:0 /* RWIUF */
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#define NV_PGC6_BSI_BOOTPHASES_GC5START_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASES_GC5STOP 9:5 /* RWIUF */
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#define NV_PGC6_BSI_BOOTPHASES_GC5STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASES_GC6START 14:10 /* RWIUF */
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#define NV_PGC6_BSI_BOOTPHASES_GC6START_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASES_GC6STOP 19:15 /* RWIUF */
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#define NV_PGC6_BSI_BOOTPHASES_GC6STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASES_ABORTSTART 24:20 /* RWIUF */
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#define NV_PGC6_BSI_BOOTPHASES_ABORTSTART_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_BOOTPHASES_ABORTSTOP 29:25 /* RWIUF */
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#define NV_PGC6_BSI_BOOTPHASES_ABORTSTOP_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAMCTRL 0x0011800c /* RW-4R */
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#define NV_PGC6_BSI_RAMCTRL__PRIV_LEVEL_MASK 0x00118060 /* */
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#define NV_PGC6_BSI_RAMCTRL_ADDR 15:0 /* RWIUF */
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#define NV_PGC6_BSI_RAMCTRL_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAMCTRL_RAUTOINCR 16:16 /* RWIUF */
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#define NV_PGC6_BSI_RAMCTRL_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAMCTRL_RAUTOINCR_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAMCTRL_WAUTOINCR 20:20 /* RWIUF */
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#define NV_PGC6_BSI_RAMCTRL_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAMCTRL_WAUTOINCR_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAMDATA 0x00118010 /* RW-4R */
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#define NV_PGC6_BSI_RAMDATA__PRIV_LEVEL_MASK 0x00118060 /* */
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#define NV_PGC6_BSI_RAMDATA_DATA 31:0 /* RWIUF */
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#define NV_PGC6_BSI_RAMDATA_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAMDATA_IMEM0_SRCADDR 15:0 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_IMEM0_SIZE 31:16 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_IMEM1_DESTADDR 15:0 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_IMEM1_TAG 31:16 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_IMEM1_SECURE 31:31 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_DMEM0_SRCADDR 15:0 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_DMEM0_SIZE 31:16 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_DMEM1_DESTADDR 15:0 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_PRIV_SRCADDR 15:0 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_PRIV_NUMWRITES 31:16 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_OPCODE 1:0 /* RW-UF */
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#define NV_PGC6_BSI_RAMDATA_OPCODE_PRIV 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_RAMDATA_OPCODE_BAR0 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAMDATA_OPCODE_RESERVED0 0x00000002 /* RW--V */
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#define NV_PGC6_BSI_RAMDATA_OPCODE_RESERVED1 0x00000003 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL 0x00118014 /* RW-4R */
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#define NV_PGC6_BSI_PADCTRL__PRIV_LEVEL_MASK 0x00118074 /* */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE 0:0 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_PADSUSPEND 1:1 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_PADSUSPEND_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_PADSUSPEND_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_PEXLPMODE 2:2 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_PEXLPMODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_PEXLPMODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_CLKREQEN 3:3 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_CLKREQEN_ENABLE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_CLKREQEN_DISABLE 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_GC5MODE 4:4 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_GC5MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_GC5MODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_PADSUSPEND 5:5 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_PADSUSPEND_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_PADSUSPEND_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_PEXLPMODE 6:6 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_PEXLPMODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_PEXLPMODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_CLKREQEN 7:7 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_CLKREQEN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_CLKREQEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_GC5MODE 8:8 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_GC5MODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_GC5MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_ALT_CTL_SEL 9:9 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_ALT_CTL_SEL_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_ALT_CTL_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_ALT_CTL_SEL 10:10 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_ALT_CTL_SEL_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_ALT_CTL_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_WAKE_CORE_CLMP 11:11 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_WAKE_CORE_CLMP_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_WAKE_CORE_CLMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_WAKE_ALT_CTL_SEL 12:12 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_WAKE_ALT_CTL_SEL_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_WAKE_ALT_CTL_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_WAKE_CORE_CLMP 13:13 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_WAKE_CORE_CLMP_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_WAKE_CORE_CLMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_WAKE_ALT_CTL_SEL 14:14 /* RWIUF */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_WAKE_ALT_CTL_SEL_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PADCTRL_OVERRIDE_WAKE_ALT_CTL_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_SPARE 0x00118018 /* RW-4R */
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#define NV_PGC6_BSI_SPARE_VAL 7:0 /* RWIUF */
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#define NV_PGC6_BSI_SPARE_VAL_INIT 0x000000f0 /* RWI-V */
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#define NV_PGC6_BSI_SPARE_BUG_1451839 7:7 /* */
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#define NV_PGC6_BSI_SPARE_BUG_1451839_DISABLE 0x00000001 /* */
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#define NV_PGC6_BSI_SPARE_BUG_1451839_ENABLE 0x00000000 /* */
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#define NV_PGC6_BSI_ANALOGCTRL 0x0011801c /* RW-4R */
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#define NV_PGC6_BSI_ANALOGCTRL__PRIV_LEVEL_MASK 0x00118070 /* */
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#define NV_PGC6_BSI_ANALOGCTRL_VAUXSVAL 3:0 /* RWIVF */
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#define NV_PGC6_BSI_ANALOGCTRL_VAUXSVAL_MIN 0x00000006 /* RW--V */
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#define NV_PGC6_BSI_ANALOGCTRL_VAUXSVAL_MAX 0x00000002 /* RW--V */
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#define NV_PGC6_BSI_ANALOGCTRL_VAUXSVAL_NOM 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_ANALOGCTRL_NVVDDTRIP 7:4 /* RWIUF */
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#define NV_PGC6_BSI_ANALOGCTRL_NVVDDTRIP_NOM 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_ANALOGCTRL_BG_LVL 10:8 /* RWIVF */
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#define NV_PGC6_BSI_ANALOGCTRL_BG_LVL_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_ANALOGCTRL_TESTPOINT_CNTL 16:12 /* RWIVF */
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#define NV_PGC6_BSI_ANALOGCTRL_TESTPOINT_CNTL_HI_Z 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_CTRL 0x00118020 /* RW-4R */
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#define NV_PGC6_BSI_PGOOD_CTRL__PRIV_LEVEL_MASK 0x00118070 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP 3:0 /* RWIVF */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_MIN 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_MAX 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP 11:8 /* RWIVF */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_MIN 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_MAX 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP 19:16 /* RWIVF */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_MIN 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_MAX 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP 27:24 /* RWIVF */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_MIN 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_MAX 0x00000008 /* RW--V */
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#define NV_PGC6_BSI_PGOOD_CTRL_HYSTERESIS_POS_MV 0x0000001E /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_HYSTERESIS_NEG_MV 0x0000001E /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_460MV 0x00000000 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_490MV 0x00000001 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_520MV 0x00000003 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_550MV 0x00000002 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_565MV 0x00000006 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_580MV 0x00000007 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_595MV 0x00000005 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_610MV 0x00000004 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_625MV 0x0000000C /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_640MV 0x0000000D /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_655MV 0x0000000F /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_670MV 0x0000000E /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_685MV 0x0000000A /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_715MV 0x0000000B /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_745MV 0x00000009 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_NVVDDTRIP_865MV 0x00000008 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_625MV 0x00000000 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_655MV 0x00000001 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_685MV 0x00000003 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_715MV 0x00000002 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_730MV 0x00000006 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_745MV 0x00000007 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_760MV 0x00000005 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_775MV 0x00000004 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_790MV 0x0000000C /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_805MV 0x0000000D /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_820MV 0x0000000F /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_835MV 0x0000000E /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_850MV 0x0000000A /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_880MV 0x0000000B /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_910MV 0x00000009 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_MSVDDTRIP_955MV 0x00000008 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_715MV 0x00000000 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_745MV 0x00000001 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_775MV 0x00000003 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_805MV 0x00000002 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_820MV 0x00000006 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_835MV 0x00000007 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_850MV 0x00000005 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_865MV 0x00000004 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_880MV 0x0000000C /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_895MV 0x0000000D /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_910MV 0x0000000F /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_925MV 0x0000000E /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_940MV 0x0000000A /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_955MV 0x0000000B /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_970MV 0x00000009 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_PEXVDDTRIP_985MV 0x00000008 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_550MV 0x00000000 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_565MV 0x00000001 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_580MV 0x00000003 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_595MV 0x00000002 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_610MV 0x00000006 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_625MV 0x00000007 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_640MV 0x00000005 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_655MV 0x00000004 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_670MV 0x0000000C /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_685MV 0x0000000D /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_700MV 0x0000000F /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_715MV 0x0000000E /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_730MV 0x0000000A /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_745MV 0x0000000B /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_760MV 0x00000009 /* */
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#define NV_PGC6_BSI_PGOOD_CTRL_FBVDDQTRIP_775MV 0x00000008 /* */
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#define NV_PGC6_BSI_PGOOD_RAW 0x00118024 /* R--4R */
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#define NV_PGC6_BSI_PGOOD_RAW_NVVDD 0:0 /* R-IUF */
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#define NV_PGC6_BSI_PGOOD_RAW_NVVDD_FALSE 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_PGOOD_RAW_NVVDD_TRUE 0x00000001 /* R---V */
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#define NV_PGC6_BSI_PGOOD_RAW_MSVDD 4:4 /* R-IUF */
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#define NV_PGC6_BSI_PGOOD_RAW_MSVDD_FALSE 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_PGOOD_RAW_MSVDD_TRUE 0x00000001 /* R---V */
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#define NV_PGC6_BSI_PGOOD_RAW_PEXVDD 8:8 /* R-IUF */
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#define NV_PGC6_BSI_PGOOD_RAW_PEXVDD_FALSE 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_PGOOD_RAW_PEXVDD_TRUE 0x00000001 /* R---V */
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#define NV_PGC6_BSI_PGOOD_RAW_FBVDDQ 12:12 /* R-IUF */
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#define NV_PGC6_BSI_PGOOD_RAW_FBVDDQ_FALSE 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_PGOOD_RAW_FBVDDQ_TRUE 0x00000001 /* R---V */
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#define NV_PGC6_BSI_PGOOD_ENABLE 0x00118028 /* RW-4R */
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#define NV_PGC6_BSI_PGOOD_ENABLE__PRIV_LEVEL_MASK 0x00118070 /* */
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#define NV_PGC6_BSI_PGOOD_ENABLE_NVVDD 0:0 /* RWIUF */
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#define NV_PGC6_BSI_PGOOD_ENABLE_NVVDD_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_ENABLE_NVVDD_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PGOOD_ENABLE_MSVDD 4:4 /* RWIUF */
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#define NV_PGC6_BSI_PGOOD_ENABLE_MSVDD_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_ENABLE_MSVDD_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PGOOD_ENABLE_PEXVDD 8:8 /* RWIUF */
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#define NV_PGC6_BSI_PGOOD_ENABLE_PEXVDD_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_ENABLE_PEXVDD_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PGOOD_ENABLE_FBVDDQ 12:12 /* RWIUF */
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#define NV_PGC6_BSI_PGOOD_ENABLE_FBVDDQ_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PGOOD_ENABLE_FBVDDQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL 0x0011802c /* RW-4R */
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#define NV_PGC6_BSI_FUSEPS18_CTRL__PRIV_LEVEL_MASK 0x001183e8 /* */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_SET 0:0 /* RWIUF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_SET_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_SET_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_RESET 4:4 /* RWIUF */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_RESET_DEASSERT 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FUSEPS18_CTRL_RESET_ASSERT 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL 0x001183f4 /* RW-4R */
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#define NV_PGC6_BSI_RAM_PGCTRL__PRIV_LEVEL_MASK 0x001183f0 /* */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK0_RETMODE 0:0 /* RWIUF */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK0_RETMODE_RPG 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK0_RETMODE_RPPG 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK0_SLEEPTRIG 1:1 /* RWIUF */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK0_SLEEPTRIG_EXIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK0_SLEEPTRIG_ENTRY 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_OVERRIDE 2:2 /* RWIUF */
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#define NV_PGC6_BSI_RAM_PGCTRL_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK1_SLEEPTRIG 3:3 /* RWIUF */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK1_SLEEPTRIG_EXIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK1_SLEEPTRIG_ENTRY 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK2_SLEEPTRIG 4:4 /* RWIUF */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK2_SLEEPTRIG_EXIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK2_SLEEPTRIG_ENTRY 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK3_SLEEPTRIG 5:5 /* RWIUF */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK3_SLEEPTRIG_EXIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK3_SLEEPTRIG_ENTRY 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK4_SLEEPTRIG 6:6 /* RWIUF */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK4_SLEEPTRIG_EXIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_RAM_PGCTRL_BANK4_SLEEPTRIG_ENTRY 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_PGSTATUS 0x001183f8 /* R--4R */
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#define NV_PGC6_BSI_RAM_PGSTATUS_SEQ_ERR_ADDR 15:0 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_SEQ_ERR_ADDR_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_SEQ_ERR_VALID 16:16 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_SEQ_ERR_VALID_NO 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_SEQ_ERR_VALID_YES 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK0_SLEEP 20:20 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK0_SLEEP_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK0_SLEEP_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK0_RET 21:21 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK0_RET_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK0_RET_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK1_SLEEP 22:22 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK1_SLEEP_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK1_SLEEP_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK1_RET 23:23 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK1_RET_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK1_RET_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK2_SLEEP 24:24 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK2_SLEEP_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK2_SLEEP_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK2_RET 25:25 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK2_RET_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK2_RET_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK3_SLEEP 26:26 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK3_SLEEP_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK3_SLEEP_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK3_RET 27:27 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK3_RET_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK3_RET_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK4_SLEEP 28:28 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK4_SLEEP_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK4_SLEEP_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK4_RET 29:29 /* R-IUF */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK4_RET_OFF 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_PGSTATUS_BANK4_RET_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES 0x00118108 /* RW-4R */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES__PRIV_LEVEL_MASK 0x00118100 /* */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_CLKREQ_IN_GC6 0:0 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_CLKREQ_IN_GC6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_CLKREQ_IN_GC6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_SW_DISARM 1:1 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_SW_DISARM_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_SW_DISARM_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PER_PADCTRL_OVERRIDE 2:2 /* RWIVF */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PER_PADCTRL_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_DOMAIN_FEATURES_PER_PADCTRL_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES 0x0011810c /* RW-4R */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES__PRIV_LEVEL_MASK 0x00118104 /* */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_RDY4TRANS_INTERLOCK 0:0 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_RDY4TRANS_INTERLOCK_ENABLE 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_RDY4TRANS_INTERLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_BAR0_OPCODE 1:1 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_BAR0_OPCODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_BAR0_OPCODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_TRANSFER 2:2 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_TRANSFER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_PRIV_LEVEL_TRANSFER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_BSI_RAM_OPCODE 3:3 /* RWIVF */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_BSI_RAM_OPCODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWRCLK_DOMAIN_FEATURES_BSI_RAM_OPCODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM 0x00118110 /* R--4R */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM_STATE 2:0 /* R-IVF */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM_STATE_IDLE 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM_STATE_PRIV 0x00000001 /* R---V */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM_STATE_BAR0_1 0x00000002 /* R---V */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM_STATE_BAR0_2 0x00000003 /* R---V */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM_STATE_BAR0_3 0x00000004 /* R---V */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM_STATE_BAR0_4 0x00000005 /* R---V */
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#define NV_PGC6_BSI_DEBUG_POSTSEQ_FSM_STATE_BAR0_5 0x00000006 /* R---V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE(i) (0x001183a8+(i)*4) /* RW-4A */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE__SIZE_1 4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE__PRIV_LEVEL_MASK 0x001183ec /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_VALUE 31:0 /* RWIUF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_BOOT_VOLTAGE_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SCRATCH(i) (0x001183b8+(i)*4) /* RW-4A */
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#define NV_PGC6_BSI_SCRATCH__SIZE_1 12 /* */
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#define NV_PGC6_BSI_SCRATCH_VALUE 31:0 /* RWIUF */
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#define NV_PGC6_BSI_SCRATCH_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_STATUS 0x00118030 /* R--4R */
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#define NV_PGC6_BSI_STATUS_TOP 2:0 /* R-IUF */
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#define NV_PGC6_BSI_STATUS_TOP_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_STATUS_TOP_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_BSI_STATUS_TOP_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_BSI_STATUS_PMUINT 6:4 /* R-IUF */
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#define NV_PGC6_BSI_STATUS_PMUINT_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_STATUS_PMUINT_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_BSI_STATUS_PMUINT_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_BSI_STATUS_SCIINT 10:8 /* R-IUF */
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#define NV_PGC6_BSI_STATUS_SCIINT_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_STATUS_SCIINT_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_BSI_STATUS_SCIINT_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_BSI_DEBUG1 0x00118034 /* R--4R */
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#define NV_PGC6_BSI_DEBUG1_MAINFSMSTATE 2:0 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG1_MAINFSMSTATE_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG1_SEQFSMSTATE 7:4 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG1_SEQFSMSTATE_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG1_LASTRAMADDR 22:8 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG1_LASTRAMADDR_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG1_CURRBOOTPHASE 28:24 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG1_CURRBOOTPHASE_MIN 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG1_CURRBOOTPHASE_MAX 0x0000001f /* R---V */
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#define NV_PGC6_BSI_DEBUG2 0x00118038 /* R--4R */
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#define NV_PGC6_BSI_DEBUG2_LASTSCIMESG 1:0 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_LASTSCIMESG_ABORT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_LASTSCIMESG_RESET 0x00000001 /* R---V */
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#define NV_PGC6_BSI_DEBUG2_LASTSCIMESG_GC5_EXIT 0x00000002 /* R---V */
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#define NV_PGC6_BSI_DEBUG2_LASTSCIMESG_GC6_EXIT 0x00000003 /* R---V */
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#define NV_PGC6_BSI_DEBUG2_BSI2SCIEVENT 4:4 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_BSI2SCIEVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_CLKREQIN 8:8 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_CLKREQIN_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_RXSTATIDLE 12:12 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_RXSTATIDLE_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_MAIN_GC5_EXIT_FLAG 13:13 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_MAIN_GC5_EXIT_FLAG_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_MAIN_GC6_EXIT_FLAG 14:14 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_MAIN_GC6_EXIT_FLAG_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_MAIN_GC5_CYA_EXIT_FLAG 15:15 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_MAIN_GC5_CYA_EXIT_FLAG_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_MAIN_GC6_CYA_EXIT_FLAG 16:16 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_MAIN_GC6_CYA_EXIT_FLAG_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_MAIN_ABORT_EXIT_FLAG 17:17 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_MAIN_ABORT_EXIT_FLAG_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_LSHIFT_EN_JTAG 18:18 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_LSHIFT_EN_JTAG_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_LSHIFT_EN_TEST 19:19 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_LSHIFT_EN_TEST_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_LSHIFT_EN_MISC 20:20 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_LSHIFT_EN_MISC_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_STRAP 22:21 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_STRAP_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG2_PRESEQ_RDY4TRANS 23:23 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG2_PRESEQ_RDY4TRANS_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_DEBUG3 0x0011803c /* R--4R */
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#define NV_PGC6_BSI_DEBUG3_LASTSCIPRIV 31:0 /* R-IUF */
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#define NV_PGC6_BSI_DEBUG3_LASTSCIPRIV_INIT 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_FGC6_PCIE 0x00118040 /* RW-4R */
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#define NV_PGC6_BSI_FGC6_PCIE__PRIV_LEVEL_MASK 0x0011806c /* */
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#define NV_PGC6_BSI_FGC6_PCIE_LATCH 0:0 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PCIE_LATCH_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PCIE_LATCH_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PCIE_CLAMP 1:1 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PCIE_CLAMP_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PCIE_CLAMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PCIE_RESET_CTRL 2:2 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PCIE_RESET_CTRL_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PCIE_RESET_CTRL_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_FGC6_PCIE_RST_PRECREDIT_IF 3:3 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_PCIE_RST_PRECREDIT_IF_DEASSERT 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_PCIE_RST_PRECREDIT_IF_ASSERT 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN 0x00118044 /* RW-4R */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN__PRIV_LEVEL_MASK 0x00118068 /* */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CLAMP_EN 0:0 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CLAMP_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CLAMP_EN_ENABLE 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CG_CTRL 1:1 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CG_CTRL_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CG_CTRL_ENABLE 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CLAMP_EN_DELAY 15:8 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CLAMP_EN_DELAY_INIT 0x0000000A /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CLAMP_DIS_DELAY 23:16 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CLAMP_DIS_DELAY_INIT 0x0000000A /* RWI-V */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CG_CTRL_DELAY 31:24 /* RWIVF */
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#define NV_PGC6_BSI_FGC6_JTAG_CHAIN_CG_CTRL_DELAY_INIT 0x0000000A /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES 0x00118048 /* RW-4R */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES__PRIV_LEVEL_MASK 0x0011807c /* */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_IFF_INTERLOCK 0:0 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_IFF_INTERLOCK_ENABLE 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_IFF_INTERLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_BSI_RAM_SCRUB 1:1 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_BSI_RAM_SCRUB_ENABLE 0x00000001 /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_BSI_RAM_SCRUB_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_RAM_ADDR 2:2 /* RWIVF */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_RAM_ADDR_BYTE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_HIGH_SECURE_FEATURES_RAM_ADDR_DWORD 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4 0x0011804c /* RW-4R */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL 2:0 /* RWIVF */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL_NONE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL_NVVDD_OK 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL_GC5_MODE 0x00000002 /* RW--V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL_LP_MODE 0x00000003 /* RW--V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL_MAIN_FSM_ACTIVE 0x00000004 /* RW--V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL_RESERVED0 0x00000005 /* RW--V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL_RESERVED1 0x00000006 /* RW--V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_SEL_RESERVED2 0x00000007 /* RW--V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_EN 4:4 /* RWIVF */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_EN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_BSI2SCI_DEBUG4_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_RAM_SCRUBBER 0x00118050 /* R--4R */
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#define NV_PGC6_BSI_RAM_SCRUBBER_STATUS 1:0 /* R-IUF */
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#define NV_PGC6_BSI_RAM_SCRUBBER_STATUS_DIRTY 0x00000000 /* R-I-V */
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#define NV_PGC6_BSI_RAM_SCRUBBER_STATUS_ON 0x00000001 /* R---V */
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#define NV_PGC6_BSI_RAM_SCRUBBER_STATUS_DONE 0x00000002 /* R---V */
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#define NV_PGC6_BSI_RAM 0x00118054 /* R--4R */
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#define NV_PGC6_BSI_RAM_SIZE 7:0 /* R-IVF */
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#define NV_PGC6_BSI_RAM_SIZE_0KB 0x00000000 /* R---V */
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#define NV_PGC6_BSI_RAM_SIZE_64KB 0x00000040 /* R-I-V */
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#define NV_PGC6_BSI_RAM_SIZE_80KB 0x00000050 /* R---V */
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#define NV_PGC6_BSI_RAM_SIZE_96KB 0x00000060 /* R---V */
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#define NV_PGC6_BSI_RAM_SIZE_112KB 0x00000070 /* R---V */
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#define NV_PGC6_BSI_RAM_SIZE_128KB 0x00000080 /* R---V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS 0x00118058 /* RW-4R */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC5 0:0 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC5_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC5_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC5_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC6 1:1 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC6_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC6_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC6_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC5_CYA 2:2 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC5_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC5_CYA_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC5_CYA_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC6_CYA 3:3 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC6_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC6_CYA_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ARMED_GC6_CYA_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_PAD_CONTROLS 4:4 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_PAD_CONTROLS_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_PAD_CONTROLS_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_PAD_CONTROLS_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC5_EXIT 5:5 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC5_EXIT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC5_EXIT_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC5_EXIT_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC6_EXIT 6:6 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC6_EXIT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC6_EXIT_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC6_EXIT_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC5_CYA_EXIT 7:7 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC5_CYA_EXIT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC5_CYA_EXIT_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC5_CYA_EXIT_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC6_CYA_EXIT 8:8 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC6_CYA_EXIT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC6_CYA_EXIT_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_GC6_CYA_EXIT_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ABORT 9:9 /* RWIUF */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ABORT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ABORT_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_XTAL_SEQUENCE_STATUS_ABORT_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS 0x0011805c /* RW-4R */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_READ_DESC 0:0 /* RWIUF */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_READ_DESC_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_READ_DESC_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_READ_DESC_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_DMEM 1:1 /* RWIUF */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_DMEM_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_DMEM_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_DMEM_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_IMEM 2:2 /* RWIUF */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_IMEM_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_IMEM_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_IMEM_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_PRIV 3:3 /* RWIUF */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_PRIV_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_PRIV_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEND_PRIV_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_RDY4TRANS 4:4 /* RWIUF */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_RDY4TRANS_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_RDY4TRANS_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_RDY4TRANS_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEQ_DONE 5:5 /* RWIUF */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEQ_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEQ_DONE_FALSE 0x00000000 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_SEQ_DONE_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_LOOP_COUNT 10:6 /* RWIUF */
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#define NV_PGC6_BSI_PWR_SEQUENCE_STATUS_LOOP_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0 0x001180c0 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0__PRIV_LEVEL_MASK 0x00118080 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1 0x001180c4 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1__PRIV_LEVEL_MASK 0x00118084 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2 0x001180c8 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2__PRIV_LEVEL_MASK 0x00118088 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3 0x001180cc /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3__PRIV_LEVEL_MASK 0x0011808c /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4 0x001180d0 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4__PRIV_LEVEL_MASK 0x00118090 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5 0x001180d4 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5__PRIV_LEVEL_MASK 0x00118094 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6 0x001180d8 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6__PRIV_LEVEL_MASK 0x00118098 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7 0x001180dc /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7__PRIV_LEVEL_MASK 0x0011809c /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_7_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8 0x001180e0 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8__PRIV_LEVEL_MASK 0x001180a0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_8_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9 0x001180e4 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9__PRIV_LEVEL_MASK 0x001180a4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_9_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10 0x001180e8 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10__PRIV_LEVEL_MASK 0x001180a8 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_10_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11 0x001180ec /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11__PRIV_LEVEL_MASK 0x001180ac /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_11_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12 0x001180f0 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12__PRIV_LEVEL_MASK 0x001180b0 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_12_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13 0x001180f4 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13__PRIV_LEVEL_MASK 0x001180b4 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_13_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14 0x001180f8 /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14__PRIV_LEVEL_MASK 0x001180b8 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_14_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15 0x001180fc /* RW-4R */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15__PRIV_LEVEL_MASK 0x001180bc /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_DATA 31:0 /* RWIVF */
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#define NV_PGC6_BSI_SECURE_SCRATCH_15_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_BSI_SECURE_PRIV_LEVEL_MASK(i) (0x00118080+(i)*4) /* */
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#define NV_PGC6_BSI_SECURE_PRIV_LEVEL_MASK__SIZE_1 16 /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH(i) (0x001180c0+(i)*4) /* */
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#define NV_PGC6_BSI_SECURE_SCRATCH__SIZE_1 16 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK 0x00118114 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK 0x00118118 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK 0x0011811c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK 0x00118120 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK 0x00118124 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK 0x00118128 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK 0x0011812c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK 0x00118130 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK 0x00118134 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK 0x00118138 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK 0x0011813c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK 0x00118140 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK 0x00118144 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK 0x00118148 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK 0x0011814c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK 0x00118150 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK 0x00118154 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK 0x00118158 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK 0x0011815c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK 0x00118160 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK 0x00118164 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK 0x00118168 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK 0x0011816c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK 0x00118170 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK 0x00118174 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK 0x00118178 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK 0x0011817c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK 0x00118180 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK 0x00118184 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK 0x00118188 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK 0x0011818c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK 0x00118190 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK 0x00118194 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK 0x00118198 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK 0x0011819c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK 0x001181a0 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK 0x001181a4 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK 0x001181a8 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK 0x00118380 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK 0x00118384 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK 0x00118388 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK 0x0011838c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK 0x00118390 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00(i) (0x001181ac+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00__SIZE_1 10 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00__PRIV_LEVEL_MASK 0x00118114 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_00_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01(i) (0x001181d4+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01__SIZE_1 8 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01__PRIV_LEVEL_MASK 0x00118118 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_01_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02(i) (0x001181f4+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02__SIZE_1 8 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02__PRIV_LEVEL_MASK 0x0011811c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_02_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03__PRIV_LEVEL_MASK 0x00118120 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04(i) (0x00118224+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04__PRIV_LEVEL_MASK 0x00118124 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_04_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05__PRIV_LEVEL_MASK 0x00118128 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06(i) (0x00118244+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06__PRIV_LEVEL_MASK 0x0011812c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_06_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07(i) (0x00118254+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07__PRIV_LEVEL_MASK 0x00118130 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_07_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08(i) (0x00118264+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08__PRIV_LEVEL_MASK 0x00118134 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_08_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09(i) (0x00118274+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09__PRIV_LEVEL_MASK 0x00118138 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_09_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10(i) (0x00118284+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10__PRIV_LEVEL_MASK 0x0011813c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_10_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11(i) (0x00118294+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11__PRIV_LEVEL_MASK 0x00118140 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_11_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12(i) (0x0011829c+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12__PRIV_LEVEL_MASK 0x00118144 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_12_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13(i) (0x001182a4+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13__PRIV_LEVEL_MASK 0x00118148 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_13_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14(i) (0x001182ac+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14__PRIV_LEVEL_MASK 0x0011814c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_14_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15(i) (0x001182b4+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15__PRIV_LEVEL_MASK 0x00118150 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_15_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16 0x001182bc /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16__PRIV_LEVEL_MASK 0x00118154 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_16_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17 0x001182c0 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17__PRIV_LEVEL_MASK 0x00118158 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_17_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18 0x001182c4 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18__PRIV_LEVEL_MASK 0x0011815c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_18_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19 0x001182c8 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19__PRIV_LEVEL_MASK 0x00118160 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_19_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20 0x001182cc /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20__PRIV_LEVEL_MASK 0x00118164 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21 0x001182d0 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21__PRIV_LEVEL_MASK 0x00118168 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_21_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22(i) (0x001182d4+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22__SIZE_1 8 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22__PRIV_LEVEL_MASK 0x0011816c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_22_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23(i) (0x001182f4+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23__PRIV_LEVEL_MASK 0x00118170 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_23_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24(i) (0x00118304+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24__PRIV_LEVEL_MASK 0x00118174 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_24_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25(i) (0x00118314+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25__PRIV_LEVEL_MASK 0x00118178 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_25_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26(i) (0x00118324+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26__SIZE_1 4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26__PRIV_LEVEL_MASK 0x0011817c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_26_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27(i) (0x00118334+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27__PRIV_LEVEL_MASK 0x00118180 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_27_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28(i) (0x0011833c+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28__PRIV_LEVEL_MASK 0x00118184 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_28_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29(i) (0x00118344+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29__PRIV_LEVEL_MASK 0x00118188 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_29_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30(i) (0x0011834c+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30__PRIV_LEVEL_MASK 0x0011818c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_30_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31(i) (0x00118354+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31__PRIV_LEVEL_MASK 0x00118190 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_31_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32(i) (0x0011835c+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32__PRIV_LEVEL_MASK 0x00118194 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_32_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33(i) (0x00118364+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33__PRIV_LEVEL_MASK 0x00118198 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_33_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34(i) (0x0011836c+(i)*4) /* RW-4A */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34__SIZE_1 2 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34__PRIV_LEVEL_MASK 0x0011819c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_34_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35 0x00118374 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35__PRIV_LEVEL_MASK 0x001181a0 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_35_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36 0x00118378 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36__PRIV_LEVEL_MASK 0x001181a4 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_36_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37 0x0011837c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37__PRIV_LEVEL_MASK 0x001181a8 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_37_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38 0x00118394 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38__PRIV_LEVEL_MASK 0x00118380 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_38_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39 0x00118398 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39__PRIV_LEVEL_MASK 0x00118384 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_39_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40 0x0011839c /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40__PRIV_LEVEL_MASK 0x00118388 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_40_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41 0x001183a0 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41__PRIV_LEVEL_MASK 0x0011838c /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_41_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42__PRIV_LEVEL_MASK 0x00118390 /* */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_DATA 31:0 /* RWIVF */
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK 0x00118b20 /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_pwr_seq_misc" /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_MISC_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK 0x00118b24 /* RW-4R */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_debug" /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gc6_sci_debug" /* */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE0 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE1 0x0000004e /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_PMU 0x0000004a /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_SEC2_PMU 0x0000004e /* RW--V */
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#define NV_PGC6_SCI_FGC6_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK 0x00118b28 /* RW-4R */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_PCIE_FN_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK 0x00118b38 /* RW-4R */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_debug" /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_PGOOD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK 0x00118f78 /* RW-4R */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_debug" /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK 0x00118b2c /* RW-4R */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_SEC_STATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK 0x00118b30 /* RW-4R */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_debug" /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_STRAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK 0x00118b34 /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_pwr_seq" /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DBG_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK 0x00118fcc /* RW-4R */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_smbus" /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_SMBUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK 0x00118fd0 /* RW-4R */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_overt" /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_OVERT_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK 0x00118fd4 /* RW-4R */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK 0x00118fd8 /* RW-4R */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_mast_fsm" /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE2 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE3 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_MAST_FSM_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK 0x00118fdc /* RW-4R */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_pwr_seq" /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_WAKE_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK 0x00118fe0 /* RW-4R */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_I2CS_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK 0x00118fe4 /* RW-4R */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_system" /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_SYSTEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK 0x00118fe8 /* RW-4R */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_debug" /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK 0x00118fec /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_pwr_seq" /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK 0x00118ff0 /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_pwr_seq" /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK 0x00118ff4 /* RW-4R */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_pwr_seq" /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_PMU 0x0000004a /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_SEC2_PMU 0x0000004e /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gc6_sci_pwr_seq" /* */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE0 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_FUSE1 0x0000004e /* RW--V */
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#define NV_PGC6_SCI_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK 0x00118ff8 /* RW-4R */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_fan" /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_FAN_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK 0x00118ffc /* RW-4R */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_gc6_sci_pwr_seq_misc" /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PGC6_SCI_VID_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_CNTL 0x00118c00 /* RW-4R */
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#define NV_PGC6_SCI_CNTL__PRIV_LEVEL_MASK 0x00118fd8 /* */
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#define NV_PGC6_SCI_CNTL_ENTRY_TRIGGER 1:0 /* RWIVF */
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#define NV_PGC6_SCI_CNTL_ENTRY_TRIGGER_DONE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_CNTL_ENTRY_TRIGGER_GC5_IN_PROG 0x00000001 /* R---V */
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#define NV_PGC6_SCI_CNTL_ENTRY_TRIGGER_GC6_IN_PROG 0x00000002 /* R---V */
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#define NV_PGC6_SCI_CNTL_ENTRY_TRIGGER_RTD3_IN_PROG 0x00000003 /* R---V */
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#define NV_PGC6_SCI_CNTL_ENTRY_TRIGGER_GC5 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_CNTL_ENTRY_TRIGGER_GC6 0x00000002 /* -W--T */
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#define NV_PGC6_SCI_CNTL_ENTRY_TRIGGER_RTD3 0x00000003 /* -W--T */
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#define NV_PGC6_SCI_CNTL_SW_STATUS_COPY_CLEAR 4:4 /* RWIVF */
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#define NV_PGC6_SCI_CNTL_SW_STATUS_COPY_CLEAR_DONE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_CNTL_SW_STATUS_COPY_CLEAR_IN_PROG 0x00000001 /* R---V */
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#define NV_PGC6_SCI_CNTL_SW_STATUS_COPY_CLEAR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_LDO_CNTL 0x00118c04 /* RW-4R */
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#define NV_PGC6_SCI_LDO_CNTL__PRIV_LEVEL_MASK 0x00118fe4 /* */
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#define NV_PGC6_SCI_LDO_CNTL_VAUXS_LVL 3:0 /* RWIVF */
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#define NV_PGC6_SCI_LDO_CNTL_VAUXS_LVL_NOM 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_LDO_CNTL_NVVDD_OK_LVL 7:4 /* RWIVF */
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#define NV_PGC6_SCI_LDO_CNTL_NVVDD_OK_LVL_NOM 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_LDO_CNTL_BG_LVL 10:8 /* RWIVF */
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#define NV_PGC6_SCI_LDO_CNTL_BG_LVL_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_LDO_CNTL_TESTPOINT_CNTL 16:12 /* RWIVF */
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#define NV_PGC6_SCI_LDO_CNTL_TESTPOINT_CNTL_HI_Z 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FSM_CFG 0x00118c08 /* RW-4R */
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#define NV_PGC6_SCI_FSM_CFG__PRIV_LEVEL_MASK 0x00118fd8 /* */
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#define NV_PGC6_SCI_FSM_CFG_SELF_DRIVE_RST 0:0 /* RWIVF */
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#define NV_PGC6_SCI_FSM_CFG_SELF_DRIVE_RST_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FSM_CFG_SELF_DRIVE_RST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FSM_CFG_RESET_GPU_EVENT 1:1 /* RWIVF */
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#define NV_PGC6_SCI_FSM_CFG_RESET_GPU_EVENT_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FSM_CFG_RESET_GPU_EVENT_ENABLE 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_FSM_CFG_SKIP_GC6_ABORT 2:2 /* RWIVF */
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#define NV_PGC6_SCI_FSM_CFG_SKIP_GC6_ABORT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FSM_CFG_SKIP_GC6_ABORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FSM_CFG_SR_UPDATE_MODE 3:3 /* RWIVF */
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#define NV_PGC6_SCI_FSM_CFG_SR_UPDATE_MODE_SECOND_EDGE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FSM_CFG_SR_UPDATE_MODE_STEADY_STATE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FSM_CFG_INTERNAL_RESET_DRIVE 4:4 /* RWIVF */
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#define NV_PGC6_SCI_FSM_CFG_INTERNAL_RESET_DRIVE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FSM_CFG_INTERNAL_RESET_DRIVE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FSM_CFG_INTERNAL_RESET_MON 5:5 /* RWIVF */
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#define NV_PGC6_SCI_FSM_CFG_INTERNAL_RESET_MON_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FSM_CFG_INTERNAL_RESET_MON_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FSM_CFG_RTD3_RESET_MON 6:6 /* RWIVF */
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#define NV_PGC6_SCI_FSM_CFG_RTD3_RESET_MON_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FSM_CFG_RTD3_RESET_MON_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_ASSERT 0x00118c10 /* RW-4R */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_ASSERT__PRIV_LEVEL_MASK 0x00118fd8 /* */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_ASSERT_TIMEOUT 13:0 /* RWIUF */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_ASSERT_TIMEOUT_ZERO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_ASSERT_TIMEOUT_2MS 0x000007d0 /* RWI-V */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_ASSERT_TIMEOUT_MAX 0x00003fff /* RW--V */
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#define NV_PGC6_SCI_TMR_GC6_ABORT_HOLDOFF 0x00118c14 /* RW-4R */
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#define NV_PGC6_SCI_TMR_GC6_ABORT_HOLDOFF__PRIV_LEVEL_MASK 0x00118fd8 /* */
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#define NV_PGC6_SCI_TMR_GC6_ABORT_HOLDOFF_TIMEOUT 13:0 /* RWIUF */
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#define NV_PGC6_SCI_TMR_GC6_ABORT_HOLDOFF_TIMEOUT_ZERO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_TMR_GC6_ABORT_HOLDOFF_TIMEOUT_10US 0x0000000a /* RWI-V */
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#define NV_PGC6_SCI_TMR_GC6_ABORT_HOLDOFF_TIMEOUT_MAX 0x00003fff /* RW--V */
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#define NV_PGC6_SCI_TMR_SYSTEM_RESET 0x00118c18 /* RW-4R */
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#define NV_PGC6_SCI_TMR_SYSTEM_RESET__PRIV_LEVEL_MASK 0x00118fd8 /* */
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#define NV_PGC6_SCI_TMR_SYSTEM_RESET_TIMEOUT 13:0 /* RWIUF */
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#define NV_PGC6_SCI_TMR_SYSTEM_RESET_TIMEOUT_ZERO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_TMR_SYSTEM_RESET_TIMEOUT_2MS 0x000007d0 /* RWI-V */
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#define NV_PGC6_SCI_TMR_SYSTEM_RESET_TIMEOUT_MAX 0x00003fff /* RW--V */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_HOLDOFF 0x00118c1c /* RW-4R */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_HOLDOFF__PRIV_LEVEL_MASK 0x00118fd8 /* */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_HOLDOFF_TIMEOUT 13:0 /* RWIUF */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_HOLDOFF_TIMEOUT_ZERO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_HOLDOFF_TIMEOUT_1US 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_TMR_GPU_EVENT_HOLDOFF_TIMEOUT_MAX 0x00003fff /* RW--V */
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#define NV_PGC6_SCI_TMR_GC5_ENTRY_HOLDOFF 0x00118c20 /* RW-4R */
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#define NV_PGC6_SCI_TMR_GC5_ENTRY_HOLDOFF__PRIV_LEVEL_MASK 0x00118fd8 /* */
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#define NV_PGC6_SCI_TMR_GC5_ENTRY_HOLDOFF_TIMEOUT 13:0 /* RWIUF */
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#define NV_PGC6_SCI_TMR_GC5_ENTRY_HOLDOFF_TIMEOUT_ZERO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_TMR_GC5_ENTRY_HOLDOFF_TIMEOUT_1US 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_TMR_GC5_ENTRY_HOLDOFF_TIMEOUT_MAX 0x00003fff /* RW--V */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL 0x00118c30 /* RW-4R */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL_TIMER 23:0 /* RWIUF */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL_TIMER_ZERO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL_TIMER_1US 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL_TIMER_1MS 0x000003e8 /* RW--V */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL_TIMER_1S 0x000f4240 /* RW--V */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL_TIMER_10S 0x00989680 /* RW--V */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL_TIMER_16S 0x00f42400 /* RW--V */
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#define NV_PGC6_SCI_WAKEUP_TMR_CNTL_TIMER_MAX 0x00ffffff /* RW--V */
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#define NV_PGC6_SCI_HPD_CONFIG(i) (0x00118dd0+(i)*4) /* RW-4A */
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#define NV_PGC6_SCI_HPD_CONFIG__SIZE_1 7 /* */
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#define NV_PGC6_SCI_HPD_CONFIG__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_HPD_CONFIG_UNPLUG_MIN_TIME 15:0 /* RWIVF */
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#define NV_PGC6_SCI_HPD_CONFIG_UNPLUG_MIN_TIME_2MS 0x000007D0 /* RWI-V */
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#define NV_PGC6_SCI_HPD_CONFIG_IRQ_PLUG_MIN_TIME 31:16 /* RWIVF */
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#define NV_PGC6_SCI_HPD_CONFIG_IRQ_PLUG_MIN_TIME_250US 0x000000FA /* RWI-V */
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#define NV_PGC6_SCI_HPD_STATUS 0x00118df0 /* R--4R */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_0 0:0 /* R-IVF */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_0_UNPLUG 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_0_PLUGIN 0x00000001 /* R---V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_1 1:1 /* R-IVF */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_1_UNPLUG 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_1_PLUGIN 0x00000001 /* R---V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_2 2:2 /* R-IVF */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_2_UNPLUG 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_2_PLUGIN 0x00000001 /* R---V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_3 3:3 /* R-IVF */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_3_UNPLUG 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_3_PLUGIN 0x00000001 /* R---V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_4 4:4 /* R-IVF */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_4_UNPLUG 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_4_PLUGIN 0x00000001 /* R---V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_5 5:5 /* R-IVF */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_5_UNPLUG 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_5_PLUGIN 0x00000001 /* R---V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_6 6:6 /* R-IVF */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_6_UNPLUG 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_6_PLUGIN 0x00000001 /* R---V */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS(i) (i):(i) /* */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_UNPLUG 0x00000000 /* */
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#define NV_PGC6_SCI_HPD_STATUS_HPD_STATUS_PLUGIN 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_EN 0x00118c34 /* RW-4R */
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#define NV_PGC6_SCI_WAKE_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_WAKE_EN_GPU_EVENT 0:0 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_GPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_GPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_WAKE_TIMER 1:1 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_WAKE_TIMER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_WAKE_TIMER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_I2CS 2:2 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_I2CS_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_I2CS_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_BSI_EVENT 3:3 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_BSI_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_BSI_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_RTD3_CPU_EVENT 4:4 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_RTD3_CPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_RTD3_CPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_XUSB_PPC_EVENT 7:7 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_XUSB_PPC_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_XUSB_PPC_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_4 12:12 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_5 13:13 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_6 14:14 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ(i) (8+(i)):(8+(i)) /* */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ__SIZE_1 7 /* */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_EN_HPD_IRQ_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN 0x00118c38 /* RW-4R */
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#define NV_PGC6_SCI_WAKE_RISE_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_0 0:0 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_1 1:1 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_2 2:2 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_3 3:3 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_4 4:4 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_5 5:5 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_6 6:6 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_MISC_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_POWER_ALERT 12:12 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_POWER_ALERT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_POWER_ALERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_0 16:16 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_1 17:17 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_2 18:18 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_3 19:19 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_4 20:20 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_5 21:21 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_6 22:22 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_RISE_EN_HPD_STATUS_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN 0x00118c3c /* RW-4R */
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#define NV_PGC6_SCI_WAKE_FALL_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_0 0:0 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_1 1:1 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_2 2:2 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_3 3:3 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_4 4:4 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_5 5:5 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_6 6:6 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_MISC_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_POWER_ALERT 12:12 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_POWER_ALERT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_POWER_ALERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_0 16:16 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_1 17:17 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_2 18:18 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_3 19:19 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_4 20:20 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_5 21:21 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_6 22:22 /* RWIVF */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_WAKE_FALL_EN_HPD_STATUS_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR0_EN 0x00118c44 /* RW-4R */
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#define NV_PGC6_SCI_SW_INTR0_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT 0:0 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_WAKE_TIMER 1:1 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_WAKE_TIMER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_WAKE_TIMER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_I2CS 2:2 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_I2CS_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_I2CS_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_BSI_EVENT 3:3 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_BSI_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_BSI_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_RTD3_CPU_EVENT 4:4 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_RTD3_CPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_RTD3_CPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_4 12:12 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_5 13:13 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_6 14:14 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_RTD3_GPU_EVENT 23:23 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_RTD3_GPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_RTD3_GPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_ENTRY_RESPONSE_ERR 24:24 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_ENTRY_RESPONSE_ERR_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_ENTRY_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_EXIT_RETRY 25:25 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_EXIT_RETRY_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_EXIT_RETRY_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC5_EXIT 26:26 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC5_EXIT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC5_EXIT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC6_EXIT 27:27 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC6_EXIT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC6_EXIT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC5_ABORT 28:28 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC5_ABORT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC5_ABORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC6_ABORT 29:29 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC6_ABORT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GC6_ABORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_SR_UPDATE 30:30 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_SR_UPDATE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_SR_UPDATE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_ENTRY_TIMEOUT 31:31 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_ENTRY_TIMEOUT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR0_EN_GPU_EVENT_ENTRY_TIMEOUT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ(i) (8+(i)):(8+(i)) /* */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR0_EN_HPD_IRQ_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN 0x00118c48 /* RW-4R */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_0 0:0 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_1 1:1 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_2 2:2 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_3 3:3 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_4 4:4 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_5 5:5 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_6 6:6 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_MISC_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_POWER_ALERT 12:12 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_POWER_ALERT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_POWER_ALERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_0 16:16 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_1 17:17 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_2 18:18 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_3 19:19 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_4 20:20 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_5 21:21 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_6 22:22 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR1_RISE_EN_HPD_STATUS_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN 0x00118c4c /* RW-4R */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_0 0:0 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_1 1:1 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_2 2:2 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_3 3:3 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_4 4:4 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_5 5:5 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_6 6:6 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_MISC_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_POWER_ALERT 12:12 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_POWER_ALERT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_POWER_ALERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_0 16:16 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_1 17:17 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_2 18:18 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_3 19:19 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_4 20:20 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_5 21:21 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_6 22:22 /* RWIVF */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR1_FALL_EN_HPD_STATUS_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR 0x00118c50 /* R--4R */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT 0:0 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_WAKE_TIMER 1:1 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_WAKE_TIMER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_WAKE_TIMER_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_I2CS 2:2 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_I2CS_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_I2CS_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_BSI_EVENT 3:3 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_BSI_EVENT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_BSI_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_RTD3_CPU_EVENT 4:4 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_RTD3_CPU_EVENT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_RTD3_CPU_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_0 8:8 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_0_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_1 9:9 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_1_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_2 10:10 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_2_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_3 11:11 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_3_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_4 12:12 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_4_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_5 13:13 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_5_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_6 14:14 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_6_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_RTD3_GPU_EVENT 23:23 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_RTD3_GPU_EVENT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_RTD3_GPU_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_ENTRY_RESPONSE_ERR 24:24 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_ENTRY_RESPONSE_ERR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_ENTRY_RESPONSE_ERR_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_EXIT_RETRY 25:25 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_EXIT_RETRY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_EXIT_RETRY_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC5_EXIT 26:26 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC5_EXIT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC5_EXIT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC6_EXIT 27:27 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC6_EXIT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC6_EXIT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC5_ABORT 28:28 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC5_ABORT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC5_ABORT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC6_ABORT 29:29 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC6_ABORT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GC6_ABORT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_SR_UPDATE 30:30 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_SR_UPDATE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_SR_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_ENTRY_TIMEOUT 31:31 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_ENTRY_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_GPU_EVENT_ENTRY_TIMEOUT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ(i) (8+(i)):(8+(i)) /* */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_NOT_PENDING 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_CURR_HPD_IRQ_PENDING 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR 0x00118c54 /* R--4R */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_0 0:0 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_0_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_1 1:1 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_1_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_2 2:2 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_2_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_3 3:3 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_3_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_4 4:4 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_4_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_5 5:5 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_5_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_6 6:6 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_6_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_0 8:8 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_0_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_1 9:9 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_1_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_2 10:10 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_2_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_3 11:11 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_MISC_3_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_POWER_ALERT 12:12 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_POWER_ALERT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_POWER_ALERT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_0 16:16 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_0_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_1 17:17 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_1_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_2 18:18 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_2_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_3 19:19 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_3_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_4 20:20 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_4_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_5 21:21 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_5_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_6 22:22 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_6_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_NOT_PENDING 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_PENDING 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_NOT_PENDING 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_CURR_HPD_STATUS_PENDING 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV 0x00118c58 /* R--4R */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT 0:0 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_WAKE_TIMER 1:1 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_WAKE_TIMER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_WAKE_TIMER_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_I2CS 2:2 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_I2CS_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_I2CS_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_BSI_EVENT 3:3 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_BSI_EVENT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_BSI_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_RTD3_CPU_EVENT 4:4 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_RTD3_CPU_EVENT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_RTD3_CPU_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_0 8:8 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_0_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_1 9:9 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_1_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_2 10:10 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_2_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_3 11:11 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_3_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_4 12:12 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_4_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_5 13:13 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_5_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_6 14:14 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_6_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_RTD3_GPU_EVENT 23:23 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_RTD3_GPU_EVENT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_RTD3_GPU_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_ENTRY_RESPONSE_ERR 24:24 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_ENTRY_RESPONSE_ERR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_ENTRY_RESPONSE_ERR_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_EXIT_RETRY 25:25 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_EXIT_RETRY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_EXIT_RETRY_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC5_EXIT 26:26 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC5_EXIT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC5_EXIT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC6_EXIT 27:27 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC6_EXIT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC6_EXIT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC5_ABORT 28:28 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC5_ABORT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC5_ABORT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC6_ABORT 29:29 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC6_ABORT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GC6_ABORT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_SR_UPDATE 30:30 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_SR_UPDATE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_SR_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_ENTRY_TIMEOUT 31:31 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_ENTRY_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_GPU_EVENT_ENTRY_TIMEOUT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ(i) (8+(i)):(8+(i)) /* */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_NOT_PENDING 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR0_STATUS_PREV_HPD_IRQ_PENDING 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV 0x00118c5c /* R--4R */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_0 0:0 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_0_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_1 1:1 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_1_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_2 2:2 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_2_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_3 3:3 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_3_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_4 4:4 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_4_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_5 5:5 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_5_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_6 6:6 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_6_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_0 8:8 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_0_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_1 9:9 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_1_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_2 10:10 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_2_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_3 11:11 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_MISC_3_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_POWER_ALERT 12:12 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_POWER_ALERT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_POWER_ALERT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_0 16:16 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_0_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_1 17:17 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_1_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_2 18:18 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_2_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_3 19:19 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_3_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_4 20:20 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_4_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_5 21:21 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_5_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_6 22:22 /* R-IVF */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_6_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_NOT_PENDING 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_PENDING 0x00000001 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_NOT_PENDING 0x00000000 /* */
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#define NV_PGC6_SCI_SW_INTR1_STATUS_PREV_HPD_STATUS_PENDING 0x00000001 /* */
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#define NV_PGC6_SCI_SW_SEC_INTR_STATUS 0x00118c6c /* RW-4R */
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#define NV_PGC6_SCI_SW_SEC_INTR_STATUS__PRIV_LEVEL_MASK 0x00118b2c /* */
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#define NV_PGC6_SCI_SW_SEC_INTR_STATUS_GC6_EXIT 0:0 /* RWIVF */
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#define NV_PGC6_SCI_SW_SEC_INTR_STATUS_GC6_EXIT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SW_SEC_INTR_STATUS_GC6_EXIT_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SW_SEC_INTR_STATUS_GC6_EXIT_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_HW_INTR_EN 0x00118b40 /* RW-4R */
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#define NV_PGC6_SCI_HW_INTR_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_HW_INTR_EN_GPU_EVENT 0:0 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_GPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_GPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_WAKE_TIMER 1:1 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_WAKE_TIMER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_WAKE_TIMER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_I2CS 2:2 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_I2CS_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_I2CS_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_BSI_EVENT 3:3 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_BSI_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_BSI_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_RTD3_CPU_EVENT 4:4 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_RTD3_CPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_RTD3_CPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_4 12:12 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_5 13:13 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_6 14:14 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_RTD3_GPU_EVENT 23:23 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_EN_RTD3_GPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_EN_RTD3_GPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ(i) (8+(i)):(8+(i)) /* */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ__SIZE_1 7 /* */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_HW_INTR_EN_HPD_IRQ_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN 0x00118b44 /* RW-4R */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_0 0:0 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_1 1:1 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_2 2:2 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_3 3:3 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_4 4:4 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_5 5:5 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_6 6:6 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_MISC_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_POWER_ALERT 12:12 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_POWER_ALERT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_POWER_ALERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_0 16:16 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_1 17:17 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_2 18:18 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_3 19:19 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_4 20:20 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_5 21:21 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_6 22:22 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_HW_INTR_RISE_EN_HPD_STATUS_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN 0x00118b48 /* RW-4R */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_0 0:0 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_1 1:1 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_2 2:2 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_3 3:3 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_4 4:4 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_5 5:5 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_6 6:6 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_MISC_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_POWER_ALERT 12:12 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_POWER_ALERT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_POWER_ALERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_0 16:16 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_1 17:17 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_2 18:18 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_3 19:19 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_4 20:20 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_5 21:21 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_6 22:22 /* RWIVF */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_HW_INTR_FALL_EN_HPD_STATUS_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_XVE_PME 0x00118b4c /* RW-4R */
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#define NV_PGC6_SCI_XVE_PME__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_XVE_PME_STATUS 0:0 /* RWEVF */
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#define NV_PGC6_SCI_XVE_PME_STATUS_NOT_PENDING 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_XVE_PME_STATUS_PENDING 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_XVE_PME_EN 1:1 /* RWEVF */
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#define NV_PGC6_SCI_XVE_PME_EN_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_XVE_PME_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_XVE_WAKE 0x00118b50 /* RW-4R */
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#define NV_PGC6_SCI_XVE_WAKE__PRIV_LEVEL_MASK 0x00118b28 /* */
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#define NV_PGC6_SCI_XVE_WAKE_FN0_FORCE_DISABLE 0:0 /* RWEVF */
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#define NV_PGC6_SCI_XVE_WAKE_FN0_FORCE_DISABLE_NO 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_XVE_WAKE_FN0_FORCE_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_XVE_WAKE_FN2_FORCE_DISABLE 2:2 /* RWEVF */
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#define NV_PGC6_SCI_XVE_WAKE_FN2_FORCE_DISABLE_NO 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_XVE_WAKE_FN2_FORCE_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_XVE_WAKE_FN3_FORCE_DISABLE 3:3 /* RWEVF */
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#define NV_PGC6_SCI_XVE_WAKE_FN3_FORCE_DISABLE_NO 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_XVE_WAKE_FN3_FORCE_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_XVE_WAKE_FSM_GPU_EVENT 16:16 /* RWEVF */
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#define NV_PGC6_SCI_XVE_WAKE_FSM_GPU_EVENT_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_XVE_WAKE_FSM_GPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_RESIDENT_TMR 0x00118c60 /* R--4R */
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#define NV_PGC6_SCI_RESIDENT_TMR_TIME 23:0 /* R-IUF */
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#define NV_PGC6_SCI_RESIDENT_TMR_TIME_ZERO 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_RESIDENT_TMR_TIME_1US 0x00000001 /* R---V */
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#define NV_PGC6_SCI_RESIDENT_TMR_TIME_1MS 0x000003e8 /* R---V */
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#define NV_PGC6_SCI_RESIDENT_TMR_TIME_1S 0x000f4240 /* R---V */
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#define NV_PGC6_SCI_RESIDENT_TMR_TIME_10S 0x00989680 /* R---V */
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#define NV_PGC6_SCI_RESIDENT_TMR_TIME_16S 0x00f42400 /* R---V */
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#define NV_PGC6_SCI_RESIDENT_TMR_TIME_MAX 0x00ffffff /* R---V */
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#define NV_PGC6_SCI_ENTRY_TMR 0x00118c64 /* R--4R */
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#define NV_PGC6_SCI_ENTRY_TMR_TIME 15:0 /* R-IUF */
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#define NV_PGC6_SCI_ENTRY_TMR_TIME_ZERO 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_ENTRY_TMR_TIME_1US 0x00000001 /* R---V */
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#define NV_PGC6_SCI_ENTRY_TMR_TIME_1MS 0x000003e8 /* R---V */
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#define NV_PGC6_SCI_ENTRY_TMR_TIME_MAX 0x0000ffff /* R---V */
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#define NV_PGC6_SCI_EXIT_TMR 0x00118c68 /* R--4R */
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#define NV_PGC6_SCI_EXIT_TMR_TIME 15:0 /* R-IUF */
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#define NV_PGC6_SCI_EXIT_TMR_TIME_ZERO 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_EXIT_TMR_TIME_1US 0x00000001 /* R---V */
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#define NV_PGC6_SCI_EXIT_TMR_TIME_1MS 0x000003e8 /* R---V */
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#define NV_PGC6_SCI_EXIT_TMR_TIME_MAX 0x0000ffff /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0 0x00118c70 /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0__PRIV_LEVEL_MASK 0x00118b20 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0_GC5_POWERUP 5:0 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0_GC5_POWERUP_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0_GC6_POWERUP 13:8 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0_GC6_POWERUP_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0_GC5_POWERDOWN 21:16 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0_GC5_POWERDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0_GC6_POWERDOWN 29:24 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC0_GC6_POWERDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1 0x00118c74 /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1__PRIV_LEVEL_MASK 0x00118b20 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1_GC5_EXIT 5:0 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1_GC5_EXIT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1_GC6_EXIT 13:8 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1_GC6_EXIT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1_GC5_ENTRY 21:16 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1_GC5_ENTRY_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1_GC6_ENTRY 29:24 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC1_GC6_ENTRY_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC2 0x00118c78 /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC2__PRIV_LEVEL_MASK 0x00118b20 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC2_ABORT 5:0 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC2_ABORT_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC2_RESET_EXEC 13:8 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC2_RESET_EXEC_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC3 0x00118c7c /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC3__PRIV_LEVEL_MASK 0x00118b34 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC3_INDEX 5:0 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC3_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC3_TRIGGER 31:31 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC3_TRIGGER_DONE 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC3_TRIGGER_BUSY 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ENTRY_VEC3_TRIGGER_EXECUTE 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_PWR_SEQ_INST(i) (0x00118c80+((i)*4)) /* RW-4A */
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#define NV_PGC6_SCI_PWR_SEQ_INST__SIZE_1 64 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST__PRIV_LEVEL_MASK 0x00118fec /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_DATA 12:0 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_DELAY_INDEX 3:0 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_DELAY_INDEX_NONE 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX 7:4 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_FB_CLAMP 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_XTAL_CORE_CLAMP 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_PAD_CLAMP 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_ALT_MUX_SEL 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_MAIN_3V3_EN 0x00000004 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_NVVDD_PEXVDD_EN 0x00000005 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_FBVDDQ_GPU_EN 0x00000006 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_FBVDD_Q_MEM_EN 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_PEXVDD_VID 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_GPU_EVENT 0x00000009 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_NVVDD_0 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_NVVDD_EN 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_NVVDD_1 0x0000000b /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_MSVDD_PSI 0x0000000b /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_NVVDD_2 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_IDLE_IN_SW 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_NVVDD_3 0x0000000d /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_FBVDD_PSI 0x0000000d /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_NVVDD_4 0x0000000e /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_PSI_EN 0x0000000e /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_INDEX_PEX_RST 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_DATA 8:8 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_DATA_DEASSERT 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_STATE_DATA_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_PWM_UPDATE 10:10 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_PWM_UPDATE_NOOP 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_PWM_UPDATE_TRIGGER 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_VID_INDEX 7:4 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_VID_INDEX_NONE 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_VID_ID 9:8 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_VID_ID_VID_PWM_0 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_VID_ID_VID_PWM_1 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_VID_ID_VID_PWM_2 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_VID_ID_VID_PWM_3 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_TARGET 11:11 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_TARGET_REG 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_TARGET_VID 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_HALT 12:12 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_HALT_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_SEQ_HALT_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PWM_HI 11:0 /* RW-VF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_PWM_HI_ZERO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE 15:13 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE_HALT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE_SET_STATE_DELAY 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE_ARM_PWM_0 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE_ARM_PWM_1 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE_ARM_PWM_2 0x00000004 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE_ARM_PWM_3 0x00000005 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE(i) (0x00118d80+((i)*4)) /* RW-4A */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE__SIZE_1 15 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE__PRIV_LEVEL_MASK 0x00118fec /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_PERIOD 7:0 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_PERIOD_NONE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_SCALE 9:8 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_SCALE_XTAL 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_SCALE_1US 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_SCALE_10US 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_SCALE_100US 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_DELAY_TABLE_IDX_RESERVED 0x0000000c /* */
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#define NV_PGC6_SCI_DELAY_TABLE_IDX_PSI_VR_SETTLEMENT 0x0000000d /* */
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#define NV_PGC6_SCI_DELAY_TABLE_IDX_VOLTAGE_SETTLEMENT_RAMP_DOWN 0x0000000e /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE(i) (0x00118bc0+((i)*4)) /* RW-4A */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE__SIZE_1 15 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE__PRIV_LEVEL_MASK 0x00118b20 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_HI 11:0 /* RWIUF */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_HI_OFF 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_VID_TABLE_IDX_GC5_NVVDDL_STEADY_STATE 0x00000000 /* */
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#define NV_PGC6_SCI_VID_TABLE_IDX_GC5_NVVDDL_SLEEP 0x00000001 /* */
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#define NV_PGC6_SCI_VID_TABLE_IDX_GC5_NVVDDS_STEADY_STATE 0x00000002 /* */
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#define NV_PGC6_SCI_VID_TABLE_IDX_GC5_NVVDDS_SLEEP 0x00000003 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE 0x00118dbc /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE__PRIV_LEVEL_MASK 0x00118b20 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FB_CLAMP 1:0 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FB_CLAMP_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FB_CLAMP_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FB_CLAMP_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FB_CLAMP_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_XTAL_CORE_CLAMP 3:2 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_XTAL_CORE_CLAMP_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_XTAL_CORE_CLAMP_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_XTAL_CORE_CLAMP_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_XTAL_CORE_CLAMP_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PAD_CLAMP 5:4 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PAD_CLAMP_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PAD_CLAMP_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PAD_CLAMP_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PAD_CLAMP_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_ALT_MUX_SEL 7:6 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_ALT_MUX_SEL_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_ALT_MUX_SEL_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_ALT_MUX_SEL_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_ALT_MUX_SEL_ARMDED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MAIN_3V3_EN 9:8 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MAIN_3V3_EN_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MAIN_3V3_EN_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MAIN_3V3_EN_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MAIN_3V3_EN_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_PEXVDD_EN 11:10 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_PEXVDD_EN_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_PEXVDD_EN_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_PEXVDD_EN_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_PEXVDD_EN_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDDQ_GPU_EN 13:12 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDDQ_GPU_EN_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDDQ_GPU_EN_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDDQ_GPU_EN_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDDQ_GPU_EN_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_Q_MEM_EN 15:14 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_Q_MEM_EN_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_Q_MEM_EN_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_Q_MEM_EN_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_Q_MEM_EN_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEXVDD_VID 17:16 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEXVDD_VID_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEXVDD_VID_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEXVDD_VID_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEXVDD_VID_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_GPU_EVENT 19:18 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_GPU_EVENT_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_GPU_EVENT_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_GPU_EVENT_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_GPU_EVENT_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_0 21:20 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_0_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_0_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_0_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_0_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_1 23:22 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_1_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_1_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_1_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_1_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_2 25:24 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_2_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_2_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_2_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_2_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_3 27:26 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_3_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_3_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_3_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_3_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_4 29:28 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_4_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_4_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_4_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_4_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEX_RST 31:30 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEX_RST_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEX_RST_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEX_RST_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PEX_RST_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_EN 21:20 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_EN_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_EN_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_EN_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_NVVDD_EN_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MSVDD_PSI 23:22 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MSVDD_PSI_INSTR 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MSVDD_PSI_DEASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MSVDD_PSI_ASSERT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_MSVDD_PSI_ARMED 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_IDLE_IN_SW 25:24 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_IDLE_IN_SW_INSTR 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_IDLE_IN_SW_DEASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_IDLE_IN_SW_ASSERT 0x00000002 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_IDLE_IN_SW_ARMED 0x00000003 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_PSI 27:26 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_PSI_INSTR 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_PSI_DEASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_PSI_ASSERT 0x00000002 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_FBVDD_PSI_ARMED 0x00000003 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PSI_EN 29:28 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PSI_EN_INSTR 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PSI_EN_DEASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PSI_EN_ASSERT 0x00000002 /* */
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#define NV_PGC6_SCI_PWR_SEQ_OVERRIDE_SEQ_STATE_PSI_EN_ARMED 0x00000003 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE 0x00118dc0 /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE__PRIV_LEVEL_MASK 0x00118ff0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FB_CLAMP 0:0 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FB_CLAMP_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FB_CLAMP_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_XTAL_CORE_CLAMP 1:1 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_XTAL_CORE_CLAMP_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_XTAL_CORE_CLAMP_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PAD_CLAMP 2:2 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PAD_CLAMP_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PAD_CLAMP_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_ALT_MUX_SEL 3:3 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_ALT_MUX_SEL_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_ALT_MUX_SEL_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_MAIN_3V3_EN 4:4 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_MAIN_3V3_EN_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_MAIN_3V3_EN_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_PEXVDD_EN 5:5 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_PEXVDD_EN_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_PEXVDD_EN_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDDQ_GPU_EN 6:6 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDDQ_GPU_EN_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDDQ_GPU_EN_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDD_Q_MEM_EN 7:7 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDD_Q_MEM_EN_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDD_Q_MEM_EN_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PEXVDD_VID 8:8 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PEXVDD_VID_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PEXVDD_VID_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_GPU_EVENT 9:9 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_GPU_EVENT_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_GPU_EVENT_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_0 10:10 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_0_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_0_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_1 11:11 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_1_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_1_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_2 12:12 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_2_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_2_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_3 13:13 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_3_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_3_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_4 14:14 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_4_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_4_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PEX_RST 15:15 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PEX_RST_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PEX_RST_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_EN 10:10 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_EN_DEASSERT 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_NVVDD_EN_ASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_MSVDD_PSI 11:11 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_MSVDD_PSI_DEASSERT 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_MSVDD_PSI_ASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_IDLE_IN_SW 12:12 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_IDLE_IN_SW_DEASSERT 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_IDLE_IN_SW_ASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDD_PSI 13:13 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDD_PSI_DEASSERT 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_FBVDD_PSI_ASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PSI_EN 14:14 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PSI_EN_DEASSERT 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ARMED_SEQ_STATE_PSI_EN_ASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE 0x00118dc4 /* R--4R */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FB_CLAMP 0:0 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FB_CLAMP_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FB_CLAMP_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_XTAL_CORE_CLAMP 1:1 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_XTAL_CORE_CLAMP_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_XTAL_CORE_CLAMP_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PAD_CLAMP 2:2 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PAD_CLAMP_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PAD_CLAMP_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_ALT_MUX_SEL 3:3 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_ALT_MUX_SEL_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_ALT_MUX_SEL_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_MAIN_3V3_EN 4:4 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_MAIN_3V3_EN_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_MAIN_3V3_EN_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_PEXVDD_EN 5:5 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_PEXVDD_EN_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_PEXVDD_EN_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDDQ_GPU_EN 6:6 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDDQ_GPU_EN_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDDQ_GPU_EN_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDD_Q_MEM_EN 7:7 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDD_Q_MEM_EN_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDD_Q_MEM_EN_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PEXVDD_VID 8:8 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PEXVDD_VID_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PEXVDD_VID_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_GPU_EVENT 9:9 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_GPU_EVENT_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_GPU_EVENT_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_0 10:10 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_0_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_0_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_1 11:11 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_1_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_1_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_2 12:12 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_2_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_2_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_3 13:13 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_3_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_3_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_4 14:14 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_4_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_4_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PEX_RST 15:15 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PEX_RST_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PEX_RST_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_EN 10:10 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_EN_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_NVVDD_EN_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_MSVDD_PSI 11:11 /* R-IVF */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_MSVDD_PSI_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_MSVDD_PSI_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_IDLE_IN_SW 12:12 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_IDLE_IN_SW_DEASSERT 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_IDLE_IN_SW_ASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDD_PSI 13:13 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDD_PSI_DEASSERT 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_FBVDD_PSI_ASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PSI_EN 14:14 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PSI_EN_DEASSERT 0x00000000 /* */
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#define NV_PGC6_SCI_PWR_SEQ_ACTIVE_SEQ_STATE_PSI_EN_ASSERT 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE 0x00118dc8 /* RW-4R */
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#define NV_PGC6_SCI_PWR_SEQ_STATE__PRIV_LEVEL_MASK 0x00118ff0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_UPDATE 0:0 /* RWIVF */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_UPDATE_DONE 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PWR_SEQ_STATE_UPDATE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_GPIO_INPUT_FILTER 0x00118e7c /* RW-4R */
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#define NV_PGC6_SCI_GPIO_INPUT_FILTER__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_GPIO_INPUT_FILTER_LIMIT 5:0 /* RWIUF */
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#define NV_PGC6_SCI_GPIO_INPUT_FILTER_LIMIT_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_FILTER_LIMIT_DEFAULT 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD(i) (0x00118e00+(i)*4) /* RW-4A */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_SELECT 5:0 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_SELECT_GPIO0 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_INVALID 8:8 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_INVALID_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_INVALID_YES 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_GLITCH_FILTER 9:9 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_GLITCH_FILTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_GLITCH_FILTER_ENABLE 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_INVERT 10:10 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_INVERT_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_INVERT_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_STATE 11:11 /* R--VF */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_STATE_DEASSERT 0x00000000 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_STATE_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT 0x00118e3c /* RW-4R */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_SELECT 5:0 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_SELECT_GPIO0 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_INVALID 8:8 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_INVALID_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_INVALID_YES 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_GLITCH_FILTER 9:9 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_GLITCH_FILTER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_GLITCH_FILTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_INVERT 10:10 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_INVERT_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_INVERT_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_STATE 11:11 /* R--VF */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_STATE_DEASSERT 0x00000000 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_GPU_EVENT_STATE_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT 0x00118e40 /* RW-4R */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_SELECT 5:0 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_SELECT_GPIO0 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_INVALID 8:8 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_INVALID_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_INVALID_YES 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_GLITCH_FILTER 9:9 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_GLITCH_FILTER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_GLITCH_FILTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_INVERT 10:10 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_INVERT_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_INVERT_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_STATE 11:11 /* R--VF */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_STATE_DEASSERT 0x00000000 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_POWER_ALERT_STATE_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC(i) (0x00118e20+(i)*4) /* RW-4A */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC__SIZE_1 4 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_SELECT 5:0 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_SELECT_GPIO0 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_INVALID 8:8 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_INVALID_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_INVALID_YES 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_GLITCH_FILTER 9:9 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_GLITCH_FILTER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_GLITCH_FILTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_INVERT 10:10 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_INVERT_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_INVERT_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_STATE 11:11 /* R--VF */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_STATE_DEASSERT 0x00000000 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_STATE_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST 0x00118e38 /* RW-4R */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST__PRIV_LEVEL_MASK 0x00118fdc /* */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_SELECT 5:0 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_SELECT_GPIO0 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_INVALID 8:8 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_INVALID_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_INVALID_YES 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_GLITCH_FILTER 9:9 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_GLITCH_FILTER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_GLITCH_FILTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_INVERT 10:10 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_INVERT_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_INVERT_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_STATE 11:11 /* R--VF */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_STATE_DEASSERT 0x00000000 /* R---V */
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#define NV_PGC6_SCI_GPIO_INPUT_SYS_PEX_RST_STATE_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL(i) (0x001188a0+(i)*4) /* RW-4A */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL__SIZE_1 36 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL__PRIV_LEVEL_MASK 0x00118ff4 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL 5:0 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_VID_PWM_0 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_VID_PWM_1 0x00000004 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SOR_BACKLIGHT 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_FSM_GPU_EVENT 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_ROSC_DIV16 0x00000005 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_XTAL_PAD 0x00000006 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_XTAL_CORE 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_DEBUG_BIT0 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_DEBUG_BIT1 0x00000009 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_DEBUG_BIT2 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_DEBUG_BIT3 0x0000000b /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_DEBUG_BIT4 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_DEBUG_BIT5 0x0000000d /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_DEBUG_BIT6 0x0000000e /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_DEBUG_BIT7 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_FB_CLAMP 0x00000010 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_XTAL_CORE_CLAMP 0x00000011 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_PAD_CLAMP 0x00000012 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_ALT_MUX_SEL 0x00000013 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_MAIN_3V3_EN 0x00000014 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_NVVDD_PEXVDD_EN 0x00000015 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_FBVDDQ_GPU_EN 0x00000016 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_FBVDD_Q_MEM_EN 0x00000017 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_PEXVDD_VID 0x00000018 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_GPU_EVENT 0x00000019 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_NVVDD_0 0x0000001a /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_NVVDD_EN 0x0000001a /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_NVVDD_1 0x0000001b /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_MSVDD_PSI 0x0000001b /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_NVVDD_2 0x0000001c /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_IDLE_IN_SW 0x0000001c /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_NVVDD_3 0x0000001d /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_FBVDD_PSI 0x0000001d /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_NVVDD_4 0x0000001e /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_PSI_EN 0x0000001e /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_SEQ_STATE_PEX_RST 0x0000001f /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_VID_PWM_2 0x00000020 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_VID_PWM_3 0x00000021 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_PGOOD_STATUS 0x00000022 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_BSI2SCI_PGOOD 0x00000023 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_DRIVE_MODE 9:8 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_DRIVE_MODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_DRIVE_MODE_FULL_DRIVE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_DRIVE_MODE_OPEN_DRAIN 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_DRIVE_MODE_OPEN_SOURCE 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_POLARITY 10:10 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_POLARITY_ACTIVE_LOW 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_POLARITY_ACTIVE_HIGH 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SCI_DRIVE 11:11 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SCI_DRIVE_GCX 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SCI_DRIVE_ALWAYS 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_NORM_OUT_DATA 14:14 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_NORM_OUT_DATA_DEASSERT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_NORM_OUT_DATA_ASSERT 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_NORM_IN_DATA 15:15 /* R-XVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_NORM_IN_DATA_LOW 0x00000000 /* R---V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_NORM_IN_DATA_HIGH 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_COPY 16:16 /* RWIVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_COPY_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_COPY_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_OUT_DATA 17:17 /* R-IVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_OUT_DATA_LOW 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_OUT_DATA_HIGH 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_OUT_ENAB 18:18 /* R-IVF */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_OUT_ENAB_ACTIVE 0x00000000 /* R---V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_PMGR_OUT_ENAB_TRISTATE 0x00000001 /* R-I-V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG 0x00118f00 /* RW-4R */
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#define NV_PGC6_SCI_GPU_I2CS_CFG__PRIV_LEVEL_MASK 0x00118fe0 /* */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_I2C_ADDR 7:1 /* RWIUF */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_I2C_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_I2C_ADDR_VALID 8:8 /* RWIVF */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_I2C_ADDR_VALID_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_I2C_ADDR_VALID_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_ARP_ADDR_VALID 9:9 /* RWIVF */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_ARP_ADDR_VALID_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_ARP_ADDR_VALID_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_INVALIDATE_THERM_IN_GC5 10:10 /* RWIVF */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_INVALIDATE_THERM_IN_GC5_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_INVALIDATE_THERM_IN_GC5_YES 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_SCL_TIMEOUT_VALUE 20:16 /* RWIUF */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_SCL_TIMEOUT_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_SCL_TIMEOUT_VALUE_UNDER_LIMIT 0x00000018 /* RWI-V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_SCL_TIMEOUT_SCALE 22:21 /* RWIVF */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_SCL_TIMEOUT_SCALE_1USEC 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_SCL_TIMEOUT_SCALE_10USEC 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_SCL_TIMEOUT_SCALE_100USEC 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_SCL_TIMEOUT_SCALE_1MSEC 0x00000003 /* RWI-V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_REPLAY_SPEED 27:24 /* RWIVF */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_REPLAY_SPEED_FASTEST 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_CFG_REPLAY_SPEED_SLOWEST 0x0000000f /* RWI-V */
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#define NV_PGC6_SCI_GPU_I2CS_REPLAY 0x00118f04 /* RW-4R */
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#define NV_PGC6_SCI_GPU_I2CS_REPLAY__PRIV_LEVEL_MASK 0x00118fe0 /* */
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#define NV_PGC6_SCI_GPU_I2CS_REPLAY_THERM_I2CS_STATE 0:0 /* RWIVF */
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#define NV_PGC6_SCI_GPU_I2CS_REPLAY_THERM_I2CS_STATE_INVALID 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_I2CS_REPLAY_THERM_I2CS_STATE_VALID 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_GPU_I2CS_REPLAY_STATUS 1:1 /* R-IVF */
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#define NV_PGC6_SCI_GPU_I2CS_REPLAY_STATUS_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_GPU_I2CS_REPLAY_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP 0x00118fb0 /* R--4R */
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#define NV_PGC6_SCI_STRAP__PRIV_LEVEL_MASK 0x00118b30 /* */
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#define NV_PGC6_SCI_STRAP_RAMCFG 4:0 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RAMCFG_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_FS_OVERT 8:8 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_FS_OVERT_DISABLE 0x00000000 /* R---V */
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#define NV_PGC6_SCI_STRAP_FS_OVERT_ENABLE 0x00000001 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DUMMY_BIT 10:9 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DUMMY_BIT_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_VGA_DEVICE 16:16 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_VGA_DEVICE_DISABLED 0x00000000 /* R---V */
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#define NV_PGC6_SCI_STRAP_VGA_DEVICE_ENABLED 0x00000001 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_SMB_ALT_ADDR 17:17 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_SMB_ALT_ADDR_DISABLED 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_SMB_ALT_ADDR_ENABLED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_DEVID_SEL 18:18 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEVID_SEL_ORIGINAL 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEVID_SEL_REBRAND 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_PCIE_CFG 19:19 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_PCIE_CFG_HIGH_POWER 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_PCIE_CFG_LOW_POWER 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_SMARTFAN 22:20 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_SMARTFAN_DISABLE_DISABLE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_SMARTFAN_33_DISABLE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_SMARTFAN_66_DISABLE 0x00000002 /* R---V */
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#define NV_PGC6_SCI_STRAP_SMARTFAN_33_33 0x00000003 /* R---V */
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#define NV_PGC6_SCI_STRAP_SMARTFAN_66_66 0x00000004 /* R---V */
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#define NV_PGC6_SCI_STRAP_SMARTFAN_66_33 0x00000005 /* R---V */
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#define NV_PGC6_SCI_STRAP_SMARTFAN_33_66 0x00000006 /* R---V */
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#define NV_PGC6_SCI_STRAP_SMARTFAN_RESERVED 0x00000007 /* R---V */
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#define NV_PGC6_SCI_STRAP_SENSE_STATUS 31:30 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_SENSE_STATUS_UNSENSED 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_SENSE_STATUS_ORIGINAL_SENSE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_SENSE_STATUS_RESENSE 0x00000002 /* R---V */
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#define NV_PGC6_SCI_STRAP_SENSE_STATUS_OVERRIDE 0x00000003 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE 0x00118fb4 /* RW-4R */
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#define NV_PGC6_SCI_STRAP_RESENSE__PRIV_LEVEL_MASK 0x00118b30 /* */
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#define NV_PGC6_SCI_STRAP_RESENSE_RAMCFG 4:0 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_RAMCFG_DISABLED 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_RAMCFG_ENABLED 0x0000001F /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_FS_OVERT 8:8 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_FS_OVERT_DISABLE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_FS_OVERT_ENABLE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_DUMMY_BIT 10:9 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_DUMMY_BIT_DISABLE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_DUMMY_BIT_ENABLE 0x00000003 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_VGA_DEVICE 16:16 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_VGA_DEVICE_DISABLED 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_VGA_DEVICE_ENABLED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMB_ALT_ADDR 17:17 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMB_ALT_ADDR_DISABLED 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMB_ALT_ADDR_ENABLED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_DEVID_SEL 18:18 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_DEVID_SEL_DISABLED 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_DEVID_SEL_ENABLED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_PCIE_CFG 19:19 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_PCIE_CFG_DISABLED 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_PCIE_CFG_ENABLED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN 22:20 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN_DISABLE_DISABLE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN_33_DISABLE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN_66_DISABLE 0x00000002 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN_33_33 0x00000003 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN_66_66 0x00000004 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN_66_33 0x00000005 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN_33_66 0x00000006 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_SMARTFAN_RESERVED 0x00000007 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_USE 30:30 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_USE_ORIGINAL_SENSE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_USE_RESENSE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_RESENSE_TRIGGER 31:31 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_RESENSE_TRIGGER_DONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_RESENSE_TRIGGER_IN_PROG 0x00000001 /* R---V */
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#define NV_PGC6_SCI_STRAP_RESENSE_TRIGGER_RESENSE 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_STRAP_OVERRIDE 0x00118fb8 /* RW-4R */
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#define NV_PGC6_SCI_STRAP_OVERRIDE__PRIV_LEVEL_MASK 0x00118b30 /* */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_RAMCFG 4:0 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_RAMCFG_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_FS_OVERT 8:8 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_FS_OVERT_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_FS_OVERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_DUMMY_BIT 10:9 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_DUMMY_BIT_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_VGA_DEVICE 16:16 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_VGA_DEVICE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_VGA_DEVICE_ENABLED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMB_ALT_ADDR 17:17 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMB_ALT_ADDR_DISABLED 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMB_ALT_ADDR_ENABLED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_DEVID_SEL 18:18 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_DEVID_SEL_ORIGINAL 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_DEVID_SEL_REBRAND 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_PCIE_CFG 19:19 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_PCIE_CFG_HIGH_POWER 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_PCIE_CFG_LOW_POWER 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN 22:20 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN_DISABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN_33_DISABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN_66_DISABLE 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN_33_33 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN_66_66 0x00000004 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN_66_33 0x00000005 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN_33_66 0x00000006 /* RW--V */
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#define NV_PGC6_SCI_STRAP_OVERRIDE_SMARTFAN_RESERVED 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE 0x00118fbc /* RW-4R */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE__PRIV_LEVEL_MASK 0x00118b30 /* */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_RAMCFG 4:0 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_RAMCFG_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_FS_OVERT 8:8 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_FS_OVERT_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_FS_OVERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_DUMMY_BIT 10:9 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_DUMMY_BIT_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_VGA_DEVICE 16:16 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_VGA_DEVICE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_VGA_DEVICE_ENABLED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_SMB_ALT_ADDR 17:17 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_SMB_ALT_ADDR_DISABLED 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_SMB_ALT_ADDR_ENABLED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_DEVID_SEL 18:18 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_DEVID_SEL_DISABLED 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_DEVID_SEL_ENABLED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_PCIE_CFG 19:19 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_PCIE_CFG_DISABLED 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_PCIE_CFG_ENABLED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_SMARTFAN 22:20 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_MASK_OVERRIDE_SMARTFAN_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_STRAP_DEBUG 0x00118fc0 /* R--4R */
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#define NV_PGC6_SCI_STRAP_DEBUG__PRIV_LEVEL_MASK 0x00118b30 /* */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP0 1:0 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP0_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP1 3:2 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP1_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP2 5:4 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP2_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_ROM_SCLK 7:6 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_ROM_SCLK_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_ROM_SO 9:8 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_ROM_SO_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_ROM_SI 11:10 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_ROM_SI_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP3 13:12 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP3_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP4 15:14 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP4_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP5 17:16 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_STRAP5_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_DEBUG_XTALOUTBUFF 19:18 /* R-EVF */
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#define NV_PGC6_SCI_STRAP_DEBUG_XTALOUTBUFF_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_STRAP_SENSE_TIMEOUT 0x00118fc4 /* RW-4R */
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#define NV_PGC6_SCI_STRAP_SENSE_TIMEOUT__PRIV_LEVEL_MASK 0x00118b30 /* */
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#define NV_PGC6_SCI_STRAP_SENSE_TIMEOUT_VALUE 14:0 /* RWEVF */
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#define NV_PGC6_SCI_STRAP_SENSE_TIMEOUT_VALUE_1MS 0x00006977 /* RWE-V */
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#define NV_PGC6_SCI_FAN_CFG0(i) (0x00118aa0+((i)*24)) /* RW-4A */
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#define NV_PGC6_SCI_FAN_CFG0__SIZE_1 2 /* */
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#define NV_PGC6_SCI_FAN_CFG0__PRIV_LEVEL_MASK 0x00118ff8 /* */
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#define NV_PGC6_SCI_FAN_CFG0_PERIOD 12:0 /* RWEVF */
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#define NV_PGC6_SCI_FAN_CFG0_PERIOD_MIN 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FAN_CFG0_PERIOD_125KHZ 0x000000d8 /* RWE-V */
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#define NV_PGC6_SCI_FAN_CFG0_PERIOD_MAX 0x00001fff /* RW--V */
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#define NV_PGC6_SCI_FAN_CFG0_SHARING 24:24 /* RWEVF */
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#define NV_PGC6_SCI_FAN_CFG0_SHARING_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FAN_CFG0_SHARING_ENABLE 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_FAN_CFG0_POLARITY 25:25 /* RWEVF */
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#define NV_PGC6_SCI_FAN_CFG0_POLARITY_ACTIVE_LOW 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FAN_CFG0_POLARITY_ACTIVE_HIGH 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FAN_CFG0_SCI_OVERRIDE 27:27 /* RWEVF */
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#define NV_PGC6_SCI_FAN_CFG0_SCI_OVERRIDE_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FAN_CFG0_SCI_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FAN_CFG0_SCI_CORE_CLMP 28:28 /* RWEVF */
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#define NV_PGC6_SCI_FAN_CFG0_SCI_CORE_CLMP_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FAN_CFG0_SCI_CORE_CLMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FAN_CFG1(i) (0x00118aa4+((i)*24)) /* RW-4A */
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#define NV_PGC6_SCI_FAN_CFG1__SIZE_1 2 /* */
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#define NV_PGC6_SCI_FAN_CFG1__PRIV_LEVEL_MASK 0x00118ff8 /* */
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#define NV_PGC6_SCI_FAN_CFG1_HI 12:0 /* RWEVF */
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#define NV_PGC6_SCI_FAN_CFG1_HI_OFF 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FAN_CFG1_HI_33 0x00000048 /* RW--V */
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#define NV_PGC6_SCI_FAN_CFG1_HI_66 0x00000090 /* RW--V */
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#define NV_PGC6_SCI_FAN_CFG1_UPDATE 31:31 /* RWEVF */
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#define NV_PGC6_SCI_FAN_CFG1_UPDATE_DONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FAN_CFG1_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_FAN_CFG1_UPDATE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT(i) (0x00118aa8+((i)*24)) /* RW-4A */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT__SIZE_1 2 /* */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT__PRIV_LEVEL_MASK 0x00118ff8 /* */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_HI 12:0 /* RWEVF */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_HI_OFF 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_OVERRIDE 24:24 /* RWEVF */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_OVERRIDE_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_FORCE 25:25 /* RWEVF */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_FORCE_NO 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FAN_DEBUG 0x00118f1c /* R--4R */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP 2:0 /* R-XVF */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_DISABLE_DISABLE 0x00000000 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_66_DISABLE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_66_66 0x00000002 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_33_DISABLE 0x00000003 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_33_33 0x00000004 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_33_66 0x00000005 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_66_33 0x00000006 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_DISABLE 0x00000000 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_66 0x00000001 /* R---V */
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#define NV_PGC6_SCI_FAN_DEBUG_PWM_STRAP_33 0x00000003 /* R---V */
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#define NV_PGC6_SCI_FAN_ACT0(i) (0x00118ab0+((i)*24)) /* RW-4A */
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#define NV_PGC6_SCI_FAN_ACT0__SIZE_1 2 /* */
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#define NV_PGC6_SCI_FAN_ACT0_PERIOD 18:0 /* R-EUF */
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#define NV_PGC6_SCI_FAN_ACT0_PERIOD_125KHZ 0x000000d8 /* R-E-V */
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#define NV_PGC6_SCI_FAN_ACT0_PERIOD_MAX 0x0007ffff /* R---V */
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#define NV_PGC6_SCI_FAN_ACT0_OVERFLOW 24:24 /* RWEVF */
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#define NV_PGC6_SCI_FAN_ACT0_OVERFLOW_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_FAN_ACT0_OVERFLOW_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_FAN_ACT0_OVERFLOW_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_FAN_ACT1(i) (0x00118ab4+((i)*24)) /* R--4A */
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#define NV_PGC6_SCI_FAN_ACT1__SIZE_1 2 /* */
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#define NV_PGC6_SCI_FAN_ACT1_HI 18:0 /* R-EUF */
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#define NV_PGC6_SCI_FAN_ACT1_HI_OFF 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_FAN_ACT1_HI_MAX 0x0007ffff /* R---V */
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#define NV_PGC6_SCI_FAN_PWM_IDX_PRIMARY_GPIO16 0x00000000 /* */
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#define NV_PGC6_SCI_FAN_PWM_IDX_SECONDARY_GPIO3 0x00000001 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE_ARM_PWM(i) (((i)==0)?0x00000002:((i)==1)?0x00000003:((i)==2)?0x00000004:((i)==3)?0x00000005:0xffffffff) /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_OPCODE_ARM_PWM__SIZE_1 4 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_VID_PWM(i) (((i)==0)?0x00000001:((i)==1)?0x00000004:((i)==2)?0x00000020:((i)==3)?0x00000021:0xffffffff) /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_SEL_VID_PWM__SIZE_1 4 /* */
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#define NV_PGC6_SCI_VID_CFG0(i) (0x00118f20+(i)*8) /* RW-4A */
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#define NV_PGC6_SCI_VID_CFG0__SIZE_1 4 /* */
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#define NV_PGC6_SCI_VID_CFG0__PRIV_LEVEL_MASK 0x00118ffc /* */
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#define NV_PGC6_SCI_VID_CFG0_PERIOD 11:0 /* RWIVF */
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#define NV_PGC6_SCI_VID_CFG0_PERIOD_MIN 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_VID_CFG0_PERIOD_125KHZ 0x000000d8 /* RWI-V */
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#define NV_PGC6_SCI_VID_CFG0_BIT_SPREAD 24:24 /* RWIVF */
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#define NV_PGC6_SCI_VID_CFG0_BIT_SPREAD_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_VID_CFG0_BIT_SPREAD_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_VID_CFG0_MIN_SPREAD 30:25 /* RWIUF */
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#define NV_PGC6_SCI_VID_CFG0_MIN_SPREAD_SHORTEST 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_VID_CFG1(i) (0x00118f24+(i)*8) /* RW-4A */
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#define NV_PGC6_SCI_VID_CFG1__SIZE_1 4 /* */
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#define NV_PGC6_SCI_VID_CFG1__PRIV_LEVEL_MASK 0x00118ffc /* */
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#define NV_PGC6_SCI_VID_CFG1_HI 11:0 /* RWIVF */
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#define NV_PGC6_SCI_VID_CFG1_HI_OFF 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_VID_CFG1_UPDATE 31:31 /* RWIVF */
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#define NV_PGC6_SCI_VID_CFG1_UPDATE_DONE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_VID_CFG1_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_VID_CFG1_UPDATE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_SOR_PWM_DIV 0x00118f40 /* RW-4R */
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#define NV_PGC6_SCI_SOR_PWM_DIV_DIVIDE 23:0 /* RWIUF */
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#define NV_PGC6_SCI_SOR_PWM_DIV_DIVIDE_PWM_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SOR_PWM_CTL 0x00118f44 /* RW-4R */
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#define NV_PGC6_SCI_SOR_PWM_CTL_DUTY_CYCLE 23:0 /* RWIUF */
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#define NV_PGC6_SCI_SOR_PWM_CTL_DUTY_CYCLE_OFF 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SOR_PWM_CTL_CLKSEL 30:30 /* C--VF */
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#define NV_PGC6_SCI_SOR_PWM_CTL_CLKSEL_XTAL 0x00000001 /* C---V */
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#define NV_PGC6_SCI_SOR_PWM_CTL_SETTING_NEW 31:31 /* RWIVF */
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#define NV_PGC6_SCI_SOR_PWM_CTL_SETTING_NEW_DONE 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SOR_PWM_CTL_SETTING_NEW_PENDING 0x00000001 /* R---V */
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#define NV_PGC6_SCI_SOR_PWM_CTL_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM 0x00118b90 /* RW-4R */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_TS_CLK_DIV 4:0 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_TS_CLK_DIV_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_TS_CLK_DIV_1MHZ 0x0000001b /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_STABLE_PERIOD 11:8 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_STABLE_PERIOD_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_STABLE_PERIOD_NOMINAL 0x00000003 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_STABLE_SCALE 13:13 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_STABLE_SCALE_16_TS_CLK 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_STABLE_SCALE_1024_TS_CLK 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_PERIOD 20:16 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_PERIOD_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_PERIOD_NOMINAL 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE 23:21 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE_1_TS_CLK 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE_10_TS_CLK 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE_100_TS_CLK 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE_1000_TS_CLK 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE_10000_TS_CLK 0x00000004 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE_100000_TS_CLK 0x00000005 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE_1000000_TS_CLK 0x00000006 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_SM_POLLING_SCALE_10000000_TS_CLK 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ 0x00118b94 /* RW-4R */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_BG_VOLTAGE 7:0 /* R-EVF */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_BG_VOLTAGE_MIN 0x00000000 /* R---V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_BG_VOLTAGE_NOMINAL 0x00000040 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_BG_VOLTAGE_MAX 0x000000ff /* R---V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_BG_TEMP_COEFF 10:8 /* R-EVF */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_BG_TEMP_COEFF_MIN 0x00000000 /* R---V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_BG_TEMP_COEFF_NOMINAL 0x00000002 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_BG_TEMP_COEFF_MAX 0x00000007 /* R---V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_CONFIG 31:11 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADJ_CONFIG_OPERATIONAL 0x0000000e /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH 0x00118b98 /* RW-4R */
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#define NV_PGC6_SCI_FS_OVERT_THRESH__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TEMP 16:8 /* RWESF */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TEMP_MIN 0x00000100 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TEMP_110C 0x0000006e /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TEMP_MAX 0x000000ff /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_PERIOD 28:24 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_PERIOD_ZERO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_PERIOD_NOMINAL 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE 31:29 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE_1US 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE_10US 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE_100US 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE_1MS 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE_10MS 0x00000004 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE_100MS 0x00000005 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE_1S 0x00000006 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_THRESH_TIME_SCALE_10S 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL 0x00118b9c /* RW-4R */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_PRESNAP_BG_VOLTAGE 7:0 /* R-EUF */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_PRESNAP_BG_VOLTAGE_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_PRESNAP_BG_TEMP_COEFF 10:8 /* R-EUF */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_PRESNAP_BG_TEMP_COEFF_INIT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_PRESNAP_BG_VALID 11:11 /* R-EVF */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_PRESNAP_BG_VALID_NO 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_PRESNAP_BG_VALID_YES 0x00000001 /* R---V */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_HW_AUTO_SNAP 31:31 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_HW_AUTO_SNAP_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_FUSECTRL_HW_AUTO_SNAP_ENABLE 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE 0x00118ba0 /* RW-4R */
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#define NV_PGC6_SCI_FS_OVERT_FUSE__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_BG_VOLTAGE 7:0 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_BG_VOLTAGE_MIN 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_BG_VOLTAGE_NOMINAL 0x00000040 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_BG_VOLTAGE_MAX 0x000000ff /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_BG_TEMP_COEFF 10:8 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_BG_TEMP_COEFF_MIN 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_BG_TEMP_COEFF_NOMINAL 0x00000002 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_BG_TEMP_COEFF_MAX 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_TEMP_COEFF_ADJ_A 20:11 /* RWESF */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_TEMP_COEFF_ADJ_A_NONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_TEMP_COEFF_ADJ_B 30:21 /* RWESF */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_TEMP_COEFF_ADJ_B_NONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_FUSE_TEMP_COEFF_ADJ_B_MINUS_15 0x000003e2 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_NOM 0x00118ba4 /* RW-4R */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_NOM__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_NOM_A 9:0 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_NOM_A_NOMINAL 0x00000226 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_NOM_B 26:16 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_NOM_B_NOMINAL 0x0000028e /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_FINAL 0x00118ba8 /* R--4R */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_FINAL__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_FINAL_A 11:0 /* R-ESF */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_FINAL_A_NOMINAL 0x00000226 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_FINAL_B 28:16 /* R-ESF */
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#define NV_PGC6_SCI_FS_OVERT_TEMP_COEFF_FINAL_B_NOMINAL 0x0000028e /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC 0x00118bac /* RW-4R */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC_RAW_CODE 13:0 /* R-EUF */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC_RAW_CODE_MIN 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC_OVERRIDE_VALUE 29:16 /* RWEUF */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC_OVERRIDE_VALUE_ZERO 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC_OVERRIDE_CTRL 31:31 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC_OVERRIDE_CTRL_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_TS_ADC_OVERRIDE_CTRL_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_TEMPERATURE 0x00118bb0 /* R--4R */
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#define NV_PGC6_SCI_FS_OVERT_TEMPERATURE__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_TEMPERATURE_INTEGER 16:8 /* R-ESF */
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#define NV_PGC6_SCI_FS_OVERT_TEMPERATURE_INTEGER_MIN 0x00000100 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_TEMPERATURE_INTEGER_MAX 0x000000ff /* R---V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL 0x00118bb4 /* RW-4R */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL__PRIV_LEVEL_MASK 0x00118fd0 /* */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_EN_VALUE 0:0 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_EN_VALUE_LOW 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_EN_VALUE_HIGH 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_EN_OVERRIDE 1:1 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_EN_OVERRIDE_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_EN_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_CTL_SEL_VALUE 2:2 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_CTL_SEL_VALUE_LOW 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_CTL_SEL_VALUE_HIGH 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_CTL_SEL_OVERRIDE 3:3 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_CTL_SEL_OVERRIDE_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_ALT_CTL_SEL_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CORE_CLMP_VALUE 4:4 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CORE_CLMP_VALUE_LOW 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CORE_CLMP_VALUE_HIGH 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CORE_CLMP_OVERRIDE 5:5 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CORE_CLMP_OVERRIDE_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CORE_CLMP_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_OVERT_CLAMP_ON_S3 8:8 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_OVERT_CLAMP_ON_S3_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_OVERT_CLAMP_ON_S3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_FAILSAFE_OVERT 16:16 /* R-EVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_FAILSAFE_OVERT_DEASSERT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_FAILSAFE_OVERT_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_LATCH_OVERT 17:17 /* R-EVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_LATCH_OVERT_DEASSERT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_LATCH_OVERT_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CFG_FAILSAFE 20:20 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CFG_FAILSAFE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CFG_FAILSAFE_ENABLE 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CFG_LATCH 21:21 /* RWEVF */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CFG_LATCH_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_FS_OVERT_PADCTL_CFG_LATCH_ENABLE 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG 0x00118b60 /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_DEV_ADDR 7:1 /* RWEUF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_DEV_ADDR_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_DEV_ADDR_VALID 8:8 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_DEV_ADDR_VALID_NO 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_DEV_ADDR_VALID_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_CAPABLE 12:12 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_CAPABLE_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_CAPABLE_YES 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_UDID_RANDOM 13:13 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_UDID_RANDOM_NO 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_UDID_RANDOM_YES 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_RSVD_DEV_ADDR_CHECK 14:14 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_RSVD_DEV_ADDR_CHECK_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_RSVD_DEV_ADDR_CHECK_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_RSVD_COMMAND_CHECK 15:15 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_RSVD_COMMAND_CHECK_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_ARP_RSVD_COMMAND_CHECK_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_TIMEOUT 21:16 /* RWEUF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_TIMEOUT_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_TIMEOUT_25MS 0x00000019 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_TIMEOUT_35MS 0x00000022 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_TIMEOUT_MAX 0x0000003f /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_SPIKE 25:24 /* RWEUF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_SPIKE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_SPIKE_74NS 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_HOLD 31:28 /* RWEUF */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_HOLD_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CFG_HOLD_222NS 0x00000006 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP 0x00118b64 /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_ARP_ADR 7:1 /* R-EUF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_ARP_ADR_INVALID 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_AV_FLAG 8:8 /* R-EVF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_AV_FLAG_INVALID 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_AV_FLAG_VALID 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_AR_FLAG 9:9 /* R-EVF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_AR_FLAG_UNRESOLVED 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_AR_FLAG_RESOLVED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_ARP_ADR_VALUE 23:17 /* RWEUF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_ARP_ADR_VALUE_INVALID 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AV_FLAG_VALUE 24:24 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AV_FLAG_VALUE_INVALID 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AV_FLAG_VALUE_VALID 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AR_FLAG_VALUE 25:25 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AR_FLAG_VALUE_UNRESOLVED 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AR_FLAG_VALUE_RESOLVED 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_ARP_ADR 28:28 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_ARP_ADR_DONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_ARP_ADR_IN_PROG 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_ARP_ADR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AV_FLAG 29:29 /* RWEUF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AV_FLAG_DONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AV_FLAG_IN_PROG 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AV_FLAG_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AR_FLAG 30:30 /* RWEUF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AR_FLAG_DONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AR_FLAG_IN_PROG 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_OVERRIDE_AR_FLAG_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_RESNAP_UDID_RAND 31:31 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_RESNAP_UDID_RAND_DONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_RESNAP_UDID_RAND_IN_PROG 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_ARP_RESNAP_UDID_RAND_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS 0x00118b6c /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_ARP_PROCESS 0:0 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_ARP_PROCESS_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_ARP_PROCESS_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_ARP_PROCESS_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_PEC 1:1 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_PEC_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_PEC_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_PEC_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_UDID_MISMATCH 2:2 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_UDID_MISMATCH_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_UDID_MISMATCH_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_UDID_MISMATCH_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_ARP_READ_COLLISION 3:3 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_ARP_READ_COLLISION_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_ARP_READ_COLLISION_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_ARP_READ_COLLISION_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_NON_ARP_READ_COLLISION 4:4 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_NON_ARP_READ_COLLISION_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_NON_ARP_READ_COLLISION_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_NON_ARP_READ_COLLISION_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_UDID_RESNAP 5:5 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_UDID_RESNAP_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_UDID_RESNAP_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_UDID_RESNAP_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_SCL_LOW_TIMEOUT 6:6 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_SCL_LOW_TIMEOUT_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_SCL_LOW_TIMEOUT_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_SCL_LOW_TIMEOUT_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_ARP_COMMAND 7:7 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_ARP_COMMAND_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_ARP_COMMAND_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_ARP_COMMAND_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_ARP_ADR 8:8 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_ARP_ADR_NONE 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_ARP_ADR_DETECTED 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_STATUS_BAD_ARP_ADR_CLEAR 0x00000001 /* -W--C */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_3 0x00118b70 /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_3__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_3_VENDOR_ID 15:0 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_3_VENDOR_ID_INIT 0x000010DE /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_3_VER_REV 23:16 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_3_VER_REV_INIT 0x0000000a /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_3_DCAP 31:24 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_3_DCAP_INIT 0x000000C1 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_2 0x00118b74 /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_2__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_2_INTERFACE 15:0 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_2_INTERFACE_INIT 0x00000004 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_2_DEVICE_ID 31:16 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_2_DEVICE_ID_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_1 0x00118b78 /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_1__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_1_SUB_DEVICE_ID 15:0 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_1_SUB_DEVICE_ID_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_1_SUB_VENDOR_ID 31:16 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_1_SUB_VENDOR_ID_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_0 0x00118b7c /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_0__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_0_VENDOR_SPEC_ID_RAND 17:0 /* RWXVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_0_VENDOR_SPEC_ID 31:18 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_UDID_0_VENDOR_SPEC_ID_INIT 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00 0x00118b80 /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_CURR 7:0 /* R-EUF */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_CURR_ZERO 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_CURR_MIN 0x00000000 /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_CURR_MAX 0x000000ff /* R---V */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_OFFSET 15:8 /* RWESF */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_OFFSET_ZERO 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_RDAT_SEL 28:28 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_RDAT_SEL_OFFSET 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_CMD00_RDAT_SEL_OFFSET_TEMP 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL 0x00118b8c /* RW-4R */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL__PRIV_LEVEL_MASK 0x00118fcc /* */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_OVERRIDE 0:0 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_OVERRIDE_ENABLE 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_CLAMP_ON_OVERT 1:1 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_CLAMP_ON_OVERT_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_CLAMP_ON_OVERT_ENABLE 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_CLAMP_ON_S3 8:8 /* RWEVF */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_CLAMP_ON_S3_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_GPU_SMBUS_PADCTL_I2CS_CLAMP_ON_S3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_MISC_PADCTL 0x00118f48 /* RW-4R */
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#define NV_PGC6_SCI_MISC_PADCTL__PRIV_LEVEL_MASK 0x00118fe4 /* */
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#define NV_PGC6_SCI_MISC_PADCTL_XTAL_FORCE_EN 0:0 /* RWIVF */
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#define NV_PGC6_SCI_MISC_PADCTL_XTAL_FORCE_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_MISC_PADCTL_XTAL_FORCE_EN_ENABLED 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL 0x00118f4c /* RW-4R */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_BUF_RST_OVERRIDE 0:0 /* RWEVF */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_BUF_RST_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_BUF_RST_OVERRIDE_ENABLE 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_BUF_RST_CORE_CLMP 1:1 /* RWEVF */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_BUF_RST_CORE_CLMP_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_BUF_RST_CORE_CLMP_ENABLE 0x00000001 /* RWE-V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_S3_ALT_CTL_SEL 4:4 /* R-EVF */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_S3_ALT_CTL_SEL_DEASSERT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_S3_ALT_CTL_SEL_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_S3_CORE_CLMP 5:5 /* R-EVF */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_S3_CORE_CLMP_DEASSERT 0x00000000 /* R-E-V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_S3_CORE_CLMP_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_DPAUX_CLAMP_ON_S3 9:9 /* RWEVF */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_DPAUX_CLAMP_ON_S3_DISABLE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_NV_MISC_PADCTL_DPAUX_CLAMP_ON_S3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FGC6_NVLINK 0x00118b1c /* RW-4R */
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#define NV_PGC6_SCI_FGC6_NVLINK__PRIV_LEVEL_MASK 0x00118b24 /* */
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#define NV_PGC6_SCI_FGC6_NVLINK_LATCH 0:0 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_NVLINK_LATCH_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FGC6_NVLINK_LATCH_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_FGC6_NVLINK_CLAMP 1:1 /* RWIVF */
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#define NV_PGC6_SCI_FGC6_NVLINK_CLAMP_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_FGC6_NVLINK_CLAMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG 0x00118f60 /* RW-4R */
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#define NV_PGC6_SCI_PTIMER_CFG_DENOMINATOR 4:0 /* RWIUF */
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#define NV_PGC6_SCI_PTIMER_CFG_DENOMINATOR_27MHZ_REF 0x0000001b /* RWI-V */
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#define NV_PGC6_SCI_PTIMER_CFG_DENOMINATOR_25MHZ_REF 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_DENOMINATOR_108MHZ_REF 0x0000001b /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_DENOMINATOR_100MHZ_REF 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_DENOMINATOR_EMULATION 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_NUMERATOR 18:16 /* RWIUF */
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#define NV_PGC6_SCI_PTIMER_CFG_NUMERATOR_27MHZ_REF 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_PTIMER_CFG_NUMERATOR_25MHZ_REF 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_NUMERATOR_108MHZ_REF 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_NUMERATOR_100MHZ_REF 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_NUMERATOR_EMULATION 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_INTEGER 29:24 /* RWIUF */
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#define NV_PGC6_SCI_PTIMER_CFG_INTEGER_27MHZ_REF 0x00000025 /* RWI-V */
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#define NV_PGC6_SCI_PTIMER_CFG_INTEGER_25MHZ_REF 0x00000028 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_INTEGER_108MHZ_REF 0x00000009 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_INTEGER_100MHZ_REF 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_PTIMER_CFG_INTEGER_EMULATION 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_PTIMER_TIME_0 0x00118f64 /* RW-4R */
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#define NV_PGC6_SCI_PTIMER_TIME_0_UPDATE 0:0 /* RWIVF */
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#define NV_PGC6_SCI_PTIMER_TIME_0_UPDATE_DONE 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PTIMER_TIME_0_UPDATE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
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#define NV_PGC6_SCI_PTIMER_TIME_1 0x00118f68 /* RW-4R */
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#define NV_PGC6_SCI_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
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#define NV_PGC6_SCI_PTIMER_READ 0x00118f6c /* RW-4R */
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#define NV_PGC6_SCI_PTIMER_READ_SAMPLE 0:0 /* RWIVF */
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#define NV_PGC6_SCI_PTIMER_READ_SAMPLE_DONE 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PTIMER_READ_SAMPLE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGC6_SCI_PTIMER_ENABLE 0x00118f70 /* RW-4R */
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#define NV_PGC6_SCI_PTIMER_ENABLE_CTL 0:0 /* RWIVF */
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#define NV_PGC6_SCI_PTIMER_ENABLE_CTL_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_PTIMER_ENABLE_CTL_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG 0x00118f50 /* RW-4R */
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#define NV_PGC6_SCI_SEC_TIMER_CFG__PRIV_LEVEL_MASK 0x00118fd4 /* */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_DENOMINATOR 4:0 /* RWIUF */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_DENOMINATOR_27MHZ_REF 0x0000001b /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_DENOMINATOR_25MHZ_REF 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_DENOMINATOR_108MHZ_REF 0x0000001b /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_DENOMINATOR_100MHZ_REF 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_DENOMINATOR_EMULATION 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_NUMERATOR 18:16 /* RWIUF */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_NUMERATOR_27MHZ_REF 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_NUMERATOR_25MHZ_REF 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_NUMERATOR_108MHZ_REF 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_NUMERATOR_100MHZ_REF 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_NUMERATOR_EMULATION 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_INTEGER 29:24 /* RWIUF */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_INTEGER_27MHZ_REF 0x00000025 /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_INTEGER_25MHZ_REF 0x00000028 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_INTEGER_108MHZ_REF 0x00000009 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_INTEGER_100MHZ_REF 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_CFG_INTEGER_EMULATION 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_0 0x00118f54 /* RW-4R */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_0__PRIV_LEVEL_MASK 0x00118fd4 /* */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_0_UPDATE 0:0 /* RWIVF */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_0_UPDATE_DONE 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_0_UPDATE_NOOP 0x00000000 /* -W--V */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_0_UPDATE_TRIGGER 0x00000001 /* -W--V */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC 31:5 /* RWIUF */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_0_NSEC_ZERO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_1 0x00118f58 /* RW-4R */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_1__PRIV_LEVEL_MASK 0x00118fd4 /* */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC 28:0 /* RWIUF */
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#define NV_PGC6_SCI_SEC_TIMER_TIME_1_NSEC_ZERO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_SEC_TIMER_UPDATE 0x00118f5c /* R--4R */
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#define NV_PGC6_SCI_SEC_TIMER_UPDATE__PRIV_LEVEL_MASK 0x00118fd4 /* */
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#define NV_PGC6_SCI_SEC_TIMER_UPDATE_COUNT 7:0 /* R-IUF */
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#define NV_PGC6_SCI_SEC_TIMER_UPDATE_COUNT_ZERO 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SEC_TIMER_UPDATE_COUNT_MAX 0x000000ff /* R---V */
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#define NV_PGC6_SCI_XP_CLKREQ 0x00118f7c /* R--4R */
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#define NV_PGC6_SCI_XP_CLKREQ_TIMER 11:0 /* R-IVF */
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#define NV_PGC6_SCI_XP_CLKREQ_TIMER_ZERO 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_SCRATCH 0x00118f74 /* RW-4R */
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#define NV_PGC6_SCI_SCRATCH_DATA 31:0 /* RWIVF */
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#define NV_PGC6_SCI_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_NV_SCRATCH(i) (0x00118f08+((i)*4)) /* RW-4A */
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#define NV_PGC6_SCI_NV_SCRATCH__SIZE_1 4 /* */
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#define NV_PGC6_SCI_NV_SCRATCH_DATA 31:0 /* RWEVF */
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#define NV_PGC6_SCI_NV_SCRATCH_DATA_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_NV_SECURE_SCRATCH 0x00118f18 /* RW-4R */
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#define NV_PGC6_SCI_NV_SECURE_SCRATCH__PRIV_LEVEL_MASK 0x00118f78 /* */
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#define NV_PGC6_SCI_NV_SECURE_SCRATCH_DATA 31:0 /* RWEVF */
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#define NV_PGC6_SCI_NV_SECURE_SCRATCH_DATA_INIT 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_SLCG 0x00118f8c /* RW-4R */
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#define NV_PGC6_SCI_SLCG__PRIV_LEVEL_MASK 0x00118fe4 /* */
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#define NV_PGC6_SCI_SLCG_ISLAND_CLK_DELAY 5:0 /* RWIUF */
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#define NV_PGC6_SCI_SLCG_ISLAND_CLK_DELAY_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_SLCG_ISLAND_CLK_DELAY_MIN 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_SLCG_ISLAND_CLK_DELAY_INIT 0x00000004 /* RWI-V */
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#define NV_PGC6_SCI_SLCG_ISLAND_CLK_DELAY_MAX 0x00000019 /* RW--V */
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#define NV_PGC6_SCI_SPARE 0x00118f80 /* RW-4R */
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#define NV_PGC6_SCI_SPARE_DATA 7:0 /* RWIVF */
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#define NV_PGC6_SCI_SPARE_DATA_INIT 0x000000F0 /* RWI-V */
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#define NV_PGC6_SCI_SPARE2 0x00118f88 /* RW-4R */
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#define NV_PGC6_SCI_SPARE2_DATA 7:0 /* RWIVF */
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#define NV_PGC6_SCI_SPARE2_DATA_INIT 0x000000F0 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_PORT 0x00118f84 /* RW-4R */
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#define NV_PGC6_SCI_DEBUG_PORT__PRIV_LEVEL_MASK 0x00118fe8 /* */
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#define NV_PGC6_SCI_DEBUG_PORT_DATA 7:0 /* R-XVF */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL 21:16 /* RWEVF */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_NONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_LDO_0 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_BSI2SCI_0 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_BSI2SCI_1 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_SCI2BSI_0 0x00000004 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_SCI2BSI_1 0x00000005 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_SCI_MSG 0x00000006 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_THERM_I2CS_0 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_THERM_I2CS_1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_THERM_I2CS_2 0x00000009 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_PAD_CLAMP_0 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_PAD_CLAMP_1 0x0000000b /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_LVL_SHIFT 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_MST_FSM_0 0x0000000d /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_MST_FSM_1 0x0000000e /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_MST_FSM_2 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_MST_FSM_3 0x00000010 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_STRAP_0 0x00000011 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_STRAP_1 0x00000012 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_SCI_PRIV 0x00000013 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_THERM_I2CS_3 0x00000014 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_WAKE_0 0x00000015 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_HPD_IRQ_0 0x00000016 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_HPD_IRQ_1 0x00000017 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_HPD_STATUS_0 0x00000018 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_HPD_STATUS_1 0x00000019 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_TIMER_0 0x0000001a /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_TIMER_1 0x0000001b /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FAN_PWM_0 0x0000001c /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_PWR_SEQ_0 0x0000001d /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_PWR_SEQ_1 0x0000001e /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_PWR_SEQ_2 0x0000001f /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FS_OVERT_0 0x00000020 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FS_OVERT_1 0x00000021 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FS_OVERT_2 0x00000022 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FS_OVERT_3 0x00000023 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FS_OVERT_4 0x00000024 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FS_OVERT_5 0x00000025 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FS_OVERT_6 0x00000026 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FS_OVERT_7 0x00000027 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_XVE_PME_0 0x0000002b /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_XVE_PME_1 0x0000002c /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_XVE_PME_2 0x0000002d /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_XVE_PME_3 0x0000002e /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_S3_PADCTL_0 0x0000002f /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_FAN_PWM_1 0x00000030 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_LOW_NIBBLE_SEL_PGOOD_0 0x00000031 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL 29:24 /* RWEVF */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_NONE 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_LDO_0 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_BSI2SCI_0 0x00000002 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_BSI2SCI_1 0x00000003 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_SCI2BSI_0 0x00000004 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_SCI2BSI_1 0x00000005 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_SCI_MSG 0x00000006 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_THERM_I2CS_0 0x00000007 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_THERM_I2CS_1 0x00000008 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_THERM_I2CS_2 0x00000009 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_PAD_CLAMP_0 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_PAD_CLAMP_1 0x0000000b /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_LVL_SHIFT 0x0000000c /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_MST_FSM_0 0x0000000d /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_MST_FSM_1 0x0000000e /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_MST_FSM_2 0x0000000f /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_MST_FSM_3 0x00000010 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_STRAP_0 0x00000011 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_STRAP_1 0x00000012 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_SCI_PRIV 0x00000013 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_THERM_I2CS_3 0x00000014 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_WAKE_0 0x00000015 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_HPD_IRQ_0 0x00000016 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_HPD_IRQ_1 0x00000017 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_HPD_STATUS_0 0x00000018 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_HPD_STATUS_1 0x00000019 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_TIMER_0 0x0000001a /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_TIMER_1 0x0000001b /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FAN_PWM_0 0x0000001c /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_PWR_SEQ_0 0x0000001d /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_PWR_SEQ_1 0x0000001e /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_PWR_SEQ_2 0x0000001f /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FS_OVERT_0 0x00000020 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FS_OVERT_1 0x00000021 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FS_OVERT_2 0x00000022 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FS_OVERT_3 0x00000023 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FS_OVERT_4 0x00000024 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FS_OVERT_5 0x00000025 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FS_OVERT_6 0x00000026 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FS_OVERT_7 0x00000027 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_XVE_PME_0 0x0000002b /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_XVE_PME_1 0x0000002c /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_XVE_PME_2 0x0000002d /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_XVE_PME_3 0x0000002e /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_S3_PADCTL_0 0x0000002f /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_FAN_PWM_1 0x00000030 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_PORT_HI_NIBBLE_SEL_PGOOD_0 0x00000031 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_STATUS 0x00118f90 /* R--4R */
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#define NV_PGC6_SCI_DEBUG_STATUS_SCI_STATUS 2:0 /* R-IVF */
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#define NV_PGC6_SCI_DEBUG_STATUS_SCI_STATUS_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_DEBUG_STATUS_SCI_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_SCI_STATUS_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_SHIM_STATUS 6:4 /* R-IVF */
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#define NV_PGC6_SCI_DEBUG_STATUS_SHIM_STATUS_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_DEBUG_STATUS_SHIM_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_SHIM_STATUS_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_REPLAY_STATUS 10:8 /* R-IVF */
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#define NV_PGC6_SCI_DEBUG_STATUS_REPLAY_STATUS_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_DEBUG_STATUS_REPLAY_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_REPLAY_STATUS_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_MASTER_FSM_STATUS 14:12 /* R-IVF */
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#define NV_PGC6_SCI_DEBUG_STATUS_MASTER_FSM_STATUS_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_DEBUG_STATUS_MASTER_FSM_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_MASTER_FSM_STATUS_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_PWR_SEQ_STATUS 18:16 /* R-IVF */
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#define NV_PGC6_SCI_DEBUG_STATUS_PWR_SEQ_STATUS_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_DEBUG_STATUS_PWR_SEQ_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_PWR_SEQ_STATUS_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_I2CS_STATUS 22:20 /* R-IVF */
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#define NV_PGC6_SCI_DEBUG_STATUS_I2CS_STATUS_EMPTY 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_DEBUG_STATUS_I2CS_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_DEBUG_STATUS_I2CS_STATUS_STALLED 0x00000005 /* R---V */
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#define NV_PGC6_SCI_DEBUG_ROSC 0x00118f94 /* RW-4R */
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#define NV_PGC6_SCI_DEBUG_ROSC__PRIV_LEVEL_MASK 0x00118fe8 /* */
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#define NV_PGC6_SCI_DEBUG_ROSC_FRC_ENABLE 0:0 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_ROSC_FRC_ENABLE_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_ROSC_FRC_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_I2CS 0x00118f98 /* RW-4R */
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#define NV_PGC6_SCI_DEBUG_I2CS__PRIV_LEVEL_MASK 0x00118fe8 /* */
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#define NV_PGC6_SCI_DEBUG_I2CS_DEV_ADDR 7:1 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_I2CS_DEV_ADDR_PROTOTYPE 0x0000004b /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_I2CS_ADDR_VALID 8:8 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_I2CS_ADDR_VALID_NO 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_I2CS_ADDR_VALID_YES 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_I2CS_SCI_BAR0_ACCESS 9:9 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_I2CS_SCI_BAR0_ACCESS_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_I2CS_SCI_BAR0_ACCESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_I2CS_TIMEOUT 21:16 /* RWIUF */
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#define NV_PGC6_SCI_DEBUG_I2CS_TIMEOUT_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_I2CS_TIMEOUT_25MS 0x00000019 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_I2CS_TIMEOUT_35MS 0x00000022 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_I2CS_SPIKE 25:24 /* RWIUF */
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#define NV_PGC6_SCI_DEBUG_I2CS_SPIKE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_I2CS_SPIKE_74NS 0x00000001 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_I2CS_HOLD 31:28 /* RWIUF */
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#define NV_PGC6_SCI_DEBUG_I2CS_HOLD_NONE 0x00000000 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_I2CS_HOLD_222NS 0x00000006 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM 0x00118fa0 /* R--4R */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE 4:0 /* R-IVF */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_FSM_RESET 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_STEADY 0x00000001 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_RTD3_ENTRY 0x00000002 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_RTD3_PWRDN 0x00000003 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_RTD3 0x00000004 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_RTD3_PWRUP 0x00000005 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_RTD3_EXIT 0x00000006 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC5_ENTRY_START 0x00000007 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC5_ABORT_CHK 0x00000008 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC5_PWRDN 0x00000009 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC5 0x0000000a /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC5_PWRUP 0x0000000b /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC5_EXIT 0x0000000c /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6_ENTRY_START1 0x0000000d /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6_ENTRY_START2 0x0000000e /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6_ABORT_CHK 0x0000000f /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6_PWRDN 0x00000010 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6 0x00000011 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6_PWRUP 0x00000012 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6_EXIT_RESET_CHK 0x00000013 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6_GPU_EVENT_RETRY 0x00000014 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_GC6_EXIT 0x00000015 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_ABORT 0x00000016 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_STATE_RESET_EXEC 0x00000017 /* R---V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_GPU_EVENT 8:8 /* R-IVF */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_GPU_EVENT_DEASSERT 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_DEBUG_MASTER_FSM_GPU_EVENT_ASSERT 0x00000001 /* R---V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR_CTRL 0x00118fa4 /* RW-4R */
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#define NV_PGC6_SCI_DEBUG_SW_INTR_CTRL__PRIV_LEVEL_MASK 0x00118fe8 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR_CTRL_FORCE_DURING 0:0 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR_CTRL_FORCE_DURING_ENTRY 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR_CTRL_FORCE_DURING_GC5_GC6 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC 0x00118fa8 /* RW-4R */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC__PRIV_LEVEL_MASK 0x00118fe8 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT 0:0 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_WAKE_TIMER 1:1 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_WAKE_TIMER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_WAKE_TIMER_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_I2CS 2:2 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_I2CS_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_I2CS_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_BSI_EVENT 3:3 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_BSI_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_BSI_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_RTD3_CPU_EVENT 4:4 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_RTD3_CPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_RTD3_CPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_4 12:12 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_5 13:13 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_6 14:14 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_RTD3_GPU_EVENT 23:23 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_RTD3_GPU_EVENT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_RTD3_GPU_EVENT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_ENTRY_RESPONSE_ERR 24:24 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_ENTRY_RESPONSE_ERR_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_ENTRY_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_EXIT_RETRY 25:25 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_EXIT_RETRY_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_EXIT_RETRY_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC5_EXIT 26:26 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC5_EXIT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC5_EXIT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC6_EXIT 27:27 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC6_EXIT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC6_EXIT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC5_ABORT 28:28 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC5_ABORT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC5_ABORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC6_ABORT 29:29 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC6_ABORT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GC6_ABORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_SR_UPDATE 30:30 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_SR_UPDATE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_SR_UPDATE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_ENTRY_TIMEOUT 31:31 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_ENTRY_TIMEOUT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_GPU_EVENT_ENTRY_TIMEOUT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ(i) (8+(i)):(8+(i)) /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ__SIZE_1 7 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR0_FRC_HPD_IRQ_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC 0x00118fac /* RW-4R */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC__PRIV_LEVEL_MASK 0x00118fe8 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_0 0:0 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_1 1:1 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_2 2:2 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_3 3:3 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_4 4:4 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_5 5:5 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_6 6:6 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_0 8:8 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_1 9:9 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_2 10:10 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_3 11:11 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_MISC_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_POWER_ALERT 12:12 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_POWER_ALERT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_POWER_ALERT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_0 16:16 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_0_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_1 17:17 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_1_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_2 18:18 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_3 19:19 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_3_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_4 20:20 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_4_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_5 21:21 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_5_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_6 22:22 /* RWIVF */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_6_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD(i) (i):(i) /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD__SIZE_1 7 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS(i) (16+(i)):(16+(i)) /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS__SIZE_1 7 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_DISABLE 0x00000000 /* */
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#define NV_PGC6_SCI_DEBUG_SW_INTR1_FRC_HPD_STATUS_ENABLE 0x00000001 /* */
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#define NV_PGC6_SCI_DEBUG_RTD3_CURRENT_TIMER 0x00118b00 /* RW-4R */
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#define NV_PGC6_SCI_DEBUG_RTD3_CURRENT_TIMER_US 23:0 /* RWEVF */
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#define NV_PGC6_SCI_DEBUG_RTD3_CURRENT_TIMER_US_ZERO 0x00000000 /* RWE-V */
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#define NV_PGC6_SCI_DEBUG_RTD3_CURRENT_TIMER_US_MAX 0x00ffffff /* RW--V */
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#define NV_PGC6_SCI_DEBUG_RTD3_ENTRY_TSTAMP 0x00118b04 /* R--4R */
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#define NV_PGC6_SCI_DEBUG_RTD3_ENTRY_TSTAMP_US 23:0 /* R-EVF */
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#define NV_PGC6_SCI_DEBUG_RTD3_ENTRY_TSTAMP_US_ZERO 0x00000000 /* R---V */
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#define NV_PGC6_SCI_DEBUG_RTD3_ENTRY_TSTAMP_US_MAX 0x00ffffff /* R-E-V */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_RST_ASSERT_TSTAMP 0x00118b08 /* R--4R */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_RST_ASSERT_TSTAMP_US 23:0 /* R-EVF */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_RST_ASSERT_TSTAMP_US_ZERO 0x00000000 /* R---V */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_RST_ASSERT_TSTAMP_US_MAX 0x00ffffff /* R-E-V */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_WAKE_ASSERT_TSTAMP 0x00118b0c /* R--4R */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_WAKE_ASSERT_TSTAMP_US 23:0 /* R-EVF */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_WAKE_ASSERT_TSTAMP_US_ZERO 0x00000000 /* R---V */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_WAKE_ASSERT_TSTAMP_US_MAX 0x00ffffff /* R-E-V */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_RST_DEASSERT_TSTAMP 0x00118b10 /* R--4R */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_RST_DEASSERT_TSTAMP_US 23:0 /* R-EVF */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_RST_DEASSERT_TSTAMP_US_ZERO 0x00000000 /* R---V */
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#define NV_PGC6_SCI_DEBUG_RTD3_PEX_RST_DEASSERT_TSTAMP_US_MAX 0x00ffffff /* R-E-V */
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#define NV_PGC6_SCI_DEBUG_RTD3_SYS_RST_ASSERT_TSTAMP 0x00118b14 /* R--4R */
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#define NV_PGC6_SCI_DEBUG_RTD3_SYS_RST_ASSERT_TSTAMP_US 23:0 /* R-EVF */
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#define NV_PGC6_SCI_DEBUG_RTD3_SYS_RST_ASSERT_TSTAMP_US_ZERO 0x00000000 /* R---V */
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#define NV_PGC6_SCI_DEBUG_RTD3_SYS_RST_ASSERT_TSTAMP_US_MAX 0x00ffffff /* R-E-V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER 0x00118fc8 /* RW-4R */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER__PRIV_LEVEL_MASK 0x00118b38 /* */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT 11:0 /* RWIUF */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT_1US 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT_10US 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT_20US 0x00000014 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT_50US 0x00000032 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT_100US 0x00000064 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT_500US 0x000001f4 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ASSERT_LIMIT_MAX 0x00000fff /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT 27:16 /* RWIUF */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT_1US 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT_10US 0x0000000a /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT_20US 0x00000014 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT_50US 0x00000032 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT_100US 0x00000064 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT_500US 0x000001f4 /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_DEASSERT_LIMIT_MAX 0x00000fff /* RW--V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ENABLE 31:31 /* RWIUF */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ENABLE_FALSE 0x00000000 /* RWI-V */
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#define NV_PGC6_SCI_BSI2SCI_PGOOD_FILTER_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGC6_SCI_PGOOD 0x00118f9c /* R--4R */
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#define NV_PGC6_SCI_PGOOD_STATUS 0:0 /* R-IVF */
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#define NV_PGC6_SCI_PGOOD_STATUS_FALSE 0x00000000 /* R-I-V */
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#define NV_PGC6_SCI_PGOOD_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_0 0x001188a0 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_1 0x001188a4 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_2 0x001188a8 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_3 0x001188ac /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_4 0x001188b0 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_5 0x001188b4 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_6 0x001188b8 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_7 0x001188bc /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_8 0x001188c0 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_9 0x001188c4 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_10 0x001188c8 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_11 0x001188cc /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_12 0x001188d0 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_13 0x001188d4 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_14 0x001188d8 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_15 0x001188dc /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_16 0x001188e0 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_17 0x001188e4 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_18 0x001188e8 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_19 0x001188ec /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_20 0x001188f0 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_21 0x001188f4 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_22 0x001188f8 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_23 0x001188fc /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_24 0x00118900 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_25 0x00118904 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_26 0x00118908 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_27 0x0011890c /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_28 0x00118910 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_29 0x00118914 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_30 0x00118918 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_31 0x0011891c /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_32 0x00118920 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_33 0x00118924 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_34 0x00118928 /* */
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#define NV_PGC6_SCI_GPIO_OUTPUT_CNTL_35 0x0011892c /* */
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#define NV_PGC6_SCI_FAN_CFG0_0 0x00118aa0 /* */
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#define NV_PGC6_SCI_FAN_CFG1_0 0x00118aa4 /* */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_0 0x00118aa8 /* */
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#define NV_PGC6_SCI_FAN_ACT0_0 0x00118ab0 /* */
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#define NV_PGC6_SCI_FAN_ACT1_0 0x00118ab4 /* */
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#define NV_PGC6_SCI_FAN_CFG0_1 0x00118ab8 /* */
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#define NV_PGC6_SCI_FAN_CFG1_1 0x00118abc /* */
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#define NV_PGC6_SCI_FAN_TEMP_ALERT_1 0x00118ac0 /* */
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#define NV_PGC6_SCI_FAN_ACT0_1 0x00118ac8 /* */
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#define NV_PGC6_SCI_FAN_ACT1_1 0x00118acc /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_0 0x00118bc0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_1 0x00118bc4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_2 0x00118bc8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_3 0x00118bcc /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_4 0x00118bd0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_5 0x00118bd4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_6 0x00118bd8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_7 0x00118bdc /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_8 0x00118be0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_9 0x00118be4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_10 0x00118be8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_11 0x00118bec /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_12 0x00118bf0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_13 0x00118bf4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_VID_TABLE_14 0x00118bf8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_0 0x00118c80 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_1 0x00118c84 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_2 0x00118c88 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_3 0x00118c8c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_4 0x00118c90 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_5 0x00118c94 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_6 0x00118c98 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_7 0x00118c9c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_8 0x00118ca0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_9 0x00118ca4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_10 0x00118ca8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_11 0x00118cac /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_12 0x00118cb0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_13 0x00118cb4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_14 0x00118cb8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_15 0x00118cbc /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_16 0x00118cc0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_17 0x00118cc4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_18 0x00118cc8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_19 0x00118ccc /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_20 0x00118cd0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_21 0x00118cd4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_22 0x00118cd8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_23 0x00118cdc /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_24 0x00118ce0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_25 0x00118ce4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_26 0x00118ce8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_27 0x00118cec /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_28 0x00118cf0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_29 0x00118cf4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_30 0x00118cf8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_31 0x00118cfc /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_32 0x00118d00 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_33 0x00118d04 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_34 0x00118d08 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_35 0x00118d0c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_36 0x00118d10 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_37 0x00118d14 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_38 0x00118d18 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_39 0x00118d1c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_40 0x00118d20 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_41 0x00118d24 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_42 0x00118d28 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_43 0x00118d2c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_44 0x00118d30 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_45 0x00118d34 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_46 0x00118d38 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_47 0x00118d3c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_48 0x00118d40 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_49 0x00118d44 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_50 0x00118d48 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_51 0x00118d4c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_52 0x00118d50 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_53 0x00118d54 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_54 0x00118d58 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_55 0x00118d5c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_56 0x00118d60 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_57 0x00118d64 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_58 0x00118d68 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_59 0x00118d6c /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_60 0x00118d70 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_61 0x00118d74 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_62 0x00118d78 /* */
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#define NV_PGC6_SCI_PWR_SEQ_INST_63 0x00118d7c /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_0 0x00118d80 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_1 0x00118d84 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_2 0x00118d88 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_3 0x00118d8c /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_4 0x00118d90 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_5 0x00118d94 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_6 0x00118d98 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_7 0x00118d9c /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_8 0x00118da0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_9 0x00118da4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_10 0x00118da8 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_11 0x00118dac /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_12 0x00118db0 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_13 0x00118db4 /* */
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#define NV_PGC6_SCI_PWR_SEQ_DELAY_TABLE_14 0x00118db8 /* */
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#define NV_PGC6_SCI_HPD_CONFIG_0 0x00118dd0 /* */
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#define NV_PGC6_SCI_HPD_CONFIG_1 0x00118dd4 /* */
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#define NV_PGC6_SCI_HPD_CONFIG_2 0x00118dd8 /* */
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#define NV_PGC6_SCI_HPD_CONFIG_3 0x00118ddc /* */
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#define NV_PGC6_SCI_HPD_CONFIG_4 0x00118de0 /* */
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#define NV_PGC6_SCI_HPD_CONFIG_5 0x00118de4 /* */
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#define NV_PGC6_SCI_HPD_CONFIG_6 0x00118de8 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_0 0x00118e00 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_1 0x00118e04 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_2 0x00118e08 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_3 0x00118e0c /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_4 0x00118e10 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_5 0x00118e14 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_HPD_6 0x00118e18 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_0 0x00118e20 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_1 0x00118e24 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_2 0x00118e28 /* */
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#define NV_PGC6_SCI_GPIO_INPUT_MISC_3 0x00118e2c /* */
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#define NV_PGC6_SCI_NV_SCRATCH_0 0x00118f08 /* */
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#define NV_PGC6_SCI_NV_SCRATCH_1 0x00118f0c /* */
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#define NV_PGC6_SCI_NV_SCRATCH_2 0x00118f10 /* */
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#define NV_PGC6_SCI_NV_SCRATCH_3 0x00118f14 /* */
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#define NV_PGC6_SCI_VID_CFG0_0 0x00118f20 /* */
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#define NV_PGC6_SCI_VID_CFG1_0 0x00118f24 /* */
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#define NV_PGC6_SCI_VID_CFG0_1 0x00118f28 /* */
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#define NV_PGC6_SCI_VID_CFG1_1 0x00118f2c /* */
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#define NV_PGC6_SCI_VID_CFG0_2 0x00118f30 /* */
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#define NV_PGC6_SCI_VID_CFG1_2 0x00118f34 /* */
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#define NV_PGC6_SCI_VID_CFG0_3 0x00118f38 /* */
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#define NV_PGC6_SCI_VID_CFG1_3 0x00118f3c /* */
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#endif // __ga102_dev_gc6_island_h__
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