1100 lines
89 KiB
C
1100 lines
89 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2015 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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//
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// DO NOT EDIT - this file automatically generated by ref2h-fuse.pl
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//
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#ifndef __ga102_dev_fuse_off_h__
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#define __ga102_dev_fuse_off_h__
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//
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// Register Offsets in range 'NV_FUSE' :
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// #define NV_FUSE 0x00825FFF:0x00820000 /* RW--D */
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//
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#define NV_FUSE_OFFSET_FUSECTRL 0x00000000 /* RW-4R */
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#define NV_FUSE_OFFSET_FUSEADDR 0x00000004 /* RW-4R */
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#define NV_FUSE_OFFSET_FUSERDATA 0x00000008 /* R--4R */
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#define NV_FUSE_OFFSET_FUSEWDATA 0x0000000C /* -W-4R */
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#define NV_FUSE_OFFSET_FUSETIME_RD1 0x00000010 /* RW-4R */
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#define NV_FUSE_OFFSET_FUSETIME_RD2 0x00000014 /* RW-4R */
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#define NV_FUSE_OFFSET_FUSETIME_PGM1 0x00000018 /* RW-4R */
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#define NV_FUSE_OFFSET_FUSETIME_PGM2 0x0000001C /* RW-4R */
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#define NV_FUSE_OFFSET_PRIV2INTFC 0x00000028 /* RW-4R */
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#define NV_FUSE_OFFSET_EN_SW_OVERRIDE 0x00000040 /* RW-4R */
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#define NV_FUSE_OFFSET_IFF_RECORD 0x00000050 /* RW-4R */
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#define NV_FUSE_OFFSET_FUSETESTRDATA 0x0000005C /* R--4R */
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#define NV_FUSE_OFFSET_DEBUGCTRL 0x00000060 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_ADDR_START 0x00000068 /* R--4R */
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#define NV_FUSE_OFFSET_SPARE_ENDIS_ADDR_START 0x0000006C /* R--4R */
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#define NV_FUSE_OFFSET_CRC_STATUS 0x00000070 /* R--4R */
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#define NV_FUSE_OFFSET_ENABLE_FUSE_PROGRAM_STATUS 0x00000078 /* R--4R */
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#define NV_FUSE_OFFSET_DISABLE_SW_OVERRIDE_STATUS 0x00000084 /* R--4R */
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#define NV_FUSE_OFFSET_IFF_SW_FUSING 0x00000088 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_10 0x00005820 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_10 0x00005824 /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_11 0x00005828 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_11 0x0000582C /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_12 0x00005830 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_12 0x00005834 /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_13 0x00005838 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_13 0x0000583C /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_14 0x00005840 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_14 0x00005844 /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_15 0x00005848 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_15 0x0000584C /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_16 0x00005850 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_16 0x00005854 /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_3 0x00005858 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_3 0x0000585C /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_4 0x00005860 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_4 0x00005864 /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_5 0x00005868 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_5 0x0000586C /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_6 0x00005870 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_6 0x00005874 /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_7 0x00005878 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_7 0x0000587C /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_8 0x00005880 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_8 0x00005884 /* R-E4R */
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#define NV_FUSE_OFFSET_RESHIFT_TRIGGER_CHAIN_9 0x00005888 /* RW-4R */
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#define NV_FUSE_OFFSET_RESHIFT_STATUS_CHAIN_9 0x0000588C /* R-E4R */
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#define NV_FUSE_OFFSET_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK 0x00003B14 /* RWE4R */
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#define NV_FUSE_OFFSET_DEBUGCTRL_PRIV_LEVEL_MASK 0x000000E0 /* RWE4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_PRIV_LEVEL_MASK 0x00003804 /* RWE4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK 0x00003800 /* RWE4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK 0x00003B04 /* RWE4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK 0x00003B18 /* RWE4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK 0x00003B00 /* RWE4R */
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#define NV_FUSE_OFFSET_FLOORSWEEP_PRIV_LEVEL_MASK 0x000000DC /* RWE4R */
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#define NV_FUSE_OFFSET_FUSECTRL_PRIV_LEVEL_MASK 0x000000F8 /* RWE4R */
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#define NV_FUSE_OFFSET_FUSETIME_PRIV_LEVEL_MASK 0x000000E4 /* RWE4R */
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#define NV_FUSE_OFFSET_IDDQINFO_PRIV_LEVEL_MASK 0x000000F0 /* RWE4R */
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#define NV_FUSE_OFFSET_KAPPAINFO_PRIV_LEVEL_MASK 0x000000D4 /* RWE4R */
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#define NV_FUSE_OFFSET_KFUSE_PRIV_LEVEL_MASK 0x00003B08 /* RWE4R */
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#define NV_FUSE_OFFSET_OPT_PRIV_LEVEL_MASK 0x000000FC /* RWE4R */
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#define NV_FUSE_OFFSET_RECONFIG_PRIV_LEVEL_MASK 0x000000D8 /* RWE4R */
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#define NV_FUSE_OFFSET_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK 0x00003B10 /* RWE4R */
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#define NV_FUSE_OFFSET_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK 0x00003B0C /* RWE4R */
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#define NV_FUSE_OFFSET_SECURITY_MONITOR_PRIV_LEVEL_MASK 0x00003B1C /* RWE4R */
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#define NV_FUSE_OFFSET_SPEEDOINFO_PRIV_LEVEL_MASK 0x000000EC /* RWE4R */
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#define NV_FUSE_OFFSET_SRAM_VMIN_PRIV_LEVEL_MASK 0x000000E8 /* RWE4R */
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#define NV_FUSE_OFFSET_TPC_FLOORSWEEP_PRIV_LEVEL_MASK 0x000000D0 /* RWE4R */
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#define NV_FUSE_OFFSET_WDATA_PRIV_LEVEL_MASK 0x000000F4 /* RWE4R */
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#define NV_FUSE_OFFSET_OPT_SCI_BG_TEMP_COEFF 0x00000100 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C0_WR_SECURE 0x00000104 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SCI_BG_VOLTAGE 0x00000108 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C1_WR_SECURE 0x0000010C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SCI_BG_VALID 0x00000110 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C2_WR_SECURE 0x00000114 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC 0x00000118 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C3_WR_SECURE 0x0000011C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C4_WR_SECURE 0x00000124 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HOST_DBG_BUS_WR_SECURE 0x00000128 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C5_WR_SECURE 0x0000012C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE 0x00000130 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C6_WR_SECURE 0x00000134 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SRAM_ECC_WR_SECURE 0x00000138 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C7_WR_SECURE 0x0000013C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_ADCS_WR_SECURE 0x00000140 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C8_WR_SECURE 0x00000144 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE 0x00000148 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_I2C9_WR_SECURE 0x0000014C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_IST_DISABLE_DEBUG_FEATURES 0x00000150 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_PADCTL_WR_SECURE 0x00000154 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_PWR_WR_SECURE 0x0000015C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE 0x00000160 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_ROM_WR_SECURE 0x00000164 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_TTU_EN 0x00000168 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_ELPG_WR_SECURE 0x0000016C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PJTAG_ACCESS_WR_SECURE 0x00000170 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_RST_WR_SECURE 0x00000174 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_KAPPA_INFO 0x00000178 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_NVENC_REV 0x0000017C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_SCRUBBER_BIN_REV 0x00000180 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_SEC2_REV 0x00000184 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE 0x00000188 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_FANTACH_WR_SECURE 0x0000018C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE 0x00000190 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FBPA_ECC_WR_SECURE 0x00000194 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_MMU_PLM_WR_SECURE 0x00000198 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE 0x0000019C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_INTRUPT_WR_SECURE 0x000001A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_UPHY_CFG_WR_SECURE 0x000001A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_PP_WR_SECURE 0x000001A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE 0x000001AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE 0x000001B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_BSI_RAM 0x000001B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE 0x000001BC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_BSI_DEBUG 0x000001C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_SCI_FAN 0x000001C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_SCI_DEBUG 0x000001C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_SCI_SYSTEM 0x000001CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE 0x000001D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE 0x000001D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE 0x000001D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE 0x000001DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE 0x000001E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE 0x000001E4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_VIDCTRL_WR_SECURE 0x000001E8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_SCI_PWR_SEQ 0x000001F0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_SCI_MAST_FSM 0x000001F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE 0x000001F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_INVALID_BITS_ATE 0x000001FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_OPENGL_EN 0x00000200 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_MCHIP_EN 0x00000204 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE 0x00000208 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NOTEBOOK 0x0000020C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PRIV_SFK_0 0x00000210 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PRIV_SFK_1 0x00000214 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_JTAG2HOST_PRIV_SEC_EN 0x00000218 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PRIV_SFK_2 0x0000021C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_I2CS_WIDE_EN 0x00000220 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_DP 0x00000224 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ECC_EN 0x00000228 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GPC_DISABLE_CP 0x0000022C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC0_DISABLE_CP 0x00000230 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBP_DISABLE_CP 0x00000234 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PRIV_SFK_3 0x00000238 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SCC_DIS 0x0000023C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE 0x00000240 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SPLIT_RAIL_SD_CLAMP_BYPASS 0x00000244 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_LANE_DISABLE_CP 0x00000248 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DISPLAY_DISABLE_CP 0x0000024C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DISABLE_GEN3_SPEED 0x00000250 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_ACR_HS_REV 0x00000254 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_GFW_REV 0x00000258 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_VENDOR_CODE 0x0000025C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FAB_CODE 0x00000260 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_LOT_CODE_0 0x00000264 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_LOT_CODE_1 0x00000268 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_WAFER_ID 0x0000026C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_X_COORDINATE 0x00000270 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_Y_COORDINATE 0x00000274 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_OPS_RESERVED 0x00000278 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_INT_TS_OTOB_EN 0x0000027C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_INT_TS_A 0x00000280 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_INT_TS_B 0x00000284 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CALIBRATE 0x00000288 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HS_DIS_NVDEC3 0x0000028C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_INT_TS_VALID 0x00000290 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_I2CS_ADDR_SEL 0x00000294 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE 0x00000298 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SW_SMC_DISABLE 0x0000029C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_ROM_FLASH_REV 0x000002A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_PR_VPR_REV 0x000002A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE 0x000002A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TITAN_EN 0x000002AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SRAM_REPAIR 0x000002B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FIB_REVISION_ID 0x000002B4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_MASK_REVISION_ID 0x000002B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_MINOR_EXT_REVISION_ID 0x000002BC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FAB_ID 0x000002C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_LTC_DISABLE 0x000002C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CP_BIN 0x000002C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_NVDEC_REV 0x000002CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DONE_MAP 0x000002D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_IDDQ 0x000002D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_OFA_DISABLE 0x000002D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PFG 0x000002DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE 0x000002E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_LTC_DISABLE_CP 0x000002E4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_XTAL16X_FSM_DISABLE 0x000002E8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_OFA_DISABLE_CP 0x000002EC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_OFA_DEFECTIVE 0x000002F0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_OFA_REV 0x000002F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HS_DIS_NVDEC4 0x000002F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HDCP_EN 0x000002FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_0 0x00000300 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_1 0x00000304 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_2 0x00000308 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_UPHY_PLL_BANDGAP_TRIM_PCIE 0x0000030C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_CLK_WR_SECURE 0x00000310 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURED_BURN_FEATURE_ENABLE 0x00000314 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_ISM_WR_SECURE 0x00000318 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING 0x0000031C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PRIVKEY_ACC_DIS 0x00000324 /* R--4R */
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#define NV_FUSE_OFFSET_OPT_FB_CONFIG 0x00000328 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SAMPLE_BIN 0x0000032C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SAMPLE_TYPE 0x00000330 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_LOCAL_TRAP_WR_SECURE 0x00000334 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PRI_SEQUENCER_WR_SECURE 0x00000338 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SUBREVISION 0x0000033C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_MEMORY_LOCKED_ENABLED 0x00000340 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PDI_0 0x00000344 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PDI_1 0x00000348 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_IQ_WR_SECURE 0x0000034C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GPC_DISABLE 0x00000350 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_SCI_OVERT 0x00000354 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DISABLE_FPF_FUSE_PROGRAMMING 0x00000358 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ZCULL_DISABLE 0x0000035C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE 0x00000360 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBP_DISABLE 0x00000364 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBIO_DISABLE 0x0000036C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVJPG_DISABLE 0x00000370 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_CLK_SWITCH_DISABLE 0x00000374 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVDEC_DISABLE 0x00000378 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DISPLAY_DISABLE 0x0000037C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_SVOP_DP 0x00000384 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_SVOP_PDP 0x00000388 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE 0x0000038C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_SVOP_SP 0x00000390 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_LANE_DISABLE 0x00000394 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SPARE_FS 0x00000398 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GLOBAL_POISON_EN 0x0000039C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_CYA_COH_WR_SECURE 0x000003A0 /* RW-4R */
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#define NV_FUSE_OFFSET_FLW0 0x000003A4 /* RW-4R */
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#define NV_FUSE_OFFSET_FLW1 0x000003A8 /* RW-4R */
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#define NV_FUSE_OFFSET_FLW2 0x000003AC /* RW-4R */
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#define NV_FUSE_OFFSET_FLW3 0x000003B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_AUTO_EN 0x000003B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0 0x000003BC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1 0x000003C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2 0x000003C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3 0x000003C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_SIGNATURE_0 0x000003CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_SIGNATURE_1 0x000003D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_SIGNATURE_2 0x000003D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_SIGNATURE_3 0x000003D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SE_CONTROL_SECURE 0x000003DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FEATURE_FUSES_OVERRIDE_DISABLE 0x000003F0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_INTERNAL_SKU 0x000003F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ROM_DRV_STR 0x000003F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_AMAP_WR_SECURE 0x000003FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_CYA_WR_SECURE 0x00000400 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_GSP_REV 0x00000404 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE 0x00000408 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE 0x0000040C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PRI_SOURCE_ISOLATION_EN 0x00000410 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVENC_DISABLE 0x00000414 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DISP_HEAD_DISABLE 0x00000418 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE 0x0000041C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE 0x00000428 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GPC2CLK_CAP 0x0000042C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PRIV_SEC_EN 0x00000434 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE 0x00000438 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE 0x0000043C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE 0x00000440 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE 0x00000444 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XBAR_CYA_WR_SECURE 0x00000448 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XBAR_PM_WR_SECURE 0x0000044C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DISP_HEAD_DISABLE_CP 0x00000450 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVDEC_DISABLE_CP 0x00000458 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVENC_DISABLE_CP 0x0000045C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBIO_DISABLE_CP 0x00000460 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_CBC_WR_SECURE 0x00000464 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HDCP22_SECRET_WR_SECURE 0x0000046C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE 0x00000470 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_DSTG_WR_SECURE 0x00000474 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE 0x00000478 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_CYA_WR_SECURE 0x0000047C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_TSTG_WR_SECURE 0x00000480 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PLTS_CGATE_WR_SECURE 0x00000484 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVJPG_DISABLE_CP 0x00000488 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_WDATA_WR_SECURE 0x0000048C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HDCP22_SECRET_RD_SECURE 0x00000490 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE 0x00000494 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HALF_FBPA_ENABLE 0x0000049C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SPEEDO_REV 0x000004A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_IDDQ_REV 0x000004A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SPEEDO0 0x000004A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SPEEDO1 0x000004AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SPEEDO2 0x000004B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FT_REV 0x000004B4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CP_REV 0x000004B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SLT_REV 0x000004BC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_TC 0x000004C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC4_DISABLE_CP 0x000004C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC5_DISABLE_CP 0x000004CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_MAJOR_REVISION_ID 0x000004D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_MINOR_REVISION_ID 0x000004D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_DEVIDA 0x000004D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CUST_ATE_REV 0x000004DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FBPA_IOBIST_WR_SECURE 0x000004E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SLT_DONE 0x000004E4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FBPA_ILA_WR_SECURE 0x000004EC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NNE_ID 0x000004F0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FT_DONE 0x000004F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVS_EN 0x000004F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SEC_DISABLE 0x000004FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_VP8_VP9_DISABLE 0x00000500 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC1_DISABLE_CP 0x00000504 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC1_DEFECTIVE 0x00000508 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC2_DEFECTIVE 0x0000050C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_VGX_EN 0x00000510 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC3_DEFECTIVE 0x00000514 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_MAGIC_BITS_B 0x00000518 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_MAGIC_BITS_C 0x0000051C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PEX_PLL_EN_TERM100 0x00000524 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_3GIO_PADCFG_LUT_ADR_R1_1 0x00000528 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_3GIO_PADCFG_LUT_ADR_R1_0 0x0000052C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_3GIO_PADCFG_LUT_ADR_R2_1 0x00000530 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_3GIO_PADCFG_LUT_ADR_R2_0 0x00000534 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_XP_DFE_ENABLE_CTRL 0x00000538 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_3GIO_PADCFG_LUT_ADR_R3_0 0x0000053C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_XP_DC_GAIN_ADAPTIVE_CTRL 0x00000540 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_3GIO_PADCFG_LUT_ADR_R3_1 0x00000544 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_XP_DYNAMIC_EQ_TRAINING_CTRL 0x00000548 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GC6_NVVDD_OK_THRESHOLD 0x0000054C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_MAGIC_BITS_A 0x00000558 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CP1_DVS_COMPLETE 0x0000055C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CP2_DVS_COMPLETE 0x00000560 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC4_DEFECTIVE 0x00000564 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GC6_ISLAND_DISABLE 0x00000568 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_DEVIDB 0x0000056C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CP1_COMPLETE 0x00000570 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CP2_COMPLETE 0x00000574 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_IDDQ_CP 0x00000578 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_BOOT_GEN23_DISABLE 0x0000057C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_BOOT_GEN3_DISABLE 0x00000580 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DEVID_SW_OVERRIDE_DIS 0x00000584 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ATE_VMIN 0x00000588 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_LTSSM_FAILSAFE_TIMEOUT_DIS 0x0000058C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_FUSEBLOW_REV 0x00000590 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ASSR_STICKY_DISABLE 0x00000594 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE 0x00000598 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_FFMA 0x0000059C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC3_DISABLE_CP 0x000005A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_BA_WR_SECURE 0x000005A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SFK_ACC_DIS 0x000005A8 /* R--4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC5_DEFECTIVE 0x000005AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_CTRL_WR_SECURE 0x000005B4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE 0x000005B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVJPG_DEFECTIVE 0x000005BC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RESET_DELAY_DISABLE 0x000005C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GPC_DEFECTIVE 0x000005C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC0_DEFECTIVE 0x000005C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBP_DEFECTIVE 0x000005CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBIO_DEFECTIVE 0x000005D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DISPLAY_DEFECTIVE 0x000005D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVENC_DEFECTIVE 0x000005DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVDEC_DEFECTIVE 0x000005E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_LANE_DEFECTIVE 0x000005E4 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_LTC_DEFECTIVE 0x000005E8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_WPR_ENABLED 0x000005EC /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_SUB_REGION_NO_OVERRIDE 0x000005F0 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_TPC_GPC2_DISABLE_CP 0x000005F4 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_SECURE_FBPA_I1500_WR_SECURE 0x000005F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_DECODE_TRAP_WR_SECURE 0x000005FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE 0x00000600 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE 0x00000604 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE 0x00000608 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_HALF_LTC_ENABLE 0x0000060C /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_NVENC_THROTTLE 0x00000610 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_SECURE_TARGET_MASK_WR_SECURE 0x00000614 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_SECURE_FBPA_MEM_WR_SECURE 0x00000618 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_SECURE_FBIO_WR_SECURE 0x00000620 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE 0x00000624 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE 0x00000628 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_ENABLE_CR_JTAG_SECURITY 0x0000062C /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE 0x00000630 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_REFURBISHED 0x00000634 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_SECURE_JTAG_SECUREID_VALID 0x00000638 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_SECURE_SECENGINE_DEBUG_DIS 0x0000063C /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_SECURE_PMU_DEBUG_DIS 0x00000640 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_SECURE_NVDEC_DEBUG_DIS 0x00000644 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_HS_DIS_NVDEC1 0x00000648 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_HS_DIS_NVDEC2 0x0000066C /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_FB_FALCON_PRI_ACCESS_DISABLE 0x00000670 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE 0x00000674 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE 0x00000678 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_VPR_ENABLED 0x0000067C /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_SECURE_HDCP22_CTRL_WR_SECURE 0x00000680 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_NVLINK_DISABLE 0x00000684 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_NVLINK_DISABLE_CP 0x00000688 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_NVLINK_DEFECTIVE 0x0000068C /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_PES_DISABLE 0x00000690 /* RW-4R */
|
|
#define NV_FUSE_OFFSET_OPT_PES_DISABLE_CP 0x00000694 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_PES_DEFECTIVE 0x00000698 /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_RAM_RTSEL_TSMCSP 0x0000069C /* RW-4R */
|
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#define NV_FUSE_OFFSET_OPT_RAM_WTSEL_TSMCSP 0x000006A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_RTSEL_TSMCPDP 0x000006A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_MTSEL_TSMCPDP 0x000006A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_WTSEL_TSMCPDP 0x000006AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_RCT_TSMCDP 0x000006B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_WCT_TSMCDP 0x000006B4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_KP_TSMCDP 0x000006B8 /* RW-4R */
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#define NV_FUSE_OFFSET_H0 0x000006BC /* RW-4R */
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#define NV_FUSE_OFFSET_H1 0x000006C0 /* RW-4R */
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#define NV_FUSE_OFFSET_H2 0x000006C4 /* RW-4R */
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#define NV_FUSE_OFFSET_H3 0x000006C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE 0x000006D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SCI_TEMP_COEFF_ADJ_A 0x000006D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SCI_TEMP_COEFF_ADJ_B 0x000006D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HDA_LPBK_DISABLE 0x000006DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SW_VPR_ENABLED 0x000006F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_CTXSW_REV 0x000006F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_MINION_DEBUG_DIS 0x000006FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_MINION_REV 0x00000700 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_NVLINK_MASK_WR_SECURE 0x00000704 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_NVLINK_BUFFER_READY_SECURE 0x00000708 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE 0x0000070C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_FBFALCON_REV 0x00000710 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_0 0x00000718 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_1 0x0000071C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_2 0x00000720 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_3 0x00000724 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_4 0x00000728 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_5 0x0000072C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_6 0x00000730 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_7 0x00000734 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_SELECTION 0x00000738 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PMU_ALGO_DISABLE 0x0000073C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_NVDEC_ALGO_DISABLE 0x00000740 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_SEC_ALGO_DISABLE 0x00000744 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_PK_ARRAY_INDEX 0x00000748 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GSP_DEBUG_DIS 0x0000074C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HOST2JTAG_SHA2_EN 0x00000750 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PKC_GSP_ALGO_DISABLE 0x00000754 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE 0x00000758 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HOST2JTAG_STANDARD_MODE 0x0000075C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC0_DISABLE 0x00000760 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC1_DISABLE 0x00000764 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC2_DISABLE 0x00000768 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC3_DISABLE 0x0000076C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC4_DISABLE 0x00000770 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC5_DISABLE 0x00000774 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC6_DISABLE 0x00000778 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC0_RECONFIG 0x00000788 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC1_RECONFIG 0x0000078C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC2_RECONFIG 0x00000790 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC3_RECONFIG 0x00000794 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC4_RECONFIG 0x00000798 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC5_RECONFIG 0x0000079C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT 0x000007A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_SVOP_PDP_SMRF 0x000007A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_XUSB_REG_SECURE_EN 0x000007C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PPC_EXT_REG_ACCESS_DIS 0x000007C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE 0x000007C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE 0x000007CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE 0x000007D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_FMLA16 0x000007D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_FMLA32 0x000007D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_IMLA0 0x000007DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_IMLA1 0x000007E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_IMLA2 0x000007E4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_IMLA3 0x000007E8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SM_SPEED_SELECT_IMLA4 0x000007EC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PERLINK_DISABLE 0x000007F0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HDCP_RAM_ACCESS_DIS 0x000007F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVJTAG_PROTECTION_ENABLE 0x000007F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_NVJPG_REV 0x000007FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0 0x00000B20 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1 0x00000B24 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2 0x00000B28 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3 0x00000B2C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4 0x00000B30 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5 0x00000B34 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6 0x00000B38 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7 0x00000B3C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8 0x00000B40 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9 0x00000B44 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10 0x00000B48 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11 0x00000B4C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12 0x00000B50 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13 0x00000B54 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14 0x00000B58 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15 0x00000B5C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16 0x00000B60 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17 0x00000B64 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18 0x00000B68 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19 0x00000B6C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE 0x00000B7C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC6_DEFECTIVE 0x00000B84 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC6_DISABLE_CP 0x00000B8C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TPC_GPC6_RECONFIG 0x00000B94 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XUSB_DEBUG_DIS 0x00000B98 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_USB2_CAL 0x00000B9C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00000BD0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE 0x00000BD4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE 0x00000BD8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE 0x00000BDC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE 0x00000BE0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE 0x00000BE8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00000BEC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00000BF0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00000BF4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00000BF8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_CLOCKS_FMON_WR_SECURE 0x00000BFC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HEVC_ENC_DISABLE 0x00000E00 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HEVC_DEC_DISABLE 0x00000E04 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SRAM_VMIN_BIN 0x00000E08 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SRAM_VMIN_BIN_REV 0x00000E0C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE 0x00000E10 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_XUSB_REV 0x00000E14 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_IST_DISABLE 0x00000E18 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DEBUG_SW_OVERRIDE_ENABLE 0x00000E20 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_UCODE_LSPMU_REV 0x00000E24 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_TSENSE_WR_SECURE 0x00001000 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_DIS_MASK 0x00001004 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_AVG 0x00001008 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_OFFSET_0 0x0000100C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_OFFSET_1 0x00001010 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_OFFSET_2 0x00001014 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_OFFSET_3 0x00001018 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_OFFSET_4 0x0000101C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_OFFSET_5 0x00001020 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_OFFSET_6 0x00001024 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_TS_CAL_OFFSET_7 0x00001028 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ROW_REMAPPER_EN 0x0000102C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_NV_P2P_PLM_WR_SECURE 0x00001030 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE 0x00001034 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE 0x00001038 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_CWD_CYA_WR_SECURE 0x0000103C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RAM_SVOP_PDPF 0x00001040 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_GCC_DBG_WR_SECURE 0x00001044 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE 0x00001050 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_FAN_WR_SECURE 0x00001054 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_RESENSE_DISABLE 0x00001058 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FUSE_FILE_VERSION 0x0000105C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SKU_ID 0x00001060 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_XV2CLK_RESET_RETIME_DISABLE 0x00001064 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_XVE_10B_TAG_REQUESTER_DISABLE 0x00001068 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE 0x0000106C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE 0x00001070 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE 0x00001074 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE 0x00001078 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE 0x0000107C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE 0x00001080 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CPM0 0x00001088 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CPM1 0x0000108C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CPM2 0x00001090 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CPM_REV 0x00001094 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE 0x000010C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SPI_CLK_DIV_SET_SEL 0x000010FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVLIPT_RESET_COND_DISABLE 0x00001100 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVLIPT_RESET_SEQ_DISABLE 0x00001104 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ROP_DISABLE 0x00001108 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ROP_DISABLE_CP 0x00001110 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ROP_DEFECTIVE 0x00001114 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SKED_CYA_WR_SECURE 0x00001118 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SKED_DEBUG_WR_SECURE 0x0000111C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HDCP22_LC128_0 0x00001120 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HDCP22_LC128_1 0x00001124 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HDCP22_LC128_2 0x00001128 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_HDCP22_LC128_3 0x0000112C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE 0x00001130 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE 0x00001134 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE 0x00001138 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE 0x0000113C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE 0x00001140 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE 0x00001144 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE 0x00001148 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE 0x0000114C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE 0x00001150 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE 0x00001154 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE 0x00001158 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE 0x0000115C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE 0x00001160 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE 0x00001164 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE 0x00001168 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE 0x0000116C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE 0x00001170 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE 0x00001174 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE 0x00001178 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE 0x0000117C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE 0x00001180 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE 0x00001184 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE 0x00001188 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE 0x0000118C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE 0x00001190 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE 0x00001194 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE 0x00001198 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE 0x0000119C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE 0x000011A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE 0x000011A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE 0x000011A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE 0x000011AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE 0x000011B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE 0x000011B4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE 0x000011B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE 0x000011BC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE 0x000011C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE 0x000011C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE 0x000011C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE 0x000011CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_THERM_DLPPE_WR_SECURE 0x000011D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_DRIVER_FUB_REV 0x000011D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ROM_PMGR_SROM_FEEDBACK_MODE 0x000011D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PMGR_SROM_FEEDBACK_CLK_ADJ 0x000011DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PMGR_IFR_ROM_ADDR_OFFSET 0x000011E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HDCP_DEBUG_MODE 0x000011E4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP0_DISABLE 0x00001200 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP1_DISABLE 0x00001204 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP2_DISABLE 0x00001208 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP3_DISABLE 0x0000120C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP4_DISABLE 0x00001210 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP5_DISABLE 0x00001214 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP0_DISABLE_CP 0x00001220 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP1_DISABLE_CP 0x00001224 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP2_DISABLE_CP 0x00001228 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP3_DISABLE_CP 0x0000122C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP4_DISABLE_CP 0x00001230 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP5_DISABLE_CP 0x00001234 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP0_DEFECTIVE 0x00001240 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP1_DEFECTIVE 0x00001244 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP2_DEFECTIVE 0x00001248 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP3_DEFECTIVE 0x0000124C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP4_DEFECTIVE 0x00001250 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_L2SLICE_FBP5_DEFECTIVE 0x00001254 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_LANE_MARGINING_CONTROL 0x000012F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RASTER_SPEED_SELECT 0x000012FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GPCRR_ENABLE 0x00001300 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_FUSE_REV 0x00001304 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_FUSE_TESTSTAGE 0x00001308 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_FUSE_REV 0x00001350 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00001378 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SPEEDO_ADJ 0x0000137C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ISFI_DISABLE 0x00001380 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_FUSE_REV 0x00001398 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_SENSE_FUSE_REV 0x000013E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ISENSE_ADC_FUSE_TESTSTAGE 0x000013E4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_KFUSE_WR_SECURE 0x00001600 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN 0x00001604 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FUSE_POD_SEC_FAULT_EN 0x00001608 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN 0x0000160C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_BLCG_RESET_PWR_SAVING_DISABLE 0x00001610 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVL_TS_DIS_MASK 0x00001700 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PMGR_SROM_LEGACY_MODE_CYA 0x00001704 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE 0x00001710 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE 0x00001714 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_INTR_1_WR_SECURE 0x00001718 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_INTR_0_WR_SECURE 0x0000171C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE 0x00001720 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE 0x00001724 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE 0x00001728 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE 0x0000172C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE 0x00001730 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE 0x00001734 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE 0x00001738 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN 0x0000173C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN 0x00001740 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SEC_FAULT_RESET_EN 0x00001748 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GC6_BSI_RAM_RPG_ENABLE 0x0000174C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE 0x00001750 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RISCV_DCLS_EN 0x00001754 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_ISFI_WR_SECURE 0x00001760 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GSP_FALCON_BOOT_FROM_HS_EN 0x00001764 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GSP_FALCON_MOD_EN_AES_RO_EN 0x00001768 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SEC_FALCON_BOOT_FROM_HS_EN 0x0000176C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SEC_FALCON_MOD_EN_AES_RO_EN 0x00001770 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PMU_FALCON_BOOT_FROM_HS_EN 0x00001774 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PMU_FALCON_MOD_EN_AES_RO_EN 0x00001778 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GSP_RISCV_DEV_DIS 0x0000177C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SEC_RISCV_DEV_DIS 0x00001780 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PMU_RISCV_DEV_DIS 0x00001784 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RISCV_DCLS_SECURITY_ACTION_HALT 0x00001788 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT 0x0000178C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT 0x00001790 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE 0x00001798 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_CLOCKS_MCLK_WR_SECURE 0x0000179C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SEC_DEFAULT_CORE_SELECT 0x00001800 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PMU_DEFAULT_CORE_SELECT 0x00001804 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_GSP_DEFAULT_CORE_SELECT 0x00001808 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE 0x00001814 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE 0x00001818 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE 0x0000181C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_IST_PRI_FILLER_WR_SECURE 0x00001820 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FB_TRIM_REV 0x00001824 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE1_VERSION 0x00004100 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE2_VERSION 0x00004104 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE3_VERSION 0x00004108 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE4_VERSION 0x0000410C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE5_VERSION 0x00004110 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE6_VERSION 0x00004114 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE7_VERSION 0x00004118 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE8_VERSION 0x0000411C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE9_VERSION 0x00004120 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE10_VERSION 0x00004124 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE11_VERSION 0x00004128 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE12_VERSION 0x0000412C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE13_VERSION 0x00004130 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE14_VERSION 0x00004134 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE15_VERSION 0x00004138 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_UCODE16_VERSION 0x0000413C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE1_VERSION 0x00004140 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE2_VERSION 0x00004144 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE3_VERSION 0x00004148 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE4_VERSION 0x0000414C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE5_VERSION 0x00004150 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE6_VERSION 0x00004154 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE7_VERSION 0x00004158 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE8_VERSION 0x0000415C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE9_VERSION 0x00004160 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE10_VERSION 0x00004164 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE11_VERSION 0x00004168 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE12_VERSION 0x0000416C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE13_VERSION 0x00004170 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE14_VERSION 0x00004174 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE15_VERSION 0x00004178 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC2_UCODE16_VERSION 0x0000417C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE1_VERSION 0x00004180 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE2_VERSION 0x00004184 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE3_VERSION 0x00004188 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE4_VERSION 0x0000418C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE5_VERSION 0x00004190 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE6_VERSION 0x00004194 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE7_VERSION 0x00004198 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE8_VERSION 0x0000419C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE9_VERSION 0x000041A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE10_VERSION 0x000041A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE11_VERSION 0x000041A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE12_VERSION 0x000041AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE13_VERSION 0x000041B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE14_VERSION 0x000041B4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE15_VERSION 0x000041B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_UCODE16_VERSION 0x000041BC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE1_VERSION 0x000041C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE2_VERSION 0x000041C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE3_VERSION 0x000041C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE4_VERSION 0x000041CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE5_VERSION 0x000041D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE6_VERSION 0x000041D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE7_VERSION 0x000041D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE8_VERSION 0x000041DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE9_VERSION 0x000041E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE10_VERSION 0x000041E4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE11_VERSION 0x000041E8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE12_VERSION 0x000041EC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE13_VERSION 0x000041F0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE14_VERSION 0x000041F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE15_VERSION 0x000041F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_UCODE16_VERSION 0x000041FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_XUSB_UCODE1_VERSION 0x00004200 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_XUSB_UCODE2_VERSION 0x00004204 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_XUSB_UCODE3_VERSION 0x00004208 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_XUSB_UCODE4_VERSION 0x0000420C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_XUSB_UCODE5_VERSION 0x00004210 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_XUSB_UCODE6_VERSION 0x00004214 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_XUSB_UCODE7_VERSION 0x00004218 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_XUSB_UCODE8_VERSION 0x0000421C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE1_VERSION 0x00004220 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE2_VERSION 0x00004224 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE3_VERSION 0x00004228 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE4_VERSION 0x0000422C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE5_VERSION 0x00004230 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE6_VERSION 0x00004234 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE7_VERSION 0x00004238 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE8_VERSION 0x0000423C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_CTKID 0x00004240 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_SCRUBBER_BIN_REV 0x00004244 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_SEC2_REV 0x00004248 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_PR_VPR_REV 0x0000424C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_ACR_HS_REV 0x00004250 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_GFW_REV 0x00004254 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_ROM_FLASH_REV 0x00004258 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_NVDEC_REV 0x0000425C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_CTXSW_REV 0x00004260 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_FBFALCON_REV 0x00004264 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_GSP_REV 0x00004268 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_0 0x0000426C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_1 0x00004270 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_2 0x00004274 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_3 0x00004278 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_4 0x0000427C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_5 0x00004280 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_6 0x00004284 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_7 0x00004288 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_8 0x0000428C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_9 0x00004290 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_10 0x00004294 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_11 0x00004298 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_12 0x0000429C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_13 0x000042A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_14 0x000042A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_15 0x000042A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_16 0x000042AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_17 0x000042B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_18 0x000042B4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_19 0x000042B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_20 0x000042BC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_21 0x000042C0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_22 0x000042C4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_23 0x000042C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_24 0x000042CC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_25 0x000042D0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_26 0x000042D4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_27 0x000042D8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_28 0x000042DC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_29 0x000042E0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_30 0x000042E4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_FEATURE_CONTROL_31 0x000042E8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SKU_CONVERSION 0x000042EC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_TPC_ENABLED_COUNT0 0x000042F0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_TPC_ENABLED_COUNT1 0x000042F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_OVERLOCK_INFO 0x000042F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_0 0x000042FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_1 0x00004304 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_2 0x00004308 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_3 0x0000430C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_4 0x00004310 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_5 0x00004314 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_6 0x00004318 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_7 0x0000431C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_8 0x00004320 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_9 0x00004324 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_10 0x00004328 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_11 0x0000432C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_12 0x00004330 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_13 0x00004334 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_14 0x00004338 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_15 0x0000433C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_FIELD_SPARE_FUSES_16 0x00004340 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC_RISCV_PL3_DISABLE 0x00004344 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_RISCV_PL3_DISABLE 0x00004348 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_RISCV_PL3_DISABLE 0x0000434C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC_FALCON_DISABLE 0x00004350 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_FALCON_DISABLE 0x00004354 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_FALCON_DISABLE 0x00004358 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE9_VERSION 0x0000435C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE10_VERSION 0x00004360 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE11_VERSION 0x00004364 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE12_VERSION 0x00004368 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE13_VERSION 0x0000436C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE14_VERSION 0x00004370 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE15_VERSION 0x00004374 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_MINION_UCODE16_VERSION 0x00004378 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_MINION_REV 0x0000437C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS 0x00004380 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_FALCON_BR_VHR_DIS 0x00004384 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC_FALCON_BR_VHR_DIS 0x00004388 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_FALCON_BR_VHR_DIS 0x0000438C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN 0x00004390 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN 0x00004394 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN 0x00004398 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_PRI_FILLER_WR_SECURE 0x0000439C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_RMA_PRI_FILLER_UNLOCK 0x000043A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_RMA_PRI_FILLER_LOCK 0x000043A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_IST_DISABLE 0x000043A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_RMA_IST_ENABLE 0x000043AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_RMA_IST_DISABLE 0x000043B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FPF_UCODE_LSPMU_REV 0x000043B4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_0 0x000043B8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_1 0x000043BC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_2 0x000043C0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_3 0x000043C4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_4 0x000043C8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_5 0x000043CC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_6 0x000043D0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_7 0x000043D4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_8 0x000043D8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_9 0x000043DC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_10 0x000043E0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_11 0x000043E4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_12 0x000043E8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_13 0x000043EC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_14 0x000043F0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_15 0x000043F4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_16 0x000043F8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_17 0x000043FC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_18 0x00004400 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_19 0x00004404 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_20 0x00004408 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_21 0x0000440C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_22 0x00004410 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_23 0x00004414 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_24 0x00004418 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_25 0x0000441C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_26 0x00004420 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_27 0x00004424 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_28 0x00004428 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_29 0x0000442C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_30 0x00004430 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_31 0x00004434 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_32 0x00004438 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_33 0x0000443C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_34 0x00004440 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_35 0x00004444 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_36 0x00004448 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_37 0x0000444C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_38 0x00004450 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_39 0x00004454 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_40 0x00004458 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_41 0x0000445C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_42 0x00004460 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_43 0x00004464 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_44 0x00004468 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_45 0x0000446C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_46 0x00004470 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_47 0x00004474 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_48 0x00004478 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_49 0x0000447C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_50 0x00004480 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_51 0x00004484 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_52 0x00004488 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_53 0x0000448C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_54 0x00004490 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_55 0x00004494 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_56 0x00004498 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_57 0x0000449C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_58 0x000044A0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_59 0x000044A4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_60 0x000044A8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_61 0x000044AC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_62 0x000044B0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_63 0x000044B4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_64 0x000044B8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_65 0x000044BC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_66 0x000044C0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_67 0x000044C4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_68 0x000044C8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_69 0x000044CC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_70 0x000044D0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_71 0x000044D4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_72 0x000044D8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_73 0x000044DC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_74 0x000044E0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_75 0x000044E4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_76 0x000044E8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_77 0x000044EC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_78 0x000044F0 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_79 0x000044F4 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_80 0x000044F8 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_81 0x000044FC /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_82 0x00004500 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_83 0x00004504 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_84 0x00004508 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_85 0x0000450C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_86 0x00004510 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_87 0x00004514 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_88 0x00004518 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_89 0x0000451C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_90 0x00004520 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_91 0x00004524 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_ENDIS_0 0x00004528 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_ENDIS_1 0x0000452C /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_ENDIS_2 0x00004530 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_ENDIS_3 0x00004534 /* RW-4R */
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#define NV_FUSE_OFFSET_SPARE_BIT_ENDIS_4 0x00004538 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_SHARED 0x00001354 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_GPC6 0x00001328 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_GPC0 0x00001358 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_SHARED 0x0000139C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_GPC1 0x00001314 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBB_PADS_TRIM 0x000011EC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_SENSE 0x000013E8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBF_PADS_TRIM 0x000011FC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_GPC5 0x000013B4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_PCIE_MAGIC_BITS_D 0x00000520 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBD_PADS_TRIM 0x000011F4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_GPC2 0x00001360 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CP2_TDIODE_OFFSET 0x00000120 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBC_PADS_TRIM 0x000011F0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_GPC6 0x000013B8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_GPC5 0x0000136C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_GPC3 0x00001364 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_GPC1 0x000013A4 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_GPC4 0x00001368 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_GPC3 0x0000131C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_GPC6 0x00001370 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_GPC0 0x00001310 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_GPC4 0x00001320 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_GPC2 0x00001318 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_LT_GPC1 0x0000135C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_GPC3 0x000013AC /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_GPC4 0x000013B0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_SHARED 0x0000130C /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_GPC0 0x000013A0 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBA_PADS_TRIM 0x000011E8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CODE_ERR_HT_GPC2 0x000013A8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_FBE_PADS_TRIM 0x000011F8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_CP1_TDIODE_OFFSET 0x000004C8 /* RW-4R */
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#define NV_FUSE_OFFSET_OPT_ADC_CAL_GPC5 0x00001324 /* RW-4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_NVJPG 0x0000080C /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_NVENC 0x00000968 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_ROP_GPC(i) (0x00002000+(i)*4) /* RWI4A */
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#define NV_FUSE_OFFSET_CTRL_OPT_ROP_GPC__SIZE_1 16 /* */
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#define NV_FUSE_OFFSET_CTRL_OPT_SEC 0x00000828 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_FBP 0x00000938 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_OFA 0x00000BC0 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_PERLINK 0x00000820 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_NVDEC 0x00000824 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_PES_GPC(i) (0x000009BC+(i)*4) /* RWI4A */
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#define NV_FUSE_OFFSET_CTRL_OPT_PES_GPC__SIZE_1 16 /* */
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#define NV_FUSE_OFFSET_CTRL_OPT_FBIO 0x00000814 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_DISP_HEAD 0x00000808 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_GPC 0x0000081C /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_SPARE_FS 0x00000830 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_PCIE_LANE 0x0000082C /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_NVLINK 0x000009B8 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_TPC_GPC(i) (0x00000838+(i)*4) /* RWI4A */
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#define NV_FUSE_OFFSET_CTRL_OPT_TPC_GPC__SIZE_1 32 /* */
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#define NV_FUSE_OFFSET_CTRL_OPT_HALF_FBPA 0x00000800 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_GC6_ISLAND 0x0000096C /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_L2SLICE_FBP(i) (0x00002080+(i)*4) /* RWI4A */
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#define NV_FUSE_OFFSET_CTRL_OPT_L2SLICE_FBP__SIZE_1 16 /* */
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#define NV_FUSE_OFFSET_CTRL_OPT_HALF_LTC 0x00000810 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_DISPLAY 0x00000804 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_FB_CONFIG 0x00000834 /* RWI4R */
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#define NV_FUSE_OFFSET_CTRL_OPT_LTC_FBP(i) (0x00000970+(i)*4) /* RWI4A */
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#define NV_FUSE_OFFSET_CTRL_OPT_LTC_FBP__SIZE_1 16 /* */
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#define NV_FUSE_OFFSET_STATUS_OPT_NVJPG 0x00000C0C /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_NVENC 0x00000D68 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_ROP_GPC(i) (0x00002880+(i)*4) /* R-I4A */
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#define NV_FUSE_OFFSET_STATUS_OPT_ROP_GPC__SIZE_1 16 /* */
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#define NV_FUSE_OFFSET_STATUS_OPT_SEC 0x00000C28 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_FBP 0x00000D38 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_OFA 0x00000E34 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_PERLINK 0x00000C20 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_NVDEC 0x00000C24 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_PES_GPC(i) (0x00000DBC+(i)*4) /* R-I4A */
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#define NV_FUSE_OFFSET_STATUS_OPT_PES_GPC__SIZE_1 16 /* */
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#define NV_FUSE_OFFSET_STATUS_OPT_FBIO 0x00000C14 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_DISP_HEAD 0x00000C08 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_GPC 0x00000C1C /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_SPARE_FS 0x00000C30 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_PCIE_LANE 0x00000C2C /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_NVLINK 0x00000DB8 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_TPC_GPC(i) (0x00000C38+(i)*4) /* R-I4A */
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#define NV_FUSE_OFFSET_STATUS_OPT_TPC_GPC__SIZE_1 32 /* */
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#define NV_FUSE_OFFSET_STATUS_OPT_HALF_FBPA 0x00000C00 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_GC6_ISLAND 0x00000D6C /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_L2SLICE_FBP(i) (0x00002900+(i)*4) /* R-I4A */
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#define NV_FUSE_OFFSET_STATUS_OPT_L2SLICE_FBP__SIZE_1 16 /* */
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#define NV_FUSE_OFFSET_STATUS_OPT_HALF_LTC 0x00000C10 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_DISPLAY 0x00000C04 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_FB_CONFIG 0x00000C34 /* R-I4R */
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#define NV_FUSE_OFFSET_STATUS_OPT_LTC_FBP(i) (0x00000D70+(i)*4) /* R-I4A */
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#define NV_FUSE_OFFSET_STATUS_OPT_LTC_FBP__SIZE_1 16 /* */
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#define NV_FUSE_OFFSET_RECONFIG_OVERRIDE_OPT_TPC_GPC(i) (0x00000A40+(i)*4) /* RWI4A */
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#define NV_FUSE_OFFSET_RECONFIG_OVERRIDE_OPT_TPC_GPC__SIZE_1 32 /* */
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#define NV_FUSE_OFFSET_DISABLE_EXTEND_OPT_TPC_GPC(i) (0x00002800+(i)*4) /* RWI4A */
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#define NV_FUSE_OFFSET_DISABLE_EXTEND_OPT_TPC_GPC__SIZE_1 32 /* */
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#define NV_FUSE_OFFSET_KFUSE_STATE 0x00005C00 /* RW-4R */
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#define NV_FUSE_OFFSET_KFUSE_ERRCOUNT 0x00005C04 /* R--4R */
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#define NV_FUSE_OFFSET_KFUSE_KEYADDR 0x00005C08 /* RW-4R */
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#define NV_FUSE_OFFSET_KFUSE_KEYS 0x00005C0C /* R--4R */
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#define NV_FUSE_OFFSET_KFUSE_DEBUG 0x00005C10 /* RW-4R */
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#define NV_FUSE_OFFSET_KFUSE_KEYSET_STATUS 0x00005C14 /* R--4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_QUADRO 0x00003808 /* RW-4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_ECC 0x0000380C /* RW-4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_ECC_1 0x00003810 /* RW-4R */
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#define NV_FUSE_OFFSET_FEATURE_READOUT 0x00003814 /* R--4R */
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#define NV_FUSE_OFFSET_FEATURE_READOUT_1 0x00003818 /* R--4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_SM_SPEED_SELECT 0x0000381C /* RW-4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_SM_SPEED_SELECT_1 0x00003820 /* RW-4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_ROW_REMAPPER 0x00003824 /* RW-4R */
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#define NV_FUSE_OFFSET_FEATURE_READOUT_2 0x00003828 /* R--4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_ECC_2 0x0000382C /* RW-4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_GFX_SPEED_SELECT 0x00003830 /* RW-4R */
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#define NV_FUSE_OFFSET_FEATURE_READOUT_3 0x00003834 /* R--4R */
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#define NV_FUSE_OFFSET_FEATURE_OVERRIDE_MEMQUAL 0x00003838 /* RW-4R */
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#define NV_FUSE_OFFSET_SECURITY_MONITOR 0x00005800 /* R--4R */
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#define NV_FUSE_OFFSET_RESHIFT_GPC_RAIL 0x00005808 /* RWE4R */
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#define NV_FUSE_OFFSET_RESHIFT_GPC_CTRL_CYA 0x0000580C /* RWE4R */
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#define NV_FUSE_OFFSET_CLAMP_EN_RESET_CONTROL 0x00005810 /* RWE4R */
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#define NV_FUSE_OFFSET_SECURITY_MONITOR_SCPM_CTRL 0x00005894 /* RWE4R */
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#define NV_FUSE_OFFSET_SECURITY_MONITOR_SCPM_MON 0x00005898 /* R--4R */
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#define NV_FUSE_OFFSET_SECURITY_MONITOR_POD_CTRL 0x0000589C /* RWE4R */
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#define NV_FUSE_OFFSET_SECURITY_MONITOR_POD_MON 0x000058A0 /* R--4R */
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#endif // __ga102_dev_fuse_off_h__
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