3643 lines
464 KiB
C
3643 lines
464 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_falcon_v4_h__
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#define __ga102_dev_falcon_v4_h__
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/* This file is autogenerated. Do not edit */
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#define NV_FALCON_NVDEC_BASE 0x00848000
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#define NV_FALCON_NVDEC0_BASE 0x00848000
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#define NV_FALCON_NVDEC1_BASE 0x0084c000
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#define NV_FALCON_MSVLD_BASE 0x00084000
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#define NV_FALCON_MSPDEC_BASE 0x00085000
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#define NV_FALCON_MSPPP_BASE 0x00086000
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#define NV_FALCON_PWR_BASE 0x0010a000
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#define NV_FALCON_CE0_BASE 0x00104000
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#define NV_FALCON_CE1_BASE 0x00105000
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#define NV_FALCON_NVENC_BASE 0x001c8000
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#define NV_FALCON_NVENC0_BASE 0x001c8000
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#define NV_FALCON_HDA_BASE 0x001c3000
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#define NV_FALCON_GSP_BASE 0x00110000
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#define NV_FALCON_MINION_BASE 0x00A06000
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#define NV_FALCON_FBFALCON_BASE 0x009A4000
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK 0x00000280 /* RWI4R */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK 0x00000284 /* RWI4R */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x00000288 /* RWI4R */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK 0x0000028c /* RWI4R */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x00000290 /* RWI4R */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x00000294 /* RWI4R */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK 0x000000e8 /* RWI4R */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK 0x000000ec /* RWI4R */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse2" /* */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFALCON_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK 0x00000298 /* RWI4R */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0000029c /* RWI4R */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x000003d0 /* RWI4R */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x000003f0 /* RWI4R */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x000003f4 /* RWI4R */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x000003f8 /* RWI4R */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x000003fc /* RWI4R */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(i) (0x000003d8+(i)*4) /* RW-4A */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_1 2 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x0000018c+(i)*16) /* RW-4A */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x000002b0+(i)*4) /* RW-4A */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK 0x00000190 /* RW-4R */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x00000194 /* RW-4R */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK 0x00000198 /* RW-4R */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x0000019c /* RW-4R */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK 0x000001a0 /* RW-4R */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x000001a4 /* RW-4R */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x000001a8 /* RW-4R */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK 0x000001bc /* RW-4R */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x000001e0 /* RW-4R */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x000001e4 /* RW-4R */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK 0x000001e8 /* RW-4R */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK 0x000001ec /* RW-4R */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x000001f0 /* RW-4R */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK 0x000001f4 /* RW-4R */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x000001f8 /* RW-4R */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK 0x000001fc /* RW-4R */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK 0x00000220 /* RW-4R */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x00000224 /* RW-4R */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK 0x0000022c /* RW-4R */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSSET 0x00000000 /* -W-4R */
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#define NV_PFALCON_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_HALT 4:4 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_EXT 15:8 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_DMA 16:16 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSSET_SHA 17:17 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR 0x00000004 /* -W-4R */
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#define NV_PFALCON_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_EXT 15:8 /* */
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#define NV_PFALCON_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQSTAT 0x00000008 /* R--4R */
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#define NV_PFALCON_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_EXT 15:8 /* */
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#define NV_PFALCON_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMODE 0x0000000c /* RW-4R */
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#define NV_PFALCON_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x00000290 /* */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SHA 17:17 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SHA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SHA_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQMODE_LVL_SHA_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK 0x000000e0 /* RW-4R */
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#define NV_PFALCON_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x000001a4 /* */
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#define NV_PFALCON_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQSCMASK_SHA 17:17 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQSCMASK_SHA_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQSCMASK_SHA_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL(i) (0x000003e0+(i)*4) /* RW-4A */
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#define NV_PFALCON_FALCON_INTR_CTRL__SIZE_1 2 /* */
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#define NV_PFALCON_FALCON_INTR_CTRL__PRIV_LEVEL_MASK NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_INTR_CTRL_VECTOR 11:0 /* RW-VF */
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#define NV_PFALCON_FALCON_INTR_CTRL_GFID 25:20 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_GFID_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_GSP 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_GSP_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_GSP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_CTRL_CPU 31:31 /* RWIVF */
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#define NV_PFALCON_FALCON_INTR_CTRL_CPU_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_INTR_CTRL_CPU_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_INTR_RETRIGGER(i) (0x000003e8+(i)*4) /* -W-4A */
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#define NV_PFALCON_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */
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#define NV_PFALCON_FALCON_INTR_RETRIGGER__PRIV_LEVEL_MASK NV_PFALCON_FALCON_INTR_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
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#define NV_PFALCON_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET 0x00000010 /* -W-4R */
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#define NV_PFALCON_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x00000290 /* */
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#define NV_PFALCON_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_HALT 4:4 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_EXT 15:8 /* */
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#define NV_PFALCON_FALCON_IRQMSET_DMA 16:16 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMSET_SHA 17:17 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMSET_SHA_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR 0x00000014 /* -W-4R */
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#define NV_PFALCON_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x00000290 /* */
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#define NV_PFALCON_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_EXT 15:8 /* */
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#define NV_PFALCON_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMCLR_SHA 17:17 /* -WXVF */
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#define NV_PFALCON_FALCON_IRQMCLR_SHA_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_IRQMASK 0x00000018 /* R--4R */
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#define NV_PFALCON_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_EXT 15:8 /* */
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#define NV_PFALCON_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQMASK_SHA 17:17 /* R-IVF */
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#define NV_PFALCON_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IRQDEST 0x0000001c /* RW-4R */
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#define NV_PFALCON_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x00000290 /* */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_HOST_EXT 15:8 /* */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
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#define NV_PFALCON_FALCON_IRQDEST2 0x0000003c /* RW-4R */
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#define NV_PFALCON_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x00000290 /* */
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#define NV_PFALCON_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_HOST_SHA 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST2_HOST_SHA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST2_HOST_SHA_FALCON 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_HOST_SHA_HOST 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_SHA 17:17 /* RWIVF */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_SHA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_SHA_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IRQDEST2_TARGET_SHA_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_GPTMRINT 0x00000020 /* RW-4R */
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#define NV_PFALCON_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x000001a0 /* */
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#define NV_PFALCON_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_GPTMRVAL 0x00000024 /* RW-4R */
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#define NV_PFALCON_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x000001a0 /* */
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#define NV_PFALCON_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_GPTMRCTL 0x00000028 /* RW-4R */
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#define NV_PFALCON_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x000001a0 /* */
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#define NV_PFALCON_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_PTIMER0 0x0000002c /* R--4R */
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#define NV_PFALCON_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x000001bc /* */
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#define NV_PFALCON_FALCON_PTIMER0_VAL 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_PTIMER1 0x00000030 /* R--4R */
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#define NV_PFALCON_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x000001bc /* */
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#define NV_PFALCON_FALCON_PTIMER1_VAL 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_WDTMRVAL 0x00000034 /* RW-4R */
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#define NV_PFALCON_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0000029c /* */
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#define NV_PFALCON_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMRCTL 0x00000038 /* RW-4R */
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#define NV_PFALCON_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0000029c /* */
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#define NV_PFALCON_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDDATA 0x00000064 /* R--4R */
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#define NV_PFALCON_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */
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#define NV_PFALCON_FALCON_MTHDID 0x00000068 /* RW-4R */
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#define NV_PFALCON_FALCON_MTHDID__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_MTHDID_ID 11:0 /* RWXVF */
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#define NV_PFALCON_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */
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#define NV_PFALCON_FALCON_MTHDID_PRIV 15:15 /* RWXVF */
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#define NV_PFALCON_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_MTHDID_WPEND 16:16 /* R-XVF */
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#define NV_PFALCON_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_MTHDWDAT 0x0000006c /* RW-4R */
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#define NV_PFALCON_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */
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#define NV_PFALCON_FALCON_MTHDCOUNT 0x00000070 /* R--4R */
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#define NV_PFALCON_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */
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#define NV_PFALCON_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_MTHDPOP 0x00000074 /* -W-4R */
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#define NV_PFALCON_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_MTHDPOP_POP 0:0 /* -WXVF */
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#define NV_PFALCON_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_MTHDRAMSZ 0x00000078 /* RW-4R */
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#define NV_PFALCON_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */
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#define NV_PFALCON_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_CURCTX 0x00000050 /* RW-4R */
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#define NV_PFALCON_FALCON_CURCTX__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */
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#define NV_PFALCON_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */
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#define NV_PFALCON_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_NXTCTX 0x00000054 /* RW-4R */
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#define NV_PFALCON_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */
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#define NV_PFALCON_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */
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#define NV_PFALCON_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_CTXACK 0x00000058 /* -W-4R */
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#define NV_PFALCON_FALCON_CTXACK__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */
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#define NV_PFALCON_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */
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#define NV_PFALCON_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_CURCTX2 0x000003c8 /* RW-4R */
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#define NV_PFALCON_FALCON_CURCTX2__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_CURCTX2_CTXGFID 5:0 /* RWIVF */
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#define NV_PFALCON_FALCON_CURCTX2_CTXGFID_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_NXTCTX2 0x000003cc /* RW-4R */
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#define NV_PFALCON_FALCON_NXTCTX2__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_NXTCTX2_CTXGFID 5:0 /* RWIVF */
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#define NV_PFALCON_FALCON_NXTCTX2_CTXGFID_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
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#define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
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#define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_ITFEN 0x00000048 /* RW-4R */
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#define NV_PFALCON_FALCON_ITFEN__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */
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#define NV_PFALCON_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS 4:4 /* RWIVF */
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#define NV_PFALCON_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */
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#define NV_PFALCON_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IDLESTATE 0x0000004c /* RW-4R */
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#define NV_PFALCON_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x000001e0 /* */
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#define NV_PFALCON_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */
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#define NV_PFALCON_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */
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#define NV_PFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */
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#define NV_PFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_IDLESTATE_INT_BUSY_SHA 24:24 /* R-IVF */
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#define NV_PFALCON_FALCON_IDLESTATE_INT_BUSY_SHA_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IDLESTATE_INT_BUSY_SHA_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_FHSTATE 0x0000005c /* R--4R */
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#define NV_PFALCON_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x000001e4 /* */
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#define NV_PFALCON_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */
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#define NV_PFALCON_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */
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#define NV_PFALCON_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */
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#define NV_PFALCON_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */
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#define NV_PFALCON_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_PRIVSTATE 0x00000060 /* RW-4R */
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#define NV_PFALCON_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x000003d0 /* */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_VPR_FORCE_STICKY 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_PRIVSTATE_VPR_FORCE_STICKY_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_PRIVSTATE_VPR_FORCE_STICKY_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_PRIVSTATE_VPR_FORCE_STICKY_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_SFTRESET 0x0000007c /* RW-4R */
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#define NV_PFALCON_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_SFTRESET_EXT 0:0 /* RWXVF */
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#define NV_PFALCON_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL 0x000000a4 /* RW-4R */
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#define NV_PFALCON_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */
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#define NV_PFALCON_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */
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#define NV_PFALCON_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */
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#define NV_PFALCON_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */
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#define NV_PFALCON_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */
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#define NV_PFALCON_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */
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#define NV_PFALCON_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_ADDR 0x000000ac /* RW-4R */
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#define NV_PFALCON_FALCON_ADDR__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_ADDR_LSB 5:0 /* RWIVF */
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#define NV_PFALCON_FALCON_ADDR_LSB_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_ADDR_MSB 11:6 /* RWIVF */
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#define NV_PFALCON_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_ADDR_EXT 11:0 /* */
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#define NV_PFALCON_FALCON_DMACTL 0x0000010c /* RW-4R */
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#define NV_PFALCON_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
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#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
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#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */
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#define NV_PFALCON_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */
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#define NV_PFALCON_FALCON_DMATRFBASE 0x00000110 /* RW-4R */
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#define NV_PFALCON_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMATRFMOFFS 0x00000114 /* RW-4R */
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#define NV_PFALCON_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMATRFCMD 0x00000118 /* RW-4R */
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#define NV_PFALCON_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */
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#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMATRFFBOFFS 0x0000011c /* RW-4R */
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#define NV_PFALCON_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB 0x00000120 /* RW-4R */
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#define NV_PFALCON_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP 0x00000124 /* RW-4R */
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#define NV_PFALCON_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMATRFBASE1 0x00000128 /* RW-4R */
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#define NV_PFALCON_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMATRFBASE1_BASE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x000002c0 /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x000002c4 /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x000002c8 /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x000002cc /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x000002d0 /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x000002d4 /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x000002d8 /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x000002dc /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CTL 0x000002e0 /* RW-4R */
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#define NV_PFALCON_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMAINFO_ERR_TAG_HIGH 0x000002e4 /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFALCON_FALCON_DMAINFO_ERR_TAG_LOW 0x000002e8 /* R--4R */
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#define NV_PFALCON_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x00000190 /* */
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#define NV_PFALCON_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */
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#define NV_PFALCON_FALCON_IMEMC__SIZE_1 1 /* */
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#define NV_PFALCON_FALCON_IMEMC__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEMC_BLK 23:8 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
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#define NV_PFALCON_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
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#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
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#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
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#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */
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#define NV_PFALCON_FALCON_IMEMD__SIZE_1 1 /* */
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#define NV_PFALCON_FALCON_IMEMD__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_IMEMD_DATA 31:0 /* RWXVF */
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#define NV_PFALCON_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */
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#define NV_PFALCON_FALCON_IMEMT__SIZE_1 1 /* */
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#define NV_PFALCON_FALCON_IMEMT__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_IMEMT_TAG 15:0 /* RWXVF */
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#define NV_PFALCON_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */
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#define NV_PFALCON_FALCON_DMEMC__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEMC_OFFS 7:2 /* */
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#define NV_PFALCON_FALCON_DMEMC_OFFS_INIT 0 /* */
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#define NV_PFALCON_FALCON_DMEMC_BLK 23:8 /* */
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#define NV_PFALCON_FALCON_DMEMC_BLK_INIT 0 /* */
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#define NV_PFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_VA 28:28 /* RWIVF */
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#define NV_PFALCON_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMEMC_MISS 29:29 /* R-IVF */
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#define NV_PFALCON_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
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#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
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#define NV_PFALCON_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */
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#define NV_PFALCON_FALCON_DMEMD__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_DMEMD_DATA 31:0 /* RWXVF */
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#define NV_PFALCON_FALCON_DMEMT(i) (0x00000210+(i)*4) /* -W-4A */
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#define NV_PFALCON_FALCON_DMEMT__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_DMEMT__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_DMEMT_TAG 15:0 /* -WXVF */
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#define NV_PFALCON_FALCON_DMEML(i) (0x000002a0+(i)*4) /* -W-4A */
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#define NV_PFALCON_FALCON_DMEML__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_DMEML__PRIV_LEVEL_MASK NV_PFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFALCON_FALCON_DMEML_LVL 2:0 /* -WXVF */
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#define NV_PFALCON_FALCON_DMEM_DUMMY 0x00000258 /* R--4R */
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#define NV_PFALCON_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */
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#define NV_PFALCON_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x00000284 /* */
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#define NV_PFALCON_FALCON_IMEM_DUMMY 0x000001b4 /* R--4R */
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#define NV_PFALCON_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */
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#define NV_PFALCON_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x00000280 /* */
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#define NV_PFALCON_FALCON_DIO_RESET_DELAY 0x00000274 /* RW-4R */
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#define NV_PFALCON_FALCON_DIO_RESET_DELAY__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_DIO_RESET_DELAY_VALUE 15:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DIO_RESET_DELAY_VALUE_INIT 0x00000100 /* RWI-V */
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#define NV_PFALCON_FALCON_DOC_CTRL 0x00000340 /* RW-4R */
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#define NV_PFALCON_FALCON_DOC_CTRL__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_DOC_CTRL_COUNT 7:0 /* R--VF */
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#define NV_PFALCON_FALCON_DOC_CTRL_RESET 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_DOC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DOC_CTRL_STOP 17:17 /* RWIVF */
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#define NV_PFALCON_FALCON_DOC_CTRL_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DOC_CTRL_EMPTY 18:18 /* R-IVF */
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#define NV_PFALCON_FALCON_DOC_CTRL_EMPTY_INIT 0x00000001 /* R-I-V */
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#define NV_PFALCON_FALCON_DOC_CTRL_WR_FINISHED 19:19 /* R-IVF */
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#define NV_PFALCON_FALCON_DOC_CTRL_WR_FINISHED_INIT 0x00000001 /* R-I-V */
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#define NV_PFALCON_FALCON_DOC_CTRL_RD_FINISHED 20:20 /* R-IVF */
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#define NV_PFALCON_FALCON_DOC_CTRL_RD_FINISHED_INIT 0x00000001 /* R-I-V */
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#define NV_PFALCON_FALCON_DOC_CTRL_WR_ERROR 21:21 /* RWIVF */
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#define NV_PFALCON_FALCON_DOC_CTRL_WR_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DOC_CTRL_RD_ERROR 22:22 /* RWIVF */
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#define NV_PFALCON_FALCON_DOC_CTRL_RD_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DOC_CTRL_PROTOCOL_ERROR 23:23 /* RWIVF */
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#define NV_PFALCON_FALCON_DOC_CTRL_PROTOCOL_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DOC_D0 0x00000344 /* RW-4R */
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#define NV_PFALCON_FALCON_DOC_D0__PRIV_LEVEL_MASK 0x000000ec /* */
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#define NV_PFALCON_FALCON_DOC_D0_DATA 31:0 /* RW-VF */
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#define NV_PFALCON_FALCON_DOC_D1 0x00000348 /* RW-4R */
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#define NV_PFALCON_FALCON_DOC_D1__PRIV_LEVEL_MASK 0x000000ec /* */
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#define NV_PFALCON_FALCON_DOC_D1_DATA 31:0 /* RW-VF */
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#define NV_PFALCON_FALCON_DOC_D2 0x0000034c /* RW-4R */
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#define NV_PFALCON_FALCON_DOC_D2__PRIV_LEVEL_MASK 0x000000ec /* */
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#define NV_PFALCON_FALCON_DOC_D2_DATA 15:0 /* RW-VF */
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#define NV_PFALCON_FALCON_DIC_CTRL 0x00000350 /* RW-4R */
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#define NV_PFALCON_FALCON_DIC_CTRL__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_DIC_CTRL_COUNT 7:0 /* R--VF */
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#define NV_PFALCON_FALCON_DIC_CTRL_RESET 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_DIC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DIC_CTRL_VALID 19:19 /* R-IVF */
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#define NV_PFALCON_FALCON_DIC_CTRL_VALID_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_DIC_CTRL_POP 20:20 /* -W-VF */
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#define NV_PFALCON_FALCON_DIC_D0 0x00000354 /* RW-4R */
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#define NV_PFALCON_FALCON_DIC_D0__PRIV_LEVEL_MASK 0x000000ec /* */
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#define NV_PFALCON_FALCON_DIC_D0_DATA 31:0 /* RW-VF */
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#define NV_PFALCON_FALCON_DIC_D1 0x00000358 /* RW-4R */
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#define NV_PFALCON_FALCON_DIC_D1__PRIV_LEVEL_MASK 0x000000ec /* */
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#define NV_PFALCON_FALCON_DIC_D1_DATA 31:0 /* RW-VF */
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#define NV_PFALCON_FALCON_DIC_D2 0x0000035c /* RW-4R */
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#define NV_PFALCON_FALCON_DIC_D2__PRIV_LEVEL_MASK 0x000000ec /* */
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#define NV_PFALCON_FALCON_DIC_D2_DATA 15:0 /* RW-VF */
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#define NV_PFALCON_FALCON_DIO_ERR 0x00000360 /* R--4R */
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#define NV_PFALCON_FALCON_DIO_ERR__PRIV_LEVEL_MASK 0x000000ec /* */
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#define NV_PFALCON_FALCON_DIO_ERR_INFO 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x00000300+(i)*4) /* RW-4A */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x000003f0 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x00000310+(i)*4) /* RW-4A */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x000003f4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x00000320+(i)*4) /* RW-4A */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x000003f8 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x00000330+(i)*4) /* RW-4A */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x000003fc /* */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_PRGNVER 0x000003d4 /* R-I4R */
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#define NV_PFALCON_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */
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#define NV_PFALCON_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */
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#define NV_PFALCON_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */
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#define NV_PFALCON_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */
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#define NV_PFALCON_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG 0x00000108 /* R--4R */
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#define NV_PFALCON_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */
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#define NV_PFALCON_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */
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#define NV_PFALCON_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG1 0x0000012c /* R--4R */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000003 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000001 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000001 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000001 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */
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#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */
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#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
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#define NV_PFALCON_FALCON_HWCFG2_SHA 0:0 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_BMEM 1:1 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_KMEM 4:4 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_VHR 7:7 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_HS 8:8 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_HWCFG3 0x00000278 /* R--4R */
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#define NV_PFALCON_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */
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#define NV_PFALCON_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */
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#define NV_PFALCON_FALCON_CGCTL 0x000000a0 /* RW-4R */
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#define NV_PFALCON_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2 0x00000134 /* RWI4R */
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#define NV_PFALCON_FALCON_CG2__PRIV_LEVEL_MASK 0x000001e8 /* */
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#define NV_PFALCON_FALCON_CG2_SLCG 17:1 /* */
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#define NV_PFALCON_FALCON_CG2_SLCG_ENABLED 0 /* */
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#define NV_PFALCON_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */
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#define NV_PFALCON_FALCON_CG2_SLCG__PROD 0x000A0 /* */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_SHA 18:18 /* RWIVF */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_SHA__PROD 1 /* */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_SHA_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CG2_SLCG_FALCON_SHA_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_ENGID 0x0000013c /* R--4R */
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#define NV_PFALCON_FALCON_ENGID_INSTID 7:0 /* R-IVF */
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#define NV_PFALCON_FALCON_ENGID_INSTID_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID 15:8 /* R--VF */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_SEC 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_DPU 0x00000002 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_NVDEC 0x00000003 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_PWR_PMU 0x00000004 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_FBFACLON 0x00000005 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_NVENC 0x00000006 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_GPCCS 0x00000007 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_FECS 0x00000008 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_MINION 0x00000009 /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_XUSB 0x0000000a /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_GSP 0x0000000b /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_NVJPG 0x0000000c /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_OFA 0x0000000d /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_PSC 0x0000000e /* R---V */
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#define NV_PFALCON_FALCON_ENGID_FAMILYID_SOE 0x0000000f /* R---V */
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#define NV_PFALCON_FALCON_SCTL 0x00000240 /* RW-4R */
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#define NV_PFALCON_FALCON_SCTL__PRIV_LEVEL_MASK 0x00000298 /* */
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#define NV_PFALCON_FALCON_SCTL_LSMODE 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_HSMODE 1:1 /* R--VF */
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#define NV_PFALCON_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_UCODE_LEVEL 5:4 /* */
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#define NV_PFALCON_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */
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#define NV_PFALCON_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL1 0x00000250 /* RW-4R */
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#define NV_PFALCON_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */
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#define NV_PFALCON_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */
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#define NV_PFALCON_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL 0x000000e4 /* RW-4R */
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#define NV_PFALCON_FALCON_HSCTL__PRIV_LEVEL_MASK 0x000000e8 /* */
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#define NV_PFALCON_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_OS 0x00000080 /* RW-4R */
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#define NV_PFALCON_FALCON_OS_VERSION 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_RM 0x00000084 /* RW-4R */
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#define NV_PFALCON_FALCON_RM_CONFIG 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_SOFT_PM 0x00000088 /* RW-4R */
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#define NV_PFALCON_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x000001ec /* */
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#define NV_PFALCON_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */
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#define NV_PFALCON_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */
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#define NV_PFALCON_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_SOFT_MODE 0x0000008c /* RW-4R */
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#define NV_PFALCON_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x000001ec /* */
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#define NV_PFALCON_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */
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#define NV_PFALCON_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DEBUG1 0x00000090 /* RW-4R */
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#define NV_PFALCON_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x00000294 /* */
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#define NV_PFALCON_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */
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#define NV_PFALCON_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */
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#define NV_PFALCON_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */
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#define NV_PFALCON_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */
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#define NV_PFALCON_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DEBUGINFO 0x00000094 /* RW-4R */
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#define NV_PFALCON_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */
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#define NV_PFALCON_FALCON_SP_MIN 0x00000270 /* RW-4R */
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#define NV_PFALCON_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x000001f0 /* */
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#define NV_PFALCON_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */
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#define NV_PFALCON_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_EXCI 0x000000d0 /* R--4R */
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#define NV_PFALCON_FALCON_EXCI__PRIV_LEVEL_MASK 0x000001f4 /* */
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#define NV_PFALCON_FALCON_EXCI_EXPC 19:0 /* R-XVF */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_BROM_CALL_INS 0x00000015 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_KMEM_VIOLATION_INS 0x00000016 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXCAUSE_BMEM_PERMISSION_INS 0x00000017 /* R---V */
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#define NV_PFALCON_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */
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#define NV_PFALCON_FALCON_EXCI2 0x000000bc /* R--4R */
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#define NV_PFALCON_FALCON_EXCI2__PRIV_LEVEL_MASK 0x000001f4 /* */
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#define NV_PFALCON_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */
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#define NV_PFALCON_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_SVEC_SPR 0x000000d4 /* R--4R */
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#define NV_PFALCON_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x000001f8 /* */
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#define NV_PFALCON_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */
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#define NV_PFALCON_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_CPUCTL 0x00000100 /* RW-4R */
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#define NV_PFALCON_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x00000288 /* */
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#define NV_PFALCON_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
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#define NV_PFALCON_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
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#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
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#define NV_PFALCON_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
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#define NV_PFALCON_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
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#define NV_PFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
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#define NV_PFALCON_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
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#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */
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#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
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#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
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#define NV_PFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
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#define NV_PFALCON_FALCON_STACKCFG 0x00000138 /* RW-4R */
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#define NV_PFALCON_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */
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#define NV_PFALCON_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */
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#define NV_PFALCON_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_BOOTVEC 0x00000104 /* RW-4R */
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#define NV_PFALCON_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x00000194 /* */
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#define NV_PFALCON_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL 0x00000254 /* RW-4R */
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#define NV_PFALCON_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x000001a8 /* */
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#define NV_PFALCON_FALCON_DBGCTL_VAL 9:0 /* */
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#define NV_PFALCON_FALCON_DBGCTL_VAL_INIT 0 /* */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_DBGCTL_CYA 31:16 /* RWIVF */
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#define NV_PFALCON_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT1 0x00000098 /* RW-4R */
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#define NV_PFALCON_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x000001fc /* */
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#define NV_PFALCON_FALCON_IBRKPT1_PC 23:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT1_EN 31:31 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT2 0x0000009c /* RW-4R */
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#define NV_PFALCON_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x000001fc /* */
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#define NV_PFALCON_FALCON_IBRKPT2_PC 23:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT2_EN 31:31 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT3 0x000000b0 /* RW-4R */
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#define NV_PFALCON_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x000001fc /* */
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#define NV_PFALCON_FALCON_IBRKPT3_PC 23:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT3_EN 31:31 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT4 0x000000b4 /* RW-4R */
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#define NV_PFALCON_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x000001fc /* */
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#define NV_PFALCON_FALCON_IBRKPT4_PC 23:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT4_EN 31:31 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT5 0x000000b8 /* RW-4R */
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#define NV_PFALCON_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x000001fc /* */
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#define NV_PFALCON_FALCON_IBRKPT5_PC 23:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT5_EN 31:31 /* RWIVF */
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#define NV_PFALCON_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD 0x00000200 /* RW-4R */
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#define NV_PFALCON_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x00000220 /* */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */
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#define NV_PFALCON_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */
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#define NV_PFALCON_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FALCON_ICD_CMD_PARM 31:16 /* */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK 31:16 /* */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_ADDR 0x00000204 /* RW-4R */
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#define NV_PFALCON_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x00000220 /* */
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#define NV_PFALCON_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_WDATA 0x00000208 /* RW-4R */
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#define NV_PFALCON_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x00000220 /* */
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#define NV_PFALCON_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */
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#define NV_PFALCON_FALCON_ICD_RDATA 0x0000020c /* R--4R */
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#define NV_PFALCON_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x00000220 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */
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#define NV_PFALCON_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */
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#define NV_PFALCON_FALCON_RSTAT0 0x000000d8 /* R--4R */
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#define NV_PFALCON_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x00000224 /* */
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#define NV_PFALCON_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_VALID 28:28 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3 0x000000dc /* R--4R */
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#define NV_PFALCON_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */
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#define NV_PFALCON_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */
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#define NV_PFALCON_FALCON_TRACEIDX 0x00000148 /* RW-4R */
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#define NV_PFALCON_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x0000019c /* */
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#define NV_PFALCON_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */
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#define NV_PFALCON_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_PFALCON_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */
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#define NV_PFALCON_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */
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#define NV_PFALCON_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_TRACEPC 0x0000014c /* R--4R */
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#define NV_PFALCON_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x0000019c /* */
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#define NV_PFALCON_FALCON_TRACEPC_PC 23:0 /* R--VF */
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#define NV_PFALCON_FALCON_TRACEINFO 0x0000017c /* R--4R */
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#define NV_PFALCON_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x0000019c /* */
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#define NV_PFALCON_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */
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#define NV_PFALCON_FALCON_IMCTL 0x00000140 /* RW-4R */
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#define NV_PFALCON_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PFALCON_FALCON_IMCTL_CMD 26:24 /* RWXVF */
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#define NV_PFALCON_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */
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#define NV_PFALCON_FALCON_IMCTL_DEBUG 0x0000015c /* RW-4R */
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#define NV_PFALCON_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PFALCON_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */
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#define NV_PFALCON_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_IMSTAT 0x00000144 /* RW-4R */
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#define NV_PFALCON_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_IMSTAT_VAL 31:0 /* RWXVF */
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#define NV_PFALCON_FALCON_IMFILLCTL 0x00000158 /* RW-4R */
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#define NV_PFALCON_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */
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#define NV_PFALCON_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMCTL 0x00000260 /* RW-4R */
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#define NV_PFALCON_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PFALCON_FALCON_DMCTL_CMD 26:24 /* RWXVF */
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#define NV_PFALCON_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */
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#define NV_PFALCON_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */
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#define NV_PFALCON_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */
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#define NV_PFALCON_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */
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#define NV_PFALCON_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */
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#define NV_PFALCON_FALCON_DMSTAT 0x00000264 /* RW-4R */
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#define NV_PFALCON_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_DMSTAT_VAL 31:0 /* RWXVF */
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#define NV_PFALCON_FALCON_DMVACTL 0x00000268 /* RW-4R */
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#define NV_PFALCON_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x00000198 /* */
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#define NV_PFALCON_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMVACTL_BOUND_INIT 0x000000a0 /* RWI-V */
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#define NV_PFALCON_FALCON_DMCYA 0x0000026c /* RW-4R */
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#define NV_PFALCON_FALCON_DMCYA__PRIV_LEVEL_MASK 0x0000028c /* */
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#define NV_PFALCON_FALCON_DMCYA_LDSTVA_DIS 0:0 /* RWIVF */
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#define NV_PFALCON_FALCON_DMCYA_LDSTVA_DIS_FALSE 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_DMCYA_LDSTVA_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_DMCYA_ROB_DIS 1:1 /* RWIVF */
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#define NV_PFALCON_FALCON_DMCYA_ROB_DIS_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMCYA_ROB_DIS_TRUE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMCYA_ROBWB_DIS 2:2 /* RWIVF */
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#define NV_PFALCON_FALCON_DMCYA_ROBWB_DIS_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMCYA_ROBWB_DIS_TRUE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_DMCYA_ROBSPR_DIS 3:3 /* RWIVF */
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#define NV_PFALCON_FALCON_DMCYA_ROBSPR_DIS_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_DMCYA_ROBSPR_DIS_TRUE 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERRSTAT 0x00000244 /* RW-4R */
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#define NV_PFALCON_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x0000022c /* */
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#define NV_PFALCON_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */
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#define NV_PFALCON_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */
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#define NV_PFALCON_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FALCON_CSBERR_ADDR 0x0000024c /* R--4R */
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#define NV_PFALCON_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x0000022c /* */
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#define NV_PFALCON_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */
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#define NV_PFALCON_FALCON_CSBERR_INFO 0x00000248 /* R--4R */
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#define NV_PFALCON_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x0000022c /* */
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#define NV_PFALCON_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */
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#endif // __ga102_dev_falcon_v4_h__
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