47 lines
2.8 KiB
C
47 lines
2.8 KiB
C
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#ifndef ACCESS_MAP_REGISTER_RANGE
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#define ACCESS_MAP_REGISTER_RANGE(start, end)
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#endif
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#ifdef MEM_FBPA_SUBP_UNICAST_FULL
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ACCESS_MAP_REGISTER_RANGE(0x9001e0, 0x9001e4) // (NV_PFB_FBPA_0_PM_SUBP(0), NV_PFB_FBPA_0_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9041e0, 0x9041e4) // (NV_PFB_FBPA_1_PM_SUBP(0), NV_PFB_FBPA_1_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9081e0, 0x9081e4) // (NV_PFB_FBPA_2_PM_SUBP(0), NV_PFB_FBPA_2_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x90c1e0, 0x90c1e4) // (NV_PFB_FBPA_3_PM_SUBP(0), NV_PFB_FBPA_3_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9101e0, 0x9101e4) // (NV_PFB_FBPA_4_PM_SUBP(0), NV_PFB_FBPA_4_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9141e0, 0x9141e4) // (NV_PFB_FBPA_5_PM_SUBP(0), NV_PFB_FBPA_5_PM_SUBP(1))
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#endif
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#ifdef MEM_FBPA_SUBP_UNICAST_HALF
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ACCESS_MAP_REGISTER_RANGE(0x9001e0, 0x9001e4) // (NV_PFB_FBPA_0_PM_SUBP(0), NV_PFB_FBPA_0_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9041e0, 0x9041e4) // (NV_PFB_FBPA_1_PM_SUBP(0), NV_PFB_FBPA_1_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9081e0, 0x9081e4) // (NV_PFB_FBPA_2_PM_SUBP(0), NV_PFB_FBPA_2_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x90c1e0, 0x90c1e4) // (NV_PFB_FBPA_3_PM_SUBP(0), NV_PFB_FBPA_3_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9101e0, 0x9101e4) // (NV_PFB_FBPA_4_PM_SUBP(0), NV_PFB_FBPA_4_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9141e0, 0x9141e4) // (NV_PFB_FBPA_5_PM_SUBP(0), NV_PFB_FBPA_5_PM_SUBP(1))
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#endif
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#ifdef MEM_FBPA_SUBP_UNICAST_QUARTER
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ACCESS_MAP_REGISTER_RANGE(0x9001e0, 0x9001e4) // (NV_PFB_FBPA_0_PM_SUBP(0), NV_PFB_FBPA_0_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9081e0, 0x9081e4) // (NV_PFB_FBPA_2_PM_SUBP(0), NV_PFB_FBPA_2_PM_SUBP(1))
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ACCESS_MAP_REGISTER_RANGE(0x9101e0, 0x9101e4) // (NV_PFB_FBPA_4_PM_SUBP(0), NV_PFB_FBPA_4_PM_SUBP(1))
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#endif
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#ifdef MEM_FBPA_SUBP_UNICAST_EIGHTH
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ACCESS_MAP_REGISTER_RANGE(0x9001e0, 0x9001e0) // (NV_PFB_FBPA_0_PM_SUBP(0), NV_PFB_FBPA_0_PM_SUBP(0))
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ACCESS_MAP_REGISTER_RANGE(0x9081e0, 0x9081e0) // (NV_PFB_FBPA_2_PM_SUBP(0), NV_PFB_FBPA_2_PM_SUBP(0))
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ACCESS_MAP_REGISTER_RANGE(0x9101e0, 0x9101e0) // (NV_PFB_FBPA_4_PM_SUBP(0), NV_PFB_FBPA_4_PM_SUBP(0))
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#endif
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#ifdef MEM_FBPA_SUBP_BROADCAST_FULL
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ACCESS_MAP_REGISTER_RANGE(0x9a01e0, 0x9a01e4) // (NV_PFB_FBPA_PM_SUBP(0), NV_PFB_FBPA_PM_SUBP(1))
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#endif
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#ifdef MEM_FBPA_SUBP_BROADCAST_HALF
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ACCESS_MAP_REGISTER_RANGE(0x9a01e0, 0x9a01e4) // (NV_PFB_FBPA_PM_SUBP(0), NV_PFB_FBPA_PM_SUBP(1))
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#endif
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#ifdef MEM_FBPA_SUBP_BROADCAST_QUARTER
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ACCESS_MAP_REGISTER_RANGE(0x9a01e0, 0x9a01e4) // (NV_PFB_FBPA_PM_SUBP(0), NV_PFB_FBPA_PM_SUBP(1))
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#endif
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#ifdef MEM_FBPA_SUBP_BROADCAST_EIGHTH
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ACCESS_MAP_REGISTER_RANGE(0x9a01e0, 0x9a01e0) // (NV_PFB_FBPA_PM_SUBP(0), NV_PFB_FBPA_PM_SUBP(0))
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#endif
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