172 lines
6.9 KiB
C
172 lines
6.9 KiB
C
// gddr6.c
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#define _GNU_SOURCE
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#include "gddr6.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <unistd.h>
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#include <string.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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#include <pci/pci.h>
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#include <signal.h>
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#define PG_SZ sysconf(_SC_PAGE_SIZE)
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#define PRINT_ERROR() \
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do { \
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fprintf(stderr, "Error at line %d, file %s (%d) [%s]\n", \
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__LINE__, __FILE__, errno, strerror(errno)); exit(1); \
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} while(0)
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#define MAX_DEVICES 32
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struct gddr6_ctx ctx = {0};
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struct device dev_table[] =
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{
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{ .offset = 0x0000E2A8, .dev_id = 0x2684, .vram = "GDDR6X", .arch = "AD102", .name = "RTX 4090" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2685, .vram = "GDDR6X", .arch = "AD102", .name = "RTX 4090 D" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2702, .vram = "GDDR6X", .arch = "AD103", .name = "RTX 4080 Super" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2704, .vram = "GDDR6X", .arch = "AD103", .name = "RTX 4080" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2705, .vram = "GDDR6X", .arch = "AD103", .name = "RTX 4070 Ti Super" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2782, .vram = "GDDR6X", .arch = "AD104", .name = "RTX 4070 Ti" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2783, .vram = "GDDR6X", .arch = "AD104", .name = "RTX 4070 Super" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2786, .vram = "GDDR6X", .arch = "AD104", .name = "RTX 4070" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2860, .vram = "GDDR6", .arch = "AD106", .name = "RTX 4070 Max-Q / Mobile" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2203, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3090 Ti" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2204, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3090" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2208, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3080 Ti" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2206, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3080" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2216, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3080 LHR" },
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{ .offset = 0x0000EE50, .dev_id = 0x2484, .vram = "GDDR6", .arch = "GA104", .name = "RTX 3070" },
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{ .offset = 0x0000EE50, .dev_id = 0x2488, .vram = "GDDR6", .arch = "GA104", .name = "RTX 3070 LHR" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2531, .vram = "GDDR6", .arch = "GA106", .name = "RTX A2000" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2571, .vram = "GDDR6", .arch = "GA106", .name = "RTX A2000" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2232, .vram = "GDDR6", .arch = "GA102", .name = "RTX A4500" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2231, .vram = "GDDR6", .arch = "GA102", .name = "RTX A5000" },
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{ .offset = 0x0000E2A8, .dev_id = 0x26B1, .vram = "GDDR6", .arch = "AD102", .name = "RTX A6000" },
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{ .offset = 0x0000E2A8, .dev_id = 0x27b8, .vram = "GDDR6", .arch = "AD104", .name = "L4" },
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{ .offset = 0x0000E2A8, .dev_id = 0x26b9, .vram = "GDDR6", .arch = "AD102", .name = "L40S" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2236, .vram = "GDDR6", .arch = "GA102", .name = "A10" },
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};
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void gddr6_init(void)
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{
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ctx.fd = open("/dev/mem", O_RDONLY);
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if (ctx.fd == -1) {
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PRINT_ERROR();
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}
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}
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int gddr6_detect_compatible_gpus(void)
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{
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ctx.devices = NULL;
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ctx.num_devices = 0;
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struct pci_access *pacc = NULL;
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struct pci_dev *pci_dev = NULL;
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ssize_t dev_table_size = (sizeof(dev_table)/sizeof(struct device));
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pacc = pci_alloc();
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pci_init(pacc);
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pci_scan_bus(pacc);
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for (pci_dev = pacc->devices; pci_dev != NULL; pci_dev = pci_dev->next)
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{
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pci_fill_info(pci_dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
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for (uint32_t i = 0; i < dev_table_size; ++i)
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{
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if (pci_dev->device_id == dev_table[i].dev_id)
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{
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struct device *new_devices = realloc(ctx.devices, (ctx.num_devices + 1) * sizeof(struct device));
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if (new_devices == NULL)
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{
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fprintf(stderr, "Memory allocation failed\n");
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pci_cleanup(pacc);
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free(ctx.devices);
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ctx.devices = NULL;
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return 0;
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}
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ctx.devices = new_devices;
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ctx.devices[ctx.num_devices] = dev_table[i];
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ctx.devices[ctx.num_devices].bar0 = (pci_dev->base_addr[0] & 0xffffffff);
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ctx.devices[ctx.num_devices].bus = pci_dev->bus;
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ctx.devices[ctx.num_devices].dev = pci_dev->dev;
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ctx.devices[ctx.num_devices].func = pci_dev->func;
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ctx.num_devices++;
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}
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}
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}
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pci_cleanup(pacc);
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return ctx.num_devices;
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}
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void gddr6_memory_map(void)
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{
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for (uint32_t i = 0; i < ctx.num_devices; i++)
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{
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ctx.devices[i].phys_addr = (ctx.devices[i].bar0 + ctx.devices[i].offset);
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ctx.devices[i].base_offset = ctx.devices[i].phys_addr & ~(PG_SZ - 1);
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ctx.devices[i].mapped_addr = mmap(0, PG_SZ, PROT_READ, MAP_SHARED, ctx.fd, ctx.devices[i].base_offset);
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if (ctx.devices[i].mapped_addr == MAP_FAILED)
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{
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ctx.devices[i].mapped_addr = NULL;
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fprintf(stderr, "Memory mapping failed for pci=%x:%x:%x\n", ctx.devices[i].bus, ctx.devices[i].dev, ctx.devices[i].func);
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fprintf(stderr, "Did you enable iomem=relaxed? Are you r00t?\n");
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exit(EXIT_FAILURE);
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} else {
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printf("Device: %s %s (%s / 0x%04x) pci=%x:%x:%x\n", ctx.devices[i].name, ctx.devices[i].vram,
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ctx.devices[i].arch, ctx.devices[i].dev_id, ctx.devices[i].bus, ctx.devices[i].dev, ctx.devices[i].func);
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}
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}
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}
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void gddr6_monitor_temperatures(void)
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{
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while (1) {
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printf("\rVRAM Temps: |");
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for (uint32_t i = 0; i < ctx.num_devices; i++)
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{
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if (ctx.devices[i].mapped_addr == NULL || ctx.devices[i].mapped_addr == MAP_FAILED)
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{
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continue;
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}
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void *virt_addr = (uint8_t *) ctx.devices[i].mapped_addr + (ctx.devices[i].phys_addr - ctx.devices[i].base_offset);
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uint32_t read_result = *((uint32_t *)virt_addr);
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uint32_t temp = ((read_result & 0x00000fff) / 0x20);
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printf(" %3u°C |", temp);
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}
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fflush(stdout);
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sleep(1);
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}
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}
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void gddr6_cleanup(int signal)
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{
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for (uint32_t i = 0; i < ctx.num_devices; i++)
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{
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if (ctx.devices[i].mapped_addr != NULL && ctx.devices[i].mapped_addr != MAP_FAILED)
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{
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munmap(ctx.devices[i].mapped_addr, PG_SZ);
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ctx.devices[i].mapped_addr = NULL;
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}
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}
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if (ctx.fd != -1)
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{
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close(ctx.fd);
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ctx.fd = -1;
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}
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if (ctx.devices)
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{
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free(ctx.devices);
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ctx.devices = NULL;
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}
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exit(signal);
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}
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