69 lines
3.6 KiB
C
69 lines
3.6 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
|
|
*
|
|
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
|
|
* information contained herein is proprietary and confidential to NVIDIA
|
|
* Corporation. Any use, reproduction, or disclosure without the written
|
|
* permission of NVIDIA Corporation is prohibited.
|
|
*
|
|
* _NVRM_COPYRIGHT_END_
|
|
*/
|
|
|
|
/* This file is autogenerated by ref2h.pl. Do not edit */
|
|
/************************************************************************|
|
|
|* *|
|
|
|* Copyright (c) 2019 by NVIDIA Corp. All rights reserved. *|
|
|
|* *|
|
|
|* This material constitutes the trade secrets and confidential, *|
|
|
|* proprietary information of NVIDIA, Corp. This material is not to be *|
|
|
|* disclosed, reproduced, copied, or used in any manner not permitted *|
|
|
|* under license from NVIDIA, Corp. *|
|
|
|* *|
|
|
|************************************************************************/
|
|
|
|
#ifndef NV_RISCV_ADDRESS_MAP_H_
|
|
#define NV_RISCV_ADDRESS_MAP_H_
|
|
|
|
#define NV_RISCV_AMAP_IROM_START 0x0000000000080000ull
|
|
#define NV_RISCV_AMAP_IROM_SIZE 0x0000000000080000ull
|
|
#define NV_RISCV_AMAP_IROM_END 0x0000000000100000ull
|
|
#define NV_RISCV_AMAP_IMEM_START 0x0000000000100000ull
|
|
#define NV_RISCV_AMAP_IMEM_SIZE 0x0000000000080000ull
|
|
#define NV_RISCV_AMAP_IMEM_END 0x0000000000180000ull
|
|
#define NV_RISCV_AMAP_DMEM_START 0x0000000000180000ull
|
|
#define NV_RISCV_AMAP_DMEM_SIZE 0x0000000000080000ull
|
|
#define NV_RISCV_AMAP_DMEM_END 0x0000000000200000ull
|
|
#define NV_RISCV_AMAP_EMEM_START 0x0000000001200000ull
|
|
#define NV_RISCV_AMAP_EMEM_SIZE 0x0000000000080000ull
|
|
#define NV_RISCV_AMAP_EMEM_END 0x0000000001280000ull
|
|
#define NV_RISCV_AMAP_INTIO_START 0x0000000001280000ull
|
|
#define NV_RISCV_AMAP_INTIO_SIZE 0x0000000000080000ull
|
|
#define NV_RISCV_AMAP_INTIO_END 0x0000000001300000ull
|
|
#define NV_RISCV_AMAP_EXTIO1_START 0x2000000000000000ull
|
|
#define NV_RISCV_AMAP_EXTIO1_SIZE 0x0000000004000000ull
|
|
#define NV_RISCV_AMAP_EXTIO1_END 0x2000000004000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM1_START 0x6060000000000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM1_SIZE 0x0020000000000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM1_END 0x6080000000000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM2_START 0x8060000000000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM2_SIZE 0x0020000000000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM2_END 0x8080000000000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM3_START 0xA000000000000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM3_SIZE 0x0002000000000000ull
|
|
#define NV_RISCV_AMAP_EXTMEM3_END 0xA002000000000000ull
|
|
|
|
/**** dGPU naming alias ****/
|
|
#define NV_RISCV_AMAP_PRIV_START NV_RISCV_AMAP_EXTIO1_START
|
|
#define NV_RISCV_AMAP_PRIV_SIZE NV_RISCV_AMAP_EXTIO1_SIZE
|
|
#define NV_RISCV_AMAP_PRIV_END NV_RISCV_AMAP_EXTIO1_END
|
|
#define NV_RISCV_AMAP_FBGPA_START NV_RISCV_AMAP_EXTMEM1_START
|
|
#define NV_RISCV_AMAP_FBGPA_SIZE NV_RISCV_AMAP_EXTMEM1_SIZE
|
|
#define NV_RISCV_AMAP_FBGPA_END NV_RISCV_AMAP_EXTMEM1_END
|
|
#define NV_RISCV_AMAP_SYSGPA_START NV_RISCV_AMAP_EXTMEM2_START
|
|
#define NV_RISCV_AMAP_SYSGPA_SIZE NV_RISCV_AMAP_EXTMEM2_SIZE
|
|
#define NV_RISCV_AMAP_SYSGPA_END NV_RISCV_AMAP_EXTMEM2_END
|
|
#define NV_RISCV_AMAP_GVA_START NV_RISCV_AMAP_EXTMEM3_START
|
|
#define NV_RISCV_AMAP_GVA_SIZE NV_RISCV_AMAP_EXTMEM3_SIZE
|
|
#define NV_RISCV_AMAP_GVA_END NV_RISCV_AMAP_EXTMEM3_END
|
|
|
|
#endif
|