6907 lines
689 KiB
C
6907 lines
689 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
|
|
*
|
|
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
|
|
* information contained herein is proprietary and confidential to NVIDIA
|
|
* Corporation. Any use, reproduction, or disclosure without the written
|
|
* permission of NVIDIA Corporation is prohibited.
|
|
*
|
|
* _NVRM_COPYRIGHT_END_
|
|
*/
|
|
|
|
#ifndef __ga102_dev_therm_h__
|
|
#define __ga102_dev_therm_h__
|
|
/* This file is autogenerated. Do not edit */
|
|
#define NV_THERM 0x020fff:0x020000 /* RW--D */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW 0x00020320 /* RW-4R */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION__FUSE_SIGNAL "therm_thermal_low" /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0 0x00020324 /* RW-4R */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION__FUSE_SIGNAL "therm_thermal_med_high_0" /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1 0x00020328 /* RW-4R */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION__FUSE_SIGNAL "therm_thermal_med_high_1" /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK 0x0002032c /* RW-4R */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_vidctrl" /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0 0x00020380 /* RW-4R */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION__FUSE_SIGNAL "therm_smartfan_0" /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1 0x00020384 /* RW-4R */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION__FUSE_SIGNAL "therm_smartfan_1" /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK 0x00020388 /* RW-4R */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_fantach" /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK 0x0002038c /* RW-4R */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_i2cslave" /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK 0x00020390 /* RW-4R */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_intrupt" /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK 0x00020398 /* RW-4R */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_pp" /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_PP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0 0x0002039c /* RW-4R */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION__FUSE_SIGNAL "therm_pwrgate_0" /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1 0x000203a0 /* RW-4R */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION__FUSE_SIGNAL "therm_pwrgate_1" /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0 0x000203a8 /* RW-4R */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION__FUSE_SIGNAL "therm_slowdown_0" /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1 0x000203b0 /* RW-4R */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION__FUSE_SIGNAL "therm_slowdown_1" /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK 0x000203b4 /* RW-4R */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "adcs" /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK 0x000206c0 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "tsense" /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK 0x00020880 /* RW-4R */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_dlppe" /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_EVENT_LATCH 0x000207e0 /* RW-4R */
|
|
#define NV_THERM_EVENT_LATCH__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVENT_LATCH_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_EXT_OVERT_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_OVERT_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_OVERT_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_EXT_POWER_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_POWER_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_POWER_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_0_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_0_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_0_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_1_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_2_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_2_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_2_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_3_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_3_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_3_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_4_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_4_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_4_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_5_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_5_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_5_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_6_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_6_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_6_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_7_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_7_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_7_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_8_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_8_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_8_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_9_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_9_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_9_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_10_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_10_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_10_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_11_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_11_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_THERMAL_11_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_0_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_0_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_0_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_1_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_EXT_ALERT_1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_BA_W0_T1_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W0_T1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W0_T1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_BA_W0_T2_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W0_T2_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W0_T2_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_BA_W1_T1_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W1_T1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W1_T1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_BA_W1_T2_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W1_T2_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W1_T2_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_BA_W2_T1_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W2_T1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W2_T1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_BA_W2_T2_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W2_T2_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_BA_W2_T2_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_VOLTAGE_HW_ADC_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_VOLTAGE_HW_ADC_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_VOLTAGE_HW_ADC_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_EDPP_VMIN_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_EDPP_VMIN_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_EDPP_VMIN_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_EVENT_LATCH_EDPP_FONLY_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_LATCH_EDPP_FONLY_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_LATCH_EDPP_FONLY_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_LATCH_STATE(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_LATCH_STATE__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_LATCH_STATE_NORMAL 0x00000000 /* */
|
|
#define NV_THERM_EVENT_LATCH_STATE_TRIGGERED 0x00000001 /* */
|
|
#define NV_THERM_EVENT_LATCH_STATE_CLEAR 0x00000001 /* */
|
|
#define NV_THERM_EVENT_SELECT 0x000207e4 /* RW-4R */
|
|
#define NV_THERM_EVENT_SELECT__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVENT_SELECT_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_EXT_OVERT_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_OVERT_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_EXT_POWER_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_POWER_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_0_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_0_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_1_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_1_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_2_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_2_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_3_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_3_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_4_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_4_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_5_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_5_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_6_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_6_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_7_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_7_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_8_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_8_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_9_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_9_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_10_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_10_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_11_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_THERMAL_11_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT_0_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT_0_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT_1_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_EXT_ALERT_1_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_BA_W0_T1_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W0_T1_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_BA_W0_T2_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W0_T2_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_BA_W1_T1_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W1_T1_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_BA_W1_T2_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W1_T2_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_BA_W2_T1_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W2_T1_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_BA_W2_T2_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_BA_W2_T2_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_VOLTAGE_HW_ADC_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_VOLTAGE_HW_ADC_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_EDPP_VMIN_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_EDPP_VMIN_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_EVENT_SELECT_EDPP_FONLY_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_SELECT_EDPP_FONLY_LATCH 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_SELECT_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_SELECT_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_SELECT_CTRL_NORMAL 0x00000000 /* */
|
|
#define NV_THERM_EVENT_SELECT_CTRL_LATCH 0x00000001 /* */
|
|
#define NV_THERM_EVENT_TRIGGER 0x00020780 /* R--4R */
|
|
#define NV_THERM_EVENT_TRIGGER__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_OVERT 0:0 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_OVERT_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_OVERT_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT 1:1 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_POWER 2:2 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_POWER_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_POWER_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_0 3:3 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_0_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_0_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_1 4:4 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_1_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_2 5:5 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_2_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_2_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_3 6:6 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_3_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_3_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_4 7:7 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_4_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_4_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_5 8:8 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_5_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_5_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_6 9:9 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_6_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_6_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_7 10:10 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_7_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_7_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_8 11:11 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_8_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_8_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_9 12:12 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_9_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_9_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_10 13:13 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_10_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_10_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_11 14:14 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_11_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_THERMAL_11_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT_0 15:15 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT_0_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT_0_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT_1 16:16 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT_1_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EXT_ALERT_1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W0_T1 20:20 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W0_T1_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W0_T1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W0_T2 21:21 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W0_T2_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W0_T2_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W1_T1 22:22 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W1_T1_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W1_T1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W1_T2 23:23 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W1_T2_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W1_T2_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W2_T1 24:24 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W2_T1_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W2_T1_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W2_T2 25:25 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W2_T2_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_BA_W2_T2_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_VOLTAGE_HW_ADC 28:28 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_VOLTAGE_HW_ADC_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_VOLTAGE_HW_ADC_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EDPP_VMIN 29:29 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_EDPP_VMIN_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EDPP_VMIN_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EDPP_FONLY 30:30 /* R--VF */
|
|
#define NV_THERM_EVENT_TRIGGER_EDPP_FONLY_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_EDPP_FONLY_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_TRIGGER_STATE(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_TRIGGER_STATE__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_TRIGGER_STATE_NORMAL 0x00000000 /* */
|
|
#define NV_THERM_EVENT_TRIGGER_STATE_TRIGGERED 0x00000001 /* */
|
|
#define NV_THERM_EVENT_INTR_TYPE 0x000207e8 /* RW-4R */
|
|
#define NV_THERM_EVENT_INTR_TYPE__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_OVERT_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_OVERT_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_POWER_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_POWER_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_0_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_0_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_1_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_1_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_2_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_2_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_3_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_3_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_4_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_4_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_5_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_5_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_6_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_6_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_7_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_7_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_8_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_8_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_9_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_9_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_10_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_10_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_11_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_THERMAL_11_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT_0_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT_0_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT_1_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EXT_ALERT_1_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W0_T1_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W0_T1_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W0_T2_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W0_T2_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W1_T1_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W1_T1_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W1_T2_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W1_T2_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W2_T1_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W2_T1_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W2_T2_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_BA_W2_T2_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_VOLTAGE_HW_ADC_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_VOLTAGE_HW_ADC_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EDPP_VMIN_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EDPP_VMIN_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EDPP_FONLY_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_EDPP_FONLY_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_TYPE_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_INTR_TYPE_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_INTR_TYPE_CTRL_EDGE 0x00000000 /* */
|
|
#define NV_THERM_EVENT_INTR_TYPE_CTRL_LEVEL 0x00000001 /* */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED 0x00020784 /* RW-4R */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_OVERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_OVERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_POWER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_POWER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_3_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_3_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_4_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_4_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_5_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_5_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_6_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_6_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_7_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_7_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_8_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_8_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_9_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_9_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_10_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_10_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_11_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_11_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_CTRL_DISABLED 0x00000000 /* */
|
|
#define NV_THERM_EVENT_INTR_ON_TRIGGERED_CTRL_ENABLED 0x00000001 /* */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL 0x00020788 /* RW-4R */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_OVERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_OVERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_POWER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_POWER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_3_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_3_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_4_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_4_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_5_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_5_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_6_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_6_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_7_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_7_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_8_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_8_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_9_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_9_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_10_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_10_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_11_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_THERMAL_11_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_CTRL_DISABLED 0x00000000 /* */
|
|
#define NV_THERM_EVENT_INTR_ON_NORMAL_CTRL_ENABLED 0x00000001 /* */
|
|
#define NV_THERM_EVENT_INTR_PENDING 0x0002078c /* RW-4R */
|
|
#define NV_THERM_EVENT_INTR_PENDING__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_OVERT_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_OVERT_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_OVERT_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_POWER_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_POWER_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_POWER_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_0_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_0_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_0_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_1_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_1_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_2_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_2_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_2_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_3_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_3_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_3_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_4_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_4_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_4_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_5_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_5_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_5_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_6_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_6_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_6_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_7_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_7_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_7_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_8_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_8_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_8_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_9_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_9_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_9_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_10_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_10_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_10_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_11_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_11_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_THERMAL_11_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_0_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_0_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_0_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_1_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_1_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EXT_ALERT_1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W0_T1_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W0_T1_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W0_T1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W0_T2_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W0_T2_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W0_T2_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W1_T1_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W1_T1_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W1_T1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W1_T2_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W1_T2_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W1_T2_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W2_T1_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W2_T1_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W2_T1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W2_T2_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W2_T2_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_BA_W2_T2_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_VOLTAGE_HW_ADC_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_VOLTAGE_HW_ADC_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_VOLTAGE_HW_ADC_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EDPP_VMIN_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EDPP_VMIN_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EDPP_VMIN_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EDPP_FONLY_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EDPP_FONLY_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_EVENT_INTR_PENDING_EDPP_FONLY_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_EVENT_INTR_PENDING_STATE(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_INTR_PENDING_STATE__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_INTR_PENDING_STATE_NO 0x00000000 /* */
|
|
#define NV_THERM_EVENT_INTR_PENDING_STATE_YES 0x00000001 /* */
|
|
#define NV_THERM_EVENT_INTR_PENDING_STATE_CLEAR 0x00000001 /* */
|
|
#define NV_THERM_EVENT_INTR_ENABLE 0x00020790 /* RW-4R */
|
|
#define NV_THERM_EVENT_INTR_ENABLE__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_OVERT_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_OVERT_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_POWER_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_POWER_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_0_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_0_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_2_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_2_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_3_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_3_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_4_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_4_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_5_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_5_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_6_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_6_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_7_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_7_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_8_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_8_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_9_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_9_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_10_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_10_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_11_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_THERMAL_11_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT_0_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT_0_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT_1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EXT_ALERT_1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W0_T1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W0_T1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W0_T2_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W0_T2_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W1_T1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W1_T1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W1_T2_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W1_T2_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W2_T1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W2_T1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W2_T2_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_BA_W2_T2_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_VOLTAGE_HW_ADC_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_VOLTAGE_HW_ADC_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EDPP_VMIN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EDPP_VMIN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EDPP_FONLY_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_EDPP_FONLY_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_CTRL_NO 0x00000000 /* */
|
|
#define NV_THERM_EVENT_INTR_ENABLE_CTRL_YES 0x00000001 /* */
|
|
#define NV_THERM_EVENT_INTR_ROUTE 0x00020794 /* RW-4R */
|
|
#define NV_THERM_EVENT_INTR_ROUTE__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_OVERT_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_OVERT_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_POWER_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_POWER_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_0_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_0_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_1_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_1_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_2_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_2_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_3_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_3_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_4_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_4_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_5_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_5_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_6_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_6_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_7_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_7_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_8_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_8_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_9_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_9_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_10_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_10_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_11_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_THERMAL_11_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT_0_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT_0_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT_1_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EXT_ALERT_1_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W0_T1_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W0_T1_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W0_T2_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W0_T2_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W1_T1_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W1_T1_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W1_T2_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W1_T2_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W2_T1_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W2_T1_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W2_T2_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_BA_W2_T2_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_VOLTAGE_HW_ADC_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_VOLTAGE_HW_ADC_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EDPP_VMIN_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EDPP_VMIN_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EDPP_FONLY_TO_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_EDPP_FONLY_TO_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_CTRL_TO_HOST 0x00000000 /* */
|
|
#define NV_THERM_EVENT_INTR_ROUTE_CTRL_TO_PMU 0x00000001 /* */
|
|
#define NV_THERM_USE_A 0x00020798 /* RW-4R */
|
|
#define NV_THERM_USE_A__PRIV_LEVEL_MASK 0x000203b0 /* */
|
|
#define NV_THERM_USE_A_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_USE_A_EXT_OVERT_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_EXT_OVERT_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_USE_A_EXT_ALERT_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_EXT_ALERT_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_USE_A_EXT_POWER_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_EXT_POWER_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_0_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_0_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_2_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_2_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_3_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_3_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_4_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_4_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_5_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_5_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_6_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_6_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_7_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_7_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_8_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_8_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_9_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_9_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_10_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_10_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_USE_A_THERMAL_11_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_THERMAL_11_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_USE_A_EXT_ALERT_0_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_EXT_ALERT_0_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_USE_A_EXT_ALERT_1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_EXT_ALERT_1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_USE_A_BA_W0_T1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_BA_W0_T1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_USE_A_BA_W0_T2_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_BA_W0_T2_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_USE_A_BA_W1_T1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_BA_W1_T1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_USE_A_BA_W1_T2_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_BA_W1_T2_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_USE_A_BA_W2_T1_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_BA_W2_T1_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_USE_A_BA_W2_T2_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_BA_W2_T2_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_USE_A_VOLTAGE_HW_ADC_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_VOLTAGE_HW_ADC_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_USE_A_EDPP_VMIN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_EDPP_VMIN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_USE_A_EDPP_FONLY_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_A_EDPP_FONLY_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_A_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_USE_A_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_USE_A_CTRL_NO 0x00000000 /* */
|
|
#define NV_THERM_USE_A_CTRL_YES 0x00000001 /* */
|
|
#define NV_THERM_USE_B 0x0002079c /* RW-4R */
|
|
#define NV_THERM_USE_B__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_USE_B_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_USE_B_EXT_OVERT_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_EXT_OVERT_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_USE_B_EXT_ALERT_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_EXT_ALERT_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_USE_B_EXT_POWER_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_EXT_POWER_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_0_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_0_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_1_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_1_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_2_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_2_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_3_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_3_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_4_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_4_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_5_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_5_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_6_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_6_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_7_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_7_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_8_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_8_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_9_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_9_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_10_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_10_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_USE_B_THERMAL_11_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_THERMAL_11_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_USE_B_EXT_ALERT_0_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_EXT_ALERT_0_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_USE_B_EXT_ALERT_1_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_EXT_ALERT_1_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_USE_B_BA_W0_T1_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_BA_W0_T1_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_USE_B_BA_W0_T2_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_BA_W0_T2_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_USE_B_BA_W1_T1_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_BA_W1_T1_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_USE_B_BA_W1_T2_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_BA_W1_T2_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_USE_B_BA_W2_T1_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_BA_W2_T1_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_USE_B_BA_W2_T2_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_USE_B_BA_W2_T2_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_USE_B_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_USE_B_VOLTAGE_HW_ADC_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_B_VOLTAGE_HW_ADC_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_B_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_USE_B_EDPP_VMIN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_B_EDPP_VMIN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_B_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_USE_B_EDPP_FONLY_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_USE_B_EDPP_FONLY_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_USE_B_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_USE_B_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_USE_B_CTRL_NO 0x00000000 /* */
|
|
#define NV_THERM_USE_B_CTRL_YES 0x00000001 /* */
|
|
#define NV_THERM_EVT_EXT_OVERT 0x00020700 /* RW-4R */
|
|
#define NV_THERM_EVT_EXT_OVERT__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_EXT_OVERT_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_OVERT_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_OVERT_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_OVERT_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_OVERT_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_OVERT_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_OVERT_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_OVERT_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT 0x00020704 /* RW-4R */
|
|
#define NV_THERM_EVT_EXT_ALERT__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_EXT_ALERT_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_ALERT_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_ALERT_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_ALERT_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_ALERT_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_POWER 0x00020708 /* RW-4R */
|
|
#define NV_THERM_EVT_EXT_POWER__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_EXT_POWER_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_POWER_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_POWER_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_POWER_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_POWER_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_POWER_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_POWER_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_POWER_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0 0x0002070c /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_0__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_0_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_0_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_0_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_0_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_0_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_0_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_0_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1 0x00020710 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_1__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_1_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_1_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_1_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_1_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_1_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_1_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2 0x00020714 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_2__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_2_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_2_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_2_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_2_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_2_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_2_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_2_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3 0x00020718 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_3__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_3_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_3_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_3_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_3_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_3_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_3_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_3_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4 0x0002071c /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_4__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_4_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_4_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_4_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_4_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_4_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_4_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_4_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5 0x00020720 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_5__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_5_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_5_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_5_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_5_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_5_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_5_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_5_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6 0x00020724 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_6__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_6_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_6_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_6_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_6_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_6_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_6_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_6_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7 0x00020728 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_7__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_7_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_7_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_7_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_7_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_7_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_7_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_7_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8 0x0002072c /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_8__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_8_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_8_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_8_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_8_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_8_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_8_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_8_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9 0x00020730 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_9__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_9_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_9_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_9_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_9_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_9_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_9_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_9_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10 0x00020734 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_10__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_10_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_10_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_10_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_10_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_10_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_10_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_10_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11 0x00020738 /* RW-4R */
|
|
#define NV_THERM_EVT_THERMAL_11__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID 23:20 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_11_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_11_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_11_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_11_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_THERMAL_11_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_THERMAL_11_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_THERMAL_11_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_0 0x0002073c /* RW-4R */
|
|
#define NV_THERM_EVT_EXT_ALERT_0__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_EXT_ALERT_0_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_ALERT_0_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_0_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_ALERT_0_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_ALERT_0_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_ALERT_0_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_0_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_0_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_1 0x00020740 /* RW-4R */
|
|
#define NV_THERM_EVT_EXT_ALERT_1__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_EXT_ALERT_1_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_ALERT_1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_ALERT_1_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_EXT_ALERT_1_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EXT_ALERT_1_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_1_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_EXT_ALERT_1_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W0_T1 0x00020750 /* RW-4R */
|
|
#define NV_THERM_EVT_BA_W0_T1__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_BA_W0_T1_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W0_T1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W0_T1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W0_T1_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W0_T1_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W0_T1_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W0_T1_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W0_T1_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W0_T2 0x00020754 /* RW-4R */
|
|
#define NV_THERM_EVT_BA_W0_T2__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_BA_W0_T2_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W0_T2_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W0_T2_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W0_T2_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W0_T2_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W0_T2_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W0_T2_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W0_T2_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W1_T1 0x00020758 /* RW-4R */
|
|
#define NV_THERM_EVT_BA_W1_T1__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_BA_W1_T1_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W1_T1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W1_T1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W1_T1_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W1_T1_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W1_T1_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W1_T1_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W1_T1_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W1_T2 0x0002075c /* RW-4R */
|
|
#define NV_THERM_EVT_BA_W1_T2__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_BA_W1_T2_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W1_T2_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W1_T2_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W1_T2_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W1_T2_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W1_T2_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W1_T2_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W1_T2_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W2_T1 0x00020760 /* RW-4R */
|
|
#define NV_THERM_EVT_BA_W2_T1__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_BA_W2_T1_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W2_T1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W2_T1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W2_T1_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W2_T1_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W2_T1_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W2_T1_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W2_T1_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W2_T2 0x00020764 /* RW-4R */
|
|
#define NV_THERM_EVT_BA_W2_T2__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_BA_W2_T2_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W2_T2_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W2_T2_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W2_T2_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_BA_W2_T2_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_BA_W2_T2_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W2_T2_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_BA_W2_T2_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC 0x00020770 /* RW-4R */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_VOLTAGE_HW_ADC_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_EDPP_VMIN 0x00020774 /* RW-4R */
|
|
#define NV_THERM_EVT_EDPP_VMIN__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_EDPP_VMIN_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_EDPP_VMIN_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_EDPP_VMIN_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EDPP_VMIN_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_EDPP_VMIN_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EDPP_VMIN_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_EDPP_VMIN_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_EDPP_VMIN_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_EDPP_FONLY 0x00020778 /* RW-4R */
|
|
#define NV_THERM_EVT_EDPP_FONLY__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_EVT_EDPP_FONLY_SLOW_FACTOR 29:24 /* RWIUF */
|
|
#define NV_THERM_EVT_EDPP_FONLY_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_EDPP_FONLY_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EDPP_FONLY_MODE 31:30 /* RWIUF */
|
|
#define NV_THERM_EVT_EDPP_FONLY_MODE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_EVT_EDPP_FONLY_MODE_INVERTED 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_EDPP_FONLY_MODE_FORCED 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_EDPP_FONLY_MODE_CLEARED 0x00000003 /* RW--V */
|
|
#define NV_THERM_OVERT_EN 0x000204a8 /* RW-4R */
|
|
#define NV_THERM_OVERT_EN__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_OVERT_EN_EXT_OVERT 0:0 /* C--VF */
|
|
#define NV_THERM_OVERT_EN_EXT_OVERT_DISABLED 0x00000000 /* C---V */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_EXT_POWER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_EXT_POWER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_3_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_3_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_4_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_4_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_5_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_5_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_6_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_6_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_7_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_7_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_8_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_8_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_9_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_9_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_10_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_10_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_THERMAL_11_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_THERMAL_11_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_BA_W0_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_BA_W0_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_BA_W1_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_BA_W1_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_BA_W2_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_BA_W2_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_OVERT_EN_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_EN_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_EN_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_OVERT_EN_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_OVERT_EN_CTRL_DISABLED 0x00000000 /* */
|
|
#define NV_THERM_OVERT_EN_CTRL_ENABLED 0x00000001 /* */
|
|
#define NV_THERM_ALERT_EN 0x000204ac /* RW-4R */
|
|
#define NV_THERM_ALERT_EN__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_ALERT_EN_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_EXT_OVERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_EXT_OVERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_EXT_POWER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_EXT_POWER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_3_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_3_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_4_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_4_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_5_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_5_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_6_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_6_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_7_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_7_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_8_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_8_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_9_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_9_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_10_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_10_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_THERMAL_11_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_THERMAL_11_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_BA_W0_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_BA_W0_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_BA_W1_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_BA_W1_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_BA_W2_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_BA_W2_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_ALERT_EN_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ALERT_EN_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ALERT_EN_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_ALERT_EN_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_ALERT_EN_CTRL_DISABLED 0x00000000 /* */
|
|
#define NV_THERM_ALERT_EN_CTRL_ENABLED 0x00000001 /* */
|
|
#define NV_THERM_MAXFAN_EN 0x000204b0 /* RW-4R */
|
|
#define NV_THERM_MAXFAN_EN__PRIV_LEVEL_MASK 0x00020380 /* */
|
|
#define NV_THERM_MAXFAN_EN_EXT_OVERT 0:0 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_EXT_OVERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_OVERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT 1:1 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_POWER 2:2 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_EXT_POWER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_POWER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_0 3:3 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_1 4:4 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_2 5:5 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_3 6:6 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_3_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_3_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_4 7:7 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_4_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_4_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_5 8:8 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_5_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_5_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_6 9:9 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_6_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_6_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_7 10:10 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_7_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_7_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_8 11:11 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_8_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_8_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_9 12:12 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_9_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_9_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_10 13:13 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_10_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_10_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_11 14:14 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_11_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_THERMAL_11_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT_0 15:15 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT_1 16:16 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W0_T1 20:20 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W0_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W0_T2 21:21 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W0_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W1_T1 22:22 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W1_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W1_T2 23:23 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W1_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W2_T1 24:24 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W2_T1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W2_T2 25:25 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_BA_W2_T2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_VOLTAGE_HW_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_EDPP_VMIN 29:29 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_EDPP_FONLY 30:30 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_EN_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MAXFAN_EN_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_MAXFAN_EN_CTRL(i) (i):(i) /* */
|
|
#define NV_THERM_MAXFAN_EN_CTRL__SIZE_1 32 /* */
|
|
#define NV_THERM_MAXFAN_EN_CTRL_DISABLED 0x00000000 /* */
|
|
#define NV_THERM_MAXFAN_EN_CTRL_ENABLED 0x00000001 /* */
|
|
#define NV_THERM_MAXFAN 0x000204b4 /* RW-4R */
|
|
#define NV_THERM_MAXFAN__PRIV_LEVEL_MASK 0x00020380 /* */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_THERM 0:0 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_THERM_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_THERM_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_THERM_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_SCI_0 1:1 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_SCI_0_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_SCI_0_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_SCI_0_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_SCI_1 2:2 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_SCI_1_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_SCI_1_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_MAXFAN_STATUS_SMARTFAN_SCI_1_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_MAXFAN_FORCE 31:31 /* RWIVF */
|
|
#define NV_THERM_MAXFAN_FORCE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_MAXFAN_FORCE_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_MAXFAN_FORCE_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_CTRL_2 0x00020108 /* RW-4R */
|
|
#define NV_THERM_CTRL_2__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT 13:12 /* RWIVF */
|
|
#define NV_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT_RISING 0x00000001 /* RW--V */
|
|
#define NV_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT_FALLING 0x00000002 /* RW--V */
|
|
#define NV_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT_BOTH 0x00000003 /* RW--V */
|
|
#define NV_THERM_CTRL_2_CLK_SLOWDOWN 22:22 /* R--VF */
|
|
#define NV_THERM_CTRL_2_CLK_SLOWDOWN_NORMAL 0x00000000 /* R---V */
|
|
#define NV_THERM_CTRL_2_CLK_SLOWDOWN_TRIGGERED 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0 0x00020100 /* RW-4R */
|
|
#define NV_THERM_INTR_0__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_INTR_0_FMON_ERROR_INTR 2:2 /* RWIVF */
|
|
#define NV_THERM_INTR_0_FMON_ERROR_INTR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_FMON_ERROR_INTR_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_FMON_ERROR_INTR_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_I2C_SCRATCH_INTR_STATE 4:4 /* RWIVF */
|
|
#define NV_THERM_INTR_0_I2C_SCRATCH_INTR_STATE_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_I2C_SCRATCH_INTR_STATE_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_I2C_SCRATCH_INTR_STATE_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_ISENSE_BEACON1_INTR 5:5 /* RWIVF */
|
|
#define NV_THERM_INTR_0_ISENSE_BEACON1_INTR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_ISENSE_BEACON1_INTR_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_ISENSE_BEACON1_INTR_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_ISENSE_BEACON2_INTR 6:6 /* RWIVF */
|
|
#define NV_THERM_INTR_0_ISENSE_BEACON2_INTR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_ISENSE_BEACON2_INTR_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_ISENSE_BEACON2_INTR_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_DLPPE_INTR 7:7 /* RWIVF */
|
|
#define NV_THERM_INTR_0_DLPPE_INTR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_DLPPE_INTR_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_DLPPE_INTR_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_PEAKPOWER 8:8 /* RWIVF */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_PEAKPOWER_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_PEAKPOWER_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_PEAKPOWER_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_CLK_SLOWDOWN 15:15 /* RWIVF */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_CLK_SLOWDOWN_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_CLK_SLOWDOWN_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_CLK_SLOWDOWN_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_SMBUS_MSGBOX 16:16 /* RWIVF */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_SMBUS_MSGBOX_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_SMBUS_MSGBOX_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_SMBUS_MSGBOX_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_CFG_ERR 18:18 /* RWIVF */
|
|
#define NV_THERM_INTR_0_CFG_ERR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_CFG_ERR_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_CFG_ERR_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_TEMPAVG_OFLOW 24:24 /* RWIVF */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_TEMPAVG_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_TEMPAVG_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_THERMAL_TRIGGER_TEMPAVG_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_SM_PIPELINE_STALLED_ENTRY 28:28 /* RWIVF */
|
|
#define NV_THERM_INTR_0_SM_PIPELINE_STALLED_ENTRY_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_SM_PIPELINE_STALLED_ENTRY_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_SM_PIPELINE_STALLED_ENTRY_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_SM_PIPELINE_STALLED_EXIT 29:29 /* RWIVF */
|
|
#define NV_THERM_INTR_0_SM_PIPELINE_STALLED_EXIT_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_0_SM_PIPELINE_STALLED_EXIT_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_INTR_0_SM_PIPELINE_STALLED_EXIT_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_INTR_0_SPARE 31:31 /* RWIVF */
|
|
#define NV_THERM_INTR_0_SPARE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_EN_0 0x00020134 /* RW-4R */
|
|
#define NV_THERM_INTR_EN_0__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_INTR_EN_0_FMON_ERROR_INTR 2:2 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_FMON_ERROR_INTR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_FMON_ERROR_INTR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_I2C_SCRATCH_INTR_STATE 4:4 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_I2C_SCRATCH_INTR_STATE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_I2C_SCRATCH_INTR_STATE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_ISENSE_BEACON1_INTR 5:5 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_ISENSE_BEACON1_INTR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_ISENSE_BEACON1_INTR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_ISENSE_BEACON2_INTR 6:6 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_ISENSE_BEACON2_INTR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_ISENSE_BEACON2_INTR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_DLPPE_INTR 7:7 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_DLPPE_INTR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_DLPPE_INTR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_PEAKPOWER 8:8 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_PEAKPOWER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_PEAKPOWER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_CLK_SLOWDOWN 15:15 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_CLK_SLOWDOWN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_CLK_SLOWDOWN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_SMBUS_MSGBOX 16:16 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_SMBUS_MSGBOX_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_SMBUS_MSGBOX_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_CFG_ERR 18:18 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_CFG_ERR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_CFG_ERR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_TEMPAVG_OFLOW 24:24 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_TEMPAVG_OFLOW_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_TEMPAVG_OFLOW_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_SM_PIPELINE_STALLED_ENTRY 28:28 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_SM_PIPELINE_STALLED_ENTRY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_SM_PIPELINE_STALLED_ENTRY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_EN_0_SM_PIPELINE_STALLED_EXIT 29:29 /* RWIVF */
|
|
#define NV_THERM_INTR_EN_0_SM_PIPELINE_STALLED_EXIT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_EN_0_SM_PIPELINE_STALLED_EXIT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE 0x000200fc /* RW-4R */
|
|
#define NV_THERM_INTR_ROUTE__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_INTR_ROUTE_FMON_ERROR_INTR 2:2 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_FMON_ERROR_INTR_HOST 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_FMON_ERROR_INTR_PMU 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_I2C_SCRATCH_INTR_STATE 4:4 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_I2C_SCRATCH_INTR_STATE_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_I2C_SCRATCH_INTR_STATE_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_ISENSE_BEACON1_INTR 5:5 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_ISENSE_BEACON1_INTR_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_ISENSE_BEACON1_INTR_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_ISENSE_BEACON2_INTR 6:6 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_ISENSE_BEACON2_INTR_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_ISENSE_BEACON2_INTR_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_DLPPE_INTR 7:7 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_DLPPE_INTR_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_DLPPE_INTR_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_PEAKPOWER 8:8 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_PEAKPOWER_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_PEAKPOWER_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_CLK_SLOWDOWN 15:15 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_CLK_SLOWDOWN_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_CLK_SLOWDOWN_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_SMBUS_MSGBOX 16:16 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_SMBUS_MSGBOX_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_SMBUS_MSGBOX_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_CFG_ERR 18:18 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_CFG_ERR_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_CFG_ERR_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_TEMPAVG_OFLOW 24:24 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_TEMPAVG_OFLOW_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_THERMAL_TRIGGER_TEMPAVG_OFLOW_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_ENTRY 28:28 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_ENTRY_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_ENTRY_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_EXIT 29:29 /* RWIVF */
|
|
#define NV_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_EXIT_HOST 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_EXIT_PMU 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL(i) (0x000207a0+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_INTR_MONITOR_CTRL__SIZE_1 8 /* */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE 5:0 /* RWIVF */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_NONE 0x0000003f /* RWI-V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_OVERT 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_ALERT 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_POWER 0x00000002 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_0 0x00000003 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_1 0x00000004 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_2 0x00000005 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_3 0x00000006 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_4 0x00000007 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_5 0x00000008 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_6 0x00000009 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_7 0x0000000a /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_8 0x0000000b /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_9 0x0000000c /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_10 0x0000000d /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_11 0x0000000e /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_ALERT_0 0x0000000f /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_ALERT_1 0x00000010 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_BEACON1 0x00000011 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_BEACON2 0x00000012 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_VOLTAGE_HW_ADC 0x00000013 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W0_T1 0x00000014 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W0_T2 0x00000015 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W1_T1 0x00000016 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W1_T2 0x00000017 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W2_T1 0x00000018 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W2_T2 0x00000019 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC 0x0000001a /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC0 0x0000001b /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC1 0x0000001c /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC2 0x0000001d /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC3 0x0000001e /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_EDPP_VMIN 0x0000001f /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_EDPP_FONLY 0x00000020 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_TRIGGER_SLOWDOWN 0x00000021 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_TEMPAVG_OFLOW 0x00000022 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_SM_PIPELINE_STALLED 0x00000023 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_DVCO_SLOWPATH_ACTIVE 0x00000024 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_IDLE_SLOWDOWN 0x00000027 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_GR 0x00000028 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_NVENC0 0x00000029 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_NVDEC 0x0000002c /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_NVDEC1 0x00000039 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_SEC 0x0000002d /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE0 0x0000002e /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE1 0x0000002f /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE2 0x00000030 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE3 0x00000031 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE4 0x00000032 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_VR 0x00000034 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_OFA0 0x00000035 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_POLARITY 28:28 /* RWIVF */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_POLARITY_LOW_ACTIVE 0x00000000 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_POLARITY_HIGH_ACTIVE 0x00000001 /* RWI-V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_TYPE 29:29 /* RWIVF */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_TYPE_EDGE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_TYPE_LEVEL 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_CLEAR 30:30 /* RWIVF */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_CLEAR_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_CLEAR_NOT_DONE 0x00000000 /* R---V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_CLEAR_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_EN 31:31 /* RWIVF */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_INTR_MONITOR_CTRL_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_INTR_MONITOR_STATE(i) (0x000207c0+((i)*4)) /* R--4A */
|
|
#define NV_THERM_INTR_MONITOR_STATE__SIZE_1 8 /* */
|
|
#define NV_THERM_INTR_MONITOR_STATE_VALUE 30:0 /* R-IVF */
|
|
#define NV_THERM_INTR_MONITOR_STATE_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_MONITOR_STATE_OVERFLOW 31:31 /* R-IVF */
|
|
#define NV_THERM_INTR_MONITOR_STATE_OVERFLOW_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_INTR_MONITOR_STATE_OVERFLOW_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_CTRL_1 0x00020004 /* RW-4R */
|
|
#define NV_THERM_CTRL_1__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_GPCCLK 24:24 /* RWIVF */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_GPCCLK_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_GPCCLK_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_SYSCLK 25:25 /* RWIVF */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_SYSCLK_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_SYSCLK_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_LTCCLK 27:27 /* RWIVF */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_LTCCLK_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CTRL_1_CLK_SLOWDOWN_INTR_LTCCLK_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_CTRL 0x0002005c /* RW-4R */
|
|
#define NV_THERM_OVERT_CTRL__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_OVERT_CTRL_OUTPUT_DRIVE_MODE 1:0 /* RWIVF */
|
|
#define NV_THERM_OVERT_CTRL_OUTPUT_DRIVE_MODE_FULL 0x00000000 /* RW--V */
|
|
#define NV_THERM_OVERT_CTRL_OUTPUT_DRIVE_MODE_OPEN_DRAIN 0x00000001 /* RWI-V */
|
|
#define NV_THERM_OVERT_CTRL_OUTPUT_DRIVE_MODE_OFF 0x00000002 /* RW--V */
|
|
#define NV_THERM_OVERT_CTRL_INPUT_DRIVE_MODE 2:2 /* RWIVF */
|
|
#define NV_THERM_OVERT_CTRL_INPUT_DRIVE_MODE_OFF 0x00000000 /* RW--V */
|
|
#define NV_THERM_OVERT_CTRL_INPUT_DRIVE_MODE_ON 0x00000001 /* RWI-V */
|
|
#define NV_THERM_OVERT_CTRL_PAD_INPUT_RCV 3:3 /* RWIVF */
|
|
#define NV_THERM_OVERT_CTRL_PAD_INPUT_RCV_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_OVERT_CTRL_PAD_INPUT_RCV_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_OVERT_CTRL_POLARITY 8:8 /* RWIVF */
|
|
#define NV_THERM_OVERT_CTRL_POLARITY_ACTIVE_HIGH 0x00000000 /* RW--V */
|
|
#define NV_THERM_OVERT_CTRL_POLARITY_ACTIVE_LOW 0x00000001 /* RWI-V */
|
|
#define NV_THERM_OVERT_CTRL_INT_OVERT_ASSERTED 15:15 /* R--VF */
|
|
#define NV_THERM_OVERT_CTRL_INT_OVERT_ASSERTED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_OVERT_CTRL_INT_OVERT_ASSERTED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_OVERT_CTRL_EXT_OVERT_ASSERTED 16:16 /* R--VF */
|
|
#define NV_THERM_OVERT_CTRL_EXT_OVERT_ASSERTED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_OVERT_CTRL_EXT_OVERT_ASSERTED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_OVERT_CTRL_SEL 17:17 /* RWIVF */
|
|
#define NV_THERM_OVERT_CTRL_SEL_LOCAL_LATCH 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_CTRL_SEL_OVERT_PAD 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_CTRL_OTOB_DISABLE 28:28 /* RWIVF */
|
|
#define NV_THERM_OVERT_CTRL_OTOB_DISABLE_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_CTRL_OTOB_DISABLE_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_OVERT_CTRL_OTOB_ENABLE 29:29 /* RWIVF */
|
|
#define NV_THERM_OVERT_CTRL_OTOB_ENABLE_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_OVERT_CTRL_OTOB_ENABLE_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT 0x00020054 /* RW-4R */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_THRESHOLD 16:3 /* RWISF */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_THRESHOLD_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_THRESHOLD_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_THRESHOLD_110C 0x00000dc0 /* RWI-V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_THRESHOLD_MAX 0x00001fff /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE 19:18 /* RWIVF */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE_16US 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE_256US 0x00000001 /* RWI-V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE_4096US 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE_65536US 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID 23:20 /* RWIVF */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_RSVD 0x00000002 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RWI-V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_PERIOD 31:24 /* RWIVF */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_PERIOD_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_PERIOD_EIGHT 0x00000008 /* RWI-V */
|
|
#define NV_THERM_EVT_DEDICATED_OVERT_FILTER_PERIOD_MAX 0x000000ff /* RW--V */
|
|
#define NV_THERM_SENSOR_0 0x00020008 /* R--4R */
|
|
#define NV_THERM_SENSOR_0__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_SENSOR_0_TEMP_CODE 13:0 /* R--VF */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE 0x00020028 /* RW-4R */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_RSVD 14:0 /* C--VF */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_TEMP_SELECT 15:15 /* RWIVF */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_TEMP_SELECT_REAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_TEMP_SELECT_OVERRIDE 0x00000001 /* RW--V */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_TEMP_VALUE 29:16 /* RWISF */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_TEMP_VALUE_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_TEMP_INTEGER 29:21 /* */
|
|
#define NV_THERM_SYS_TSENSE_OVERRIDE_TEMP_INTEGER_ZERO 0x00000000 /* */
|
|
#define NV_THERM_SENSOR_1 0x0002000c /* RW-4R */
|
|
#define NV_THERM_SENSOR_1__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_SENSOR_1_SELECT_SW_A 0:0 /* RWIVF */
|
|
#define NV_THERM_SENSOR_1_SELECT_SW_A_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_1_SELECT_SW_A_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_SENSOR_1_SELECT_SW_B 1:1 /* RWIVF */
|
|
#define NV_THERM_SENSOR_1_SELECT_SW_B_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_1_SELECT_SW_B_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_SENSOR_1_TS_STABLE_CNT 21:2 /* RWIVF */
|
|
#define NV_THERM_SENSOR_1_TS_STABLE_CNT_INIT 0x00000834 /* RWI-V */
|
|
#define NV_THERM_SENSOR_1_TS_STABLE_CNT_RST 31:31 /* RWIVF */
|
|
#define NV_THERM_SENSOR_1_TS_STABLE_CNT_RST_CNT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_1_TS_STABLE_CNT_RST_RST 0x00000001 /* RW--V */
|
|
#define NV_THERM_SENSOR_2 0x00020010 /* RW-4R */
|
|
#define NV_THERM_SENSOR_2__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_SENSOR_2_SW_A 9:0 /* RWIUF */
|
|
#define NV_THERM_SENSOR_2_SW_A_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_2_SW_A_40NM 0x000003ac /* RW--V */
|
|
#define NV_THERM_SENSOR_2_SW_B 26:16 /* RWIUF */
|
|
#define NV_THERM_SENSOR_2_SW_B_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_2_SW_B_40NM 0x000005ef /* RW--V */
|
|
#define NV_THERM_SENSOR_3 0x00020014 /* R--4R */
|
|
#define NV_THERM_SENSOR_3__PRIV_LEVEL_MASK 0x00020320 /* */
|
|
#define NV_THERM_SENSOR_3_HW_A 9:0 /* R--UF */
|
|
#define NV_THERM_SENSOR_3_HW_B 26:16 /* R--UF */
|
|
#define NV_THERM_SENSOR_4 0x0002001c /* R--4R */
|
|
#define NV_THERM_SENSOR_4__PRIV_LEVEL_MASK 0x00020320 /* */
|
|
#define NV_THERM_SENSOR_4_HW_A_NOMINAL 9:0 /* C--UF */
|
|
#define NV_THERM_SENSOR_4_HW_A_NOMINAL_DEF 0x00000226 /* C---V */
|
|
#define NV_THERM_SENSOR_4_HW_B_NOMINAL 26:16 /* C--UF */
|
|
#define NV_THERM_SENSOR_4_HW_B_NOMINAL_DEF 0x0000028e /* C---V */
|
|
#define NV_THERM_SENSOR_6 0x000200f0 /* RW-4R */
|
|
#define NV_THERM_SENSOR_6__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_SENSOR_6_POWER 0:0 /* RWIVF */
|
|
#define NV_THERM_SENSOR_6_POWER_ON 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_6_POWER_OFF 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_6_XTAL_GATE_INVALIDATE_TEMP 1:1 /* RWIVF */
|
|
#define NV_THERM_SENSOR_6_XTAL_GATE_INVALIDATE_TEMP_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_6_XTAL_GATE_INVALIDATE_TEMP_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_6_XTAL_GATE_STATUS 2:2 /* R--VF */
|
|
#define NV_THERM_SENSOR_6_XTAL_GATE_STATUS_GATED 0x00000001 /* R---V */
|
|
#define NV_THERM_SENSOR_6_XTAL_GATE_STATUS_RUNNING 0x00000000 /* R---V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_PERIOD 23:16 /* RWIUF */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_PERIOD_NONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_PERIOD_MAX 0x000000ff /* RW--V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_SCALE 25:24 /* RWIVF */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_SCALE_16US 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_SCALE_256US 0x00000001 /* RW--V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_SCALE_4096US 0x00000002 /* RW--V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_SCALE_65536US 0x00000003 /* RW--V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_STATUS 31:31 /* RWIVF */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_STATUS_VALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_STATUS_ERROR 0x00000001 /* R---V */
|
|
#define NV_THERM_SENSOR_6_POLLING_INTERVAL_STATUS_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_SENSOR_7 0x000200f4 /* RW-4R */
|
|
#define NV_THERM_SENSOR_7__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_SENSOR_7_DEBUG_TS_ADC_OUT 13:0 /* RWIUF */
|
|
#define NV_THERM_SENSOR_7_DEBUG_TS_ADC_OUT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_7_DEBUG_TS_ADC_OVERRIDE 15:15 /* RWIVF */
|
|
#define NV_THERM_SENSOR_7_DEBUG_TS_ADC_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_7_DEBUG_TS_ADC_OVERRIDE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_SENSOR_7_DEBUG_TS_POWER_DOWN 16:16 /* R-IVF */
|
|
#define NV_THERM_SENSOR_7_DEBUG_TS_POWER_DOWN_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_SENSOR_7_DEBUG_TS_POWER_DOWN_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE 0x00020460 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE__PRIV_LEVEL_MASK 0x00020320 /* */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_INTEGER 16:8 /* */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_INTEGER_ZERO 0x00000000 /* */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_INTEGER_MIN 0x000001d8 /* */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_INTEGER_MAX 0x00000096 /* */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_STATE 30:30 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_STATE_INVALID 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SOURCE 31:31 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE 0x00020464 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE__PRIV_LEVEL_MASK 0x00020320 /* */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_INTEGER 16:8 /* */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_INTEGER_ZERO 0x00000000 /* */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_INTEGER_MIN 0x000001d8 /* */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_INTEGER_MAX 0x00000096 /* */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_STATE 30:30 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_STATE_INVALID 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SOURCE 31:31 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT 0x00020468 /* RW-4R */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_FIXED_POINT 16:3 /* RWISF */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_FIXED_POINT_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_FIXED_POINT_MIN 0x00002000 /* RW--V */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_FIXED_POINT_MAX 0x00001fff /* RW--V */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_INTEGER 16:8 /* */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_INTEGER_ZERO 0x00000000 /* */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_INTEGER_MIN 0x00000100 /* */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_INTEGER_MAX 0x000000ff /* */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_MUNGED 24:24 /* RWIVF */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_MUNGED_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_MUNGED_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_STATE 30:30 /* RWIVF */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_STATE_INVALID 0x00000000 /* RW--V */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_STATE_VALID 0x00000001 /* RWI-V */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_SOURCE 31:31 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_CONSTANT_SOURCE_SW_OVERRIDE 0x00000001 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX 0x0002046c /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_MAX__PRIV_LEVEL_MASK 0x00020320 /* */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_FIXED_POINT_MIN 0x00002000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_FIXED_POINT_MAX 0x00001fff /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_INTEGER 16:8 /* */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_INTEGER_ZERO 0x00000000 /* */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_INTEGER_MIN 0x00000100 /* */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_INTEGER_MAX 0x000000ff /* */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_STATE 30:30 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_STATE_INVALID 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_SOURCE 31:31 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_SOURCE_HW_LOGIC 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_MAX_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX 0x00020470 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT_INIT 0x00002000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_INTEGER_INIT 0x00000100 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG 0x00020474 /* RW-4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_FORMULA 25:25 /* RWIVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_FORMULA_0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_FORMULA_1 0x00000001 /* RW--V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX 0x00020478 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT_INIT 0x00002000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER_INIT 0x00000100 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG 0x0002047c /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_SYS_TSENSE_HS_OFFSET 0x000204a0 /* RW-4R */
|
|
#define NV_THERM_SYS_TSENSE_HS_OFFSET__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_SYS_TSENSE_HS_OFFSET_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_SYS_TSENSE_HS_OFFSET_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_SYS_TSENSE_HS_OFFSET_FIXED_POINT 16:3 /* RWISF */
|
|
#define NV_THERM_SYS_TSENSE_HS_OFFSET_FIXED_POINT_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SYS_TSENSE_HS_OFFSET_INTEGER 16:8 /* */
|
|
#define NV_THERM_SENSOR_9 0x000204a4 /* RW-4R */
|
|
#define NV_THERM_SENSOR_9__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_SENSOR_9_MAX_SYS_TSENSE 0:0 /* RWIVF */
|
|
#define NV_THERM_SENSOR_9_MAX_SYS_TSENSE_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_MAX_SYS_TSENSE_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_9_MAX_OFFSET_SYS_TSENSE 1:1 /* RWIVF */
|
|
#define NV_THERM_SENSOR_9_MAX_OFFSET_SYS_TSENSE_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_MAX_OFFSET_SYS_TSENSE_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_9_MAX_CONSTANT 2:2 /* RWIVF */
|
|
#define NV_THERM_SENSOR_9_MAX_CONSTANT_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_MAX_CONSTANT_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_MAX 4:4 /* RWIVF */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_MAX_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_MAX_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_AVG 5:5 /* RWIVF */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_AVG_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_AVG_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_OFFSET_MAX 6:6 /* RWIVF */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_OFFSET_MAX_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_OFFSET_MAX_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_OFFSET_AVG 7:7 /* RWIVF */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_OFFSET_AVG_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_MAX_GPU_OFFSET_AVG_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_9_MAX_SOURCE(i) (i):(i) /* */
|
|
#define NV_THERM_SENSOR_9_MAX_SOURCE__SIZE_1 10 /* */
|
|
#define NV_THERM_SENSOR_9_MAX_SOURCE_NO 0x00000000 /* */
|
|
#define NV_THERM_SENSOR_9_MAX_SOURCE_YES 0x00000001 /* */
|
|
#define NV_THERM_SENSOR_9_I2CS 31:28 /* RWIVF */
|
|
#define NV_THERM_SENSOR_9_I2CS_SYS_TSENSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SENSOR_9_I2CS_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_I2CS_CONSTANT 0x00000002 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_I2CS_MAX 0x00000003 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_I2CS_GPU_MAX 0x00000004 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_I2CS_GPU_AVG 0x00000005 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_I2CS_GPU_OFFSET_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_SENSOR_9_I2CS_GPU_OFFSET_AVG 0x00000007 /* RW--V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX 0x00020448 /* RW-4R */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_SYS_TSENSE 0:0 /* RWIVF */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_SYS_TSENSE_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_SYS_TSENSE_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_OFFSET_SYS_TSENSE 1:1 /* RWIVF */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_OFFSET_SYS_TSENSE_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_OFFSET_SYS_TSENSE_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_MAX 4:4 /* RWIVF */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_MAX_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_MAX_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_AVG 5:5 /* RWIVF */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_AVG_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_AVG_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_MAX 6:6 /* RWIVF */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_MAX_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_MAX_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_AVG 7:7 /* RWIVF */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_AVG_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_AVG_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_FIXED_POINT 30:17 /* R--SF */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_INTEGER 30:22 /* */
|
|
#define NV_THERM_SENSOR_DEDICATED_OVERT_MAX_INTEGER_ZERO 0x00000000 /* */
|
|
#define NV_THERM_WEIGHT_1 0x00020024 /* RW-4R */
|
|
#define NV_THERM_WEIGHT_1__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_WEIGHT_1_XBAR 7:0 /* RWIUF */
|
|
#define NV_THERM_WEIGHT_1_XBAR_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1(i) (0x00020154+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_STEP_SIZE 4:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_STEP_SIZE_MAX 0x00000015 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_STEP_SIZE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_WINDOW_SIZE 11:5 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_WINDOW_SIZE_MAX 0x00000040 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_WINDOW_SIZE_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_NVVDD_FACTOR_A_LUT_EN 12:12 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_NVVDD_FACTOR_A_LUT_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_NVVDD_FACTOR_A_LUT_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_NVVDD_LEAKAGE_C_LUT_EN 13:13 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_NVVDD_LEAKAGE_C_LUT_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_NVVDD_LEAKAGE_C_LUT_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_MSVDD_FACTOR_A_LUT_EN 14:14 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_MSVDD_FACTOR_A_LUT_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_MSVDD_FACTOR_A_LUT_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_MSVDD_LEAKAGE_C_LUT_EN 15:15 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_MSVDD_LEAKAGE_C_LUT_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_MSVDD_LEAKAGE_C_LUT_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_NVVDD 17:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_NVVDD_SYS_ADC 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_NVVDD_GPC_ADC_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_NVVDD_GPC_ADC_AVG 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_MSVDD 19:18 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_MSVDD_SYS_ADC 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_MSVDD_GPC_ADC_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_MSVDD_GPC_ADC_AVG 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_T1_HW_ADC_MODE 20:20 /* RWIVF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_T1_HW_ADC_MODE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_T1_HW_ADC_MODE_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_T1_HW_ADC_MODE_ADC 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_T2_HW_ADC_MODE 21:21 /* RWIVF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_T2_HW_ADC_MODE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_T2_HW_ADC_MODE_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_T2_HW_ADC_MODE_ADC 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_GPC 22:22 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_GPC_NVVDD 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_GPC_MSVDD 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_FBP 23:23 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_FBP_NVVDD 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_FBP_MSVDD 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_XBAR 24:24 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_XBAR_NVVDD 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_XBAR_MSVDD 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_PEAK_EN 25:25 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_PEAK_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_PEAK_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_SRC_NVVDD 27:27 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_SRC_NVVDD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_SRC_NVVDD_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_SRC_MSVDD 28:28 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_SRC_MSVDD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_BA_SRC_MSVDD_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_WINDOW_RST 30:30 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_WINDOW_RST_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_WINDOW_RST_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_WINDOW_RST_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_WINDOW_EN 31:31 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_WINDOW_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG1_WINDOW_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG2(i) (0x00020170+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG2__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG2__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_VAL 19:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_EN 31:31 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG3(i) (0x00020190+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG3__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG3__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_VAL 19:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_EN 31:31 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG4(i) (0x000201c0+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG4__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG4__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_VAL 19:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_EN 31:31 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG5(i) (0x000201f0+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG5__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG5__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_VAL 19:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_EN 31:31 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6(i) (0x00020680+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_FACTOR_A 9:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_FACTOR_A_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT 20:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R1 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R2 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R3 0x00000003 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R4 0x00000004 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R5 0x00000005 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R6 0x00000006 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R7 0x00000007 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R8 0x00000008 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R9 0x00000009 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R10 0x0000000a /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R11 0x0000000b /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R12 0x0000000c /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R13 0x0000000d /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R14 0x0000000e /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R15 0x0000000f /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L16 0x00000010 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L15 0x00000011 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L14 0x00000012 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L13 0x00000013 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L12 0x00000014 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L11 0x00000015 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L10 0x00000016 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L9 0x00000017 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L8 0x00000018 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L7 0x00000019 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L6 0x0000001a /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L5 0x0000001b /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L4 0x0000001c /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L3 0x0000001d /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L2 0x0000001e /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L1 0x0000001f /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG7(i) (0x000206f0+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG7__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG7__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG7_NVVDD_LEAKAGE_C 19:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG7_NVVDD_LEAKAGE_C_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8(i) (0x000202e8+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_FACTOR_A 9:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_FACTOR_A_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT 20:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R1 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R2 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R3 0x00000003 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R4 0x00000004 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R5 0x00000005 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R6 0x00000006 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R7 0x00000007 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R8 0x00000008 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R9 0x00000009 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R10 0x0000000a /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R11 0x0000000b /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R12 0x0000000c /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R13 0x0000000d /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R14 0x0000000e /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R15 0x0000000f /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L16 0x00000010 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L15 0x00000011 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L14 0x00000012 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L13 0x00000013 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L12 0x00000014 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L11 0x00000015 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L10 0x00000016 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L9 0x00000017 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L8 0x00000018 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L7 0x00000019 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L6 0x0000001a /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L5 0x0000001b /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L4 0x0000001c /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L3 0x0000001d /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L2 0x0000001e /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L1 0x0000001f /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG9(i) (0x000202f4+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG9__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG9__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG9_MSVDD_LEAKAGE_C 19:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG9_MSVDD_LEAKAGE_C_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG10(i) (0x00020330+((i)*4)) /* R--4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG10__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG10__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG10_WIN_SUM_VALUE 19:0 /* R-IUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG10_WIN_SUM_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11(i) (0x00020358+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_SIGNIFICAND 8:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_SIGNIFICAND_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT 14:12 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R1 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R2 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R3 0x00000003 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R4 0x00000004 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R5 0x00000005 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R6 0x00000006 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R7 0x00000007 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_SIGNIFICAND 24:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_SIGNIFICAND_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT 30:28 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R1 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R2 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R3 0x00000003 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R4 0x00000004 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R5 0x00000005 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R6 0x00000006 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R7 0x00000007 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12(i) (0x00020364+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_SIGNIFICAND 8:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_SIGNIFICAND_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT 14:12 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R1 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R2 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R3 0x00000003 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R4 0x00000004 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R5 0x00000005 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R6 0x00000006 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R7 0x00000007 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD 19:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_MAX 0x00000008 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_256 0x00000008 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_128 0x00000007 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_64 0x00000006 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_32 0x00000005 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_16 0x00000004 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_8 0x00000003 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_4 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_2 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_1 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG13(i) (0x00020370+((i)*4)) /* R--4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG13__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG13__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG13_DP_PREDICT_BA_VALUE 19:0 /* R-IUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG13_DP_PREDICT_BA_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14(i) (0x000203f0+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_DATA 19:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_INDEX 26:20 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_WRITE_EN 29:29 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_WRITE_EN_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_WRITE_EN_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_WRITE_EN_WRITE 0x00000001 /* -W--T */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_SEL 31:30 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_SEL_NVVDD_FACTOR_A 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_SEL_NVVDD_LEAKAGE_C 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_SEL_MSVDD_FACTOR_A 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_CONFIG14_LUT_SEL_MSVDD_LEAKAGE_C 0x00000003 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT 0x000200c0 /* RW-4R */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_STEP_OFLOW 12:12 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_STEP_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_STEP_OFLOW 13:13 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_STEP_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_STEP_OFLOW 14:14 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_STEP_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_PEAK_OFLOW 15:15 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_PEAK_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_PEAK_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_PEAK_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_PEAK_OFLOW 16:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_PEAK_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_PEAK_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_PEAK_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_PEAK_OFLOW 17:17 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_PEAK_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_PEAK_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_PEAK_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBA_OFLOW 18:18 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBA_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBA_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBA_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBA_OFLOW 19:19 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBA_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBA_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBA_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBA_OFLOW 20:20 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBA_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBA_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBA_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBG3_STEP_OFLOW 21:21 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBG3_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBG3_STEP_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBG3_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBG3_STEP_OFLOW 22:22 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBG3_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBG3_STEP_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBG3_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBG3_STEP_OFLOW 23:23 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBG3_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBG3_STEP_OFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBG3_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0 0x000200d0 /* RW-4R */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX 2:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX_0 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX_1 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX_2 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SELECT 17:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_INIT 0x00000003 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_DYNAMIC 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_LEAKAGE 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_TOTAL 0x00000002 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_RESERVED 0x00000003 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SHIFT 22:18 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SHIFT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SHIFT_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_DEBUG0_DP2_SHIFT_MAX 0x00000010 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL(i) (0x00020110+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_LOGGING 0:0 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_LOGGING_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_LOGGING_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_LOGGING_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_RST 2:2 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_RST_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_RST_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_RST_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_WHEN_OVERFLOW 3:3 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_WHEN_OVERFLOW_SATURATE 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_WHEN_OVERFLOW_ROLLOVER 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT 4:4 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_DIRECT_READ 0x00000000 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP_MODE 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP 5:5 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_PEAKPOWER_ACC_PWR(i) (0x000201d0+((i)*4)) /* R--4A */
|
|
#define NV_THERM_PEAKPOWER_ACC_PWR__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_PWR__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_PWR_TOTAL_POWER 31:0 /* R-XVF */
|
|
#define NV_THERM_PEAKPOWER_ACC_LKG(i) (0x000201b0+((i)*4)) /* R--4A */
|
|
#define NV_THERM_PEAKPOWER_ACC_LKG__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_LKG__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_LKG_LEAKAGE_POWER 31:0 /* R-XVF */
|
|
#define NV_THERM_PEAKPOWER_ACC_STEPS(i) (0x000202b0+((i)*4)) /* R--4A */
|
|
#define NV_THERM_PEAKPOWER_ACC_STEPS__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_STEPS__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_STEPS_STEPS_CNT 31:0 /* R-XVF */
|
|
#define NV_THERM_PEAKPOWER_ACC_BA(i) (0x00020310+((i)*4)) /* R--4A */
|
|
#define NV_THERM_PEAKPOWER_ACC_BA__SIZE_1 3 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_BA__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_ACC_BA_TOTAL_BA 31:0 /* R-XVF */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR 0x0002031c /* RW-4R */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR_ADC_OUT 6:0 /* R-XVF */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR_LENGTH 19:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR_LENGTH_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_BYPASS_DATA 30:24 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_BYPASS_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_SEL 31:31 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_SEL_IIR 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_SEL_BYPASS 0x00000001 /* RW--V */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR 0x0002037c /* RW-4R */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_ADC_OUT 6:0 /* R-XVF */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_ADC_IDX 11:8 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_ADC_IDX_GPC0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_LENGTH 19:16 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_LENGTH_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_BYPASS_DATA 30:24 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_BYPASS_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_SEL 31:31 /* RWIUF */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_SEL_IIR 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_SEL_BYPASS 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_NAFLL_ADC_DISABLE 0x000202bc /* RW-4R */
|
|
#define NV_THERM_GPC_NAFLL_ADC_DISABLE__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_GPC_NAFLL_ADC_DISABLE_MASK 7:0 /* RWIVF */
|
|
#define NV_THERM_GPC_NAFLL_ADC_DISABLE_MASK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL 0x00020600 /* RW-4R */
|
|
#define NV_THERM_BA_TRAINING_CTRL__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_BA_TRAINING_CTRL_PRIV_POLLING_MODE 0:0 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_PRIV_POLLING_MODE_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_PRIV_POLLING_MODE_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_MODE 1:1 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_MODE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_MODE_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_MODE_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MTRAIN_SWITCH 2:2 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MTRAIN_SWITCH_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MTRAIN_SWITCH_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_RESET 3:3 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_RESET_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_RESET_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_RESET_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_BA_TRAINING_CTRL_TRANSCFG_IDX 6:4 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_TRANSCFG_IDX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_MODE_VBIOS_SET 7:7 /* RWIVF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_MODE_VBIOS_SET_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_MODE_VBIOS_SET_TRUE 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_DMA_MODE_VBIOS_SET_FALSE 0x00000000 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE 11:8 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_4KB 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_8KB 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_16KB 0x00000002 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_32KB 0x00000003 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_64KB 0x00000004 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_128KB 0x00000005 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_256KB 0x00000006 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_512KB 0x00000007 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_1MB 0x00000008 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_2MB 0x00000009 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_4MB 0x0000000a /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_8MB 0x0000000b /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_16MB 0x0000000c /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_32MB 0x0000000d /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_64MB 0x0000000e /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_128MB 0x0000000f /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_FST_GPIO_P_W 16:12 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_FST_GPIO_P_W_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_MODE 20:20 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_MODE_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_MODE_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_RESET 21:21 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_RESET_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_RESET_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_RESET_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_DMA 22:22 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_DMA_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_DMA_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_SNAP 23:23 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_SNAP_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_SNAP_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_SNAP_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFRAM_0_STATUS 24:24 /* R--VF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFRAM_0_STATUS_IDLE 0x00000000 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFRAM_0_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFRAM_1_STATUS 25:25 /* R--VF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFRAM_1_STATUS_IDLE 0x00000000 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_BUFRAM_1_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MTRAIN_DBUF 26:26 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MTRAIN_DBUF_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MTRAIN_DBUF_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_ERR_STATUS 27:27 /* RWIVF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_ERR_STATUS_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_ERR_STATUS_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SW_TRIGGER_ERR_STATUS_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD 30:28 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_1US 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_2US 0x00000002 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_4US 0x00000003 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_8US 0x00000004 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_16US 0x00000005 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_32US 0x00000006 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_64US 0x00000007 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SKIP_HW_FLUSH 31:31 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SKIP_HW_FLUSH_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_CTRL_SKIP_HW_FLUSH_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_TIMING 0x00020604 /* RW-4R */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_TIMING__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_TIMING_TRUN_PERIOD 15:0 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_TIMING_TRUN_PERIOD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_DMABASE_LOW 0x00020608 /* RW-4R */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_DMABASE_LOW__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_DMABASE_LOW_BASE_ADDR 31:0 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_DMABASE_LOW_BASE_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_DMABASE_HIGH 0x0002060c /* RW-4R */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_DMABASE_HIGH__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_DMABASE_HIGH_BASE_ADDR 8:0 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_ATRAIN_DMABASE_HIGH_BASE_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL 0x00020610 /* RW-4R */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_INDEX 9:0 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_LOW_RD_INCR 20:20 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_LOW_RD_INCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_LOW_RD_INCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_HIGH_RD_INCR 21:21 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_HIGH_RD_INCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_HIGH_RD_INCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_BUFRAM_SEL 23:22 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_BUFRAM_SEL_0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_BUFRAM_SEL_1 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_BUFRAM_SEL_SHADOW 0x00000002 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_SEL_1R_MODE 24:24 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_SEL_1R_MODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_SEL_1R_MODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_SNAP 31:31 /* RWIUF */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_SNAP_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_SNAP_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_BA_TRAINING_SNAP_CTRL_SNAP_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_BA_TRAINING_DATA_LOW 0x00020614 /* R--4R */
|
|
#define NV_THERM_BA_TRAINING_DATA_LOW_DATA 31:0 /* R--UF */
|
|
#define NV_THERM_BA_TRAINING_DATA_HIGH 0x00020618 /* R--4R */
|
|
#define NV_THERM_BA_TRAINING_DATA_HIGH_DATA 31:0 /* R--UF */
|
|
#define NV_THERM_BA_TRAINING_SW_TRIGGER_COUNT 0x000206bc /* R--4R */
|
|
#define NV_THERM_BA_TRAINING_SW_TRIGGER_COUNT_VALUE 31:0 /* R--UF */
|
|
#define NV_THERM_VOLTAGE_HW_ADC 0x000200d4 /* RW-4R */
|
|
#define NV_THERM_VOLTAGE_HW_ADC__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_VALUE 6:0 /* RWIVF */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_EN 7:7 /* RWIVF */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_EN_DIS 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_EN_EN 0x00000001 /* RW--V */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_VALUE 14:8 /* RWIVF */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_EN 15:15 /* RWIVF */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_EN_DIS 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_EN_EN 0x00000001 /* RW--V */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_HYS_VALUE 27:16 /* RWIVF */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_HYS_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_SEL_ADC 28:28 /* RWIVF */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_SEL_ADC_SYS_ADC 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VOLTAGE_HW_ADC_SEL_ADC_GPC_ADC_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX 0x00020038 /* RW-4R */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX 4:0 /* RWIVF */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_MAX 0x0000000a /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_GR 0x00000000 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_NVENC0 0x00000008 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_NVDEC 0x00000005 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_NVDEC1 0x00000006 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_CE0 0x00000001 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_CE1 0x00000002 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_CE2 0x00000003 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_CE3 0x00000004 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_CE4 0x0000000a /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_OFA0 0x00000009 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_INDEX_INDEX_SEC 0x00000007 /* RW--V */
|
|
#define NV_THERM_ELCG_DBG_DATA 0x0002003c /* R--4R */
|
|
#define NV_THERM_ELCG_DBG_DATA__APERTURE_INDEX_OFFSET (0x00000038-0x0000003c) /* */
|
|
#define NV_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST 2:0 /* R-IVF */
|
|
#define NV_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_ENABLED 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_IDLE_FILTER 0x00000001 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_DISABLE_WAIT4ACK 0x00000002 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_DISABLED 0x00000003 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_ENABLE_WAIT2ACK 0x00000004 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_ENABLE_WAIT4NREQ 0x00000005 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_CG_ST 7:4 /* R-IVF */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_CG_ST_ENG_ENABLED 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_CG_ST_ENG_DISABLING_WAIT2 0x00000001 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_CG_ST_ENG_DISABLED 0x00000002 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_CG_ST_ENG_ENABLING 0x00000003 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST 7:4 /* R--VF */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_ENABLED 0x00000000 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_IDLE_FILT 0x00000001 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_DISABLING 0x00000002 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_DISABLING_WAIT1 0x00000003 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_DISABLING_WAIT2 0x00000004 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_DISABLED 0x00000005 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_CHK_CLK 0x00000006 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_ENABLING 0x00000007 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_ACK_CLEAR 0x00000008 /* R---V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CLK_DISABLE 31:31 /* R-IVF */
|
|
#define NV_THERM_ELCG_DBG_DATA_CLK_DISABLE_DEASSERTED 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ELCG_DBG_DATA_CLK_DISABLE_ASSERTED 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_0 0x00020044 /* R--4R */
|
|
#define NV_THERM_DBG_0__PRIV_LEVEL_MASK 0x00020320 /* */
|
|
#define NV_THERM_DBG_0_FUSE_A_ERR 31:31 /* R-XVF */
|
|
#define NV_THERM_DBG_3 0x00020040 /* R--4R */
|
|
#define NV_THERM_DBG_3__PRIV_LEVEL_MASK 0x0002039c /* */
|
|
#define NV_THERM_DBG_3_GPC_CLK_FORCE 30:29 /* R-XVF */
|
|
#define NV_THERM_DBG_3_GPC_CLK_FORCE_CLK_RUN 0x00000000 /* R---V */
|
|
#define NV_THERM_DBG_3_GPC_CLK_FORCE_CLK_AUTO 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_3_GPC_CLK_FORCE_CLK_STOP 0x00000002 /* R---V */
|
|
#define NV_THERM_DBG_3_GPC_GATEABLE 31:31 /* R-XVF */
|
|
#define NV_THERM_DBG_3_GPC_GATEABLE_DEASSERTED 0x00000000 /* R---V */
|
|
#define NV_THERM_DBG_3_GPC_GATEABLE_ASSERTED 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_4 0x00020298 /* R--4R */
|
|
#define NV_THERM_DBG_4__PRIV_LEVEL_MASK 0x0002039c /* */
|
|
#define NV_THERM_DBG_4_THERMALCTL_HW_SLOW_COND 19:19 /* R-XVF */
|
|
#define NV_THERM_DBG_4_THERMALCTL_HW_SLOW_COND_DISABLED 0x00000000 /* R---V */
|
|
#define NV_THERM_DBG_4_THERMALCTL_HW_SLOW_COND_ENABLED 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_FECS_ST 24:22 /* R-XVF */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_FECS_ST_ON_BUSY 0x00000000 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_FECS_ST_ON_IDLE 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_FECS_ST_WAIT_DREQ_ACK 0x00000002 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_FECS_ST_OFF 0x00000003 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_FECS_ST_WAKEUP 0x00000004 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_FECS_ST_WAIT_EN_ACK 0x00000005 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST 27:25 /* R-XVF */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_ON_BUSY 0x00000000 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_ON_IDLE 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_WAIT_DREQ_ACK 0x00000002 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_OFF 0x00000003 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_WAKEUP 0x00000004 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_WAIT_EN_ACK 0x00000005 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE 29:28 /* R-XVF */
|
|
#define NV_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE_AUTO 0x00000000 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE_SLOW 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE_FORCE_ON 0x00000002 /* R---V */
|
|
#define NV_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE_FORCE_POWER 0x00000003 /* R---V */
|
|
#define NV_THERM_DBG_6 0x00020304 /* R--4R */
|
|
#define NV_THERM_DBG_6_ELCG_GTCTL_FECSC_ST 5:3 /* R-IVF */
|
|
#define NV_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_ON_BUSY 0x00000000 /* R-I-V */
|
|
#define NV_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_ON_IDLE 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_WAIT_DREQ_ACK 0x00000002 /* R---V */
|
|
#define NV_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_OFF 0x00000003 /* R---V */
|
|
#define NV_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_WAKEUP 0x00000004 /* R---V */
|
|
#define NV_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_WAIT_EN_ACK 0x00000005 /* R---V */
|
|
#define NV_THERM_DBG_6_SPARE 31:6 /* C--VF */
|
|
#define NV_THERM_DBG_6_SPARE_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_CONFIG1 0x00020050 /* RW-4R */
|
|
#define NV_THERM_CONFIG1__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_CONFIG1_BA_ENABLE 20:20 /* RWIVF */
|
|
#define NV_THERM_CONFIG1_BA_ENABLE_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CONFIG1_BA_ENABLE_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_CONFIG2 0x00020130 /* RW-4R */
|
|
#define NV_THERM_CONFIG2__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION 11:8 /* RWIUF */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_128K 0x0000000f /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_512 0x00000007 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_256 0x00000006 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_128 0x00000005 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_64 0x00000004 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_32 0x00000003 /* RWI-V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_16 0x00000002 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_8 0x00000001 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_4 0x00000000 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE 15:12 /* RWIUF */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_1 0x00000001 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_2 0x00000002 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_4 0x00000004 /* RW--V */
|
|
#define NV_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_8 0x00000008 /* RW--V */
|
|
#define NV_THERM_CONFIG2_SLOWDOWN_FACTOR_EXTENDED 24:24 /* RWIUF */
|
|
#define NV_THERM_CONFIG2_SLOWDOWN_FACTOR_EXTENDED_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CONFIG2_GRAD_ENABLE 31:31 /* RWIUF */
|
|
#define NV_THERM_CONFIG2_GRAD_ENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PWM_0 0x00020060 /* RW-4R */
|
|
#define NV_THERM_SLOWDOWN_PWM_0__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_SLOWDOWN_PWM_0_PERIOD 24:0 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PWM_0_PERIOD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PWM_0_PERIOD_MAX 0x00ffffff /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PWM_0_EN 31:31 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PWM_0_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PWM_0_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PWM_0_EN__PROD 0x00000000 /* RW--V */
|
|
#define NV_THERM_SLOWDOWN_PWM_1 0x00020064 /* RW-4R */
|
|
#define NV_THERM_SLOWDOWN_PWM_1__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_SLOWDOWN_PWM_1_HI 24:0 /* RWIVF */
|
|
#define NV_THERM_SLOWDOWN_PWM_1_HI_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SLOWDOWN_PWM_1_HI_MAX 0x00ffffff /* RW--V */
|
|
#define NV_THERM_GRAD_STEPPING0 0x000202c0 /* RW-4R */
|
|
#define NV_THERM_GRAD_STEPPING0__PRIV_LEVEL_MASK 0x000203b0 /* */
|
|
#define NV_THERM_GRAD_STEPPING0_FEATURE 0:0 /* RWIVF */
|
|
#define NV_THERM_GRAD_STEPPING0_FEATURE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING0_FEATURE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_GRAD_STEPPING0_MODE 2:2 /* RWIVF */
|
|
#define NV_THERM_GRAD_STEPPING0_MODE_SYMMETRIC 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING0_MODE_ASYMMETRIC 0x00000001 /* RW--V */
|
|
#define NV_THERM_GRAD_STEPPING0_DVCO_FEATURE 4:4 /* RWIVF */
|
|
#define NV_THERM_GRAD_STEPPING0_DVCO_FEATURE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING0_DVCO_FEATURE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_GRAD_STEPPING1 0x000202c4 /* RW-4R */
|
|
#define NV_THERM_GRAD_STEPPING1__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_GRAD_STEPPING1_PDIV_DURATION 16:0 /* RWIUF */
|
|
#define NV_THERM_GRAD_STEPPING1_PDIV_DURATION_IMMEDIATE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING1_PDIV_DURATION_MAX 0x0001ffff /* RW--V */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE(i) (0x000202c8+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE__SIZE_1 2 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0 5:0 /* RWIVF */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR1 11:6 /* RWIVF */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR1_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR2 17:12 /* RWIVF */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR3 23:18 /* RWIVF */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR3_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR4 29:24 /* RWIVF */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR4_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR(i) (5+(i)*6):((i)*6) /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR__SIZE_1 5 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY1 0x00000000 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY1P5 0x00000001 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY2 0x00000002 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY2P5 0x00000003 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY3 0x00000004 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY3P5 0x00000005 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY4 0x00000006 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY4P5 0x00000007 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY5 0x00000008 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY5P5 0x00000009 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY6 0x0000000a /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY6P5 0x0000000b /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY7 0x0000000c /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY7P5 0x0000000d /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY8 0x0000000e /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY8P5 0x0000000f /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY9 0x00000010 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY9P5 0x00000011 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY10 0x00000012 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY10P5 0x00000013 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY11 0x00000014 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY11P5 0x00000015 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY12 0x00000016 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY12P5 0x00000017 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY13 0x00000018 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY13P5 0x00000019 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY14 0x0000001a /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY14P5 0x0000001b /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY15 0x0000001c /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY15P5 0x0000001d /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY16 0x0000001e /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY16P5 0x0000001f /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY17 0x00000020 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY18 0x00000022 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY19 0x00000024 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY20 0x00000026 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY21 0x00000028 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY22 0x0000002a /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY23 0x0000002c /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY24 0x0000002e /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY25 0x00000030 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY26 0x00000032 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY27 0x00000034 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY28 0x00000036 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY29 0x00000038 /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY30 0x0000003a /* */
|
|
#define NV_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY31 0x0000003c /* */
|
|
#define NV_THERM_CONFIG3 0x00020140 /* RW-4R */
|
|
#define NV_THERM_CONFIG3__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_CONFIG3_BA_METER_SHIFT 3:0 /* RWIUF */
|
|
#define NV_THERM_CONFIG3_BA_METER_SHIFT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CONFIG3_BA_SELECT 30:30 /* RWIUF */
|
|
#define NV_THERM_CONFIG3_BA_SELECT_ACC_PWR 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CONFIG3_BA_SELECT_ACC_BA 0x00000001 /* RW--V */
|
|
#define NV_THERM_CONFIG3_BA_METER_ENABLE 31:31 /* RWIUF */
|
|
#define NV_THERM_CONFIG3_BA_METER_ENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_METER_PULSE_WIDTH 0x00020148 /* RW-4R */
|
|
#define NV_THERM_BA_METER_PULSE_WIDTH__PRIV_LEVEL_MASK 0x00020398 /* */
|
|
#define NV_THERM_BA_METER_PULSE_WIDTH_MIN 15:0 /* RWIUF */
|
|
#define NV_THERM_BA_METER_PULSE_WIDTH_MIN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_BA_METER_PULSE_WIDTH_MAX 31:16 /* RWIUF */
|
|
#define NV_THERM_BA_METER_PULSE_WIDTH_MAX_INIT 0x0000ff00 /* RWI-V */
|
|
#define NV_THERM_I2CS_SCRATCH 0x000200bc /* RW-4R */
|
|
#define NV_THERM_I2CS_SCRATCH__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
|
|
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0(i) (0x00020160+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_CLK_SLOWDOWN_0__SIZE_1 4 /* */
|
|
#define NV_THERM_CLK_SLOWDOWN_0__PRIV_LEVEL_MASK 0x000203b0 /* */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR 5:0 /* RWIUF */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DIV2 0x00000001 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DIV4 0x00000002 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DIV8 0x00000003 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DIV16 0x00000004 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_USE_LOCAL 7:7 /* RWIVF */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_USE_LOCAL_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_USE_LOCAL_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 /* RWIUF */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DIV2 0x00000001 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DIV4 0x00000002 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DIV8 0x00000003 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DIV16 0x00000004 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_1(i) (0x00020180+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_CLK_SLOWDOWN_1__SIZE_1 4 /* */
|
|
#define NV_THERM_CLK_SLOWDOWN_1__PRIV_LEVEL_MASK 0x000203b0 /* */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR 5:0 /* RWIUF */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DIV2 0x00000001 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DIV4 0x00000002 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DIV8 0x00000003 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DIV16 0x00000004 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_TRIGGER 7:7 /* RWIUF */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_TRIGGER_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_TRIGGER_UNSET 0x00000000 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_1_SW_THERM_TRIGGER_SET 0x00000001 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2(i) (0x000201a0+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_CLK_SLOWDOWN_2__SIZE_1 4 /* */
|
|
#define NV_THERM_CLK_SLOWDOWN_2__PRIV_LEVEL_MASK 0x000203b0 /* */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_SELECT 3:0 /* RWIVF */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_SELECT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE 6:4 /* RWIVF */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_ENG 0x00000000 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_PMU 0x00000001 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_SLOW 0x00000002 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_ALWAYS 0x00000003 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_NEVER 0x00000004 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_SELECT 11:8 /* RWIVF */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_SELECT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE 14:12 /* RWIVF */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_ENG 0x00000000 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_PMU 0x00000001 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_SLOW 0x00000002 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_ALWAYS 0x00000003 /* RW--V */
|
|
#define NV_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_NEVER 0x00000004 /* RWI-V */
|
|
#define NV_THERM_CLK_TIMING_0(i) (0x000203c0+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_CLK_TIMING_0__SIZE_1 11 /* */
|
|
#define NV_THERM_CLK_TIMING_0__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_CLK_TIMING_0_GRAD_SLOWDOWN 16:16 /* RWIVF */
|
|
#define NV_THERM_CLK_TIMING_0_GRAD_SLOWDOWN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_CLK_TIMING_0_GRAD_SLOWDOWN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_CLK_STATUS(i) (0x000201e0+((i)*4)) /* R--4A */
|
|
#define NV_THERM_CLK_STATUS__SIZE_1 4 /* */
|
|
#define NV_THERM_CLK_STATUS__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_CLK_STATUS_SLOWDOWN_FACTOR 5:0 /* R--UF */
|
|
#define NV_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DISABLED 0x00000000 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DIV2 0x00000001 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DIV4 0x00000002 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DIV8 0x00000003 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DIV16 0x00000004 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SW_THERM 17:17 /* R--VF */
|
|
#define NV_THERM_CLK_STATUS_SW_THERM_INACTIVE 0x00000000 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SW_THERM_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_IDLE_SLOW 18:18 /* R--VF */
|
|
#define NV_THERM_CLK_STATUS_IDLE_SLOW_INACTIVE 0x00000000 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_IDLE_SLOW_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_HW_FAILSAFE 19:19 /* R--VF */
|
|
#define NV_THERM_CLK_STATUS_HW_FAILSAFE_INACTIVE 0x00000000 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_HW_FAILSAFE_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_IDLE_SLOW_COND 20:20 /* R--VF */
|
|
#define NV_THERM_CLK_STATUS_IDLE_SLOW_COND_NOT_SATISFY 0x00000000 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_IDLE_SLOW_COND_SATISFY 0x00000001 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SWITCHING 31:30 /* R--VF */
|
|
#define NV_THERM_CLK_STATUS_SWITCHING_STATIC 0x00000000 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SWITCHING_TRANSITION 0x00000001 /* R---V */
|
|
#define NV_THERM_CLK_STATUS_SWITCHING_UNAVAILABLE 0x00000003 /* R---V */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR 0x00020128 /* RW-4R */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR__PRIV_LEVEL_MASK 0x000203a8 /* */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_HW_FAILSAFE_FORCE_DISABLE 0:0 /* RWIVF */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_HW_FAILSAFE_FORCE_DISABLE_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_HW_FAILSAFE_FORCE_DISABLE_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_IDLE_FORCE_DISABLE 1:1 /* RWIVF */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_IDLE_FORCE_DISABLE_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_IDLE_FORCE_DISABLE_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_SW_FORCE_DISABLE 2:2 /* RWIVF */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_SW_FORCE_DISABLE_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_SLOWDOWN_FACTOR_SW_FORCE_DISABLE_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWER_6 0x00020078 /* RW-4R */
|
|
#define NV_THERM_POWER_6__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_PERIOD 23:16 /* RWIVF */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_PERIOD_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_PERIOD_EIGHT 0x00000008 /* RWI-V */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_PERIOD_MAX 0x000000ff /* RW--V */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_SCALE 25:24 /* RWIVF */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_SCALE_16US 0x00000000 /* RW--V */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_SCALE_256US 0x00000001 /* RWI-V */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_SCALE_4096US 0x00000002 /* RW--V */
|
|
#define NV_THERM_POWER_6_THERMAL_FILTER_SCALE_65536US 0x00000003 /* RW--V */
|
|
#define NV_THERM_POWER_7 0x00020094 /* RW-4R */
|
|
#define NV_THERM_POWER_7__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_POWER_7_EXTOVERT_FILTER_PERIOD 23:16 /* RWIVF */
|
|
#define NV_THERM_POWER_7_EXTOVERT_FILTER_PERIOD_NONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_7_EXTOVERT_FILTER_PERIOD_MAX 0x000000ff /* RW--V */
|
|
#define NV_THERM_POWER_7_EXTOVERT_FILTER_SCALE 25:24 /* RWIVF */
|
|
#define NV_THERM_POWER_7_EXTOVERT_FILTER_SCALE_16US 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_7_EXTOVERT_FILTER_SCALE_256US 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWER_7_EXTOVERT_FILTER_SCALE_4096US 0x00000002 /* RW--V */
|
|
#define NV_THERM_POWER_7_EXTOVERT_FILTER_SCALE_65536US 0x00000003 /* RW--V */
|
|
#define NV_THERM_POWER_8 0x00020098 /* RW-4R */
|
|
#define NV_THERM_POWER_8__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_POWER_8_EXTALERT_FILTER_PERIOD 23:16 /* RWIVF */
|
|
#define NV_THERM_POWER_8_EXTALERT_FILTER_PERIOD_NONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_8_EXTALERT_FILTER_PERIOD_MAX 0x000000ff /* RW--V */
|
|
#define NV_THERM_POWER_8_EXTALERT_FILTER_SCALE 25:24 /* RWIVF */
|
|
#define NV_THERM_POWER_8_EXTALERT_FILTER_SCALE_16US 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_8_EXTALERT_FILTER_SCALE_256US 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWER_8_EXTALERT_FILTER_SCALE_4096US 0x00000002 /* RW--V */
|
|
#define NV_THERM_POWER_8_EXTALERT_FILTER_SCALE_65536US 0x00000003 /* RW--V */
|
|
#define NV_THERM_POWER_9 0x0002009c /* RW-4R */
|
|
#define NV_THERM_POWER_9__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_POWER_9_EXTPOWER_FILTER_PERIOD 23:16 /* RWIVF */
|
|
#define NV_THERM_POWER_9_EXTPOWER_FILTER_PERIOD_NONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_9_EXTPOWER_FILTER_PERIOD_MAX 0x000000ff /* RW--V */
|
|
#define NV_THERM_POWER_9_EXTPOWER_FILTER_SCALE 25:24 /* RWIVF */
|
|
#define NV_THERM_POWER_9_EXTPOWER_FILTER_SCALE_16US 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_9_EXTPOWER_FILTER_SCALE_256US 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWER_9_EXTPOWER_FILTER_SCALE_4096US 0x00000002 /* RW--V */
|
|
#define NV_THERM_POWER_9_EXTPOWER_FILTER_SCALE_65536US 0x00000003 /* RW--V */
|
|
#define NV_THERM_POWER_10 0x000200f8 /* RW-4R */
|
|
#define NV_THERM_POWER_10__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_POWER_10_EXT_ALERT_FILTER_PERIOD 23:16 /* RWIVF */
|
|
#define NV_THERM_POWER_10_EXT_ALERT_FILTER_PERIOD_NONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_10_EXT_ALERT_FILTER_PERIOD_MAX 0x000000ff /* RW--V */
|
|
#define NV_THERM_POWER_10_EXT_ALERT_FILTER_SCALE 25:24 /* RWIVF */
|
|
#define NV_THERM_POWER_10_EXT_ALERT_FILTER_SCALE_16US 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWER_10_EXT_ALERT_FILTER_SCALE_256US 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWER_10_EXT_ALERT_FILTER_SCALE_4096US 0x00000002 /* RW--V */
|
|
#define NV_THERM_POWER_10_EXT_ALERT_FILTER_SCALE_65536US 0x00000003 /* RW--V */
|
|
#define NV_THERM_I2C_ADDR 0x00020018 /* RW-4R */
|
|
#define NV_THERM_I2C_ADDR__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_ADDR_0 7:0 /* RWIVF */
|
|
#define NV_THERM_I2C_ADDR_0_INIT 0x0000009e /* RWI-V */
|
|
#define NV_THERM_I2C_ADDR_1 15:8 /* RWIVF */
|
|
#define NV_THERM_I2C_ADDR_1_INIT 0x0000009c /* RWI-V */
|
|
#define NV_THERM_I2C_ADDR_2 23:16 /* RWIVF */
|
|
#define NV_THERM_I2C_ADDR_2_INIT 0x0000009a /* RWI-V */
|
|
#define NV_THERM_I2C_ADDR_3 31:24 /* RWIVF */
|
|
#define NV_THERM_I2C_ADDR_3_INIT 0x00000098 /* RWI-V */
|
|
#define NV_THERM_STRAP_CTRL 0x00020034 /* RW-4R */
|
|
#define NV_THERM_STRAP_CTRL__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_STRAP_CTRL_SMB_ALT_ADDR 1:0 /* RWIVF */
|
|
#define NV_THERM_STRAP_CTRL_SMB_ALT_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_STRAP_CTRL_SMB_ALT_ADDR_STRAP 0x00000000 /* RW--V */
|
|
#define NV_THERM_STRAP_CTRL_SMB_ALT_ADDR_HIGH 0x00000003 /* RW--V */
|
|
#define NV_THERM_STRAP_CTRL_SMB_ALT_ADDR_LOW 0x00000002 /* RW--V */
|
|
#define NV_THERM_I2C_CFG 0x00020080 /* RW-4R */
|
|
#define NV_THERM_I2C_CFG__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_CFG_TIMEOUT 7:0 /* RWIVF */
|
|
#define NV_THERM_I2C_CFG_TIMEOUT_INIT 0x0000001b /* RWI-V */
|
|
#define NV_THERM_I2C_CFG_SPIKE 10:8 /* RWIVF */
|
|
#define NV_THERM_I2C_CFG_SPIKE_INIT 0x00000004 /* RWI-V */
|
|
#define NV_THERM_I2C_CFG_HOLD 19:16 /* RWIVF */
|
|
#define NV_THERM_I2C_CFG_HOLD_INIT 0x00000006 /* RWI-V */
|
|
#define NV_THERM_I2C_CFG_SETUP 23:20 /* RWIVF */
|
|
#define NV_THERM_I2C_CFG_SETUP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_CFG_PRIV_ENABLE 24:24 /* RWIVF */
|
|
#define NV_THERM_I2C_CFG_PRIV_ENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_CFG_SPARE 31:25 /* RWIVF */
|
|
#define NV_THERM_I2C_CFG_SPARE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_CLK_DIV 0x000200b8 /* RW-4R */
|
|
#define NV_THERM_I2C_CLK_DIV__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_CLK_DIV_VAL 2:0 /* RWIVF */
|
|
#define NV_THERM_I2C_CLK_DIV_VAL_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ARP_CFG 0x000200a0 /* RW-4R */
|
|
#define NV_THERM_ARP_CFG__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_ARP_CFG_ENABLE 24:24 /* RWIVF */
|
|
#define NV_THERM_ARP_CFG_ENABLE_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ARP_CFG_OVERRIDE_RAND 16:16 /* RWIVF */
|
|
#define NV_THERM_ARP_CFG_OVERRIDE_RAND_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_CFG_OVERRIDE_FLAG 8:8 /* RWIVF */
|
|
#define NV_THERM_ARP_CFG_OVERRIDE_FLAG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_CFG_RSVD_COMMAND_CHECK 4:4 /* RWIVF */
|
|
#define NV_THERM_ARP_CFG_RSVD_COMMAND_CHECK_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_THERM_ARP_CFG_RSVD_COMMAND_CHECK_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ARP_CFG_RSVD_DEV_ADDR_CHECK 3:3 /* RWIVF */
|
|
#define NV_THERM_ARP_CFG_RSVD_DEV_ADDR_CHECK_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_CFG_RSVD_DEV_ADDR_CHECK_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_ARP_CFG_AV_FLAG 1:1 /* RWIVF */
|
|
#define NV_THERM_ARP_CFG_AV_FLAG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_CFG_AR_FLAG 0:0 /* RWIVF */
|
|
#define NV_THERM_ARP_CFG_AR_FLAG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_STATUS 0x000200a4 /* R--4R */
|
|
#define NV_THERM_ARP_STATUS__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_ARP_STATUS_ARP_ADR 31:25 /* R-IVF */
|
|
#define NV_THERM_ARP_STATUS_ARP_ADR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ARP_STATUS_AV_FLAG 24:24 /* R-IUF */
|
|
#define NV_THERM_ARP_STATUS_AV_FLAG_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ARP_STATUS_AR_FLAG 16:16 /* R-IUF */
|
|
#define NV_THERM_ARP_STATUS_AR_FLAG_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ARP_STATUS_RANDOM 15:0 /* R-IUF */
|
|
#define NV_THERM_ARP_STATUS_RANDOM_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ARP_UDID_3 0x000200a8 /* RW-4R */
|
|
#define NV_THERM_ARP_UDID_3__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_ARP_UDID_3_DCAP 31:24 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_3_DCAP_INIT 0x000000c1 /* RWI-V */
|
|
#define NV_THERM_ARP_UDID_3_VER_REV 23:16 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_3_VER_REV_INIT 0x00000009 /* RWI-V */
|
|
#define NV_THERM_ARP_UDID_3_VENDOR_ID 15:0 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_3_VENDOR_ID_INIT 0x000010de /* RWI-V */
|
|
#define NV_THERM_ARP_UDID_2 0x000200ac /* RW-4R */
|
|
#define NV_THERM_ARP_UDID_2__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_ARP_UDID_2_DEV_ID 31:16 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_2_DEV_ID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_UDID_2_INTERFACE 15:0 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_2_INTERFACE_INIT 0x00000004 /* RWI-V */
|
|
#define NV_THERM_ARP_UDID_1 0x000200b0 /* RW-4R */
|
|
#define NV_THERM_ARP_UDID_1__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_ARP_UDID_1_SUB_VENDOR 31:16 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_1_SUB_VENDOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_UDID_1_SUB_DEVICE 15:0 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_1_SUB_DEVICE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_UDID_0 0x000200b4 /* RW-4R */
|
|
#define NV_THERM_ARP_UDID_0__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_ARP_UDID_0_VENDOR_SPEC 31:16 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_0_VENDOR_SPEC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ARP_UDID_0_VENDOR_RAND 15:0 /* RWIVF */
|
|
#define NV_THERM_ARP_UDID_0_VENDOR_RAND_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_STATE 0x00020084 /* R--4R */
|
|
#define NV_THERM_I2CS_STATE__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_STATE_VALUE 31:0 /* R-IUF */
|
|
#define NV_THERM_I2CS_STATE_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2CS_STATE_VALUE_SLAVE_ADR 6:0 /* */
|
|
#define NV_THERM_I2CS_STATE_VALUE_SLAVE_IDLE 7:7 /* */
|
|
#define NV_THERM_I2CS_STATE_VALUE_COMMAND 15:8 /* */
|
|
#define NV_THERM_I2CS_STATE_VALUE_DATA_IN 23:16 /* */
|
|
#define NV_THERM_I2CS_STATE_VALUE_PEC 31:24 /* */
|
|
#define NV_THERM_I2CS_PRIV_ADDR 0x00020088 /* R--4R */
|
|
#define NV_THERM_I2CS_PRIV_ADDR__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_PRIV_ADDR_VALUE 31:0 /* R-IUF */
|
|
#define NV_THERM_I2CS_PRIV_ADDR_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2CS_PRIV_RDATA 0x0002008c /* R--4R */
|
|
#define NV_THERM_I2CS_PRIV_RDATA__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_PRIV_RDATA_VALUE 31:0 /* R-IUF */
|
|
#define NV_THERM_I2CS_PRIV_RDATA_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2CS_PRIV_WDATA 0x00020090 /* R--4R */
|
|
#define NV_THERM_I2CS_PRIV_WDATA__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_PRIV_WDATA_VALUE 31:0 /* R-IUF */
|
|
#define NV_THERM_I2CS_PRIV_WDATA_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TSENSE_0 0x00020124 /* RW-4R */
|
|
#define NV_THERM_TSENSE_0__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_TSENSE_0_CALI_SRC 9:9 /* RWIVF */
|
|
#define NV_THERM_TSENSE_0_CALI_SRC_FUSE 0x00000001 /* RWI-V */
|
|
#define NV_THERM_TSENSE_0_CALI_SRC_REG 0x00000000 /* RW--V */
|
|
#define NV_THERM_TSENSE_0_TC_SRC 10:10 /* RWIVF */
|
|
#define NV_THERM_TSENSE_0_TC_SRC_FUSE 0x00000001 /* RWI-V */
|
|
#define NV_THERM_TSENSE_0_TC_SRC_REG 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWM0 0x000200d8 /* RW-4R */
|
|
#define NV_THERM_PWM0__PRIV_LEVEL_MASK 0x00020384 /* */
|
|
#define NV_THERM_PWM0_PERIOD 12:0 /* RWIVF */
|
|
#define NV_THERM_PWM0_PERIOD_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_PWM0_PERIOD_125KHZ 0x000000d8 /* RWI-V */
|
|
#define NV_THERM_PWM0_PERIOD_MAX 0x00001fff /* RW--V */
|
|
#define NV_THERM_PWM0_SHARING 24:24 /* RWIVF */
|
|
#define NV_THERM_PWM0_SHARING_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_THERM_PWM0_SHARING_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_THERM_PWM_TEMP_ALERT 0x000200cc /* RW-4R */
|
|
#define NV_THERM_PWM_TEMP_ALERT__PRIV_LEVEL_MASK 0x00020384 /* */
|
|
#define NV_THERM_PWM_TEMP_ALERT_HI 12:0 /* RWIVF */
|
|
#define NV_THERM_PWM_TEMP_ALERT_HI_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PWM_TEMP_ALERT_OVERRIDE 24:24 /* RWIVF */
|
|
#define NV_THERM_PWM_TEMP_ALERT_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PWM_TEMP_ALERT_OVERRIDE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_PWM_TEMP_ALERT_FAKE 25:25 /* RWIVF */
|
|
#define NV_THERM_PWM_TEMP_ALERT_FAKE_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PWM_TEMP_ALERT_FAKE_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_PWM1 0x000200dc /* RW-4R */
|
|
#define NV_THERM_PWM1__PRIV_LEVEL_MASK 0x00020384 /* */
|
|
#define NV_THERM_PWM1_HI 12:0 /* RWIVF */
|
|
#define NV_THERM_PWM1_HI_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_PWM1_NEW_REQUEST 30:30 /* RWIVF */
|
|
#define NV_THERM_PWM1_NEW_REQUEST_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PWM1_NEW_REQUEST_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_PWM1_SETTING_NEW 31:31 /* R-IVF */
|
|
#define NV_THERM_PWM1_SETTING_NEW_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PWM1_SETTING_NEW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_PWM_ACT0 0x000200c4 /* RW-4R */
|
|
#define NV_THERM_PWM_ACT0__PRIV_LEVEL_MASK 0x00020380 /* */
|
|
#define NV_THERM_PWM_ACT0_PERIOD 18:0 /* R-IUF */
|
|
#define NV_THERM_PWM_ACT0_PERIOD_125KHZ 0x000000d8 /* R-I-V */
|
|
#define NV_THERM_PWM_ACT0_PERIOD_MAX 0x0007ffff /* R---V */
|
|
#define NV_THERM_PWM_ACT0_OVERFLOW 24:24 /* RWIVF */
|
|
#define NV_THERM_PWM_ACT0_OVERFLOW_NONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PWM_ACT0_OVERFLOW_DETECTED 0x00000001 /* R---V */
|
|
#define NV_THERM_PWM_ACT0_OVERFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_PWM_ACT1 0x000200c8 /* R--4R */
|
|
#define NV_THERM_PWM_ACT1__PRIV_LEVEL_MASK 0x00020380 /* */
|
|
#define NV_THERM_PWM_ACT1_HI 18:0 /* R-IUF */
|
|
#define NV_THERM_PWM_ACT1_HI_OFF 0x00000000 /* R-I-V */
|
|
#define NV_THERM_PWM_ACT1_HI_MAX 0x0007ffff /* R---V */
|
|
#define NV_THERM_VID0_PWM(i) (0x00020340+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_VID0_PWM__SIZE_1 4 /* */
|
|
#define NV_THERM_VID0_PWM__PRIV_LEVEL_MASK 0x0002032c /* */
|
|
#define NV_THERM_VID0_PWM_PERIOD 11:0 /* RWIVF */
|
|
#define NV_THERM_VID0_PWM_PERIOD_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_VID0_PWM_PERIOD_125KHZ 0x00000360 /* RWI-V */
|
|
#define NV_THERM_VID0_PWM_PERIOD_MAX 0x00000fff /* RW--V */
|
|
#define NV_THERM_VID0_PWM_SAFE_VOLTAGE_EN 12:12 /* RWIVF */
|
|
#define NV_THERM_VID0_PWM_SAFE_VOLTAGE_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID0_PWM_SAFE_VOLTAGE_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_VID0_PWM_IPC_HI_OFFSET_UPDATE 13:13 /* RWIVF */
|
|
#define NV_THERM_VID0_PWM_IPC_HI_OFFSET_UPDATE_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID0_PWM_IPC_HI_OFFSET_UPDATE_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_VID0_PWM_USE_IPC 14:14 /* RWIVF */
|
|
#define NV_THERM_VID0_PWM_USE_IPC_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID0_PWM_USE_IPC_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_VID0_PWM_USE_FIXED_SLEWRATE 15:15 /* RWIVF */
|
|
#define NV_THERM_VID0_PWM_USE_FIXED_SLEWRATE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID0_PWM_USE_FIXED_SLEWRATE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_VID0_PWM_DELAY_PERIOD 23:16 /* RWIVF */
|
|
#define NV_THERM_VID0_PWM_DELAY_PERIOD_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID0_PWM_BIT_SPREAD 24:24 /* RWIVF */
|
|
#define NV_THERM_VID0_PWM_BIT_SPREAD_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID0_PWM_BIT_SPREAD_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_VID0_PWM_MIN_SPREAD 30:25 /* RWIUF */
|
|
#define NV_THERM_VID0_PWM_MIN_SPREAD_SHORTEST 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID1_PWM(i) (0x00020414+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_VID1_PWM__SIZE_1 4 /* */
|
|
#define NV_THERM_VID1_PWM__PRIV_LEVEL_MASK 0x0002032c /* */
|
|
#define NV_THERM_VID1_PWM_HI 11:0 /* RWIVF */
|
|
#define NV_THERM_VID1_PWM_HI_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID2_PWM(i) (0x000202d0+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_VID2_PWM__SIZE_1 4 /* */
|
|
#define NV_THERM_VID2_PWM__PRIV_LEVEL_MASK 0x0002032c /* */
|
|
#define NV_THERM_VID2_PWM_IPC_HI_MIN 11:0 /* RWIVF */
|
|
#define NV_THERM_VID2_PWM_IPC_HI_MIN_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID3_PWM(i) (0x0002042c+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_VID3_PWM__SIZE_1 4 /* */
|
|
#define NV_THERM_VID3_PWM__PRIV_LEVEL_MASK 0x0002032c /* */
|
|
#define NV_THERM_VID3_PWM_RISING 11:0 /* RWIVF */
|
|
#define NV_THERM_VID3_PWM_RISING_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID3_PWM_FALLING 23:12 /* RWIVF */
|
|
#define NV_THERM_VID3_PWM_FALLING_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID3_PWM_REPEAT 27:24 /* RWIVF */
|
|
#define NV_THERM_VID3_PWM_REPEAT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID3_PWM_STEP 31:28 /* RWIVF */
|
|
#define NV_THERM_VID3_PWM_STEP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID4_PWM(i) (0x000208e8+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_VID4_PWM__SIZE_1 4 /* */
|
|
#define NV_THERM_VID4_PWM__PRIV_LEVEL_MASK 0x0002032c /* */
|
|
#define NV_THERM_VID4_PWM_SAFE_VOLTAGE_HI 11:0 /* RWIVF */
|
|
#define NV_THERM_VID4_PWM_SAFE_VOLTAGE_HI_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK 0x0002033c /* RW-4R */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK__PRIV_LEVEL_MASK 0x0002032c /* */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW(i) (i):(i) /* */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW__SIZE_1 4 /* */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW_DONE 0x00000000 /* */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW_PENDING 0x00000001 /* */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW_TRIGGER 0x00000001 /* */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_0_SETTING_NEW 0:0 /* RWIVF */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_0_SETTING_NEW_DONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_0_SETTING_NEW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_0_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_1_SETTING_NEW 1:1 /* RWIVF */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_1_SETTING_NEW_DONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_1_SETTING_NEW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_1_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_2_SETTING_NEW 2:2 /* RWIVF */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_2_SETTING_NEW_DONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_2_SETTING_NEW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_2_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_3_SETTING_NEW 3:3 /* RWIVF */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_3_SETTING_NEW_DONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_3_SETTING_NEW_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_VID_PWM_TRIGGER_MASK_3_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_FAN_TACHA(i) (0x000204e0+((i)*8)) /* RW-4A */
|
|
#define NV_THERM_FAN_TACHA__SIZE_1 2 /* */
|
|
#define NV_THERM_FAN_TACHA__PRIV_LEVEL_MASK 0x00020388 /* */
|
|
#define NV_THERM_FAN_TACHA_PERIOD 18:0 /* R-IUF */
|
|
#define NV_THERM_FAN_TACHA_PERIOD_MIN 0x00000000 /* R-I-V */
|
|
#define NV_THERM_FAN_TACHA_PERIOD_MAX 0x0007ffff /* R---V */
|
|
#define NV_THERM_FAN_TACHA_OVERFLOW 24:24 /* RWIVF */
|
|
#define NV_THERM_FAN_TACHA_OVERFLOW_NONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_FAN_TACHA_OVERFLOW_DETECTED 0x00000001 /* R---V */
|
|
#define NV_THERM_FAN_TACHA_OVERFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_FAN_TACHA_WIN_LENGTH 26:25 /* RWIVF */
|
|
#define NV_THERM_FAN_TACHA_WIN_LENGTH_ONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_FAN_TACHA_WIN_LENGTH_TWO 0x00000001 /* RW--V */
|
|
#define NV_THERM_FAN_TACHA_WIN_LENGTH_FOUR 0x00000002 /* RW--V */
|
|
#define NV_THERM_FAN_TACHA_WIN_LENGTH_EIGHT 0x00000003 /* RW--V */
|
|
#define NV_THERM_FAN_TACHB(i) (0x000204e4+((i)*8)) /* R--4A */
|
|
#define NV_THERM_FAN_TACHB__SIZE_1 2 /* */
|
|
#define NV_THERM_FAN_TACHB__PRIV_LEVEL_MASK 0x00020388 /* */
|
|
#define NV_THERM_FAN_TACHB_HI 18:0 /* R-IUF */
|
|
#define NV_THERM_FAN_TACHB_HI_OFF 0x00000000 /* R-I-V */
|
|
#define NV_THERM_FAN_TACHB_HI_MAX 0x0007ffff /* R---V */
|
|
#define NV_THERM_MSGBOX_COMMAND 0x000200e0 /* RW-4R */
|
|
#define NV_THERM_MSGBOX_COMMAND__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_MSGBOX_COMMAND_DATA 30:0 /* RWIVF */
|
|
#define NV_THERM_MSGBOX_COMMAND_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MSGBOX_COMMAND_INTR 31:31 /* RWIVF */
|
|
#define NV_THERM_MSGBOX_COMMAND_INTR_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MSGBOX_COMMAND_INTR_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_MSGBOX_DATA_IN 0x000200e4 /* RW-4R */
|
|
#define NV_THERM_MSGBOX_DATA_IN__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_MSGBOX_DATA_IN_DATA 31:0 /* RWIVF */
|
|
#define NV_THERM_MSGBOX_DATA_IN_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MSGBOX_DATA_OUT 0x000200e8 /* RW-4R */
|
|
#define NV_THERM_MSGBOX_DATA_OUT__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_MSGBOX_DATA_OUT_DATA 31:0 /* RWIVF */
|
|
#define NV_THERM_MSGBOX_DATA_OUT_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_MSGBOX_MUTEX 0x000200ec /* RW-4R */
|
|
#define NV_THERM_MSGBOX_MUTEX__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_MSGBOX_MUTEX_CLIENT 7:0 /* RWIVF */
|
|
#define NV_THERM_MSGBOX_MUTEX_CLIENT_NONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_THERMAL_I2CS_ENABLE 0x000203fc /* RW-4R */
|
|
#define NV_THERM_THERMAL_I2CS_ENABLE__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_THERMAL_I2CS_ENABLE_WRITE 0:0 /* RWIUF */
|
|
#define NV_THERM_THERMAL_I2CS_ENABLE_WRITE_DIS 0x00000000 /* RWI-V */
|
|
#define NV_THERM_THERMAL_I2CS_ENABLE_WRITE_EN 0x00000001 /* RW--V */
|
|
#define NV_THERM_THERMAL_I2CS_ENABLE_READ 1:1 /* RWIUF */
|
|
#define NV_THERM_THERMAL_I2CS_ENABLE_READ_DIS 0x00000000 /* RWI-V */
|
|
#define NV_THERM_THERMAL_I2CS_ENABLE_READ_EN 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_00 0x00020400 /* R--4R */
|
|
#define NV_THERM_I2CS_SENSOR_00__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_00_RLTS 7:0 /* R-IUF */
|
|
#define NV_THERM_I2CS_SENSOR_00_RLTS_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2CS_SENSOR_01 0x00020404 /* RW-4R */
|
|
#define NV_THERM_I2CS_SENSOR_01__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_0 0:0 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_0_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_0_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_1 1:1 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_1_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_1_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_2 2:2 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_2_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_2_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_3 3:3 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_3_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_3_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_4 4:4 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_4_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_4_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_5 5:5 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_5_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_5_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_6 6:6 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_6_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_6_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_7 7:7 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_7_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_01_RSL_THERMAL_7_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_02 0x00020408 /* RW-4R */
|
|
#define NV_THERM_I2CS_SENSOR_02__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_8 0:0 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_8_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_8_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_9 1:1 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_9_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_9_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_10 2:2 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_10_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_10_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_11 3:3 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_11_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_02_RSL_THERMAL_11_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_03 0x0002040c /* RW-4R */
|
|
#define NV_THERM_I2CS_SENSOR_03__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_0_EN 0:0 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_0_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_0_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_1_EN 1:1 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_1_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_1_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_2_EN 2:2 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_2_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_2_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_3_EN 3:3 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_3_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_3_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_4_EN 4:4 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_4_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_4_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_5_EN 5:5 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_5_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_5_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_6_EN 6:6 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_6_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_6_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_7_EN 7:7 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_7_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_03_RCL_THERMAL_7_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_04 0x00020410 /* RW-4R */
|
|
#define NV_THERM_I2CS_SENSOR_04__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_8_EN 0:0 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_8_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_8_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_9_EN 1:1 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_9_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_9_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_10_EN 2:2 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_10_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_10_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_11_EN 3:3 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_11_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_04_RCL_THERMAL_11_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_11 0x00020444 /* R--4R */
|
|
#define NV_THERM_I2CS_SENSOR_11__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_11_RIET 7:0 /* R-IUF */
|
|
#define NV_THERM_I2CS_SENSOR_11_RIET_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2CS_SENSOR_13 0x0002044c /* R--4R */
|
|
#define NV_THERM_I2CS_SENSOR_13__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_13_UNCLAMPED_TEMP 7:0 /* R-ISF */
|
|
#define NV_THERM_I2CS_SENSOR_13_UNCLAMPED_TEMP_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2CS_SENSOR_14 0x00020450 /* R--4R */
|
|
#define NV_THERM_I2CS_SENSOR_14__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_14_NEG_TEMP_OFFSET 7:0 /* C--UF */
|
|
#define NV_THERM_I2CS_SENSOR_14_NEG_TEMP_OFFSET_INIT 0x00000040 /* C---V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG 0x000204c8 /* RW-4R */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_VOLT 7:0 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_VOLT_INIT 0x00000040 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_TEMP_COEF 10:8 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_TEMP_COEF_INIT 0x00000002 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_MODE 11:11 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_MODE_AVG 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_MODE_NO_AVG 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_VPTAT_BIAS_CURRENT 13:12 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_VPTAT_BIAS_CURRENT_INIT 0x00000003 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_BYPASS 14:14 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_BYPASS_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_BYPASS_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_STARTUP_BIAS_CURRENT 15:15 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BANDGAP_STARTUP_BIAS_CURRENT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT 19:16 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_TRISTATE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_GND 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VBG 0x00000002 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VPTAT 0x00000003 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_SELA_2 0x00000004 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_IB0 0x00000006 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_IPTAT 0x00000008 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_IBG 0x00000009 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VDD 0x0000000c /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VMOD 0x0000000d /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VDD1V8_IN 0x0000000e /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_PLL_ADC_TEST_IN 0x0000000f /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_PTAT_BIPOLAR_SWAP 20:20 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_PTAT_BIPOLAR_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_PTAT_BIPOLAR_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_PTAT_OPAMP_SWAP 21:21 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_PTAT_OPAMP_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_PTAT_OPAMP_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_PTAT_SOURCE 25:22 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_PTAT_SOURCE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_STOP_SWAP 26:26 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_STOP_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_STOP_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BYPASS_PTAT 27:27 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BYPASS_PTAT_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_BYPASS_PTAT_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_SEND_VBG 28:28 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_SEND_VBG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_AVERAGE_VBG 29:29 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_AVERAGE_VBG_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_AVERAGE_VBG_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_START_BANDGAP 30:30 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_START_BANDGAP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_STOP_SWAPPING_BJT 31:31 /* RWIUF */
|
|
#define NV_THERM_I2CS_SENSOR_TSCFG_STOP_SWAPPING_BJT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_FE 0x000207f8 /* RW-4R */
|
|
#define NV_THERM_I2CS_SENSOR_FE__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_FE_VENDOR_ID 15:0 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_FE_VENDOR_ID_INIT 0x000010de /* RWI-V */
|
|
#define NV_THERM_I2CS_SENSOR_FF 0x000207fc /* RW-4R */
|
|
#define NV_THERM_I2CS_SENSOR_FF__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2CS_SENSOR_FF_REV_ID 7:0 /* RWIVF */
|
|
#define NV_THERM_I2CS_SENSOR_FF_REV_ID_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GLOBAL_OVERRIDES 0x00020280 /* RW-4R */
|
|
#define NV_THERM_GLOBAL_OVERRIDES__PRIV_LEVEL_MASK 0x000203a0 /* */
|
|
#define NV_THERM_GLOBAL_OVERRIDES_NONHOST_BLK_CLK 0:0 /* RWIVF */
|
|
#define NV_THERM_GLOBAL_OVERRIDES_NONHOST_BLK_CLK_RUN 0x00000000 /* RW--V */
|
|
#define NV_THERM_GLOBAL_OVERRIDES_NONHOST_BLK_CLK_AUTO 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL(i) (0x00020200+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_GATE_CTRL__SIZE_1 11 /* */
|
|
#define NV_THERM_GATE_CTRL__PRIV_LEVEL_MASK 0x000203a0 /* */
|
|
#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 0x00000001 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 0x00000002 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0x00000000 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_IDLE_HOLDOFF 4:4 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_IDLE_HOLDOFF_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_IDLE_HOLDOFF_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_BLK_PWR 7:6 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_BLK_PWR_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_BLK_PWR_AUTO 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP_MAX 0x0000001f /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP__PROD 0x00000002 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT_MAX 0x00000007 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT__PROD 0x00000001 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_BEFORE 19:16 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_BEFORE_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_BEFORE_INIT 0x00000008 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_BEFORE_MAX 0x0000000f /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_BEFORE__PROD 0x00000008 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER_INIT 0x00000005 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER_MAX 0x0000000f /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER__PROD 0x00000005 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_BLK_OVR_DELAY_BEFORE 27:24 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_BLK_OVR_DELAY_BEFORE_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_BLK_OVR_DELAY_BEFORE_INIT 0x00000002 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_BLK_OVR_DELAY_BEFORE_MAX 0x0000000f /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_BLK_OVR_DELAY_AFTER 31:28 /* RWIVF */
|
|
#define NV_THERM_GATE_CTRL_BLK_OVR_DELAY_AFTER_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_GATE_CTRL_BLK_OVR_DELAY_AFTER_INIT 0x00000002 /* RWI-V */
|
|
#define NV_THERM_GATE_CTRL_BLK_OVR_DELAY_AFTER_MAX 0x0000000f /* RW--V */
|
|
#define NV_THERM_FECS_IDLE_FILTER 0x00020288 /* RW-4R */
|
|
#define NV_THERM_FECS_IDLE_FILTER__PRIV_LEVEL_MASK 0x0002039c /* */
|
|
#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 /* RWIVF */
|
|
#define NV_THERM_FECS_IDLE_FILTER_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_FECS_IDLE_FILTER_VALUE_MAX 0xffffffff /* RW--V */
|
|
#define NV_THERM_FECS_IDLE_FILTER_VALUE__PROD 0x00000000 /* RW--V */
|
|
#define NV_THERM_HUBMMU_IDLE_FILTER 0x0002028c /* RW-4R */
|
|
#define NV_THERM_HUBMMU_IDLE_FILTER__PRIV_LEVEL_MASK 0x0002039c /* */
|
|
#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 /* RWIVF */
|
|
#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE_MAX 0xffffffff /* RW--V */
|
|
#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE__PROD 0x00000000 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF 0x00020290 /* RW-4R */
|
|
#define NV_THERM_ENG_HOLDOFF__PRIV_LEVEL_MASK 0x000203a0 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG0 0:0 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG0_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG0_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG1 1:1 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG1_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG1_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG2 2:2 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG2_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG2_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG3 3:3 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG3_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG3_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG4 4:4 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG4_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG4_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG5 5:5 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG5_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG5_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG6 6:6 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG6_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG6_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG7 7:7 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG7_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG7_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG8 8:8 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG8_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG8_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG9 9:9 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG9_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG9_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG10 10:10 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG10_NOTBLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG10_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG_HW_SIZE 26 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG(i) (0+(i)):(0+(i)) /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG__SIZE_1 11 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG_NOTBLOCKED 0x00000000 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENG_BLOCKED 0x00000001 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS 0x00020294 /* R--4R */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS__PRIV_LEVEL_MASK 0x0002039c /* */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG0 0:0 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG0_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG0_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG1 1:1 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG1_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG1_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG2 2:2 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG2_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG2_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG3 3:3 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG3_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG3_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG4 4:4 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG4_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG4_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG5 5:5 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG5_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG5_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG6 6:6 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG6_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG6_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG7 7:7 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG7_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG7_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG8 8:8 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG8_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG8_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG9 9:9 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG9_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG9_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG10 10:10 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG10_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG10_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG(i) (0+(i)):(0+(i)) /* */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG__SIZE_1 11 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG_NOTBLOCKED 0x00000000 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_STATUS_ENG_BLOCKED 0x00000001 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER 0x0002030c /* R--4R */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER__PRIV_LEVEL_MASK 0x0002039c /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG0 0:0 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG0_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG0_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG1 1:1 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG1_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG1_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG2 2:2 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG2_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG2_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG3 3:3 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG3_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG3_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG4 4:4 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG4_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG4_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG5 5:5 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG5_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG5_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG6 6:6 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG6_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG6_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG7 7:7 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG7_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG7_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG8 8:8 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG8_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG8_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG9 9:9 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG9_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG9_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG10 10:10 /* R-IVF */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG10_NOT_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG10_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG(i) (0+(i)):(0+(i)) /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG__SIZE_1 11 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG_NOTDONE 0x00000000 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_ENTER_ENG_DONE 0x00000001 /* */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN 0x00020308 /* RW-4R */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN__PRIV_LEVEL_MASK 0x0002039c /* */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG0 0:0 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG1 1:1 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG2 2:2 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG3 3:3 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG3_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG3_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG4 4:4 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG4_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG4_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG5 5:5 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG5_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG5_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG6 6:6 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG6_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG6_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG7 7:7 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG7_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG7_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG8 8:8 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG8_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG8_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG9 9:9 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG9_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG9_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG10 10:10 /* RWIVF */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG10_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ENG_HOLDOFF_INTR_EN_ENG10_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWERCTRL_0 0x0002029c /* RW-4R */
|
|
#define NV_THERM_POWERCTRL_0__PRIV_LEVEL_MASK 0x00020320 /* */
|
|
#define NV_THERM_POWERCTRL_0_FULLP_PULLDOWN 21:21 /* RWIVF */
|
|
#define NV_THERM_POWERCTRL_0_FULLP_PULLDOWN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWERCTRL_0_FULLP_PULLDOWN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_POWERCTRL_0_PADS_WEAKPULL 22:22 /* RWIVF */
|
|
#define NV_THERM_POWERCTRL_0_PADS_WEAKPULL_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_POWERCTRL_0_PADS_WEAKPULL_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_DBG_2 0x0002007c /* RW-4R */
|
|
#define NV_THERM_DBG_2__PRIV_LEVEL_MASK 0x0002039c /* */
|
|
#define NV_THERM_DBG_2_CFG_ERR_REASON 23:16 /* R-IVF */
|
|
#define NV_THERM_DBG_2_CFG_ERR_REASON_NONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_DBG_2_FAST_TIMER_MODE 24:24 /* RWIVF */
|
|
#define NV_THERM_DBG_2_FAST_TIMER_MODE_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DBG_2_FAST_TIMER_MODE_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_DBG_2_ENG_SM 25:25 /* RWIVF */
|
|
#define NV_THERM_DBG_2_ENG_SM_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DBG_2_ENG_SM_RUN_ALWAYS 0x00000001 /* RW--V */
|
|
#define NV_THERM_DBG_2_FBP_CLK_FORCE 30:29 /* R-XVF */
|
|
#define NV_THERM_DBG_2_FBP_CLK_FORCE_CLK_RUN 0x00000000 /* R---V */
|
|
#define NV_THERM_DBG_2_FBP_CLK_FORCE_CLK_AUTO 0x00000001 /* R---V */
|
|
#define NV_THERM_DBG_2_FBP_CLK_FORCE_CLK_STOP 0x00000002 /* R---V */
|
|
#define NV_THERM_DBG_2_FBP_GATEABLE 31:31 /* R-XVF */
|
|
#define NV_THERM_DBG_2_FBP_GATEABLE_DEASSERTED 0x00000000 /* R---V */
|
|
#define NV_THERM_DBG_2_FBP_GATEABLE_ASSERTED 0x00000001 /* R---V */
|
|
#define NV_THERM_ECO 0x0002050c /* RW-4R */
|
|
#define NV_THERM_ECO_BIT0 0:0 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT1 1:1 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT2 2:2 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT3 3:3 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT4 4:4 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT5 5:5 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT5_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT6 6:6 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT6_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT7 7:7 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT7_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT8 8:8 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT8_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT9 9:9 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT9_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT10 10:10 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT10_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT11 11:11 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT11_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT12 12:12 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT12_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT13 13:13 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT13_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT14 14:14 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT14_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_ECO_BIT15 15:15 /* RWIVF */
|
|
#define NV_THERM_ECO_BIT15_INIT 0x00000001 /* RWI-V */
|
|
#define NV_THERM_STATISTICS_BA_MAX 0x00020500 /* RW-4R */
|
|
#define NV_THERM_STATISTICS_BA_MAX_DATA 19:0 /* R-IUF */
|
|
#define NV_THERM_STATISTICS_BA_MAX_DATA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_STATISTICS_BA_MAX_RESET 31:31 /* RWIVF */
|
|
#define NV_THERM_STATISTICS_BA_MAX_RESET_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_STATISTICS_BA_MAX_RESET_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_STATISTICS_BA_MIN 0x00020504 /* RW-4R */
|
|
#define NV_THERM_STATISTICS_BA_MIN_DATA 19:0 /* R-IUF */
|
|
#define NV_THERM_STATISTICS_BA_MIN_DATA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_STATISTICS_BA_MIN_RESET 31:31 /* RWIVF */
|
|
#define NV_THERM_STATISTICS_BA_MIN_RESET_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_STATISTICS_BA_MIN_RESET_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_STATISTICS_BA_MAXDBA 0x00020508 /* RW-4R */
|
|
#define NV_THERM_STATISTICS_BA_MAXDBA_DATA 19:0 /* R-IUF */
|
|
#define NV_THERM_STATISTICS_BA_MAXDBA_DATA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_STATISTICS_BA_MAXDBA_RESET 31:31 /* RWIVF */
|
|
#define NV_THERM_STATISTICS_BA_MAXDBA_RESET_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_STATISTICS_BA_MAXDBA_RESET_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_STATISTICS_TEMP_AVG 0x00020510 /* RW-4R */
|
|
#define NV_THERM_STATISTICS_TEMP_AVG_DATA 7:0 /* R-IUF */
|
|
#define NV_THERM_STATISTICS_TEMP_AVG_DATA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_STATISTICS_TEMP_AVG_RESET 8:8 /* RWIVF */
|
|
#define NV_THERM_STATISTICS_TEMP_AVG_RESET_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_STATISTICS_TEMP_AVG_RESET_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_STATISTICS_CTRL 0x00020514 /* RW-4R */
|
|
#define NV_THERM_STATISTICS_CTRL_BA 0:0 /* RWIVF */
|
|
#define NV_THERM_STATISTICS_CTRL_BA_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_STATISTICS_CTRL_BA_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_STATISTICS_CTRL_TEMP 1:1 /* RWIVF */
|
|
#define NV_THERM_STATISTICS_CTRL_TEMP_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_STATISTICS_CTRL_TEMP_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH0_ADDR 0x0002051c /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH0_ADDR__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH0_ADDR_VALUE 7:1 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH0_ADDR_VALUE_INIT 0x0000004a /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH0_ADDR_READY 31:31 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH0_ADDR_READY_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH0_ADDR_READY_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH1_ADDR 0x00020520 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH1_ADDR__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH1_ADDR_VALUE 7:1 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH1_ADDR_VALUE_INIT 0x0000004b /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH1_ADDR_READY 31:31 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH1_ADDR_READY_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH1_ADDR_READY_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0 0x00020524 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_INDEX 8:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_INDEX_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_INDEX_MAX 0x000001ff /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_READINCR 16:16 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_READINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_READINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_WRITEINCR 17:17 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_WRITEINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX0_WRITEINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1 0x00020538 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_INDEX 8:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_INDEX_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_INDEX_MAX 0x000001ff /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_READINCR 16:16 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_READINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_READINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_WRITEINCR 17:17 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_WRITEINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX1_WRITEINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2 0x0002054c /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_INDEX 8:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_INDEX_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_INDEX_MAX 0x000001ff /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_READINCR 16:16 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_READINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_READINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_WRITEINCR 17:17 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_WRITEINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX2_WRITEINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3 0x00020560 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_INDEX 8:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_INDEX_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_INDEX_MAX 0x000001ff /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_READINCR 16:16 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_READINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_READINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_WRITEINCR 17:17 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_WRITEINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INDEX3_WRITEINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_DATA0 0x00020528 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_DATA0__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_DATA0__APERTURE_INDEX_OFFSET (0x00000524-0x00000528) /* */
|
|
#define NV_THERM_I2C_SCRATCH_DATA0_VALUE 31:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_DATA0_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_DATA1 0x0002053c /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_DATA1__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_DATA1__APERTURE_INDEX_OFFSET (0x00000538-0x0000053c) /* */
|
|
#define NV_THERM_I2C_SCRATCH_DATA1_VALUE 31:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_DATA1_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_DATA2 0x00020550 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_DATA2__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_DATA2__APERTURE_INDEX_OFFSET (0x0000054c-0x00000550) /* */
|
|
#define NV_THERM_I2C_SCRATCH_DATA2_VALUE 31:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_DATA2_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_DATA3 0x00020564 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_DATA3__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_DATA3__APERTURE_INDEX_OFFSET (0x00000560-0x00000564) /* */
|
|
#define NV_THERM_I2C_SCRATCH_DATA3_VALUE 31:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_DATA3_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0 0x0002052c /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0__APERTURE_INDEX_OFFSET (0x00000524-0x0000052c) /* */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE 31:30 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE_SET_NACK 0x00000000 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE_SET_RO 0x00000001 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE_SET_RW 0x00000002 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE_SET_NONE 0x00000003 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE_NACK 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE_RO 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE_RW 0x00000002 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE0_STATE_NONE 0x00000003 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1 0x00020540 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1__APERTURE_INDEX_OFFSET (0x00000538-0x00000540) /* */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE 31:30 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE_SET_NACK 0x00000000 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE_SET_RO 0x00000001 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE_SET_RW 0x00000002 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE_SET_NONE 0x00000003 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE_NACK 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE_RO 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE_RW 0x00000002 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE1_STATE_NONE 0x00000003 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2 0x00020554 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2__APERTURE_INDEX_OFFSET (0x0000054c-0x00000554) /* */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE 31:30 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE_SET_NACK 0x00000000 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE_SET_RO 0x00000001 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE_SET_RW 0x00000002 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE_SET_NONE 0x00000003 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE_NACK 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE_RO 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE_RW 0x00000002 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE2_STATE_NONE 0x00000003 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3 0x00020568 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3__APERTURE_INDEX_OFFSET (0x00000560-0x00000568) /* */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE 31:30 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE_SET_NACK 0x00000000 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE_SET_RO 0x00000001 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE_SET_RW 0x00000002 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE_SET_NONE 0x00000003 /* -W--V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE_NACK 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE_RO 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE_RW 0x00000002 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_STATE3_STATE_NONE 0x00000003 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_CTRL(i) (0x00020530+((i)*20)) /* RW-4A */
|
|
#define NV_THERM_I2C_SCRATCH_CTRL__SIZE_1 4 /* */
|
|
#define NV_THERM_I2C_SCRATCH_CTRL__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE 31:30 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE_INVALID 0x00000000 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE_RO 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE_RW 0x00000002 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE_NONE 0x00000003 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_MUTEX(i) (0x00020534+((i)*20)) /* RW-4A */
|
|
#define NV_THERM_I2C_SCRATCH_MUTEX__SIZE_1 4 /* */
|
|
#define NV_THERM_I2C_SCRATCH_MUTEX__PRIV_LEVEL_MASK 0x0002038c /* */
|
|
#define NV_THERM_I2C_SCRATCH_MUTEX_CLIENT 7:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_MUTEX_CLIENT_NONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE 0x00020588 /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR63 0:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR63_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR63_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR63_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR127 1:1 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR127_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR127_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR127_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR191 2:2 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR191_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR191_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR191_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR255 3:3 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR255_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR255_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR255_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR319 4:4 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR319_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR319_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR319_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR383 5:5 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR383_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR383_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR383_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR447 6:6 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR447_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR447_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR447_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR511 7:7 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR511_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR511_PENDING 0x00000001 /* R---V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_STATE_ADDR511_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN 0x0002058c /* RW-4R */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN__PRIV_LEVEL_MASK 0x00020390 /* */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR63 0:0 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR63_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR63_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR127 1:1 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR127_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR127_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR191 2:2 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR191_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR191_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR255 3:3 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR255_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR255_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR319 4:4 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR319_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR319_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR383 5:5 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR383_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR383_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR447 6:6 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR447_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR447_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR511 7:7 /* RWIVF */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR511_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_I2C_SCRATCH_INTR_EN_ADDR511_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_CG1 0x000206b8 /* RW-4R */
|
|
#define NV_THERM_CG1_SLCG 3:0 /* RWIVF */
|
|
#define NV_THERM_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_CG1_SLCG_DISABLED 0x0000000f /* RWI-V */
|
|
#define NV_THERM_CG1_SLCG__PROD 0x00000009 /* RW--V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK(i) (0x00020800+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK__SIZE_1 8 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK(i) (0x00020820+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK__SIZE_1 8 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_3_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_3_SOURCE_ENABLE_IFF_GSP_PMU_ENABLED 0x0008004a /* RWI-V */
|
|
#define NV_THERM_SCRATCH(i) (0x00020598+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_SCRATCH__SIZE_1 8 /* */
|
|
#define NV_THERM_SCRATCH_VAL 31:0 /* RWIUF */
|
|
#define NV_THERM_SCRATCH_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SECURE_SCRATCH(i) (0x000205b8+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_SECURE_SCRATCH__SIZE_1 8 /* */
|
|
#define NV_THERM_SECURE_SCRATCH__PRIV_LEVEL_MASK NV_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK /* */
|
|
#define NV_THERM_SECURE_SCRATCH_VAL 31:0 /* RWIUF */
|
|
#define NV_THERM_SECURE_SCRATCH_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SECURE_WR_SCRATCH(i) (0x000205d8+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_SECURE_WR_SCRATCH__SIZE_1 8 /* */
|
|
#define NV_THERM_SECURE_WR_SCRATCH__PRIV_LEVEL_MASK NV_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK /* */
|
|
#define NV_THERM_SECURE_WR_SCRATCH_VAL 31:0 /* RWIUF */
|
|
#define NV_THERM_SECURE_WR_SCRATCH_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DUMMY 0x0002004c /* RW-4R */
|
|
#define NV_THERM_DUMMY__PRIV_LEVEL_MASK 0x00020324 /* */
|
|
#define NV_THERM_DUMMY_VALUE 0:0 /* RWIUF */
|
|
#define NV_THERM_DUMMY_VALUE_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX 0x00020874 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX__PRIV_LEVEL_MASK 0x000203a0 /* */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_INDEX 2:0 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_INDEX_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_READINCR 8:8 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_WRITEINCR 9:9 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY 0x00020878 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY__APERTURE_INDEX_OFFSET (0x00000874-0x00000878) /* */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY__PRIV_LEVEL_MASK 0x000203a0 /* */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_NEW_SETTING 31:31 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_NEW_SETTING_NO_CMD 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_CONFIG_COPY_NEW_SETTING_SEND 0x00000001 /* RW--T */
|
|
#define NV_THERM_GPC_INDEX 0x00020860 /* RW-4R */
|
|
#define NV_THERM_GPC_INDEX__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_INDEX_INDEX 2:0 /* RWIVF */
|
|
#define NV_THERM_GPC_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_INDEX_INDEX_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_GPC_INDEX_READINCR 8:8 /* RWIVF */
|
|
#define NV_THERM_GPC_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_INDEX_WRITEINCR 9:9 /* RWIVF */
|
|
#define NV_THERM_GPC_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE 0x00020864 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE__APERTURE_INDEX_OFFSET (0x00000860-0x00000864) /* */
|
|
#define NV_THERM_GPC_TSENSE__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_TSENSE_TS_ADC_OUT 13:0 /* R--VF */
|
|
#define NV_THERM_GPC_TSENSE_STREAM_RAW_CODE 16:16 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_STREAM_RAW_CODE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_STREAM_RAW_CODE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_TS_BJT_SEL 23:20 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_TS_BJT_SEL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_TS_PD 24:24 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_TS_PD_DEASSERT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_TS_PD_ASSERT 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_CONTROL_SRC 28:28 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_CONTROL_SRC_LOGIC 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_CONTROL_SRC_REG 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_CALI_SRC 29:29 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_CALI_SRC_FUSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_CALI_SRC_REG 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_TC_SRC 30:30 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_TC_SRC_FUSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_TC_SRC_REG 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ 0x00020868 /* RW-4R */
|
|
#define NV_THERM_GPC_TS_ADJ__APERTURE_INDEX_OFFSET (0x00000860-0x00000868) /* */
|
|
#define NV_THERM_GPC_TS_ADJ__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_TS_ADJ_VALUE 31:0 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_VALUE_INIT 0x00007240 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_VOLT 7:0 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_VOLT_INIT 0x00000040 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_TEMP_COEF 10:8 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_TEMP_COEF_INIT 0x00000002 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_MODE 11:11 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_MODE_AVG 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_MODE_NO_AVG 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_VPTAT_BIAS_CURRENT 13:12 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_VPTAT_BIAS_CURRENT_INIT 0x00000003 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_BYPASS 14:14 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_BYPASS_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_BYPASS_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_STARTUP_BIAS_CURRENT 15:15 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_BANDGAP_STARTUP_BIAS_CURRENT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT 19:16 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_TRISTATE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_GND 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VBG 0x00000002 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VPTAT 0x00000003 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_SELA_2 0x00000004 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_IB0 0x00000006 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_IPTAT 0x00000008 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_IBG 0x00000009 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VDD 0x0000000c /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VMID 0x0000000d /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VDD1V8_IN 0x0000000e /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_PLL_ADC_TEST_IN 0x0000000f /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_PTAT_BIPOLAR_SWAP 20:20 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_PTAT_BIPOLAR_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_PTAT_BIPOLAR_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_PTAT_OPAMP_SWAP 21:21 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_PTAT_OPAMP_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_PTAT_OPAMP_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_PTAT_SOURCE 25:22 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_PTAT_SOURCE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_STOP_SWAP 26:26 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_STOP_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_STOP_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_BYPASS_PTAT 27:27 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_BYPASS_PTAT_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_BYPASS_PTAT_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_SEND_VBG 28:28 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_SEND_VBG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_AVERAGE_VBG 29:29 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_AVERAGE_VBG_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_AVERAGE_VBG_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_ADJ_START_BANDGAP 30:30 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_START_BANDGAP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_ADJ_STOP_SWAPPING_BJT 31:31 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_ADJ_STOP_SWAPPING_BJT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_RAWCODE_OVERRIDE 0x0002086c /* RW-4R */
|
|
#define NV_THERM_GPC_RAWCODE_OVERRIDE__APERTURE_INDEX_OFFSET (0x00000860-0x0000086c) /* */
|
|
#define NV_THERM_GPC_RAWCODE_OVERRIDE__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_RAWCODE_OVERRIDE_VALUE 13:0 /* RWIUF */
|
|
#define NV_THERM_GPC_RAWCODE_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_RAWCODE_OVERRIDE_EN 16:16 /* RWIUF */
|
|
#define NV_THERM_GPC_RAWCODE_OVERRIDE_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_RAWCODE_OVERRIDE_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL 0x00020870 /* RW-4R */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL__APERTURE_INDEX_OFFSET (0x00000860-0x00000870) /* */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL_SAMPLE_DELAY 13:0 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL_SAMPLE_DELAY_INIT 0x00000834 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL_AUTO_POLLING 15:15 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL_AUTO_POLLING_OFF 0x00000000 /* RW--V */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL_AUTO_POLLING_ON 0x00000001 /* RWI-V */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL_POLLING_INTERVAL 31:16 /* RWIUF */
|
|
#define NV_THERM_GPC_TS_AUTO_CONTROL_POLLING_INTERVAL_INIT 0x0000005a /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX 0x000206d4 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_GPC_BJT_INDEX 3:0 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_GPC_BJT_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_GPC_BJT_INDEX_MAX 0x00000002 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_GPC_INDEX 19:16 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_GPC_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_GPC_INDEX_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_READINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_RAW_CODE 0x000206ec /* R--4R */
|
|
#define NV_THERM_GPC_TSENSE_RAW_CODE_VALUE 13:0 /* R--VF */
|
|
#define NV_THERM_GPC_TSENSE_RAW_CODE_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_GPC_TSENSE_RAW_CODE_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_GPC_TSENSE_RAW_CODE_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_GPC_TSENSE_RAW_CODE_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_GPC_TSENSE_RAW_CODE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_GPC_TSENSE_RAW_CODE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED 0x000204b8 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_FIXED_POINT_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_INTEGER_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED 0x000204bc /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_FIXED_POINT_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_INTEGER_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE 0x000204c0 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_INTEGER_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE 0x000204c4 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_INTEGER_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX 0x000206d0 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_BJT_INDEX 3:0 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_BJT_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_BJT_INDEX_MAX 0x00000002 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_INDEX 19:16 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_INDEX_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_READINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_WRITEINCR 31:31 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE 0x000206d8 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_RSVD 14:0 /* C--VF */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_TEMP_SELECT 15:15 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_TEMP_SELECT_REAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_TEMP_SELECT_OVERRIDE 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_TEMP_VALUE 29:16 /* RWISF */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_TEMP_VALUE_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_TEMP_INTEGER 29:21 /* */
|
|
#define NV_THERM_GPC_TSENSE_OVERRIDE_TEMP_INTEGER_ZERO 0x00000000 /* */
|
|
#define NV_THERM_TSENSE_GLOBAL_OVERRIDE 0x000206dc /* RW-4R */
|
|
#define NV_THERM_TSENSE_GLOBAL_OVERRIDE__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_TSENSE_GLOBAL_OVERRIDE_VALUE 13:0 /* RWISF */
|
|
#define NV_THERM_TSENSE_GLOBAL_OVERRIDE_VALUE_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_TSENSE_GLOBAL_OVERRIDE_EN 16:16 /* RWIVF */
|
|
#define NV_THERM_TSENSE_GLOBAL_OVERRIDE_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_TSENSE_GLOBAL_OVERRIDE_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX 0x000206cc /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_BJT_INDEX 3:0 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_BJT_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_BJT_INDEX_MAX 0x00000002 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_INDEX 19:16 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_INDEX_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_READINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_WRITEINCR 31:31 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET 0x000206e4 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_FIXED_POINT 16:3 /* RWISF */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_FIXED_POINT_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_HS_OFFSET_INTEGER 16:8 /* */
|
|
#define NV_THERM_ADC_RAW_CORRECTION 0x0002061c /* RW-4R */
|
|
#define NV_THERM_ADC_RAW_CORRECTION__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_RAW_CORRECTION_VALUE 10:0 /* RWIUF */
|
|
#define NV_THERM_ADC_RAW_CORRECTION_VALUE_INIT 0x00000040 /* RWI-V */
|
|
#define NV_THERM_ADC_RAW_CORRECTION_FLIP_POLARITY 16:16 /* RWIUF */
|
|
#define NV_THERM_ADC_RAW_CORRECTION_FLIP_POLARITY_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_RAW_CORRECTION_FLIP_POLARITY_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL 0x00020620 /* RW-4R */
|
|
#define NV_THERM_ADC_CTRL__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_CTRL_ADC_SENSING 0:0 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL_ADC_SENSING_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL_ADC_SENSING_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL_ADC_ACC 1:1 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL_ADC_ACC_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL_ADC_ACC_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL_SNAP 2:2 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL_SNAP_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ADC_CTRL_SNAP_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_ADC_CTRL_SNAP_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_ADC_CTRL_DEVICE_MODE 3:3 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL_DEVICE_MODE_NON_ALT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL_DEVICE_MODE_ALT 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL_ACTIVE_CHANNELS_NUM 8:4 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL_ACTIVE_CHANNELS_NUM_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL_ACTIVE_CHANNELS_NUM_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL_ACTIVE_CHANNELS_NUM_MAX 0x00000010 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL_ADC_IIR_LENGTH 15:12 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL_ADC_IIR_LENGTH_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL_SAMPLE_DELAY 31:24 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL_SAMPLE_DELAY_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL2 0x000206c4 /* RW-4R */
|
|
#define NV_THERM_ADC_CTRL2__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON1 4:0 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL2_BEACON1_NONE 0x00000010 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL2_BEACON1_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_BEACON1_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_BEACON1_CH2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET1 12:8 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET1_NONE 0x00000010 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET1_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET1_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET1_CH2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_BEACON2 20:16 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL2_BEACON2_NONE 0x00000010 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL2_BEACON2_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_BEACON2_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_BEACON2_CH2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET2 28:24 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET2_NONE 0x00000010 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET2_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET2_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET2_CH2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL2_BEACON(i) ((i)*16+4):((i)*16) /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON__SIZE_1 2 /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET(i) ((i)*16+12):((i)*16+8) /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET__SIZE_1 2 /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON_NONE 0x00000010 /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON_CH(i) 0x00000000+(i) /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET_NONE 0x00000010 /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET_CH(i) 0x00000000+(i) /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON1_CH(i) 0x00000000+(i) /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON1_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON2_CH(i) 0x00000000+(i) /* */
|
|
#define NV_THERM_ADC_CTRL2_BEACON2_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET1_CH(i) 0x00000000+(i) /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET1_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET2_CH(i) 0x00000000+(i) /* */
|
|
#define NV_THERM_ADC_CTRL2_OFFSET2_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_CTRL3 0x000206c8 /* RW-4R */
|
|
#define NV_THERM_ADC_CTRL3__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_CTRL3_BEACON1_THRESH 10:0 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL3_BEACON1_THRESH_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL3_BEACON1_COMP 11:11 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL3_BEACON1_COMP_GT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL3_BEACON1_COMP_LT 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL3_BEACON2_THRESH 26:16 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL3_BEACON2_THRESH_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL3_BEACON2_COMP 27:27 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL3_BEACON2_COMP_GT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_CTRL3_BEACON2_COMP_LT 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_CTRL3_BEACON_THRESH(i) ((i)*16+10):((i)*16) /* */
|
|
#define NV_THERM_ADC_CTRL3_BEACON_THRESH__SIZE_1 2 /* */
|
|
#define NV_THERM_ADC_CTRL3_BEACON_COMP(i) ((i)*16+11):((i)*16+11) /* */
|
|
#define NV_THERM_ADC_CTRL3_BEACON_COMP__SIZE_1 2 /* */
|
|
#define NV_THERM_ADC_CTRL3_BEACON_COMP_GT 0x00000000 /* */
|
|
#define NV_THERM_ADC_CTRL3_BEACON_COMP_LT 0x00000001 /* */
|
|
#define NV_THERM_ADC_CTRL4 0x00020590 /* RW-4R */
|
|
#define NV_THERM_ADC_CTRL4__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_CTRL4_NEG2POS_BIAS 10:0 /* RWIUF */
|
|
#define NV_THERM_ADC_CTRL4_NEG2POS_BIAS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP 0x00020594 /* RW-4R */
|
|
#define NV_THERM_ADC_OFFSET_MAP__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH0 1:0 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH0_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH0_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH0_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH1 3:2 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH1_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH1_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH1_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH2 5:4 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH2_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH2_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH2_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH3 7:6 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH3_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH3_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH3_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH4 9:8 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH4_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH4_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH4_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH5 11:10 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH5_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH5_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH5_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH6 13:12 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH6_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH6_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH6_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH7 15:14 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH7_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH7_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH7_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH8 17:16 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH8_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH8_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH8_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH9 19:18 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH9_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH9_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH9_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH10 21:20 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH10_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH10_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH10_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH11 23:22 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH11_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH11_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH11_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH12 25:24 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH12_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH12_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH12_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH13 27:26 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH13_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH13_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH13_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH14 29:28 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH14_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH14_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH14_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH15 31:30 /* RWIUF */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH15_NO_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH15_OFFSET1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH15_OFFSET2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH(i) ((i)*2+1):((i)*2) /* */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH_NO_OFFSET 0x00000000 /* */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH_OFFSET(i) ((i)+1) /* */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH_OFFSET__SIZE_1 2 /* */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH_OFFSET1 0x00000001 /* */
|
|
#define NV_THERM_ADC_OFFSET_MAP_CH_OFFSET2 0x00000002 /* */
|
|
#define NV_THERM_ADC_PWM 0x00020624 /* RW-4R */
|
|
#define NV_THERM_ADC_PWM__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_PWM_HI 11:0 /* RWIUF */
|
|
#define NV_THERM_ADC_PWM_HI_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ADC_PWM_PERIOD 27:16 /* RWIUF */
|
|
#define NV_THERM_ADC_PWM_PERIOD_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ADC_SW_RESET 0x00020628 /* RW-4R */
|
|
#define NV_THERM_ADC_SW_RESET__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_SW_RESET_RST 0:0 /* RWIUF */
|
|
#define NV_THERM_ADC_SW_RESET_RST_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ADC_SW_RESET_RST_CLEARED 0x00000000 /* R---V */
|
|
#define NV_THERM_ADC_SW_RESET_RST_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_ADC_SW_RESET_LENGTH 15:8 /* RWIUF */
|
|
#define NV_THERM_ADC_SW_RESET_LENGTH_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX 0x0002062c /* RW-4R */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX 2:0 /* RWIUF */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_MAX 0x00000007 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP0_CFG 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP1_CFG 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP2_CFG 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP3_CFG 0x00000003 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP4_CFG 0x00000004 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP5_CFG 0x00000005 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP6_CFG 0x00000006 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP7_CFG 0x00000007 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_READINCR 8:8 /* RWIUF */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_WRITEINCR 9:9 /* RWIUF */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP(i) (i) /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA 0x00020630 /* RW-4R */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA__APERTURE_INDEX_OFFSET (0x0002062c-0x00020630) /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE 31:0 /* RWIVF */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_OP1 3:0 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_OP2 19:16 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_ENABLE 31:31 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_ENABLE_OFF 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_ENABLE_ON 0x00000001 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP0_CFG_INIT 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP0_CFG_OP1 3:0 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP0_CFG_OP2 19:16 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP0_CFG_ENABLE 31:31 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP1_CFG_INIT 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP1_CFG_OP1 3:0 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP1_CFG_OP2 19:16 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP1_CFG_ENABLE 31:31 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP2_CFG_INIT 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP2_CFG_OP1 3:0 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP2_CFG_OP2 19:16 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP2_CFG_ENABLE 31:31 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP3_CFG_INIT 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP3_CFG_OP1 3:0 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP3_CFG_OP2 19:16 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP3_CFG_ENABLE 31:31 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP4_CFG_INIT 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP4_CFG_OP1 3:0 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP4_CFG_OP2 19:16 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP4_CFG_ENABLE 31:31 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP5_CFG_INIT 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP5_CFG_OP1 3:0 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP5_CFG_OP2 19:16 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP5_CFG_ENABLE 31:31 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP6_CFG_INIT 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP6_CFG_OP1 3:0 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP6_CFG_OP2 19:16 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP6_CFG_ENABLE 31:31 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP7_CFG_INIT 0x00000000 /* */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP7_CFG_OP1 3:0 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP7_CFG_OP2 19:16 /* RW--F */
|
|
#define NV_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP7_CFG_ENABLE 31:31 /* RW--F */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX 0x00020634 /* RW-4R */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX 3:0 /* RWIUF */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_MAX 0x0000000f /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH3 0x00000003 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH4 0x00000004 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH5 0x00000005 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH6 0x00000006 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH7 0x00000007 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH8 0x00000008 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH9 0x00000009 /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH10 0x0000000a /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH11 0x0000000b /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH12 0x0000000c /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH13 0x0000000d /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH14 0x0000000e /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH15 0x0000000f /* RW--V */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH(i) (i) /* */
|
|
#define NV_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_IIR_VALUE_DATA 0x00020638 /* R--4R */
|
|
#define NV_THERM_ADC_IIR_VALUE_DATA_VALUE 31:0 /* R--VF */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX 0x0002063c /* RW-4R */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX 5:0 /* RWIUF */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_MAX 0x0000002f /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH0_LB 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH0_UB 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH0_SMPCNT 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH1_LB 0x00000003 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH1_UB 0x00000004 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH1_SMPCNT 0x00000005 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH2_LB 0x00000006 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH2_UB 0x00000007 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH2_SMPCNT 0x00000008 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH3_LB 0x00000009 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH3_UB 0x0000000a /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH3_SMPCNT 0x0000000b /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH4_LB 0x0000000c /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH4_UB 0x0000000d /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH4_SMPCNT 0x0000000e /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH5_LB 0x0000000f /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH5_UB 0x00000010 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH5_SMPCNT 0x00000011 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH6_LB 0x00000012 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH6_UB 0x00000013 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH6_SMPCNT 0x00000014 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH7_LB 0x00000015 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH7_UB 0x00000016 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH7_SMPCNT 0x00000017 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH8_LB 0x00000018 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH8_UB 0x00000019 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH8_SMPCNT 0x0000001a /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH9_LB 0x0000001b /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH9_UB 0x0000001c /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH9_SMPCNT 0x0000001d /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH10_LB 0x0000001e /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH10_UB 0x0000001f /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH10_SMPCNT 0x00000020 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH11_LB 0x00000021 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH11_UB 0x00000022 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH11_SMPCNT 0x00000023 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH12_LB 0x00000024 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH12_UB 0x00000025 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH12_SMPCNT 0x00000026 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH13_LB 0x00000027 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH13_UB 0x00000028 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH13_SMPCNT 0x00000029 /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH14_LB 0x0000002a /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH14_UB 0x0000002b /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH14_SMPCNT 0x0000002c /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH15_LB 0x0000002d /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH15_UB 0x0000002e /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH15_SMPCNT 0x0000002f /* RW--V */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_LB_CH(i) ((i)*3) /* */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_LB_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_UB_CH(i) ((i)*3+1) /* */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_UB_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_SMPCNT_CH(i) ((i)*3+2) /* */
|
|
#define NV_THERM_ADC_ACC_VALUE_INDEX_INDEX_SMPCNT_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_ADC_ACC_VALUE_DATA 0x00020640 /* R--4R */
|
|
#define NV_THERM_ADC_ACC_VALUE_DATA_VALUE 31:0 /* R--VF */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX 0x00020644 /* RW-4R */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX 2:0 /* RWIUF */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_MAX 0x00000007 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP0 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP1 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP2 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP3 0x00000003 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP4 0x00000004 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP5 0x00000005 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP6 0x00000006 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP7 0x00000007 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP(i) (i) /* */
|
|
#define NV_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_ADC_MUL_VALUE_DATA 0x00020648 /* R--4R */
|
|
#define NV_THERM_ADC_MUL_VALUE_DATA_VALUE 31:0 /* R--VF */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX 0x0002064c /* RW-4R */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX 4:0 /* RWIUF */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_MAX 0x00000017 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP0_LB 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP0_UB 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP0_SMPCNT 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP1_LB 0x00000003 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP1_UB 0x00000004 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP1_SMPCNT 0x00000005 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP2_LB 0x00000006 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP2_UB 0x00000007 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP2_SMPCNT 0x00000008 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP3_LB 0x00000009 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP3_UB 0x0000000a /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP3_SMPCNT 0x0000000b /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP4_LB 0x0000000c /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP4_UB 0x0000000d /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP4_SMPCNT 0x0000000e /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP5_LB 0x0000000f /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP5_UB 0x00000010 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP5_SMPCNT 0x00000011 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP6_LB 0x00000012 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP6_UB 0x00000013 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP6_SMPCNT 0x00000014 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP7_LB 0x00000015 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP7_UB 0x00000016 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP7_SMPCNT 0x00000017 /* RW--V */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_LB_CHP(i) ((i)*3) /* */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_LB_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_UB_CHP(i) ((i)*3+1) /* */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_UB_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_SMPCNT_CHP(i) ((i)*3+2) /* */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_SMPCNT_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_DATA 0x00020650 /* R--4R */
|
|
#define NV_THERM_ADC_MUL_ACC_VALUE_DATA_VALUE 31:0 /* R--VF */
|
|
#define NV_THERM_IPC_CTRL(i) (0x00020654+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_IPC_CTRL__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_OP 5:0 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_OP_CH0 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH2 0x00000002 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH3 0x00000003 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH4 0x00000004 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH5 0x00000005 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH6 0x00000006 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH7 0x00000007 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH8 0x00000008 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH9 0x00000009 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH10 0x0000000a /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH11 0x0000000b /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH12 0x0000000c /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH13 0x0000000d /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH14 0x0000000e /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH15 0x0000000f /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP1 0x00000011 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP2 0x00000012 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP3 0x00000013 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP4 0x00000014 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP5 0x00000015 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP6 0x00000016 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP7 0x00000017 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_OP_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP(i) 16+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_OP_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_OP_BA_W(i) (24+(i)) /* */
|
|
#define NV_THERM_IPC_CTRL_OP_BA_W__SIZE_1 3 /* */
|
|
#define NV_THERM_IPC_CTRL_OP_SUM(i) (27+(i)) /* */
|
|
#define NV_THERM_IPC_CTRL_OP_SUM__SIZE_1 2 /* */
|
|
#define NV_THERM_IPC_CTRL_OP_BA_W0 0x00000018 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_BA_W1 0x00000019 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_BA_W2 0x0000001a /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_SUM1 0x0000001b /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_OP_SUM2 0x0000001c /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_EN 31:31 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_EN_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_INDEX 0x000204f8 /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX 7:0 /* RWIVF */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_HEADER 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_MAX 0x00000043 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_RAUTOINCR 8:8 /* RWIVF */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_RAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_WAUTOINCR 9:9 /* RWIVF */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_WAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_AX0_AY_DS_IPC(i) ((i)*17) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_AX0_AY_DS_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_AX1_AX2_IPC(i) ((i)*17+1) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_AX1_AX2_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_AY1_AY2_IPC(i) ((i)*17+2) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_AY1_AY2_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_A_FLOOR_IPC(i) ((i)*17+3) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_A_FLOOR_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_A_CEIL_IPC(i) ((i)*17+4) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_A_CEIL_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_BX0_BY_DS_IPC(i) ((i)*17+5) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_BX0_BY_DS_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_BX1_BX2_IPC(i) ((i)*17+6) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_BX1_BX2_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_BY1_BY2_IPC(i) ((i)*17+7) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_BY1_BY2_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_B_FLOOR_IPC(i) ((i)*17+8) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_B_FLOOR_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_B_CEIL_IPC(i) ((i)*17+9) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_B_CEIL_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_CX0_CY_DS_IPC_DS_IPC(i) ((i)*17+10) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_CX0_CY_DS_IPC_DS_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_CX1_CX2_IPC(i) ((i)*17+11) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_CX1_CX2_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_CY1_CY2_IPC(i) ((i)*17+12) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_CY1_CY2_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_C_FLOOR_IPC(i) ((i)*17+13) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_C_FLOOR_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_C_CEIL_IPC(i) ((i)*17+14) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_C_CEIL_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_LAST_FLOOR_C_TARGET_IPC(i) ((i)*17+15) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_LAST_FLOOR_C_TARGET_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_LAST_CEIL_INTEGRATOR_IPC(i) ((i)*17+16) /* */
|
|
#define NV_THERM_IPC_CTRL_INDEX_INDEX_LAST_CEIL_INTEGRATOR_IPC__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA 0x000204fc /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_DATA__APERTURE_INDEX_OFFSET (0x000004f8-0x000004fc) /* */
|
|
#define NV_THERM_IPC_CTRL_DATA__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE 23:0 /* RWIVF */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE__INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_AX0 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_AY_DS 15:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_AX1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_AX2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_AY1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_AY2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_A_FLOOR 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_A_CEIL 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_BX0 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_BY_DS 15:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_BX1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_BX2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_BY1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_BY2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_B_FLOOR 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_B_CEIL 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_CX0 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_CY_DS 15:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_IPC_DS 20:16 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_CX1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_CX2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_CY1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_CY2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_C_FLOOR 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_C_CEIL 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_LAST_FLOOR 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_C_TARGET 20:20 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_C_TARGET_PRE 0x00000000 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_C_TARGET_POST 0x00000001 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_LAST_CEIL 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_LAST_INTEGRATOR 20:20 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_LAST_INTEGRATOR_DIS 0x00000000 /* */
|
|
#define NV_THERM_IPC_CTRL_DATA_VALUE_LAST_INTEGRATOR_EN 0x00000001 /* */
|
|
#define NV_THERM_IPC_REF(i) (0x00020664+((i)*4)) /* RW-4A */
|
|
#define NV_THERM_IPC_REF__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_REF__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_REF_VALUE 31:0 /* RWIUF */
|
|
#define NV_THERM_IPC_REF_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT 0x00020574 /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1 7:0 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_NO_CH 0x000000ff /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2 15:8 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_NO_CH 0x000000ff /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3 23:16 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_NO_CH 0x000000ff /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4 31:24 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_NO_CH 0x000000ff /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT(i) ((i)*8+7):((i)*8) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_INPUT__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_NO_CH 0x000000ff /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_INPUT_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT 0x00020578 /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1 7:0 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_NO_CH 0x000000ff /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2 15:8 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_NO_CH 0x000000ff /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3 23:16 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_NO_CH 0x000000ff /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4 31:24 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_NO_CH 0x000000ff /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CH0 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CH1 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CHP0 0x00000010 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT(i) ((i)*8+7):((i)*8) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_INPUT__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_NO_CH 0x000000ff /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_CH(i) (i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_CH__SIZE_1 16 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_CHP(i) 0x00000010+(i) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_INPUT_CHP__SIZE_1 8 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF 0x0002057c /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF1 7:0 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF2 15:8 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF3 23:16 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF4 31:24 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF(i) ((i)*8+7):((i)*8) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM1_SF_SF__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF 0x00020580 /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF1 7:0 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF2 15:8 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF3 23:16 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF4 31:24 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF(i) ((i)*8+7):((i)*8) /* */
|
|
#define NV_THERM_IPC_CTRL_SUM2_SF_SF__SIZE_1 4 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX 0x00020480 /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX 5:0 /* RWIVF */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_HEADER 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_MAX 0x00000009 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_SEED_UPPER 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_SEED_LOWER 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_SEED_VALUE_REPEAT 0x00000002 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_AX0_AY_DS 0x00000003 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_AX1_AX2 0x00000004 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_AY1_AY2 0x00000005 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_BX0_BY_DS 0x00000006 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_BX1_BX2 0x00000007 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_BY1_BY2 0x00000008 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_INDEX_VID_DOWNSHIFT 0x00000009 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_RAUTOINCR 6:6 /* RWIVF */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_RAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_WAUTOINCR 7:7 /* RWIVF */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_FA_INDEX_WAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA 0x00020484 /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA__APERTURE_INDEX_OFFSET (0x00000480-0x00000484) /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE 31:0 /* RWIVF */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE__INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_SEED_UPPER 31:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_SEED_LOWER 31:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_SEED_VALUE 19:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_SEED_REPEAT 31:20 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_AX0 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_AY_DS 15:12 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_AX1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_AX2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_AY1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_AY2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_BX0 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_BY_DS 15:12 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_BX1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_BX2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_BY1 11:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_BY2 23:12 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_DATA_VALUE_VID_DOWNSHIFT 4:0 /* */
|
|
#define NV_THERM_IPC_CTRL_FA 0x00020584 /* RW-4R */
|
|
#define NV_THERM_IPC_CTRL_FA__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_SNAP 27:27 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_SNAP_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_SNAP_NOT_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_SNAP_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_MODE 28:28 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_MODE_CONTINUOUS 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_MODE_SNAP 0x00000001 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_CLEAR 29:29 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_CLEAR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_CLEAR_DONE 0x00000000 /* R---V */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_CLEAR_NOT_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_IPC_CTRL_FA_ACC_CLEAR_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_IPC_CTRL_FA_GEN_UPDATE 30:30 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_FA_GEN_UPDATE_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_IPC_CTRL_FA_GEN_UPDATE_NOT_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_IPC_CTRL_FA_GEN_UPDATE_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_IPC_CTRL_FA_EN 31:31 /* RWIUF */
|
|
#define NV_THERM_IPC_CTRL_FA_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_CTRL_FA_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX 0x000205f8 /* RW-4R */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX 5:0 /* RWIUF */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_MAX 0x00000008 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_PRE_S1_UB 0x00000000 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_PRE_S1_LB 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_PRE_S2_UB 0x00000002 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_PRE_S2_LB 0x00000003 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_POST_S1_UB 0x00000004 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_POST_S1_LB 0x00000005 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_POST_S2_UB 0x00000006 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_POST_S2_LB 0x00000007 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_COUNT 0x00000008 /* RW--V */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA 0x000205fc /* R--4R */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA__APERTURE_INDEX_OFFSET (0x000005f8-0x000005fc) /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE 31:0 /* R--VF */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_COUNT 31:0 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_PRE_S1_UB 31:0 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_PRE_S1_LB 31:0 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_PRE_S2_UB 31:0 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_PRE_S2_LB 31:0 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_POST_S1_UB 31:0 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_POST_S1_LB 31:0 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_POST_S2_UB 31:0 /* */
|
|
#define NV_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_POST_S2_LB 31:0 /* */
|
|
#define NV_THERM_IPC_DEBUG 0x00020690 /* RW-4R */
|
|
#define NV_THERM_IPC_DEBUG__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_IPC_DEBUG_IPC_HI_OFFSET_OVERRIDE 12:0 /* RWIUF */
|
|
#define NV_THERM_IPC_DEBUG_IPC_HI_OFFSET_OVERRIDE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_DEBUG_IPC_OVERRIDE_EN 13:13 /* RWIUF */
|
|
#define NV_THERM_IPC_DEBUG_IPC_OVERRIDE_EN_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_DEBUG_IPC_OVERRIDE_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_DEBUG_SEL_IDX 16:14 /* RWIUF */
|
|
#define NV_THERM_IPC_DEBUG_SEL_IDX_HI_OFFSET 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_DEBUG_SEL_IDX_PWM0_HI_ACTIVE 0x00000001 /* RW--V */
|
|
#define NV_THERM_IPC_DEBUG_SEL_IDX_PWM1_HI_ACTIVE 0x00000002 /* RW--V */
|
|
#define NV_THERM_IPC_DEBUG_SEL_IDX_PWM2_HI_ACTIVE 0x00000003 /* RW--V */
|
|
#define NV_THERM_IPC_DEBUG_SEL_IDX_PWM3_HI_ACTIVE 0x00000004 /* RW--V */
|
|
#define NV_THERM_IPC_DEBUG_SEL_VAL 29:17 /* R--UF */
|
|
#define NV_THERM_IPC_DEBUG_SNAP 30:30 /* RWIUF */
|
|
#define NV_THERM_IPC_DEBUG_SNAP_DONE 0x00000000 /* R-I-V */
|
|
#define NV_THERM_IPC_DEBUG_SNAP_NOT_DONE 0x00000001 /* R---V */
|
|
#define NV_THERM_IPC_DEBUG_SNAP_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_IPC_DEBUG_MODE_CTRL 31:31 /* RWIUF */
|
|
#define NV_THERM_IPC_DEBUG_MODE_CTRL_CONTINUOUS 0x00000000 /* RWI-V */
|
|
#define NV_THERM_IPC_DEBUG_MODE_CTRL_SNAP 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_DEBUG 0x00020694 /* RW-4R */
|
|
#define NV_THERM_ADC_DEBUG__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_DEBUG_MIN_ADC 10:0 /* RWIUF */
|
|
#define NV_THERM_ADC_DEBUG_MIN_ADC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_DEBUG_MAX_ADC 21:11 /* RWIUF */
|
|
#define NV_THERM_ADC_DEBUG_MAX_ADC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_DEBUG_STEP_PERIOD 26:23 /* RWIUF */
|
|
#define NV_THERM_ADC_DEBUG_STEP_PERIOD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_DEBUG_MODE 31:29 /* RWIUF */
|
|
#define NV_THERM_ADC_DEBUG_MODE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_ADC_DEBUG_MODE_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_THERM_ADC_DEBUG_MODE_INC 0x00000001 /* RW--V */
|
|
#define NV_THERM_ADC_DEBUG_MODE_DEC 0x00000002 /* RW--V */
|
|
#define NV_THERM_ADC_DEBUG_MODE_CMOV 0x00000003 /* RW--V */
|
|
#define NV_THERM_ADC_DEBUG_MODE_SW_OVERRIDE 0x00000004 /* RW--V */
|
|
#define NV_THERM_ADC_DEBUG2 0x000206fc /* RW-4R */
|
|
#define NV_THERM_ADC_DEBUG2__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_ADC_DEBUG2_SW_FORCED_ADC 10:0 /* RWIUF */
|
|
#define NV_THERM_ADC_DEBUG2_SW_FORCED_ADC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL 0x00020698 /* RW-4R */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SM_CNT_THRESHOLD 7:0 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SM_CNT_THRESHOLD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SM_CNT_THRESHOLD_1 15:8 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SM_CNT_THRESHOLD_1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT 16:16 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_1 17:17 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_1_OFF 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_1_ON 0x00000001 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SEL_ADC 20:20 /* RWIVF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SEL_ADC_SYS_ADC 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SEL_ADC_GPC_ADC_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_IIR_LENGTH 27:24 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_IIR_LENGTH_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_IIR_LENGTH_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_IIR_LENGTH_MAX 0x00000009 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_MODE_SEL 29:28 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_MODE_SEL_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_MODE_SEL_VIDPWM_DLY 0x00000001 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_MODE_SEL_NAFLL_ADC 0x00000002 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_MODE_SEL_SW 0x00000003 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SW_ISSUE_OK 30:30 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SW_ISSUE_OK_LOW 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_SW_ISSUE_OK_HIGH 0x00000001 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_IGNORE_SM_CNT_THRESHOLD 31:31 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_IGNORE_SM_CNT_THRESHOLD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_CTRL_IGNORE_SM_CNT_THRESHOLD_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_SM_HIGH_POWER_HYSTERESIS 0x0002069c /* RW-4R */
|
|
#define NV_THERM_SM_HIGH_POWER_HYSTERESIS__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_SM_HIGH_POWER_HYSTERESIS_CNT 31:0 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_HYSTERESIS_CNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SM_HIGH_POWER_HYSTERESIS_1 0x000206b0 /* RW-4R */
|
|
#define NV_THERM_SM_HIGH_POWER_HYSTERESIS_1__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_SM_HIGH_POWER_HYSTERESIS_1_CNT 31:0 /* RWIUF */
|
|
#define NV_THERM_SM_HIGH_POWER_HYSTERESIS_1_CNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SAFE_VOLTAGE_CFG 0x000206a0 /* RW-4R */
|
|
#define NV_THERM_SAFE_VOLTAGE_CFG__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_SAFE_VOLTAGE_CFG_NAFLL_ADC 15:0 /* RWIUF */
|
|
#define NV_THERM_SAFE_VOLTAGE_CFG_NAFLL_ADC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SAFE_VOLTAGE_CFG_DELAY 31:16 /* RWIUF */
|
|
#define NV_THERM_SAFE_VOLTAGE_CFG_DELAY_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_SAFE_VOLTAGE_DEBUG 0x000206a8 /* R--4R */
|
|
#define NV_THERM_SAFE_VOLTAGE_DEBUG__PRIV_LEVEL_MASK 0x000203b4 /* */
|
|
#define NV_THERM_SAFE_VOLTAGE_DEBUG_NAFLL_ADC_IIR 15:0 /* R--VF */
|
|
#define NV_THERM_SAFE_VOLTAGE_DEBUG_NAFLL_ADC_RAW 22:16 /* R--VF */
|
|
#define NV_THERM_DLPPE_NNET 0x00020884 /* RW-4R */
|
|
#define NV_THERM_DLPPE_NNET__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ 2:0 /* RWIVF */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_DONE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_0_IN_PROG 0x00000001 /* R---V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_1_IN_PROG 0x00000002 /* R---V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_2_IN_PROG 0x00000003 /* R---V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_3_IN_PROG 0x00000004 /* R---V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_4_IN_PROG 0x00000005 /* R---V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_5_IN_PROG 0x00000006 /* R---V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_6_IN_PROG 0x00000007 /* R---V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_0_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_1_TRIGGER 0x00000002 /* -W--T */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_2_TRIGGER 0x00000003 /* -W--T */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_3_TRIGGER 0x00000004 /* -W--T */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_4_TRIGGER 0x00000005 /* -W--T */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_5_TRIGGER 0x00000006 /* -W--T */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK_6_TRIGGER 0x00000007 /* -W--T */
|
|
#define NV_THERM_DLPPE_NNET_LOOP_START 12:8 /* RWIUF */
|
|
#define NV_THERM_DLPPE_NNET_LOOP_START_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_NNET_LOOP_START_MAX 0x0000001f /* RW--V */
|
|
#define NV_THERM_DLPPE_NNET_LOOP_END 20:16 /* RWIUF */
|
|
#define NV_THERM_DLPPE_NNET_LOOP_END_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_NNET_LOOP_END_MAX 0x0000001f /* RW--V */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK(i) ((i)+1) /* */
|
|
#define NV_THERM_DLPPE_NNET_ID_REQ_NETWORK__SIZE_1 7 /* */
|
|
#define NV_THERM_DLPPE_CFG 0x00020888 /* RW-4R */
|
|
#define NV_THERM_DLPPE_CFG__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_CFG_ROUNDING_MODE 2:0 /* RWIVF */
|
|
#define NV_THERM_DLPPE_CFG_ROUNDING_MODE_TO_NEAREST_EVEN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_CFG_ROUNDING_MODE_TOWARDS_ZERO 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_CFG_ROUNDING_MODE_TOWARDS_POSITIVE_INFINITY 0x00000002 /* RW--V */
|
|
#define NV_THERM_DLPPE_CFG_ROUNDING_MODE_TOWARDS_NEGATIVE_INFINITY 0x00000003 /* RW--V */
|
|
#define NV_THERM_DLPPE_CFG_ROUNDING_MODE_TO_NEAREST_UP 0x00000004 /* RW--V */
|
|
#define NV_THERM_DLPPE_CFG_ROUNDING_MODE_AWAY_FROM_ZERO 0x00000005 /* RW--V */
|
|
#define NV_THERM_DLPPE_CFG_CLAMP_INFINITY_TO_NORMAL 3:3 /* RWIVF */
|
|
#define NV_THERM_DLPPE_CFG_CLAMP_INFINITY_TO_NORMAL_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_CFG_CLAMP_INFINITY_TO_NORMAL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR 0x000208a0 /* RW-4R */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_ADDR 8:0 /* RWIUF */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_ADDR_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_ADDR_HEADER 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_ADDR_MAX 0x000001fc /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_RAUTOINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_RAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_WAUTOINCR 31:31 /* RWIVF */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_DSCR_ADDR_RAM_WAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA 0x000208a4 /* RW-4R */
|
|
#define NV_THERM_DLPPE_DSCR_DATA__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_RAM_DATA 31:0 /* RWXUF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_HEADER_NUM_NETWORKS 7:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_HEADER_NUM_NETWORKS_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_HEADER_NUM_NETWORKS_MAX 0x00000007 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_HEADER_VERSION 31:28 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_NUM_LAYERS 7:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_NUM_LAYERS_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_NUM_LAYERS_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_NUM_LAYERS_MAX 0x0000001f /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_LOOP_MAX 15:8 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_LOOP_MAX_INDEX_0 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_LOOP_MAX_INDEX_MAX 0x0000001f /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_STATUS_OFFSET 31:16 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_STATUS_OFFSET_MAX 0x000007fc /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_NEURONS 15:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_NEURONS_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_NEURONS_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_NEURONS_MAX 0x0000007f /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_INPUTS 31:16 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_INPUTS_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_INPUTS_MIN 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_INPUTS_MAX 0x000000ff /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D1_SWIZZLE_OFFSET 15:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D1_SWIZZLE_OFFSET_MAX 0x000007fc /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D1_WEIGHT_OFFSET 31:16 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D1_WEIGHT_OFFSET_MAX 0x00007ffe /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D2_OUTPUT_OFFSET 15:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D2_OUTPUT_OFFSET_MAX 0x000007fc /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D2_ACTIVATION_OFFSET 31:16 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D2_ACTIVATION_OFFSET_MAX 0x00007ffe /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_OUTPUT_STRIDE 0:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_OUTPUT_STRIDE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_OUTPUT_STRIDE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_STRIDE 1:1 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_STRIDE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_STRIDE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_FORMAT 2:2 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_FORMAT_FP32 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_FORMAT_FP16 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL 19:16 /* RW-UF */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL_RELU 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL_LEAKY_RELU 0x00000002 /* RW--V */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR 0x000208a8 /* RW-4R */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_ADDR 10:0 /* RWIUF */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_ADDR_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_ADDR_MAX 0x000007fc /* RW--V */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_RAUTOINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_RAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_WAUTOINCR 31:31 /* RWIVF */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_SWZL_ADDR_RAM_WAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_SWZL_DATA 0x000208ac /* RW-4R */
|
|
#define NV_THERM_DLPPE_SWZL_DATA__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_SWZL_DATA_INPUT_POINTER 10:0 /* RWXUF */
|
|
#define NV_THERM_DLPPE_SWZL_DATA_INPUT_POINTER_MIN 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_SWZL_DATA_INPUT_POINTER_MAX 0x000007fc /* RW--V */
|
|
#define NV_THERM_DLPPE_SWZL_DATA_INPUT_STRIDE 26:16 /* RWXUF */
|
|
#define NV_THERM_DLPPE_SWZL_DATA_INPUT_STRIDE_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_SWZL_DATA_INPUT_STRIDE_MAX 0x000007fc /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_ADDR 0x000208b0 /* RW-4R */
|
|
#define NV_THERM_DLPPE_PARM_ADDR__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_ADDR 10:0 /* RWIUF */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_ADDR_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_ADDR_MAX 0x000007fc /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_RAUTOINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_RAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_WAUTOINCR 31:31 /* RWIVF */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_PARM_ADDR_RAM_WAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA 0x000208b4 /* RW-4R */
|
|
#define NV_THERM_DLPPE_PARM_DATA__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_PARM_DATA_RAM_DATA 31:0 /* RWXUF */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP32_DATA 31:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTIONS 3:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTIONS_NONE 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INVALID 0:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INVALID_NOT_PENDING 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INVALID_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_UNDERFLOW 1:1 /* RW-UF */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_UNDERFLOW_NOT_PENDING 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_UNDERFLOW_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_OVERFLOW 2:2 /* RW-UF */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_OVERFLOW_NOT_PENDING 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_OVERFLOW_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INEXACT 3:3 /* RW-UF */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INEXACT_NOT_PENDING 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INEXACT_PENDING 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR 0x000208b8 /* RW-4R */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_ADDR 14:0 /* RWIUF */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_ADDR_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_ADDR_MAX 0x00007ffc /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_RAUTOINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_RAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_WAUTOINCR 31:31 /* RWIVF */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_DLPPE_WEIGHT_ADDR_RAM_WAUTOINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA 0x000208bc /* RW-4R */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA__PRIV_LEVEL_MASK 0x00020880 /* */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_RAM_DATA 31:0 /* RWXUF */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_NEGATIVE_INFINITY 0xff800000 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_NEGATIVE_ONE 0xbf800000 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_NEGATIVE_ZERO 0x80000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_POSITIVE_ZERO 0x00000000 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_POSITIVE_ONE 0x3f800000 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_POSITIVE_INFINITY 0x7f800000 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_NAN 0x7f800001 /* RW--V */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_FP16_DATA_0 15:0 /* RW-UF */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_FP16_DATA_1 31:16 /* RW-UF */
|
|
#define NV_THERM_DLPPE_WEIGHT_DATA_FP32_DATA 31:0 /* RW-UF */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK 0x000208c0 /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "tsense" /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_CONFIG_COPY 0x000208c4 /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE_CONFIG_COPY__PRIV_LEVEL_MASK 0x000208c0 /* */
|
|
#define NV_THERM_NVL_TSENSE_CONFIG_COPY_NEW_SETTING 31:31 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_CONFIG_COPY_NEW_SETTING_NO_CMD 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_CONFIG_COPY_NEW_SETTING_SEND 0x00000001 /* RW--T */
|
|
#define NV_THERM_NVL_TSENSE 0x000208c8 /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE__PRIV_LEVEL_MASK 0x000208c0 /* */
|
|
#define NV_THERM_NVL_TSENSE_TS_ADC_OUT 13:0 /* R--VF */
|
|
#define NV_THERM_NVL_TSENSE_STREAM_RAW_CODE 16:16 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_STREAM_RAW_CODE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_STREAM_RAW_CODE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_TS_BJT_SEL 23:20 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_TS_BJT_SEL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_TS_PD 24:24 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_TS_PD_DEASSERT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_TS_PD_ASSERT 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_CONTROL_SRC 28:28 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_CONTROL_SRC_LOGIC 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_CONTROL_SRC_REG 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_CALI_SRC 29:29 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_CALI_SRC_FUSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_CALI_SRC_REG 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_TC_SRC 30:30 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_TC_SRC_FUSE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_TC_SRC_REG 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ 0x000208cc /* RW-4R */
|
|
#define NV_THERM_NVL_TS_ADJ__PRIV_LEVEL_MASK 0x000208c0 /* */
|
|
#define NV_THERM_NVL_TS_ADJ_VALUE 31:0 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_VALUE_INIT 0x00007240 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_VOLT 7:0 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_VOLT_INIT 0x00000040 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_TEMP_COEF 10:8 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_TEMP_COEF_INIT 0x00000002 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_MODE 11:11 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_MODE_AVG 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_MODE_NO_AVG 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_VPTAT_BIAS_CURRENT 13:12 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_VPTAT_BIAS_CURRENT_INIT 0x00000003 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_BYPASS 14:14 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_BYPASS_NO 0x00000000 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_BYPASS_YES 0x00000001 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_STARTUP_BIAS_CURRENT 15:15 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_BANDGAP_STARTUP_BIAS_CURRENT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT 19:16 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_TRISTATE 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_GND 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VBG 0x00000002 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VPTAT 0x00000003 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_SELA_2 0x00000004 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_IB0 0x00000006 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_IPTAT 0x00000008 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_IBG 0x00000009 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VDD 0x0000000c /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VMID 0x0000000d /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VDD1V8_IN 0x0000000e /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_PLL_ADC_TEST_IN 0x0000000f /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_PTAT_BIPOLAR_SWAP 20:20 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_PTAT_BIPOLAR_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_PTAT_BIPOLAR_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_PTAT_OPAMP_SWAP 21:21 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_PTAT_OPAMP_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_PTAT_OPAMP_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_PTAT_SOURCE 25:22 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_PTAT_SOURCE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_STOP_SWAP 26:26 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_STOP_SWAP_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_STOP_SWAP_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_BYPASS_PTAT 27:27 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_BYPASS_PTAT_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_BYPASS_PTAT_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_SEND_VBG 28:28 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_SEND_VBG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_AVERAGE_VBG 29:29 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_AVERAGE_VBG_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_AVERAGE_VBG_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_ADJ_START_BANDGAP 30:30 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_START_BANDGAP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_ADJ_STOP_SWAPPING_BJT 31:31 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_ADJ_STOP_SWAPPING_BJT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_RAWCODE_OVERRIDE 0x000208d0 /* RW-4R */
|
|
#define NV_THERM_NVL_RAWCODE_OVERRIDE__PRIV_LEVEL_MASK 0x000208c0 /* */
|
|
#define NV_THERM_NVL_RAWCODE_OVERRIDE_VALUE 13:0 /* RWIUF */
|
|
#define NV_THERM_NVL_RAWCODE_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_RAWCODE_OVERRIDE_EN 16:16 /* RWIUF */
|
|
#define NV_THERM_NVL_RAWCODE_OVERRIDE_EN_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_RAWCODE_OVERRIDE_EN_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL 0x000208d4 /* RW-4R */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL__PRIV_LEVEL_MASK 0x000208c0 /* */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL_SAMPLE_DELAY 13:0 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL_SAMPLE_DELAY_INIT 0x00000834 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL_AUTO_POLLING 15:15 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL_AUTO_POLLING_OFF 0x00000000 /* RW--V */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL_AUTO_POLLING_ON 0x00000001 /* RWI-V */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL_POLLING_INTERVAL 31:16 /* RWIUF */
|
|
#define NV_THERM_NVL_TS_AUTO_CONTROL_POLLING_INTERVAL_INIT 0x0000005a /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_INDEX 0x000208d8 /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_INDEX 0:0 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_INDEX_MAX 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_READINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE 0x000208dc /* R--4R */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE__APERTURE_INDEX_OFFSET (0x000008d8-0x000008dc) /* */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE_VALUE 13:0 /* R--VF */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_NVL_TSENSE_RAW_CODE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE 0x000208e0 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE__APERTURE_INDEX_OFFSET (0x000008d8-0x000008e0) /* */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE 0x000208e4 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE__APERTURE_INDEX_OFFSET (0x000008d8-0x000008e4) /* */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX 0x0002010c /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_INDEX 0:0 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_INDEX_MAX 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_READINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_WRITEINCR 31:31 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE 0x0002011c /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE__APERTURE_INDEX_OFFSET (0x0000010c-0x0000011c) /* */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE__PRIV_LEVEL_MASK 0x00020328 /* */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_RSVD 14:0 /* C--VF */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_TEMP_SELECT 15:15 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_TEMP_SELECT_REAL 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_TEMP_SELECT_OVERRIDE 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_TEMP_VALUE 29:16 /* RWISF */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_TEMP_VALUE_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_TEMP_INTEGER 29:21 /* */
|
|
#define NV_THERM_NVL_TSENSE_OVERRIDE_TEMP_INTEGER_ZERO 0x00000000 /* */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX 0x00020030 /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX__PRIV_LEVEL_MASK 0x000208c0 /* */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_INDEX 0:0 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_INDEX_MAX 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_READINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_WRITEINCR 31:31 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET 0x00020048 /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET__APERTURE_INDEX_OFFSET (0x00000030-0x00000048) /* */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET__PRIV_LEVEL_MASK 0x000208c0 /* */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_FIXED_POINT 16:3 /* RWISF */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_FIXED_POINT_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_HS_OFFSET_INTEGER 16:8 /* */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL 0x00020058 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL_TIMEOUT_PERIOD 7:0 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL_TIMEOUT_PERIOD_INIT 0x0000003c /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL_UPDATE_PERIOD 15:8 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL_UPDATE_PERIOD_INIT 0x0000001e /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL 0x000201dc /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL__PRIV_LEVEL_MASK 0x000206c0 /* */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_RAMP_UP_STEP 13:0 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_RAMP_UP_STEP_INIT 0x000000a0 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_RAMP_DOWN_STEP 27:14 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_RAMP_DOWN_STEP_INIT 0x000000a0 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_AVG_SRC 28:28 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_AVG_SRC_UNMUNGED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_AVG_SRC_MUNGED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_MAX_SRC 29:29 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_MAX_SRC_UNMUNGED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_MAX_SRC_MUNGED 0x00000001 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_ENABLE 31:31 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INTERPOLATION_CTRL_ENABLE_YES 0x00000001 /* RW--V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED 0x000203b8 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG 0x000203bc /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TSENSE_GLOBAL_SNAPSHOT 0x0002085c /* RW-4R */
|
|
#define NV_THERM_TSENSE_GLOBAL_SNAPSHOT_CMD 0:0 /* RWIVF */
|
|
#define NV_THERM_TSENSE_GLOBAL_SNAPSHOT_CMD_NO_CMD 0x00000000 /* RWI-V */
|
|
#define NV_THERM_TSENSE_GLOBAL_SNAPSHOT_CMD_TRIGGER 0x00000001 /* RW--T */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT 0x00020074 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT 0x00020104 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT 0x00020840 /* RW-4R */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_BJT_INDEX 3:0 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_BJT_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_BJT_INDEX_MAX 0x00000002 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_INDEX 19:16 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_INDEX_MAX 0x00000006 /* RW--V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_READINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_GPC_TSENSE_INDEX_SNAPSHOT_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT 0x00020844 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT 0x00020848 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT 0x0002013c /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT 0x0002014c /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT 0x0002084c /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT_INIT 0x00002000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER_INIT 0x00000100 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT 0x00020850 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT 0x00020854 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT_INIT 0x00002000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER 16:8 /* R-ISF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER_INIT 0x00000100 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT 0x00020858 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT 0x0002019c /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT 0x000201cc /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_MUNGED 24:24 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_SNAPSHOT 0x00020068 /* RW-4R */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_SNAPSHOT_INDEX 0:0 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_SNAPSHOT_INDEX_MIN 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_SNAPSHOT_INDEX_MAX 0x00000001 /* RW--V */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_SNAPSHOT_READINCR 30:30 /* RWIVF */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_SNAPSHOT_READINCR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_THERM_NVL_TSENSE_INDEX_SNAPSHOT_READINCR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT 0x0002006c /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT__APERTURE_INDEX_OFFSET (0x00000068-0x0000006c) /* */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT 0x00020070 /* R--4R */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT__APERTURE_INDEX_OFFSET (0x00000068-0x00000070) /* */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_INTEGER 16:8 /* R--SF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_MUNGED 24:24 /* R--VF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */
|
|
#define NV_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */
|
|
#endif // __ga102_dev_therm_h__
|