/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_pwr_csb_h__ #define __ga102_dev_pwr_csb_h__ /* This file is autogenerated. Do not edit */ #define NV_CPWR 0x01fff:0x00000 #define NV_CPWR_PMU_PG_ENG_NAMEMAP /* ----G */ #define NV_CPWR_PMU_PG_ENG_NAMEMAP_INDEX 3:0 /* RW-VF */ #define NV_CPWR_PMU_PG_ENG_NAMEMAP_INDEX_GR 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_ENG_NAMEMAP_INDEX_VD 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ENG_NAMEMAP_INDEX_MSPG 0x00000004 /* R---V */ #define NV_CPWR_PMU_PG_ENG_NAMEMAP_INDEX_DI 0x00000002 /* R---V */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT_SUCCEED 0x00000000 /* ----V */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT_FALCON_TOUT 0x00000001 /* ----V */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT_HOST_TOUT 0x00000002 /* ----V */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT_FECS_TOUT 0x00000003 /* ----V */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT_HOST_ERROR 0x00000004 /* ----V */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT_FECS_ERROR 0x00000005 /* ----V */ #define NV_CPWR_FALCON_EMEM_APERTURE_OFFSET 0x10000000 /* ----V */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY_GR_ELPG 1:1 /* ----F */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY_VD_ELPG 2:2 /* ----F */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY_FBIF 3:3 /* ----F */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY_CSBREG 4:4 /* ----F */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY_MS_ELPG 5:5 /* ----F */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY_BAR0MASTER 6:6 /* ----F */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY_SCP 7:7 /* ----F */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY_TIE0 15:8 /* ----F */ #define NV_CPWR_FALCON_FHSTATE_EXT_HALTED_GR_ELPG 1:1 /* ----F */ #define NV_CPWR_FALCON_FHSTATE_EXT_HALTED_VD_ELPG 2:2 /* ----F */ #define NV_CPWR_FALCON_FHSTATE_EXT_HALTED_FBIF 3:3 /* ----F */ #define NV_CPWR_FALCON_FHSTATE_EXT_HALTED_CSBREG 4:4 /* ----F */ #define NV_CPWR_FALCON_FHSTATE_EXT_HALTED_MS_ELPG 5:5 /* ----F */ #define NV_CPWR_FALCON_FHSTATE_EXT_HALTED_BAR0MASTER 6:6 /* ----F */ #define NV_CPWR_FALCON_FHSTATE_EXT_HALTED_TIE1 15:7 /* ----F */ #define NV_CPWR_PMU_IDLE_STATUS_VD 6:4 /* ----F */ #define NV_CPWR_PMU_IDLE_STATUS_FB 11:7 /* ----F */ #define NV_CPWR_PMU_IDLE_STATUS_AZA 15:13 /* ----F */ #define NV_CPWR_PMU_IDLE_STATUS_CE 21:19 /* ----F */ #define NV_CPWR_PMU_IDLE_STATUS_1_MS 4:2 /* ----F */ #define NV_CPWR_PMU_IDLE_STATUS_ENGINE 31:0 /* ----F */ #define NV_CPWR_PMU_IDLE_STATUS_ENGINE_BUSY 0x00000000 /* ----V */ #define NV_CPWR_PMU_IDLE_STATUS_ENGINE_IDLE 0xffffffff /* ----V */ #define NV_CPWR_PMU_IDLE_STATUS_1_ENGINE 31:0 /* ----F */ #define NV_CPWR_PMU_IDLE_STATUS_1_ENGINE_BUSY 0x00000000 /* ----V */ #define NV_CPWR_PMU_IDLE_STATUS_1_ENGINE_IDLE 0xffffffff /* ----V */ #define NV_CPWR_PMU_HISTOGRAM_BINS_IDX(histogramIdx,regIdx) (0x000008e0+(regIdx)*16+(histogramIdx)*4) /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS_IDX__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS_IDX__SIZE_2 8 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_ST(i) (4*(i)):(4*(i)) /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_ST__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_BUSY_SET(i) (1+4*(i)):(1+4*(i)) /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_BUSY_SET__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_BUSY_CLR(i) (2+4*(i)):(2+4*(i)) /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_BUSY_CLR__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_ST_IDLE 0 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_ST_BUSY 1 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_BUSY_SET_TRIGGER 1 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_BUSY_CLR_TRIGGER 1 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_BUSY_SET_INIT 0 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_ENG_BUSY_CLR_INIT 0 /* */ #define NV_CPWR_PMU_BAR0_EXT_STALL_ON_FECS_FAST_PATH 26:26 /* */ #define NV_CPWR_PMU_BAR0_EXT_STALL_ON_FECS_FAST_PATH_NO 0 /* */ #define NV_CPWR_PMU_BAR0_EXT_STALL_ON_FECS_FAST_PATH_YES 1 /* */ #define NV_CPWR_PMU_BAR0_EXT_USE_FECS_FAST_PATH 27:27 /* */ #define NV_CPWR_PMU_BAR0_EXT_USE_FECS_FAST_PATH_NO 0 /* */ #define NV_CPWR_PMU_BAR0_EXT_USE_FECS_FAST_PATH_YES 1 /* */ #define NV_CPWR_PMU_BAR0_EXT_USE_EMEM_APERTURE 28:28 /* */ #define NV_CPWR_PMU_BAR0_EXT_USE_EMEM_APERTURE_NO 0 /* */ #define NV_CPWR_PMU_BAR0_EXT_USE_EMEM_APERTURE_YES 1 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_ZONE_DELAY 3:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_ZONE_DELAY__WIDTH 4 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_FAST_MODE 4:4 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_FAST_MODE__WIDTH 1 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_FAST_MODE_EN 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_FAST_MODE_DIS 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_CLAMP_DELAY 13:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_CLAMP_DELAY__WIDTH 6 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_ZONE_DELAY 3:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_ZONE_DELAY__WIDTH 4 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_FAST_MODE 4:4 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_FAST_MODE__WIDTH 1 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_FAST_MODE_EN 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_FAST_MODE_DIS 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_RET_EN_DELAY 13:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_RET_EN_DELAY__WIDTH 6 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_GROUP_TOP_ORDER_GR_LOGIC 5:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_GROUP_TOP_ORDER_GR_RAM 13:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_GROUP_TOP_ORDER_MS_RAM 21:16 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_GROUP_TOP_ORDER_DI_RAM 28:24 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_INDEX 5:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_INDEX_MIN 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_READINCR 8:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_WRITEINCR 9:9 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ORDER 5:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ZONE_ORDER_SEL 9:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_EN 31:31 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_EN_INIT 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX 5:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR 8:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ORDER 5:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_EN 31:31 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_EN_INIT 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX 5:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR 8:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_EN 31:31 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_EN_INIT 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_INDEX 4:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_READINCR 8:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_EN 31:31 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_EN_INIT 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX 2:0 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT 0x00000000 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX 6:4 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT 0x00000001 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX 10:8 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT 0x00000002 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX 14:12 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT 0x00000003 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX 18:16 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT 0x00000004 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX 22:20 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT 0x00000005 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX 26:24 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT 0x00000006 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX 30:28 /* */ #define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT 0x00000007 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_MMODE 0x00000000 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_RISCV_CTL 0x00000001 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_PIC 0x00000002 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_TIMER 0x00000003 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_HOSTIF 0x00000004 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_DMA 0x00000005 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_PMB 0x00000006 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_DIO 0x00000007 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_KEY 0x00000008 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_DEBUG 0x00000009 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_SHA 0x0000000a /* */ #define NV_CPWR_DEVICE_MAP_GROUP_KMEM 0x0000000b /* */ #define NV_CPWR_DEVICE_MAP_GROUP_BROM 0x0000000c /* */ #define NV_CPWR_DEVICE_MAP_GROUP_ROM_PATCH 0x0000000d /* */ #define NV_CPWR_DEVICE_MAP_GROUP_IOPMP 0x0000000e /* */ #define NV_CPWR_DEVICE_MAP_GROUP_NOACCESS 0x0000000f /* */ #define NV_CPWR_DEVICE_MAP_GROUP_SCP 0x00000010 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_FBIF 0x00000011 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_FALCON_ONLY 0x00000012 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_PRGN_CTL 0x00000013 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_SCRATCH_GROUP0 0x00000014 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_SCRATCH_GROUP1 0x00000015 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_SCRATCH_GROUP2 0x00000016 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_SCRATCH_GROUP3 0x00000017 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_PLM 0x00000018 /* */ #define NV_CPWR_DEVICE_MAP_GROUP_HUB_DIO 0x00000019 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK 0x00000280 /* RWI4R */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK 0x00000284 /* RWI4R */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x00000288 /* RWI4R */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK 0x0000028c /* RWI4R */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x00000290 /* RWI4R */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x00000294 /* RWI4R */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK 0x000000e8 /* RWI4R */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK 0x000000ec /* RWI4R */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse2" /* */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK 0x00000298 /* RWI4R */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0000029c /* RWI4R */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x000003d0 /* RWI4R */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK 0x000003c4 /* RWI4R */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x000003f0 /* RWI4R */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000014 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x000003f4 /* RWI4R */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000015 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x000003f8 /* RWI4R */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000016 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x000003fc /* RWI4R */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000017 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x0000018c+(i)*16) /* RW-4A */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x000002b0+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK 0x00000190 /* RW-4R */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x00000194 /* RW-4R */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK 0x00000198 /* RW-4R */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x0000019c /* RW-4R */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK 0x000001a0 /* RW-4R */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x000001a4 /* RW-4R */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x000001a8 /* RW-4R */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK 0x000001ac /* RW-4R */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x000001b0 /* RW-4R */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK 0x000001b8 /* RWI4R */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK 0x000001bc /* RW-4R */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x000001e0 /* RW-4R */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x000001e4 /* RW-4R */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK 0x000001e8 /* RW-4R */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK 0x000001ec /* RW-4R */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x000001f0 /* RW-4R */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK 0x000001f4 /* RW-4R */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x000001f8 /* RW-4R */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK 0x000001fc /* RW-4R */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK 0x00000220 /* RW-4R */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x00000224 /* RW-4R */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK 0x00000228 /* RW-4R */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK 0x0000022c /* RW-4R */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_IRQSSET 0x00000000 /* -W-4R */ #define NV_CPWR_FALCON_IRQSSET__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_EXT_CTXE 8:8 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_CTXE_SET 1 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_LIMITV 9:9 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_LIMITV_SET 1 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_ECC 10:10 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_ECC_SET 1 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_SECOND 11:11 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_SECOND_SET 1 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_THERM 12:12 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_THERM_SET 1 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_MISCIO 13:13 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_MISCIO_SET 1 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_RTTIMER 14:14 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_RTTIMER_SET 1 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_RSVD8 15:15 /* */ #define NV_CPWR_FALCON_IRQSSET_EXT_RSVD8_SET 1 /* */ #define NV_CPWR_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_SHA 17:17 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_MEMERR 18:18 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_MEMERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_ICD 22:22 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_ICD_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_IOPMP 23:23 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_IOPMP_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSSET_CORE_MISMATCH 24:24 /* -WXVF */ #define NV_CPWR_FALCON_IRQSSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR 0x00000004 /* -W-4R */ #define NV_CPWR_FALCON_IRQSCLR__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_CPWR_FALCON_IRQSCLR_EXT_CTXE 8:8 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXT_CTXE_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXT_LIMITV 9:9 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXT_LIMITV_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXT_ECC 10:10 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXT_ECC_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXT_SECOND 11:11 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXT_SECOND_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXT_THERM 12:12 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXT_THERM_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXT_MISCIO 13:13 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXT_MISCIO_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXT_RTTIMER 14:14 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXT_RTTIMER_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_EXT_RSVD8 15:15 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_EXT_RSVD8_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_ICD 22:22 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_ICD_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_IOPMP 23:23 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_IOPMP_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSCLR_CORE_MISMATCH 24:24 /* -WXVF */ #define NV_CPWR_FALCON_IRQSCLR_CORE_MISMATCH_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQSTAT 0x00000008 /* R--4R */ #define NV_CPWR_FALCON_IRQSTAT__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_CPWR_FALCON_IRQSTAT_EXT_CTXE 8:8 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXT_CTXE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_CTXE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_LIMITV 9:9 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXT_LIMITV_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_LIMITV_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_ECC 10:10 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXT_ECC_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_ECC_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_SECOND 11:11 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXT_SECOND_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_SECOND_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_THERM 12:12 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXT_THERM_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_THERM_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_MISCIO 13:13 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXT_MISCIO_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_MISCIO_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_RTTIMER 14:14 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXT_RTTIMER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_RTTIMER_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_RSVD8 15:15 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_EXT_RSVD8_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_EXT_RSVD8_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */ #define NV_CPWR_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */ #define NV_CPWR_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */ #define NV_CPWR_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_CORE_MISMATCH 24:24 /* R-XVF */ #define NV_CPWR_FALCON_IRQSTAT_CORE_MISMATCH_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSTAT_CORE_MISMATCH_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IRQMODE 0x0000000c /* RW-4R */ #define NV_CPWR_FALCON_IRQMODE__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_INIT 0x000000fc /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_CTXE 8:8 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_CTXE_TRUE 1 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_CTXE_FALSE 0 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_LIMITV 9:9 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_LIMITV_TRUE 1 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_LIMITV_FALSE 0 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_ECC 10:10 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_ECC_TRUE 1 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_ECC_FALSE 0 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_SECOND 11:11 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_SECOND_TRUE 1 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_SECOND_FALSE 0 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_THERM 12:12 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_THERM_TRUE 1 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_THERM_FALSE 0 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_MISCIO 13:13 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_MISCIO_TRUE 1 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_MISCIO_FALSE 0 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_RTTIMER 14:14 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_RTTIMER_TRUE 1 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_RTTIMER_FALSE 0 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_RSVD8 15:15 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_RSVD8_TRUE 1 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_EXT_RSVD8_FALSE 0 /* */ #define NV_CPWR_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SHA 17:17 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_SHA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SHA_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_SHA_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_MEMERR 18:18 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_MEMERR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_MEMERR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_MEMERR_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_ICD 22:22 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_ICD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_ICD_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_ICD_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_IOPMP 23:23 /* RWIVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_IOPMP_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_IOPMP_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_IOPMP_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQMODE_LVL_CORE_MISMATCH 24:24 /* R-IVF */ #define NV_CPWR_FALCON_IRQMODE_LVL_CORE_MISMATCH_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_IRQMODE_LVL_CORE_MISMATCH_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMODE_LVL_CORE_MISMATCH_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IRQSCMASK 0x000000e0 /* RW-4R */ #define NV_CPWR_FALCON_IRQSCMASK__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x000001a4 /* */ #define NV_CPWR_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_CTXE 8:8 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_CTXE_ENABLE 1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_CTXE_DISABLE 0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_LIMITV 9:9 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_LIMITV_ENABLE 1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_LIMITV_DISABLE 0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_ECC 10:10 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_ECC_ENABLE 1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_ECC_DISABLE 0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_SECOND 11:11 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_SECOND_ENABLE 1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_SECOND_DISABLE 0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_THERM 12:12 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_THERM_ENABLE 1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_THERM_DISABLE 0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_MISCIO 13:13 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_MISCIO_ENABLE 1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_MISCIO_DISABLE 0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_RTTIMER 14:14 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_RTTIMER_ENABLE 1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_RTTIMER_DISABLE 0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_RSVD8 15:15 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_RSVD8_ENABLE 1 /* */ #define NV_CPWR_FALCON_IRQSCMASK_EXT_RSVD8_DISABLE 0 /* */ #define NV_CPWR_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_SHA 17:17 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_SHA_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_SHA_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_MEMERR 18:18 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_MEMERR_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_MEMERR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_ICD 22:22 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_ICD_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_ICD_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_IOPMP 23:23 /* RWIVF */ #define NV_CPWR_FALCON_IRQSCMASK_IOPMP_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_IRQSCMASK_IOPMP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQSCMASK_CORE_MISMATCH 24:24 /* R-IVF */ #define NV_CPWR_FALCON_IRQSCMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQSCMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMSET 0x00000010 /* -W-4R */ #define NV_CPWR_FALCON_IRQMSET__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_CPWR_FALCON_IRQMSET_EXT_CTXE 8:8 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXT_CTXE_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXT_LIMITV 9:9 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXT_LIMITV_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXT_ECC 10:10 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXT_ECC_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXT_SECOND 11:11 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXT_SECOND_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXT_THERM 12:12 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXT_THERM_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXT_MISCIO 13:13 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXT_MISCIO_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXT_RTTIMER 14:14 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXT_RTTIMER_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_EXT_RSVD8 15:15 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_EXT_RSVD8_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_SHA 17:17 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_SHA_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_MEMERR 18:18 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_MEMERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_ICD 22:22 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_ICD_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_IOPMP 23:23 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_IOPMP_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMSET_CORE_MISMATCH 24:24 /* -WXVF */ #define NV_CPWR_FALCON_IRQMSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR 0x00000014 /* -W-4R */ #define NV_CPWR_FALCON_IRQMCLR__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_CPWR_FALCON_IRQMCLR_EXT_CTXE 8:8 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXT_CTXE_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXT_LIMITV 9:9 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXT_LIMITV_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXT_ECC 10:10 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXT_ECC_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXT_SECOND 11:11 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXT_SECOND_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXT_THERM 12:12 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXT_THERM_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXT_MISCIO 13:13 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXT_MISCIO_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXT_RTTIMER 14:14 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXT_RTTIMER_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_EXT_RSVD8 15:15 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_EXT_RSVD8_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_SHA 17:17 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_SHA_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_MEMERR 18:18 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_MEMERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_ICD 22:22 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_ICD_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_IOPMP 23:23 /* -WXVF */ #define NV_CPWR_FALCON_IRQMCLR_IOPMP_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_IRQMCLR_CORE_MISMATCH 24:24 /* -WXVF */ #define NV_CPWR_FALCON_IRQMASK 0x00000018 /* R--4R */ #define NV_CPWR_FALCON_IRQMASK__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_CPWR_FALCON_IRQMASK_EXT_CTXE 8:8 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXT_CTXE_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT_CTXE_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_EXT_LIMITV 9:9 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXT_LIMITV_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT_LIMITV_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_EXT_ECC 10:10 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXT_ECC_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT_ECC_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_EXT_SECOND 11:11 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXT_SECOND_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT_SECOND_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_EXT_THERM 12:12 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXT_THERM_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT_THERM_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_EXT_MISCIO 13:13 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXT_MISCIO_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT_MISCIO_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_EXT_RTTIMER 14:14 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXT_RTTIMER_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT_RTTIMER_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_EXT_RSVD8 15:15 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_EXT_RSVD8_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_EXT_RSVD8_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_SHA 17:17 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_MEMERR 18:18 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_MEMERR_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_MEMERR_DISABLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_ICD 22:22 /* R-XVF */ #define NV_CPWR_FALCON_IRQMASK_ICD_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_ICD_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_IOPMP 23:23 /* R-XVF */ #define NV_CPWR_FALCON_IRQMASK_IOPMP_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_IOPMP_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IRQMASK_CORE_MISMATCH 24:24 /* R-IVF */ #define NV_CPWR_FALCON_IRQMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_IRQMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IRQDEST 0x0000001c /* RW-4R */ #define NV_CPWR_FALCON_IRQDEST__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_CTXE 8:8 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_CTXE_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_CTXE_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_LIMITV 9:9 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_LIMITV_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_LIMITV_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_ECC 10:10 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_ECC_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_ECC_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_SECOND 11:11 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_SECOND_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_SECOND_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_THERM 12:12 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_THERM_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_THERM_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_MISCIO 13:13 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_MISCIO_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_MISCIO_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_RTTIMER 14:14 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_RTTIMER_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_RTTIMER_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_RSVD8 15:15 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_RSVD8_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_HOST_EXT_RSVD8_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_CTXE 24:24 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV 25:25 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_ECC 26:26 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_ECC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_ECC_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_ECC_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_ECC_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_ECC_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_SECOND 27:27 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_THERM 28:28 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_THERM_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_THERM_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_THERM_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_THERM_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_THERM_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO 29:29 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER 30:30 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8 31:31 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2 0x0000003c /* RW-4R */ #define NV_CPWR_FALCON_IRQDEST2__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_SHA 1:1 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_HOST_SHA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_SHA_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_SHA_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_MEMERR 2:2 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_HOST_MEMERR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_MEMERR_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_MEMERR_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_ICD 6:6 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_HOST_ICD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_ICD_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_ICD_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_IOPMP 7:7 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_HOST_IOPMP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_IOPMP_FALCON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_IOPMP_HOST 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_CORE_MISMATCH 8:8 /* R-IVF */ #define NV_CPWR_FALCON_IRQDEST2_HOST_CORE_MISMATCH_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_CORE_MISMATCH_FALCON 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IRQDEST2_HOST_CORE_MISMATCH_HOST 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_SHA 17:17 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_SHA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_SHA_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_SHA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_MEMERR 18:18 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_MEMERR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_MEMERR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_MEMERR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_MEMERR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_MEMERR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_ICD 22:22 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_ICD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_ICD_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_ICD_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_ICD_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_ICD_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_IOPMP 23:23 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_IOPMP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_IOPMP_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_IOPMP_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_IOPMP_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_IOPMP_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH 24:24 /* RWIVF */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_GPTMRINT 0x00000020 /* RW-4R */ #define NV_CPWR_FALCON_GPTMRINT__DEVICE_MAP 0x00000003 /* */ #define NV_CPWR_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x000001a0 /* */ #define NV_CPWR_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_GPTMRVAL 0x00000024 /* RW-4R */ #define NV_CPWR_FALCON_GPTMRVAL__DEVICE_MAP 0x00000003 /* */ #define NV_CPWR_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x000001a0 /* */ #define NV_CPWR_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_GPTMRCTL 0x00000028 /* RW-4R */ #define NV_CPWR_FALCON_GPTMRCTL__DEVICE_MAP 0x00000003 /* */ #define NV_CPWR_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x000001a0 /* */ #define NV_CPWR_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_CPWR_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_CPWR_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_PTIMER0 0x0000002c /* R--4R */ #define NV_CPWR_FALCON_PTIMER0__DEVICE_MAP 0x00000003 /* */ #define NV_CPWR_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x000001bc /* */ #define NV_CPWR_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_PTIMER1 0x00000030 /* R--4R */ #define NV_CPWR_FALCON_PTIMER1__DEVICE_MAP 0x00000003 /* */ #define NV_CPWR_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x000001bc /* */ #define NV_CPWR_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_WDTMRVAL 0x00000034 /* RW-4R */ #define NV_CPWR_FALCON_WDTMRVAL__DEVICE_MAP 0x00000003 /* */ #define NV_CPWR_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0000029c /* */ #define NV_CPWR_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_WDTMRCTL 0x00000038 /* RW-4R */ #define NV_CPWR_FALCON_WDTMRCTL__DEVICE_MAP 0x00000003 /* */ #define NV_CPWR_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0000029c /* */ #define NV_CPWR_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_CPWR_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_CPWR_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_MTHDDATA 0x00000064 /* R--4R */ #define NV_CPWR_FALCON_MTHDDATA__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_CPWR_FALCON_MTHDID 0x00000068 /* RW-4R */ #define NV_CPWR_FALCON_MTHDID__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_MTHDID__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_CPWR_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_CPWR_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_CPWR_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_CPWR_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */ #define NV_CPWR_FALCON_MTHDWDAT 0x0000006c /* RW-4R */ #define NV_CPWR_FALCON_MTHDWDAT__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_CPWR_FALCON_MTHDCOUNT 0x00000070 /* R--4R */ #define NV_CPWR_FALCON_MTHDCOUNT__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_CPWR_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_MTHDPOP 0x00000074 /* -W-4R */ #define NV_CPWR_FALCON_MTHDPOP__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_CPWR_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_MTHDRAMSZ 0x00000078 /* RW-4R */ #define NV_CPWR_FALCON_MTHDRAMSZ__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_CPWR_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_CURCTX 0x00000050 /* RW-4R */ #define NV_CPWR_FALCON_CURCTX__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_CURCTX__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_CPWR_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_CPWR_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_CPWR_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_NXTCTX 0x00000054 /* RW-4R */ #define NV_CPWR_FALCON_NXTCTX__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_CPWR_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_CPWR_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_CPWR_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_CTXACK 0x00000058 /* -W-4R */ #define NV_CPWR_FALCON_CTXACK__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_CTXACK__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_CPWR_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_CPWR_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_MAILBOX0 0x00000040 /* RW-4R */ #define NV_CPWR_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_CPWR_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_MAILBOX1 0x00000044 /* RW-4R */ #define NV_CPWR_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_CPWR_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_ITFEN 0x00000048 /* RW-4R */ #define NV_CPWR_FALCON_ITFEN__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_ITFEN__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_CPWR_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_CPWR_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_CPWR_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS 4:4 /* RWIVF */ #define NV_CPWR_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_CPWR_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_CPWR_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IDLESTATE 0x0000004c /* RW-4R */ #define NV_CPWR_FALCON_IDLESTATE__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x000001e0 /* */ #define NV_CPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_CPWR_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_CPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_CPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_IDLESTATE_RISCV_BUSY 20:20 /* R--VF */ #define NV_CPWR_FALCON_IDLESTATE_RISCV_BUSY_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_IDLESTATE_RISCV_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IDLESTATE_INT_BUSY_SHA 24:24 /* R-IVF */ #define NV_CPWR_FALCON_IDLESTATE_INT_BUSY_SHA_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IDLESTATE_INT_BUSY_SHA_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_FHSTATE 0x0000005c /* R--4R */ #define NV_CPWR_FALCON_FHSTATE__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x000001e4 /* */ #define NV_CPWR_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_CPWR_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_CPWR_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_CPWR_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_CPWR_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_FHSTATE_RISCV_HALTED 20:20 /* R--VF */ #define NV_CPWR_FALCON_FHSTATE_RISCV_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_FHSTATE_RISCV_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_PRIVSTATE 0x00000060 /* RW-4R */ #define NV_CPWR_FALCON_PRIVSTATE__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x000003d0 /* */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SFTRESET 0x0000007c /* RW-4R */ #define NV_CPWR_FALCON_SFTRESET__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_CPWR_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL 0x000000a4 /* RW-4R */ #define NV_CPWR_FALCON_ENGCTL__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_CPWR_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_CPWR_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_CPWR_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_CPWR_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_CPWR_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_CPWR_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_ADDR 0x000000ac /* RW-4R */ #define NV_CPWR_FALCON_ADDR__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_ADDR__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_ADDR_LSB 5:0 /* R-IVF */ #define NV_CPWR_FALCON_ADDR_LSB_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_CPWR_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_ADDR_EXT 11:0 /* */ #define NV_CPWR_FALCON_PRICFG 0x000000f8 /* R--4R */ #define NV_CPWR_FALCON_PRICFG__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_PRICFG_ALL 31:0 /* R--VF */ #define NV_CPWR_FALCON_DMACTL 0x0000010c /* RW-4R */ #define NV_CPWR_FALCON_DMACTL__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_CPWR_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_CPWR_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_CPWR_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */ #define NV_CPWR_FALCON_DMACTL_DCACHE_INVALIDATING 8:8 /* R--VF */ #define NV_CPWR_FALCON_DMACTL_DCACHE_INVALIDATING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMACTL_DCACHE_INVALIDATING_DONE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMACTL_ICACHE_INVALIDATING 9:9 /* R--VF */ #define NV_CPWR_FALCON_DMACTL_ICACHE_INVALIDATING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMACTL_ICACHE_INVALIDATING_DONE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_CPWR_FALCON_DMATRFBASE 0x00000110 /* RW-4R */ #define NV_CPWR_FALCON_DMATRFBASE__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_CPWR_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMATRFMOFFS 0x00000114 /* RW-4R */ #define NV_CPWR_FALCON_DMATRFMOFFS__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_CPWR_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMATRFCMD 0x00000118 /* RW-4R */ #define NV_CPWR_FALCON_DMATRFCMD__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_CPWR_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_CPWR_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */ #define NV_CPWR_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_CPWR_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_CPWR_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_CPWR_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_CPWR_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_CPWR_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_CPWR_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_CPWR_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_CPWR_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_CPWR_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMATRFFBOFFS 0x0000011c /* RW-4R */ #define NV_CPWR_FALCON_DMATRFFBOFFS__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_CPWR_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMAPOLL_FB 0x00000120 /* RW-4R */ #define NV_CPWR_FALCON_DMAPOLL_FB__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_CPWR_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_CPWR_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_CPWR_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_CPWR_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_CPWR_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_CPWR_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMAPOLL_CP 0x00000124 /* RW-4R */ #define NV_CPWR_FALCON_DMAPOLL_CP__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_CPWR_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_CPWR_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_CPWR_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_CPWR_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_CPWR_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_CPWR_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMATRFBASE1 0x00000128 /* RW-4R */ #define NV_CPWR_FALCON_DMATRFBASE1__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */ #define NV_CPWR_FALCON_DMATRFBASE1_BASE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x000002c0 /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_LOW__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x000002c4 /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x000002c8 /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_LOW__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x000002cc /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x000002d0 /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_LOW__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x000002d4 /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x000002d8 /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_LOW__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x000002dc /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CTL 0x000002e0 /* RW-4R */ #define NV_CPWR_FALCON_DMAINFO_CTL__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_CPWR_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_CPWR_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMAINFO_ERR_TAG_HIGH 0x000002e4 /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_ERR_TAG_HIGH__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_CPWR_FALCON_DMAINFO_ERR_TAG_LOW 0x000002e8 /* R--4R */ #define NV_CPWR_FALCON_DMAINFO_ERR_TAG_LOW__DEVICE_MAP 0x00000005 /* */ #define NV_CPWR_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x00000190 /* */ #define NV_CPWR_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_IMEMC(i) (0x00000180+(i)*16) /* RW-4A */ #define NV_CPWR_FALCON_IMEMC__SIZE_1 1 /* */ #define NV_CPWR_FALCON_IMEMC__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_IMEMC__PRIV_LEVEL_MASK NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CPWR_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_CPWR_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_CPWR_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_CPWR_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_CPWR_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_CPWR_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_CPWR_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_CPWR_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_CPWR_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IMEMD(i) (0x00000184+(i)*16) /* RW-4A */ #define NV_CPWR_FALCON_IMEMD__SIZE_1 1 /* */ #define NV_CPWR_FALCON_IMEMD__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_IMEMD__PRIV_LEVEL_MASK NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CPWR_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_CPWR_FALCON_IMEMT(i) (0x00000188+(i)*16) /* RW-4A */ #define NV_CPWR_FALCON_IMEMT__SIZE_1 1 /* */ #define NV_CPWR_FALCON_IMEMT__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IMEMT__PRIV_LEVEL_MASK NV_CPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CPWR_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_CPWR_FALCON_DMEMC(i) (0x000001c0+(i)*8) /* RW-4A */ #define NV_CPWR_FALCON_DMEMC__SIZE_1 4 /* */ #define NV_CPWR_FALCON_DMEMC__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_DMEMC__PRIV_LEVEL_MASK NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CPWR_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_CPWR_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_CPWR_FALCON_DMEMC_OFFS_INIT 0 /* */ #define NV_CPWR_FALCON_DMEMC_BLK 23:8 /* */ #define NV_CPWR_FALCON_DMEMC_BLK_INIT 0 /* */ #define NV_CPWR_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_CPWR_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_CPWR_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_CPWR_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_CPWR_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_CPWR_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_CPWR_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_CPWR_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_CPWR_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_DMEMD(i) (0x000001c4+(i)*8) /* RW-4A */ #define NV_CPWR_FALCON_DMEMD__SIZE_1 4 /* */ #define NV_CPWR_FALCON_DMEMD__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_DMEMD__PRIV_LEVEL_MASK NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CPWR_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_CPWR_FALCON_DMEMT(i) (0x00000210+(i)*4) /* -W-4A */ #define NV_CPWR_FALCON_DMEMT__SIZE_1 4 /* */ #define NV_CPWR_FALCON_DMEMT__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_DMEMT__PRIV_LEVEL_MASK NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CPWR_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_CPWR_FALCON_DMEML(i) (0x000002a0+(i)*4) /* -W-4A */ #define NV_CPWR_FALCON_DMEML__SIZE_1 4 /* */ #define NV_CPWR_FALCON_DMEML__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_DMEML__PRIV_LEVEL_MASK NV_CPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CPWR_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_CPWR_FALCON_LOCKPMB 0x00000170 /* RW-4R */ #define NV_CPWR_FALCON_LOCKPMB__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_LOCKPMB_IMEM 0:0 /* RWIVF */ #define NV_CPWR_FALCON_LOCKPMB_IMEM_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_LOCKPMB_IMEM_LOCK 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_LOCKPMB_IMEM_UNLOCK 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_LOCKPMB_DMEM 1:1 /* RWIVF */ #define NV_CPWR_FALCON_LOCKPMB_DMEM_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_LOCKPMB_DMEM_LOCK 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_LOCKPMB_DMEM_UNLOCK 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_LOCKPMB_EXT2MEM 4:4 /* RWIVF */ #define NV_CPWR_FALCON_LOCKPMB_EXT2MEM_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_LOCKPMB_EXT2MEM_LOCK 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_LOCKPMB_EXT2MEM_UNLOCK 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE0 0x00000174 /* RW-4R */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE0__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE0__PRIV_LEVEL_MASK 0x000001ac /* */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE0_START_BLOCK 15:0 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE0_START_BLOCK_INIT 0x0000ffff /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE0_END_BLOCK 31:16 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE0_END_BLOCK_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE1 0x00000178 /* RW-4R */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE1__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE1__PRIV_LEVEL_MASK 0x000001ac /* */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE1_START_BLOCK 15:0 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE1_START_BLOCK_INIT 0x0000ffff /* RWI-V */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE1_END_BLOCK 31:16 /* RWIVF */ #define NV_CPWR_FALCON_DMEM_PRIV_RANGE1_END_BLOCK_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEM_DUMMY 0x00000258 /* R--4R */ #define NV_CPWR_FALCON_DMEM_DUMMY__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_CPWR_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x00000284 /* */ #define NV_CPWR_FALCON_IMEM_DUMMY 0x000001b4 /* R--4R */ #define NV_CPWR_FALCON_IMEM_DUMMY__DEVICE_MAP 0x00000006 /* */ #define NV_CPWR_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_CPWR_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x00000280 /* */ #define NV_CPWR_FALCON_DIO_RESET_DELAY 0x00000274 /* RW-4R */ #define NV_CPWR_FALCON_DIO_RESET_DELAY__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DIO_RESET_DELAY__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DIO_RESET_DELAY_VALUE 15:0 /* RWIVF */ #define NV_CPWR_FALCON_DIO_RESET_DELAY_VALUE_INIT 0x00000100 /* RWI-V */ #define NV_CPWR_FALCON_DOC_CTRL 0x00000340 /* RW-4R */ #define NV_CPWR_FALCON_DOC_CTRL__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DOC_CTRL__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DOC_CTRL_COUNT 7:0 /* R--VF */ #define NV_CPWR_FALCON_DOC_CTRL_RESET 16:16 /* RWIVF */ #define NV_CPWR_FALCON_DOC_CTRL_RESET_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DOC_CTRL_STOP 17:17 /* RWIVF */ #define NV_CPWR_FALCON_DOC_CTRL_STOP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DOC_CTRL_EMPTY 18:18 /* R-IVF */ #define NV_CPWR_FALCON_DOC_CTRL_EMPTY_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_DOC_CTRL_WR_FINISHED 19:19 /* R-IVF */ #define NV_CPWR_FALCON_DOC_CTRL_WR_FINISHED_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_DOC_CTRL_RD_FINISHED 20:20 /* R-IVF */ #define NV_CPWR_FALCON_DOC_CTRL_RD_FINISHED_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_DOC_CTRL_WR_ERROR 21:21 /* RWIVF */ #define NV_CPWR_FALCON_DOC_CTRL_WR_ERROR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DOC_CTRL_RD_ERROR 22:22 /* RWIVF */ #define NV_CPWR_FALCON_DOC_CTRL_RD_ERROR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DOC_CTRL_PROTOCOL_ERROR 23:23 /* RWIVF */ #define NV_CPWR_FALCON_DOC_CTRL_PROTOCOL_ERROR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DOC_D0 0x00000344 /* RW-4R */ #define NV_CPWR_FALCON_DOC_D0__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DOC_D0__PRIV_LEVEL_MASK 0x000000ec /* */ #define NV_CPWR_FALCON_DOC_D0_DATA 31:0 /* RW-VF */ #define NV_CPWR_FALCON_DOC_D1 0x00000348 /* RW-4R */ #define NV_CPWR_FALCON_DOC_D1__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DOC_D1__PRIV_LEVEL_MASK 0x000000ec /* */ #define NV_CPWR_FALCON_DOC_D1_DATA 31:0 /* RW-VF */ #define NV_CPWR_FALCON_DOC_D2 0x0000034c /* RW-4R */ #define NV_CPWR_FALCON_DOC_D2__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DOC_D2__PRIV_LEVEL_MASK 0x000000ec /* */ #define NV_CPWR_FALCON_DOC_D2_DATA 15:0 /* RW-VF */ #define NV_CPWR_FALCON_DIC_CTRL 0x00000350 /* RW-4R */ #define NV_CPWR_FALCON_DIC_CTRL__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DIC_CTRL__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DIC_CTRL_COUNT 7:0 /* R--VF */ #define NV_CPWR_FALCON_DIC_CTRL_RESET 16:16 /* RWIVF */ #define NV_CPWR_FALCON_DIC_CTRL_RESET_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DIC_CTRL_VALID 19:19 /* R-IVF */ #define NV_CPWR_FALCON_DIC_CTRL_VALID_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_DIC_CTRL_POP 20:20 /* -W-VF */ #define NV_CPWR_FALCON_DIC_D0 0x00000354 /* RW-4R */ #define NV_CPWR_FALCON_DIC_D0__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DIC_D0__PRIV_LEVEL_MASK 0x000000ec /* */ #define NV_CPWR_FALCON_DIC_D0_DATA 31:0 /* RW-VF */ #define NV_CPWR_FALCON_DIC_D1 0x00000358 /* RW-4R */ #define NV_CPWR_FALCON_DIC_D1__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DIC_D1__PRIV_LEVEL_MASK 0x000000ec /* */ #define NV_CPWR_FALCON_DIC_D1_DATA 31:0 /* RW-VF */ #define NV_CPWR_FALCON_DIC_D2 0x0000035c /* RW-4R */ #define NV_CPWR_FALCON_DIC_D2__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DIC_D2__PRIV_LEVEL_MASK 0x000000ec /* */ #define NV_CPWR_FALCON_DIC_D2_DATA 15:0 /* RW-VF */ #define NV_CPWR_FALCON_DIO_ERR 0x00000360 /* R--4R */ #define NV_CPWR_FALCON_DIO_ERR__DEVICE_MAP 0x00000007 /* */ #define NV_CPWR_FALCON_DIO_ERR__PRIV_LEVEL_MASK 0x000000ec /* */ #define NV_CPWR_FALCON_DIO_ERR_INFO 31:0 /* R--VF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x00000300+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0__DEVICE_MAP 0x00000014 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x000003f0 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x00000310+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1__DEVICE_MAP 0x00000015 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x000003f4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x00000320+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x000003f8 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x00000330+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3__DEVICE_MAP 0x00000017 /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x000003fc /* */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PRGNVER 0x000003d4 /* R-I4R */ #define NV_CPWR_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_CPWR_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */ #define NV_CPWR_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_CPWR_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_CPWR_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG 0x00000108 /* R--4R */ #define NV_CPWR_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_CPWR_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_CPWR_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_CPWR_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_CPWR_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_CPWR_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_CPWR_FALCON_HWCFG1 0x0000012c /* R--4R */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000003 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000004 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000010 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_CPWR_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2 0x000000f4 /* R--4R */ #define NV_CPWR_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_CPWR_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_HWCFG3 0x00000278 /* R--4R */ #define NV_CPWR_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_CPWR_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_CPWR_FALCON_CGCTL 0x000000a0 /* RW-4R */ #define NV_CPWR_FALCON_CGCTL__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_CPWR_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_CG2 0x00000134 /* RWI4R */ #define NV_CPWR_FALCON_CG2__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_FALCON_CG2__PRIV_LEVEL_MASK 0x000001e8 /* */ #define NV_CPWR_FALCON_CG2_SLCG 17:1 /* */ #define NV_CPWR_FALCON_CG2_SLCG_ENABLED 0 /* */ #define NV_CPWR_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */ #define NV_CPWR_FALCON_CG2_SLCG__PROD 0x000A0 /* */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_SHA 18:18 /* RWIVF */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_SHA__PROD 1 /* */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_SHA_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CG2_SLCG_FALCON_SHA_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_ENGID 0x0000013c /* R--4R */ #define NV_CPWR_FALCON_ENGID_INSTID 7:0 /* R-IVF */ #define NV_CPWR_FALCON_ENGID_INSTID_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_ENGID_FAMILYID 15:8 /* R--VF */ #define NV_CPWR_FALCON_ENGID_FAMILYID_SEC 0x00000001 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_DPU 0x00000002 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_NVDEC 0x00000003 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_PWR_PMU 0x00000004 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_FBFACLON 0x00000005 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_NVENC 0x00000006 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_GPCCS 0x00000007 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_FECS 0x00000008 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_MINION 0x00000009 /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_XUSB 0x0000000a /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_GSP 0x0000000b /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_NVJPG 0x0000000c /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_OFA 0x0000000d /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_PSC 0x0000000e /* R---V */ #define NV_CPWR_FALCON_ENGID_FAMILYID_SOE 0x0000000f /* R---V */ #define NV_CPWR_FALCON_ENGINE 0x000003c0 /* RW-4R */ #define NV_CPWR_FALCON_ENGINE__PRIV_LEVEL_MASK 0x000003c4 /* */ #define NV_CPWR_FALCON_ENGINE_RESET 0:0 /* RWIVF */ #define NV_CPWR_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SCTL 0x00000240 /* RW-4R */ #define NV_CPWR_FALCON_SCTL__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_SCTL__PRIV_LEVEL_MASK 0x00000298 /* */ #define NV_CPWR_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_CPWR_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_CPWR_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */ #define NV_CPWR_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_CPWR_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SCTL1 0x00000250 /* RW-4R */ #define NV_CPWR_FALCON_SCTL1__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_CPWR_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_CPWR_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_CPWR_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_CPWR_FALCON_HSCTL 0x000000e4 /* RW-4R */ #define NV_CPWR_FALCON_HSCTL__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_HSCTL__PRIV_LEVEL_MASK 0x000000e8 /* */ #define NV_CPWR_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_CPWR_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL 0x000002f4 /* RW-4R */ #define NV_CPWR_FALCON_SAFETY_CTRL__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x000001b0 /* */ #define NV_CPWR_FALCON_SAFETY_CTRL_FUSE_OPT_RISCV_DCLS_EN 17:17 /* R-IVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_FUSE_OPT_RISCV_DCLS_EN_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN 11:10 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN_FALSE 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS 7:6 /* RWIVF */ #define NV_CPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_FALSE 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY 0x000003b8 /* RW-4R */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY__PRIV_LEVEL_MASK 0x000001b0 /* */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH 31:24 /* RWIVF */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH_TRUE 0x000000a5 /* RW--V */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH_FALSE 0x0000005a /* RWI-V */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT 23:16 /* RW-VF */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT_ENABLED 0x000000a5 /* RW--V */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT_DISABLED 0x0000005a /* RW--V */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET 15:8 /* RW-VF */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET_ENABLED 0x000000a5 /* RW--V */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET_DISABLED 0x0000005a /* RW--V */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT 7:0 /* RW-VF */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT_ENABLED 0x000000a5 /* RW--V */ #define NV_CPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT_DISABLED 0x0000005a /* RW--V */ #define NV_CPWR_FALCON_OS 0x00000080 /* RW-4R */ #define NV_CPWR_FALCON_OS__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_CPWR_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_RM 0x00000084 /* RW-4R */ #define NV_CPWR_FALCON_RM__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_CPWR_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SOFT_PM 0x00000088 /* RW-4R */ #define NV_CPWR_FALCON_SOFT_PM__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x000001ec /* */ #define NV_CPWR_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_CPWR_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_CPWR_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_CPWR_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SOFT_MODE 0x0000008c /* RW-4R */ #define NV_CPWR_FALCON_SOFT_MODE__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x000001ec /* */ #define NV_CPWR_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_CPWR_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PMM 0x000000a8 /* RW-4R */ #define NV_CPWR_FALCON_PMM__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_PMM__PRIV_LEVEL_MASK 0x000001ec /* */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_CODE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_IPND 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_SB 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x00000009 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0000000a /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0000000b /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0000000d /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0000000e /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x00000010 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x00000011 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_CPWR_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x00000009 /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0x0000000a /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0x0000000b /* RW--V */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_CPWR_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */ #define NV_CPWR_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x00000009 /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0x0000000a /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0x0000000b /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0x0000000d /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0x0000000e /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_CPWR_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_CPWR_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DEBUG1 0x00000090 /* RW-4R */ #define NV_CPWR_FALCON_DEBUG1__DEVICE_MAP 0x00000004 /* */ #define NV_CPWR_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x00000294 /* */ #define NV_CPWR_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_CPWR_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */ #define NV_CPWR_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_CPWR_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_CPWR_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_CPWR_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DEBUGINFO 0x00000094 /* RW-4R */ #define NV_CPWR_FALCON_DEBUGINFO__DEVICE_MAP 0x00000013 /* */ #define NV_CPWR_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_CPWR_FALCON_SP_MIN 0x00000270 /* RW-4R */ #define NV_CPWR_FALCON_SP_MIN__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x000001f0 /* */ #define NV_CPWR_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_CPWR_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_EXCI 0x000000d0 /* R--4R */ #define NV_CPWR_FALCON_EXCI__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_EXCI__PRIV_LEVEL_MASK 0x000001f4 /* */ #define NV_CPWR_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_CPWR_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_BROM_CALL_INS 0x00000015 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_KMEM_VIOLATION_INS 0x00000016 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXCAUSE_BMEM_PERMISSION_INS 0x00000017 /* R---V */ #define NV_CPWR_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_CPWR_FALCON_EXCI2 0x000000bc /* R--4R */ #define NV_CPWR_FALCON_EXCI2__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_EXCI2__PRIV_LEVEL_MASK 0x000001f4 /* */ #define NV_CPWR_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_CPWR_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SVEC_SPR 0x000000d4 /* R--4R */ #define NV_CPWR_FALCON_SVEC_SPR__DEVICE_MAP 0x00000010 /* */ #define NV_CPWR_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x000001f8 /* */ #define NV_CPWR_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_CPWR_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_CPUCTL 0x00000100 /* RW-4R */ #define NV_CPWR_FALCON_CPUCTL__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x00000288 /* */ #define NV_CPWR_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_CPWR_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_CPWR_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_CPWR_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_CPWR_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_CPWR_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_CPWR_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_CPWR_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_CPUCTL_ALIAS 0x00000130 /* -W-4R */ #define NV_CPWR_FALCON_CPUCTL_ALIAS__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_CPWR_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_FALCON_STACKCFG 0x00000138 /* RW-4R */ #define NV_CPWR_FALCON_STACKCFG__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_CPWR_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_CPWR_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_BOOTVEC 0x00000104 /* RW-4R */ #define NV_CPWR_FALCON_BOOTVEC__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x00000194 /* */ #define NV_CPWR_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_CPWR_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL 0x00000254 /* RW-4R */ #define NV_CPWR_FALCON_DBGCTL__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x000001a8 /* */ #define NV_CPWR_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_CPWR_FALCON_DBGCTL_VAL_INIT 0 /* */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_CPWR_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */ #define NV_CPWR_FALCON_IBRKPT1 0x00000098 /* RW-4R */ #define NV_CPWR_FALCON_IBRKPT1__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x000001fc /* */ #define NV_CPWR_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT2 0x0000009c /* RW-4R */ #define NV_CPWR_FALCON_IBRKPT2__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x000001fc /* */ #define NV_CPWR_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT3 0x000000b0 /* RW-4R */ #define NV_CPWR_FALCON_IBRKPT3__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x000001fc /* */ #define NV_CPWR_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT4 0x000000b4 /* RW-4R */ #define NV_CPWR_FALCON_IBRKPT4__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x000001fc /* */ #define NV_CPWR_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT5 0x000000b8 /* RW-4R */ #define NV_CPWR_FALCON_IBRKPT5__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x000001fc /* */ #define NV_CPWR_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_CPWR_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD 0x00000200 /* RW-4R */ #define NV_CPWR_FALCON_ICD_CMD__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x00000220 /* */ #define NV_CPWR_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_CPWR_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_CPWR_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_CPWR_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_CPWR_FALCON_ICD_ADDR 0x00000204 /* RW-4R */ #define NV_CPWR_FALCON_ICD_ADDR__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x00000220 /* */ #define NV_CPWR_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_CPWR_FALCON_ICD_WDATA 0x00000208 /* RW-4R */ #define NV_CPWR_FALCON_ICD_WDATA__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x00000220 /* */ #define NV_CPWR_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_CPWR_FALCON_ICD_RDATA 0x0000020c /* R--4R */ #define NV_CPWR_FALCON_ICD_RDATA__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x00000220 /* */ #define NV_CPWR_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_CPWR_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_CPWR_FALCON_RSTAT0 0x000000d8 /* R--4R */ #define NV_CPWR_FALCON_RSTAT0__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x00000224 /* */ #define NV_CPWR_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3 0x000000dc /* R--4R */ #define NV_CPWR_FALCON_RSTAT3__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_CPWR_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_CPWR_FALCON_TRACEIDX 0x00000148 /* RW-4R */ #define NV_CPWR_FALCON_TRACEIDX__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x0000019c /* */ #define NV_CPWR_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_CPWR_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_CPWR_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_CPWR_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_TRACEPC 0x0000014c /* R--4R */ #define NV_CPWR_FALCON_TRACEPC__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x0000019c /* */ #define NV_CPWR_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_CPWR_FALCON_TRACEINFO 0x0000017c /* R--4R */ #define NV_CPWR_FALCON_TRACEINFO__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x0000019c /* */ #define NV_CPWR_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_CPWR_FALCON_IMCTL 0x00000140 /* RW-4R */ #define NV_CPWR_FALCON_IMCTL__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_CPWR_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_CPWR_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_IMCTL_DEBUG 0x0000015c /* RW-4R */ #define NV_CPWR_FALCON_IMCTL_DEBUG__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_CPWR_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_CPWR_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_IMSTAT 0x00000144 /* RW-4R */ #define NV_CPWR_FALCON_IMSTAT__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_CPWR_FALCON_IMFILLRNG0 0x00000150 /* RW-4R */ #define NV_CPWR_FALCON_IMFILLRNG0__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_CPWR_FALCON_IMFILLRNG0_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_CPWR_FALCON_IMFILLRNG0_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMFILLRNG1 0x00000154 /* RW-4R */ #define NV_CPWR_FALCON_IMFILLRNG1__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_CPWR_FALCON_IMFILLRNG1_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_CPWR_FALCON_IMFILLRNG1_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_IMFILLCTL 0x00000158 /* RW-4R */ #define NV_CPWR_FALCON_IMFILLCTL__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_CPWR_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMCTL 0x00000260 /* RW-4R */ #define NV_CPWR_FALCON_DMCTL__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_CPWR_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_CPWR_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_DMSTAT 0x00000264 /* RW-4R */ #define NV_CPWR_FALCON_DMSTAT__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_CPWR_FALCON_DMVACTL 0x00000268 /* RW-4R */ #define NV_CPWR_FALCON_DMVACTL__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x00000198 /* */ #define NV_CPWR_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_CPWR_FALCON_DMVACTL_BOUND_INIT 0x00000100 /* RWI-V */ #define NV_CPWR_FALCON_DMCYA 0x0000026c /* RW-4R */ #define NV_CPWR_FALCON_DMCYA__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_DMCYA__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DMCYA_LDSTVA_DIS 0:0 /* RWIVF */ #define NV_CPWR_FALCON_DMCYA_LDSTVA_DIS_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMCYA_LDSTVA_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMCYA_ROB_DIS 1:1 /* RWIVF */ #define NV_CPWR_FALCON_DMCYA_ROB_DIS_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMCYA_ROB_DIS_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMCYA_ROBWB_DIS 2:2 /* RWIVF */ #define NV_CPWR_FALCON_DMCYA_ROBWB_DIS_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMCYA_ROBWB_DIS_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_DMCYA_ROBSPR_DIS 3:3 /* RWIVF */ #define NV_CPWR_FALCON_DMCYA_ROBSPR_DIS_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMCYA_ROBSPR_DIS_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CMEMBASE 0x00000160 /* RW-4R */ #define NV_CPWR_FALCON_CMEMBASE__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_CMEMBASE__PRIV_LEVEL_MASK 0x00000198 /* */ #define NV_CPWR_FALCON_CMEMBASE_VAL 31:18 /* RWIVF */ #define NV_CPWR_FALCON_CMEMBASE_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMAPERT 0x00000164 /* RW-4R */ #define NV_CPWR_FALCON_DMEMAPERT__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_DMEMAPERT__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_FALCON_DMEMAPERT_TIME_OUT 7:0 /* RWIVF */ #define NV_CPWR_FALCON_DMEMAPERT_TIME_OUT__PROD 0x000000ff /* RW--V */ #define NV_CPWR_FALCON_DMEMAPERT_TIME_OUT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMAPERT_TIME_UNIT 11:8 /* RWIVF */ #define NV_CPWR_FALCON_DMEMAPERT_TIME_UNIT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMAPERT_ENABLE 16:16 /* RWIVF */ #define NV_CPWR_FALCON_DMEMAPERT_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_DMEMAPERT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_DMEMAPERT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_DMEMAPERT_LDSTQ_NUM 19:17 /* R--VF */ #define NV_CPWR_FALCON_EXTERRSTAT 0x0000016c /* RW-4R */ #define NV_CPWR_FALCON_EXTERRSTAT__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_EXTERRSTAT__PRIV_LEVEL_MASK 0x00000228 /* */ #define NV_CPWR_FALCON_EXTERRSTAT_PC 23:0 /* R--VF */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT 27:24 /* R--VF */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT_ACK_POS 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXTERRSTAT_STAT_ACK_TOUT 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_EXTERRSTAT_VALID 31:31 /* RWIVF */ #define NV_CPWR_FALCON_EXTERRSTAT_VALID_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_EXTERRSTAT_VALID_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_EXTERRSTAT_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_EXTERRADDR 0x00000168 /* R--4R */ #define NV_CPWR_FALCON_EXTERRADDR__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_EXTERRADDR__PRIV_LEVEL_MASK 0x00000228 /* */ #define NV_CPWR_FALCON_EXTERRADDR_ADDR 31:0 /* R--VF */ #define NV_CPWR_FALCON_EXTERR_INFO 0x0000025c /* R--4R */ #define NV_CPWR_FALCON_EXTERR_INFO__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_EXTERR_INFO__PRIV_LEVEL_MASK 0x00000228 /* */ #define NV_CPWR_FALCON_EXTERR_INFO_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_CSBERRSTAT 0x00000244 /* RW-4R */ #define NV_CPWR_FALCON_CSBERRSTAT__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x0000022c /* */ #define NV_CPWR_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_CPWR_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_CPWR_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_CPWR_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_CSBERR_ADDR 0x0000024c /* R--4R */ #define NV_CPWR_FALCON_CSBERR_ADDR__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x0000022c /* */ #define NV_CPWR_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_CSBERR_INFO 0x00000248 /* R--4R */ #define NV_CPWR_FALCON_CSBERR_INFO__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x0000022c /* */ #define NV_CPWR_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #define NV_CPWR_FALCON_KMEM_PDUK_IDX 0 #define NV_CPWR_FALCON_KMEM_PMUK_IDX 1 #define NV_CPWR_FALCON_KMEM_KEK_IDX 2 #define NV_CPWR_FALCON_KMEM_EK_LOW_IDX 3 #define NV_CPWR_FALCON_KMEM_EK_HIGH_IDX 4 #define NV_CPWR_FALCON_KMEM_MPK_LOW_IDX 6 #define NV_CPWR_FALCON_KMEM_MPK_HIGH_IDX 7 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_READ 0:0 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_READ_ENABLE 0x00000001 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_READ_DISABLE 0x00000000 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE 1:1 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE_ENABLE 0x00000001 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE_DISABLE 0x00000000 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_READ 2:2 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_READ_ENABLE 0x00000001 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_READ_DISABLE 0x00000000 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE 3:3 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE_ENABLE 0x00000001 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE_DISABLE 0x00000000 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_READ 4:4 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_READ_ENABLE 0x00000001 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_READ_DISABLE 0x00000000 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE 5:5 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE_ENABLE 0x00000001 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE_DISABLE 0x00000000 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_READ 6:6 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_READ_ENABLE 0x00000001 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_READ_DISABLE 0x00000000 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE 7:7 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE_ENABLE 0x00000001 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE_DISABLE 0x00000000 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_ACL_K0 8:8 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_ACL_K3 9:9 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_RECYCLABLE 10:10 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_PRIV_EN 11:11 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_NS_63LOADABLE 12:12 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_LS_63LOADABLE 13:13 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_HS_63LOADABLE 14:14 #define NV_CPWR_FALCON_KMEM_PROTECTINFO_UCODEIDMASK 31:15 #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK 0x00001250 /* RWI4R */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK 0x0000125c /* RWI4R */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK 0x00001254 /* RWI4R */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK 0x00001128 /* RWI4R */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK__SETLVL_SIGNAL "setlvlm" /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK__CLRLVL_SIGNAL "clrlvlm" /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG 0x00001004 /* RW-4R */ #define NV_CPWR_FALCON_SHA_CONFIG__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_MODE 31:24 /* RWIVF */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA1 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA224 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA256 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA384 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA512 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA512_224 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA512_256 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_ALG 15:12 /* RWIVF */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_ALG_SHA 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG_ENC_ALG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_CONFIG_DST 4:2 /* RWIVF */ #define NV_CPWR_FALCON_SHA_CONFIG_DST_HASH_REG 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_CONFIG_DST_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_CONFIG__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_TASK_CONFIG 0x00001008 /* RWI4R */ #define NV_CPWR_FALCON_SHA_TASK_CONFIG__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH 0:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SHA_TASK_CONFIG__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_IN_ADDR 0x0000100c /* RW-4R */ #define NV_CPWR_FALCON_SHA_IN_ADDR__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_IN_ADDR_VAL 31:0 /* RWXVF */ #define NV_CPWR_FALCON_SHA_IN_ADDR__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_IN_ADDR_HI 0x00001010 /* RW-4R */ #define NV_CPWR_FALCON_SHA_IN_ADDR_HI__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_IN_ADDR_HI_MSB 31:24 /* RWXVF */ #define NV_CPWR_FALCON_SHA_IN_ADDR_HI_SZ 23:0 /* RWXVF */ #define NV_CPWR_FALCON_SHA_IN_ADDR_HI__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_MSG_LENGTH(i) (0x0000101c+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_SHA_MSG_LENGTH__SIZE_1 4 /* */ #define NV_CPWR_FALCON_SHA_MSG_LENGTH__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_MSG_LENGTH_VAL 31:0 /* RW-VF */ #define NV_CPWR_FALCON_SHA_MSG_LENGTH__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_MSG_LEFT(i) (0x0000102c+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_SHA_MSG_LEFT__SIZE_1 4 /* */ #define NV_CPWR_FALCON_SHA_MSG_LEFT__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_MSG_LEFT_VAL 31:0 /* RW-VF */ #define NV_CPWR_FALCON_SHA_MSG_LEFT__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_HASH_RESULT(i) (0x0000103c+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_SHA_HASH_RESULT__SIZE_1 16 /* */ #define NV_CPWR_FALCON_SHA_HASH_RESULT__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_HASH_RESULT_VAL 31:0 /* RW-VF */ #define NV_CPWR_FALCON_SHA_HASH_RESULT__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_OPERATION 0x0000107c /* RWI4R */ #define NV_CPWR_FALCON_SHA_OPERATION__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_OPERATION_LAST_BUF 16:16 /* RWIVF */ #define NV_CPWR_FALCON_SHA_OPERATION_LAST_BUF_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_SHA_OPERATION_LAST_BUF_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_OPERATION_SOFTRESET 6:6 /* RWIVF */ #define NV_CPWR_FALCON_SHA_OPERATION_SOFTRESET_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_OPERATION_SOFTRESET_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_OPERATION_HALT 5:5 /* RWIVF */ #define NV_CPWR_FALCON_SHA_OPERATION_HALT_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_OPERATION_HALT_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_OPERATION_OP 2:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_OPERATION_OP_NOP 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_OPERATION_OP_START 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_OPERATION_OP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_OPERATION__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_STATUS 0x00001080 /* R-I4R */ #define NV_CPWR_FALCON_SHA_STATUS__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_STATUS__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_STATUS_STATE 2:0 /* R-IVF */ #define NV_CPWR_FALCON_SHA_STATUS_STATE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_STATUS_STATE_IDLE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_SHA_STATUS_STATE_BUSY 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_STATUS_STATE_HALTED 0x00000007 /* R---V */ #define NV_CPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR 0x00001084 /* R--4R */ #define NV_CPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */ #define NV_CPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI 0x00001088 /* R--4R */ #define NV_CPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_CPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN 0x0000108c /* RW-4R */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK 0:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_SET 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_UNSET 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK 1:1 /* RWIVF */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_SET 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_UNSET 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR 0x00001090 /* R--4R */ #define NV_CPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */ #define NV_CPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI 0x00001094 /* R--4R */ #define NV_CPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_CPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS 0x00001130 /* RWI4R */ #define NV_CPWR_FALCON_SHA_ERR_STATUS__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_LEVEL_ERR 12:12 /* RWIVF */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_LEVEL_ERR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_LEVEL_ERR_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_LEVEL_ERR_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_MULTI_HIT 11:11 /* RWIVF */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_MULTI_HIT_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_MULTI_HIT_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_MULTI_HIT_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_MISS 10:10 /* RWIVF */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_MISS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_MISS_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_MISS_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_PA_FAULT 9:9 /* RWIVF */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_PA_FAULT_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_PA_FAULT_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_PA_FAULT_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_FBIF_ERR 8:8 /* RWIVF */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_FBIF_ERR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_FBIF_ERR_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_FBIF_ERR_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG 4:4 /* RWIVF */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_NS_ACCESS 0:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_NS_ACCESS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_NS_ACCESS_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_ERR_STATUS_NS_ACCESS_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_ERR_STATUS__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_ERR_ADDR 0x00001120 /* R--4R */ #define NV_CPWR_FALCON_SHA_ERR_ADDR__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_ERR_ADDR_VAL 31:0 /* R-XVF */ #define NV_CPWR_FALCON_SHA_ERR_ADDR__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_ERR_ADDR_HI 0x00001124 /* R--4R */ #define NV_CPWR_FALCON_SHA_ERR_ADDR_HI__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_ERR_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_CPWR_FALCON_SHA_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_INT_STATUS 0x00001134 /* RWI4R */ #define NV_CPWR_FALCON_SHA_INT_STATUS__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_INT_STATUS_ERR_STATUS 16:16 /* RWIVF */ #define NV_CPWR_FALCON_SHA_INT_STATUS_ERR_STATUS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_INT_STATUS_ERR_STATUS_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_INT_STATUS_ERR_STATUS_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_INT_STATUS_OP_DONE 4:4 /* RWIVF */ #define NV_CPWR_FALCON_SHA_INT_STATUS_OP_DONE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_INT_STATUS_OP_DONE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_INT_STATUS_OP_DONE_CLEAR 1 /* */ #define NV_CPWR_FALCON_SHA_INT_STATUS__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_INT_ENABLE 0x00001138 /* RWI4R */ #define NV_CPWR_FALCON_SHA_INT_ENABLE__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_INT_ENABLE_ERR_STATUS 16:16 /* RWIVF */ #define NV_CPWR_FALCON_SHA_INT_ENABLE_ERR_STATUS_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_INT_ENABLE_ERR_STATUS_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_INT_ENABLE_OP_DONE 4:4 /* RWIVF */ #define NV_CPWR_FALCON_SHA_INT_ENABLE_OP_DONE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_INT_ENABLE_OP_DONE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_INT_ENABLE__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_MUTEX 0x00001100 /* -W-4R */ #define NV_CPWR_FALCON_SHA_MUTEX__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_MUTEX_VAL 7:0 /* -W-VF */ #define NV_CPWR_FALCON_SHA_MUTEX__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_MUTEX_RELEASE 0x00001104 /* -W-4R */ #define NV_CPWR_FALCON_SHA_MUTEX_RELEASE__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_MUTEX_RELEASE_VAL 7:0 /* -W-VF */ #define NV_CPWR_FALCON_SHA_MUTEX_RELEASE__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_MUTEX_STATUS 0x00001108 /* R-I4R */ #define NV_CPWR_FALCON_SHA_MUTEX_STATUS__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_MUTEX_STATUS__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_MUTEX_STATUS_LOCKED 7:0 /* R-IVF */ #define NV_CPWR_FALCON_SHA_MUTEX_STATUS_LOCKED_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG 0x00001110 /* RW-4R */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_FB_BASE 24:16 /* RWXVF */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION 7:7 /* RWIVF */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_CTXDMA 6:4 /* RWXVF */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_SRC 1:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_SRC_DMEM 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_SRC_IMEM 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG_SRC_FB 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_SHA_SRC_CONFIG__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_REQ_CTRL 0x00001114 /* RW-4R */ #define NV_CPWR_FALCON_SHA_REQ_CTRL__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_REQ_CTRL_WINDOW 31:16 /* RWIVF */ #define NV_CPWR_FALCON_SHA_REQ_CTRL_WINDOW_INIT 0x00001000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_REQ_CTRL_LIMIT 15:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_REQ_CTRL_LIMIT_INIT 0x00000800 /* RWI-V */ #define NV_CPWR_FALCON_SHA_REQ_CTRL__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_CTRL 0x00001098 /* RWI4R */ #define NV_CPWR_FALCON_SHA_CTRL__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_FALCON_SHA_CTRL__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_CTRL_FB_DIS 0:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_CTRL_FB_DIS_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_CTRL_FB_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_CYA 0x00001118 /* RWI4R */ #define NV_CPWR_FALCON_SHA_CYA__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_CYA_BW_THROTTLE_DIS 0:0 /* RWIVF */ #define NV_CPWR_FALCON_SHA_CYA_BW_THROTTLE_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_SHA_CYA_BW_THROTTLE_DIS_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_SHA_CYA__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_INFO 0x0000111c /* R-I4R */ #define NV_CPWR_FALCON_SHA_DBG_INFO__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_INFO__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_INFO_PW_HALTED 13:13 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_INFO_PW_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_PW_HALTED_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_IDMA_HALTED 12:12 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_INFO_IDMA_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_IDMA_HALTED_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_ALU_HALTED 11:11 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_INFO_ALU_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_ALU_HALTED_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_PW_IDLE 10:10 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_INFO_PW_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_PW_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_IDMA_IDLE 9:9 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_INFO_IDMA_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_IDMA_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_ALU_IDLE 8:8 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_INFO_ALU_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_ALU_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_CORE_STATUS 6:4 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_INFO_CORE_STATUS_IDLE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_CORE_STATUS_BUSY 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_INFO_SECURE_LEVEL 1:0 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_INFO_SECURE_LEVEL_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_0 0x00001140 /* R--4R */ #define NV_CPWR_FALCON_SHA_DBG_REG_0__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_0__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_0_SHA_SHA_PREPROC_STATE 11:10 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_0_SHA_WD_NUMBER 9:6 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_0_SHA_SHA_HASH_STATE 5:3 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_0_SHA_BYTE_COUNTER 2:0 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_1 0x00001144 /* R-I4R */ #define NV_CPWR_FALCON_SHA_DBG_REG_1__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_1__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN 18:18 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN 17:17 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS 14:14 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_2 0x00001148 /* R--4R */ #define NV_CPWR_FALCON_SHA_DBG_REG_2__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_2__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_SIZE 23:0 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_ADDR 31:24 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_3 0x0000114c /* R--4R */ #define NV_CPWR_FALCON_SHA_DBG_REG_3__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_3__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_3_SHA_IDMA_RESP_DMA_ADDR 31:0 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_4 0x00001150 /* R--4R */ #define NV_CPWR_FALCON_SHA_DBG_REG_4__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_4__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_4_SHA_IDMA_RESP_DMA_ADDR 8:0 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_4_SHA_IDMA_CORRECTED_RESP_DMA_SIZE 31:11 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_5 0x00001154 /* R--4R */ #define NV_CPWR_FALCON_SHA_DBG_REG_5__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_5__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_5_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 31:0 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6 0x00001158 /* R--4R */ #define NV_CPWR_FALCON_SHA_DBG_REG_6__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_6__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 12:0 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_FREE_COUNT 21:16 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH 24:24 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE 25:25 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE 26:26 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA 27:27 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_TRUE 0x00000001 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_LASTBUF 28:28 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0 29:29 /* R-IVF */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_SHA_DBG_REG_7 0x0000115c /* R--4R */ #define NV_CPWR_FALCON_SHA_DBG_REG_7__DEVICE_MAP 0x0000000a /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_7__PRIV_LEVEL_MASK 0x00001128 /* */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_PVLD 25:25 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_READ 24:24 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PRDY 23:23 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PVLD 22:22 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PRDY 21:21 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PVLD 20:20 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_VALID 15:15 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_STALL 14:14 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_PVLD 9:9 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_STALL 8:8 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PVLD 7:7 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PRDY 6:6 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PVLD 5:5 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PRDY 4:4 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_REQ 1:1 /* R--VF */ #define NV_CPWR_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_BUSY 0:0 /* R--VF */ #define NV_CPWR_FALCON_VER 0x00001188 /* R-I4R */ #define NV_CPWR_FALCON_VER_MAJOR 3:0 /* R-IVF */ #define NV_CPWR_FALCON_VER_MAJOR_DEFT 0x00000002 /* R-I-V */ #define NV_CPWR_FALCON_VER_MINOR 17:4 /* R-IVF */ #define NV_CPWR_FALCON_VER_MINOR_DEFT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_VER_BUGFIX 31:18 /* R-IVF */ #define NV_CPWR_FALCON_VER_BUGFIX_DEFT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_MOD_SEL 0x00001180 /* RWI4R */ #define NV_CPWR_FALCON_MOD_SEL__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_MOD_SEL_ALGO 7:0 /* RWIVF */ #define NV_CPWR_FALCON_MOD_SEL_ALGO_AES 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_MOD_SEL_ALGO_RSA3K 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_MOD_EN 0x00001184 /* RW-4R */ #define NV_CPWR_FALCON_MOD_EN__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_MOD_EN_AES 0:0 /* RWIVF */ #define NV_CPWR_FALCON_MOD_EN_AES_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_MOD_EN_AES_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_MOD_EN_RSA3K 1:1 /* RWIVF */ #define NV_CPWR_FALCON_MOD_EN_RSA3K_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_MOD_EN_RSA3K_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_PKCBROM_VER 0x0000118c /* R--4R */ #define NV_CPWR_FALCON_PKCBROM_VER__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_PKCBROM_VER_DEV 11:0 /* R--VF */ #define NV_CPWR_FALCON_PKCBROM_VER_ECO 15:12 /* R--VF */ #define NV_CPWR_FALCON_PKCBROM_VER_MINOR 23:16 /* R--VF */ #define NV_CPWR_FALCON_PKCBROM_VER_MAJOR 31:24 /* R--VF */ #define NV_CPWR_FALCON_VHRCFG_BASE 0x00001190 /* R-I4R */ #define NV_CPWR_FALCON_VHRCFG_BASE_VAL 31:0 /* R-IVF */ #define NV_CPWR_FALCON_VHRCFG_BASE_VAL_SEC 0x00008200 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_BASE_VAL_PWR_PMU 0x000083f0 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_BASE_VAL_NVDEC 0x00008490 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_BASE_VAL_GSP 0x000087a0 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_BASE_VAL_SOE 0x00008200 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_BASE_VAL_PSC 0x00000000 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_BASE_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM 0x000011e8 /* R-I4R */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM_VAL 31:0 /* R-IVF */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM_VAL_SEC 0x0000000a /* R---V */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM_VAL_PWR_PMU 0x00000003 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM_VAL_NVDEC 0x00000010 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM_VAL_GSP 0x00000003 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM_VAL_SOE 0x0000000a /* R---V */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM_VAL_PSC 0x00000000 /* R---V */ #define NV_CPWR_FALCON_VHRCFG_ENTNUM_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_BMEMBASE 0x00001194 /* R-I4R */ #define NV_CPWR_FALCON_BMEMBASE__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_BMEMBASE_VAL 31:0 /* R-IVF */ #define NV_CPWR_FALCON_BMEMBASE_VAL_DEFT 0x02100000 /* R-I-V */ #define NV_CPWR_FALCON_BROM_CURR_UCODE_ID 0x00001198 /* RWI4R */ #define NV_CPWR_FALCON_BROM_CURR_UCODE_ID__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_BROM_CURR_UCODE_ID__PRIV_LEVEL_MASK 0x00001250 /* */ #define NV_CPWR_FALCON_BROM_CURR_UCODE_ID_VAL 7:0 /* RWIVF */ #define NV_CPWR_FALCON_BROM_CURR_UCODE_ID_VAL_DEFT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_BROM_CURR_UCODE_ID_VAL_MAX 0x00000010 /* RW--V */ #define NV_CPWR_FALCON_UCODE_VERSION(i) (0x000011a8+(i)*4) /* R-I4A */ #define NV_CPWR_FALCON_UCODE_VERSION__SIZE_1 16 /* */ #define NV_CPWR_FALCON_UCODE_VERSION__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_FALCON_UCODE_VERSION_VER 7:0 /* R-IVF */ #define NV_CPWR_FALCON_UCODE_VERSION_VER_DEF 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK 0x0000119c /* RWI4R */ #define NV_CPWR_FALCON_BROM_ENGIDMASK__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_BROM_ENGIDMASK__PRIV_LEVEL_MASK 0x00001250 /* */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_SEC 0:0 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_SEC_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_SEC_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_DPU 1:1 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_DPU_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_DPU_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVDEC 2:2 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVDEC_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVDEC_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_PMU 3:3 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_PMU_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_PMU_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_FBFALCON 4:4 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_FBFALCON_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_FBFALCON_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVENC 5:5 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVENC_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVENC_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_GPCCS 6:6 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_GPCCS_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_GPCCS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_FECS 7:7 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_FECS_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_FECS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_MINION 8:8 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_MINION_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_MINION_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_XUSB 9:9 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_XUSB_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_XUSB_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_GSP 10:10 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_GSP_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_GSP_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVJPG 11:11 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVJPG_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_NVJPG_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_OFA 12:12 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_OFA_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_OFA_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_PSC 13:13 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_PSC_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_PSC_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_SOE 14:14 /* RWIVF */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_SOE_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_BROM_ENGIDMASK_SOE_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL 0x000011ec /* RWI4R */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL__PRIV_LEVEL_MASK 0x0000125c /* */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_HWVER_VALID 0:0 /* R-IVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY 1:1 /* R-IVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD 4:4 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_CTKID_VALID 8:8 /* R-IVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY 9:9 /* R-IVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD 12:12 /* RWIVF */ #define NV_CPWR_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_PR_CTKID 0x000011f0 /* R-I4R */ #define NV_CPWR_FALCON_PR_CTKID__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_FALCON_PR_CTKID_VAL 7:0 /* R-IVF */ #define NV_CPWR_FALCON_PR_CTKID_VAL_DEF 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_BROM_FUNID 0x000011a0 /* R-I4R */ #define NV_CPWR_FALCON_BROM_FUNID__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_BROM_FUNID_ID 7:0 /* R-IVF */ #define NV_CPWR_FALCON_BROM_FUNID_ID_DEFT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_BROM_FUNID_ID_DECFUSEKEY 0x00000001 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_ID_GENTK 0x00000002 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_ID_DECMPK 0x00000003 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_ID_SIGBYMPK 0x00000004 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_ID_CLRMPK 0x00000005 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_ID_ECDSASIGN 0x00000006 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_ID_ECDSAVERIF 0x00000007 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_CALLER_LVL 9:8 /* R-IVF */ #define NV_CPWR_FALCON_BROM_FUNID_CALLER_LVL_0 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_BROM_FUNID_CALLER_LVL_1 0x00000001 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_CALLER_LVL_2 0x00000002 /* R---V */ #define NV_CPWR_FALCON_BROM_FUNID_CALLER_LVL_3 0x00000003 /* R---V */ #define NV_CPWR_FALCON_BROM_PARAADDR(i) (0x00001210+(i)*4) /* RWI4A */ #define NV_CPWR_FALCON_BROM_PARAADDR__SIZE_1 1 /* */ #define NV_CPWR_FALCON_BROM_PARAADDR__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_BROM_PARAADDR__PRIV_LEVEL_MASK 0x00001250 /* */ #define NV_CPWR_FALCON_BROM_PARAADDR_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_BROM_PARAADDR_VAL_DEFT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_BROM_RETCODE 0x000011a4 /* RW-4R */ #define NV_CPWR_FALCON_BROM_RETCODE__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR 7:0 /* RWIVF */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_SUCCESS 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLFUNID 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_PA_FAULT 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NOT_IN_DMEM 0x00000003 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NO_ENOUGH_SPACE 0x00000004 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_VA_NOT_VALID 0x00000005 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_4BYTES 0x00000006 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_16BYTES 0x00000007 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_32BYTES 0x00000008 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_OUTPUT_NOT_ALLOWED 0x00000009 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_TK_PTR_IS_NS_READABLE 0x0000000a /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_NOT_CALLED_BY_HS 0x0000000b /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_CALL_FROM_LVL0 0x0000000c /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLUCODEID 0x0000000d /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_DISPOSE_MPK_FAIL 0x0000000e /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_CTKID_INVALID 0x0000000f /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLTKID 0x00000010 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_INVLDPMUK 0x00000011 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_INVLDPDUK 0x00000012 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_INVLDMPK 0x00000013 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_SIGFAIL 0x00000014 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_PDI_INVALID 0x00000015 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_LOAD_KMEM2SCP_FAIL 0x00000016 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_WRONG_PROTECTINFO 0x00000017 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_KSLT_K3_IS_0 0x00000018 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF16B 0x00000019 /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF32B 0x0000001a /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_RSVD_ZEROS 0x0000001b /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_MPK_IS_VALID 0x0000001c /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_SCP_ERR 0x0000001d /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_256BYTES 0x0000001e /* RW--V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERRID 19:8 /* RWIVF */ #define NV_CPWR_FALCON_BROM_RETCODE_ERRID_DEFT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_BROM_RETCODE_FUNID 23:20 /* RWIVF */ #define NV_CPWR_FALCON_BROM_RETCODE_FUNID_DEFT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_BROM_RETCODE_ERRINFO 31:24 /* RWIVF */ #define NV_CPWR_FALCON_BROM_RETCODE_ERRINFO_DEFT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_KMEMBASE 0x000011f4 /* R-I4R */ #define NV_CPWR_FALCON_KMEMBASE__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_KMEMBASE_VAL 31:0 /* R-IVF */ #define NV_CPWR_FALCON_KMEMBASE_VAL_DEF 0x02000000 /* R-I-V */ #define NV_CPWR_FALCON_KMEMC(i) (0x000011f8+(i)*4) /* RWI4A */ #define NV_CPWR_FALCON_KMEMC__SIZE_1 2 /* */ #define NV_CPWR_FALCON_KMEMC__DEVICE_MAP 0x0000000b /* */ #define NV_CPWR_FALCON_KMEMC__PRIV_LEVEL_MASK 0x00001254 /* */ #define NV_CPWR_FALCON_KMEMC_OFFS 15:2 /* RWIVF */ #define NV_CPWR_FALCON_KMEMC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_KMEMC_OFFS_PROTINFO 0x00000400 /* RW--V */ #define NV_CPWR_FALCON_KMEMC_OFFS_MAX 0x000005ff /* RW--V */ #define NV_CPWR_FALCON_KMEMC_AINCW 24:24 /* RWIVF */ #define NV_CPWR_FALCON_KMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_KMEMC_AINCW_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_KMEMC_AINCR 25:25 /* RWIVF */ #define NV_CPWR_FALCON_KMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_KMEMC_AINCR_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_KMEMC_ERR 28:26 /* R-IVF */ #define NV_CPWR_FALCON_KMEMC_ERR_SUCCESS 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KMEMC_ERR_1 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KMEMC_ERR_2 0x00000002 /* R---V */ #define NV_CPWR_FALCON_KMEMC_ERR_3 0x00000003 /* R---V */ #define NV_CPWR_FALCON_KMEMC_ERR_4 0x00000004 /* R---V */ #define NV_CPWR_FALCON_KMEMC_ERR_5 0x00000005 /* R---V */ #define NV_CPWR_FALCON_KMEMC_ERR_6 0x00000006 /* R---V */ #define NV_CPWR_FALCON_KMEMC_ERR_7 0x00000007 /* R---V */ #define NV_CPWR_FALCON_KMEMD(i) (0x00001200+(i)*4) /* RW-4A */ #define NV_CPWR_FALCON_KMEMD__SIZE_1 2 /* */ #define NV_CPWR_FALCON_KMEMD__DEVICE_MAP 0x0000000b /* */ #define NV_CPWR_FALCON_KMEMD__PRIV_LEVEL_MASK 0x00001254 /* */ #define NV_CPWR_FALCON_KMEMD_DATA 31:0 /* RW-VF */ #define NV_CPWR_FALCON_KMEM_CTL 0x00001208 /* RWI4R */ #define NV_CPWR_FALCON_KMEM_CTL__DEVICE_MAP 0x0000000b /* */ #define NV_CPWR_FALCON_KMEM_CTL__PRIV_LEVEL_MASK 0x00001254 /* */ #define NV_CPWR_FALCON_KMEM_CTL_IDX 7:0 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_CTL_IDX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_KMEM_CTL_CMD 19:16 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_CTL_CMD_NOP 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_KMEM_CTL_CMD_DISPOSE 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_KMEM_CTL_CMD_LOADTO63 0x00000002 /* RW--V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT 23:20 /* R-IVF */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_NOP 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_DONE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_RECYCLABLE_IS_0 0x00000002 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_PRIVDISABLED 0x00000003 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_NOTWRITEABLE 0x00000004 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_DONE 0x00000005 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_LOADABLE_IS_0 0x00000006 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_PRIVDISABLED 0x00000007 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_UCODIDMASK_IS_0 0x00000008 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_SLOT_MASK 0x00000009 /* R---V */ #define NV_CPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_SLOT_MASK 0x0000000a /* R---V */ #define NV_CPWR_FALCON_KMEMCFG 0x0000120c /* R-I4R */ #define NV_CPWR_FALCON_KMEMCFG_NUMOFKSLT 15:0 /* R-IVF */ #define NV_CPWR_FALCON_KMEMCFG_NUMOFKSLT_DEFT 0x00000100 /* R-I-V */ #define NV_CPWR_FALCON_KMEMCFG_KSLT_LENGTH 21:16 /* R-IVF */ #define NV_CPWR_FALCON_KMEMCFG_KSLT_LENGTH_DEFT 0x00000010 /* R-I-V */ #define NV_CPWR_FALCON_KMEMCFG_PROTECTINFO_LENGTH 25:22 /* R-IVF */ #define NV_CPWR_FALCON_KMEMCFG_PROTECTINFO_LENGTH_DEFT 0x00000008 /* R-I-V */ #define NV_CPWR_FALCON_KMEMCFG_BROM_USED_SLOTS 31:26 /* R-IVF */ #define NV_CPWR_FALCON_KMEMCFG_BROM_USED_SLOTS_DEFT 0x00000010 /* R-I-V */ #define NV_CPWR_FALCON_KMEM_VALID(i) (0x00001218+(i)*4) /* R-I4A */ #define NV_CPWR_FALCON_KMEM_VALID__SIZE_1 8 /* */ #define NV_CPWR_FALCON_KMEM_VALID__DEVICE_MAP 0x0000000b /* */ #define NV_CPWR_FALCON_KMEM_VALID__PRIV_LEVEL_MASK 0x00001254 /* */ #define NV_CPWR_FALCON_KMEM_VALID_VAL 31:0 /* R-IVF */ #define NV_CPWR_FALCON_KMEM_VALID_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KMEM_VIOLATION_CTL 0x00001238 /* RWI4R */ #define NV_CPWR_FALCON_KMEM_VIOLATION_CTL__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_KMEM_VIOLATION_CTL__PRIV_LEVEL_MASK 0x00001254 /* */ #define NV_CPWR_FALCON_KMEM_VIOLATION_CTL_ACT 0:0 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_VIOLATION_CTL_ACT_HALT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_KMEM_VIOLATION_CTL_ACT_EXC 0x00000001 /* RW--V */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF 0x0000123c /* R-I4R */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF__DEVICE_MAP 0x00000012 /* */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP 0:0 /* R-IVF */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_READ 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_WRITE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL 5:4 /* R-IVF */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID 15:8 /* R-IVF */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX 23:16 /* R-IVF */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET 24:24 /* R-IVF */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_KSLT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_PROTINFO 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KMEM_SLOT_MASK 0x00001240 /* RWI4R */ #define NV_CPWR_FALCON_KMEM_SLOT_MASK__DEVICE_MAP 0x00000008 /* */ #define NV_CPWR_FALCON_KMEM_SLOT_MASK__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_FALCON_KMEM_SLOT_MASK_VAL 31:0 /* RWIVF */ #define NV_CPWR_FALCON_KMEM_SLOT_MASK_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FALCON_KEYGLOB_CTRL 0x00001248 /* RWI4R */ #define NV_CPWR_FALCON_KEYGLOB_CTRL__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_FALCON_KEYGLOB_CTRL__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_INDEX 7:0 /* R-IVF */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_INDEX_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_STAT_VALID 16:16 /* R-IVF */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_STAT_VALID_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_STAT_VALID_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_STAT_BUSY 17:17 /* R-IVF */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_STAT_BUSY_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_STAT_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_STAT_RELOAD 20:20 /* RWIVF */ #define NV_CPWR_FALCON_KEYGLOB_CTRL_STAT_RELOAD_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FALCON_KEYGLOB_DATA 0x0000124c /* R--4R */ #define NV_CPWR_FALCON_KEYGLOB_DATA__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_FALCON_KEYGLOB_DATA__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_FALCON_KEYGLOB_DATA_VAL 31:0 /* R-XVF */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK 0x00001304 /* RWI4R */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK 0x00001308 /* RWI4R */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK 0x00001300 /* RWI4R */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK 0x00001314 /* RWI4R */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK 0x00001310 /* RWI4R */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK 0x00001664 /* RWI4R */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK 0x00001690 /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK 0x0000130c /* RWI4R */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK 0x00001318 /* RWI4R */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK 0x0000131c /* RWI4R */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_RISCV_IRQMSET 0x00001520 /* -W-4R */ #define NV_CPWR_RISCV_IRQMSET__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_IRQMSET__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_RISCV_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_EXT 15:8 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_EXT_CTXE 8:8 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_CTXE_SET 1 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_LIMITV 9:9 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_LIMITV_SET 1 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_ECC 10:10 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_ECC_SET 1 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_SECOND 11:11 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_SECOND_SET 1 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_THERM 12:12 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_THERM_SET 1 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_MISCIO 13:13 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_MISCIO_SET 1 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_RTTIMER 14:14 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_RTTIMER_SET 1 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_RSVD8 15:15 /* */ #define NV_CPWR_RISCV_IRQMSET_EXT_RSVD8_SET 1 /* */ #define NV_CPWR_RISCV_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_SHA 17:17 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_SHA_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_MEMERR 18:18 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_MEMERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_ICD 22:22 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_ICD_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_IOPMP 23:23 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_IOPMP_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMSET_CORE_MISMATCH 24:24 /* -WXVF */ #define NV_CPWR_RISCV_IRQMSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR 0x00001524 /* -W-4R */ #define NV_CPWR_RISCV_IRQMCLR__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_IRQMCLR__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_RISCV_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_EXT 15:8 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_EXT_CTXE 8:8 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_CTXE_SET 1 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_LIMITV 9:9 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_LIMITV_SET 1 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_ECC 10:10 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_ECC_SET 1 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_SECOND 11:11 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_SECOND_SET 1 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_THERM 12:12 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_THERM_SET 1 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_MISCIO 13:13 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_MISCIO_SET 1 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_RTTIMER 14:14 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_RTTIMER_SET 1 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_RSVD8 15:15 /* */ #define NV_CPWR_RISCV_IRQMCLR_EXT_RSVD8_SET 1 /* */ #define NV_CPWR_RISCV_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_SHA 17:17 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_SHA_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_MEMERR 18:18 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_MEMERR_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_ICD 22:22 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_ICD_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMCLR_IOPMP 23:23 /* -WXVF */ #define NV_CPWR_RISCV_IRQMCLR_IOPMP_SET 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_IRQMASK 0x00001528 /* R-I4R */ #define NV_CPWR_RISCV_IRQMASK__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_GPTMR_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_GPTMR_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_WDTMR_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_WDTMR_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_MTHD_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_MTHD_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_CTXSW_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_CTXSW_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_HALT_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_HALT_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXTERR_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXTERR_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_SWGEN0_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_SWGEN0_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_SWGEN1_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_SWGEN1_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_EXT 15:8 /* */ #define NV_CPWR_RISCV_IRQMASK_EXT_CTXE 8:8 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXT_CTXE_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXT_CTXE_SET 1 /* */ #define NV_CPWR_RISCV_IRQMASK_EXT_LIMITV 9:9 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXT_LIMITV_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXT_LIMITV_SET 1 /* */ #define NV_CPWR_RISCV_IRQMASK_EXT_ECC 10:10 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXT_ECC_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXT_ECC_SET 1 /* */ #define NV_CPWR_RISCV_IRQMASK_EXT_SECOND 11:11 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXT_SECOND_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXT_SECOND_SET 1 /* */ #define NV_CPWR_RISCV_IRQMASK_EXT_THERM 12:12 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXT_THERM_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXT_THERM_SET 1 /* */ #define NV_CPWR_RISCV_IRQMASK_EXT_MISCIO 13:13 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXT_MISCIO_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXT_MISCIO_SET 1 /* */ #define NV_CPWR_RISCV_IRQMASK_EXT_RTTIMER 14:14 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXT_RTTIMER_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXT_RTTIMER_SET 1 /* */ #define NV_CPWR_RISCV_IRQMASK_EXT_RSVD8 15:15 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_EXT_RSVD8_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_EXT_RSVD8_SET 1 /* */ #define NV_CPWR_RISCV_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_DMA_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_DMA_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_SHA 17:17 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_SHA_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_SHA_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_MEMERR 18:18 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_MEMERR_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_MEMERR_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_ICD 22:22 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_ICD_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_ICD_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_IOPMP 23:23 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_IOPMP_UNSET 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_IOPMP_SET 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IRQMASK_CORE_MISMATCH 24:24 /* R-IVF */ #define NV_CPWR_RISCV_IRQMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R-I-V */ #define NV_CPWR_RISCV_IRQMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_RISCV_IRQDEST 0x0000152c /* RW-4R */ #define NV_CPWR_RISCV_IRQDEST__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_IRQDEST__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_RISCV_IRQDEST_GPTMR 0:0 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_GPTMR_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_GPTMR_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_WDTMR 1:1 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_WDTMR_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_WDTMR_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_MTHD 2:2 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_MTHD_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_MTHD_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_CTXSW 3:3 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_CTXSW_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_CTXSW_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_HALT 4:4 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_HALT_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_HALT_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXTERR 5:5 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXTERR_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXTERR_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_SWGEN0 6:6 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_SWGEN0_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_SWGEN0_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_SWGEN1 7:7 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_SWGEN1_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_SWGEN1_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXT 15:8 /* */ #define NV_CPWR_RISCV_IRQDEST_EXT_CTXE 8:8 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXT_CTXE_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXT_CTXE_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXT_LIMITV 9:9 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXT_LIMITV_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXT_LIMITV_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXT_ECC 10:10 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXT_ECC_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXT_ECC_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXT_SECOND 11:11 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXT_SECOND_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXT_SECOND_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXT_THERM 12:12 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXT_THERM_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXT_THERM_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXT_MISCIO 13:13 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXT_MISCIO_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXT_MISCIO_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXT_RTTIMER 14:14 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXT_RTTIMER_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXT_RTTIMER_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_EXT_RSVD8 15:15 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_EXT_RSVD8_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_EXT_RSVD8_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_DMA 16:16 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_DMA_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_DMA_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_SHA 17:17 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_SHA_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_SHA_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_MEMERR 18:18 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_MEMERR_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_MEMERR_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_ICD 22:22 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_ICD_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_ICD_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_IOPMP 23:23 /* RWIVF */ #define NV_CPWR_RISCV_IRQDEST_IOPMP_RISCV 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDEST_IOPMP_HOST 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDEST_CORE_MISMATCH 24:24 /* R-IVF */ #define NV_CPWR_RISCV_IRQDEST_CORE_MISMATCH_RISCV 0x00000000 /* R---V */ #define NV_CPWR_RISCV_IRQDEST_CORE_MISMATCH_HOST 0x00000001 /* R-I-V */ #define NV_CPWR_RISCV_IRQTYPE 0x00001530 /* RWI4R */ #define NV_CPWR_RISCV_IRQTYPE__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_IRQTYPE__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_RISCV_IRQTYPE_GPTMR 0:0 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_GPTMR_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_WDTMR 1:1 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_WDTMR_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_MTHD 2:2 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_MTHD_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_CTXSW 3:3 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_CTXSW_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_HALT 4:4 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_HALT_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_HALT_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXTERR 5:5 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXTERR_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_SWGEN0 6:6 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_SWGEN0_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_SWGEN1 7:7 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_SWGEN1_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXT 15:8 /* */ #define NV_CPWR_RISCV_IRQTYPE_EXT_CTXE 8:8 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXT_CTXE_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_CTXE_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_LIMITV 9:9 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXT_LIMITV_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_LIMITV_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_ECC 10:10 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXT_ECC_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_ECC_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_SECOND 11:11 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXT_SECOND_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_SECOND_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_THERM 12:12 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXT_THERM_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_THERM_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_MISCIO 13:13 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXT_MISCIO_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_MISCIO_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_RTTIMER 14:14 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXT_RTTIMER_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_RTTIMER_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_RSVD8 15:15 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_EXT_RSVD8_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_EXT_RSVD8_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_DMA 16:16 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_DMA_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_DMA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_SHA 17:17 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_SHA_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_SHA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_MEMERR 18:18 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_MEMERR_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_MEMERR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_ICD 22:22 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_ICD_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_ICD_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_IOPMP 23:23 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_IOPMP_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_IOPMP_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQTYPE_CORE_MISMATCH 24:24 /* RWIVF */ #define NV_CPWR_RISCV_IRQTYPE_CORE_MISMATCH_HOST_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQTYPE_CORE_MISMATCH_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG 0x00001534 /* RWI4R */ #define NV_CPWR_RISCV_IRQDELEG__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_IRQDELEG__PRIV_LEVEL_MASK 0x00000290 /* */ #define NV_CPWR_RISCV_IRQDELEG_GPTMR 0:0 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_GPTMR_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_GPTMR_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_WDTMR 1:1 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_WDTMR_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_WDTMR_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_MTHD 2:2 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_MTHD_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_MTHD_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_CTXSW 3:3 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_CTXSW_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_CTXSW_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_HALT 4:4 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_HALT_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_HALT_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXTERR 5:5 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXTERR_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXTERR_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_SWGEN0 6:6 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_SWGEN0_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_SWGEN0_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_SWGEN1 7:7 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_SWGEN1_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_SWGEN1_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXT 15:8 /* */ #define NV_CPWR_RISCV_IRQDELEG_EXT_CTXE 8:8 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXT_CTXE_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_CTXE_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_LIMITV 9:9 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXT_LIMITV_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_LIMITV_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_ECC 10:10 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXT_ECC_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_ECC_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_SECOND 11:11 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXT_SECOND_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_SECOND_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_THERM 12:12 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXT_THERM_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_THERM_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_MISCIO 13:13 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXT_MISCIO_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_MISCIO_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_RTTIMER 14:14 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXT_RTTIMER_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_RTTIMER_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_RSVD8 15:15 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_EXT_RSVD8_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_EXT_RSVD8_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_DMA 16:16 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_DMA_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_DMA_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_SHA 17:17 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_SHA_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_SHA_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_MEMERR 18:18 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_MEMERR_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_MEMERR_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_ICD 22:22 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_ICD_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_ICD_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_IOPMP 23:23 /* RWIVF */ #define NV_CPWR_RISCV_IRQDELEG_IOPMP_RISCV_MEIP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IRQDELEG_IOPMP_RISCV_SEIP 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IRQDELEG_CORE_MISMATCH 24:24 /* R-IVF */ #define NV_CPWR_RISCV_IRQDELEG_CORE_MISMATCH_RISCV_MEIP 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IRQDELEG_CORE_MISMATCH_RISCV_SEIP 0x00000001 /* R---V */ #define NV_CPWR_RISCV_BOOT_VECTOR_HI 0x00001384 /* RWI4R */ #define NV_CPWR_RISCV_BOOT_VECTOR_HI__PRIV_LEVEL_MASK 0x00001310 /* */ #define NV_CPWR_RISCV_BOOT_VECTOR_HI_VECTOR 31:0 /* RWIVF */ #define NV_CPWR_RISCV_BOOT_VECTOR_HI_VECTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BOOT_VECTOR_LO 0x00001380 /* RWI4R */ #define NV_CPWR_RISCV_BOOT_VECTOR_LO__PRIV_LEVEL_MASK 0x00001310 /* */ #define NV_CPWR_RISCV_BOOT_VECTOR_LO_VECTOR 31:0 /* RWIVF */ #define NV_CPWR_RISCV_BOOT_VECTOR_LO_VECTOR_INIT 0x00080000 /* RWI-V */ #define NV_CPWR_RISCV_CPUCTL 0x00001388 /* RWI4R */ #define NV_CPWR_RISCV_CPUCTL__PRIV_LEVEL_MASK 0x00001308 /* */ #define NV_CPWR_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */ #define NV_CPWR_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */ #define NV_CPWR_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */ #define NV_CPWR_RISCV_CPUCTL_HALTED_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */ #define NV_CPWR_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */ #define NV_CPWR_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */ #define NV_CPWR_RISCV_NVCONFIG 0x00001390 /* RWI4R */ #define NV_CPWR_RISCV_NVCONFIG__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_NVCONFIG__PRIV_LEVEL_MASK 0x0000130c /* */ #define NV_CPWR_RISCV_NVCONFIG_WR_ALLOC_EN 0:0 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_WR_ALLOC_EN_RST 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_LD_MERGE_EN 1:1 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_LD_MERGE_EN_RST 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_ST_WAIT_CSB_ACK_EN 2:2 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_ST_WAIT_CSB_ACK_EN_RST 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_ST_WAIT_FBIF_ACK_EN 3:3 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_ST_WAIT_FBIF_ACK_EN_RST 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_VB_FWD_EN 4:4 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_VB_FWD_EN_RST 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_WRITE_BACK_EN 6:6 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_WRITE_BACK_EN_RST 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_ST_COMMIT_ISSUE_EN 7:7 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_ST_COMMIT_ISSUE_EN_RST 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_TLB_FIX_SIZE_EN 8:8 /* RWIVF */ #define NV_CPWR_RISCV_NVCONFIG_TLB_FIX_SIZE_EN_RST 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_NVCONFIG_SYSOP_CSR_EN 9:9 /* R-IVF */ #define NV_CPWR_RISCV_NVCONFIG_SYSOP_CSR_EN_RST 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_NVCONFIG_FENCE_FBFLUSH_EN 10:10 /* R-IVF */ #define NV_CPWR_RISCV_NVCONFIG_FENCE_FBFLUSH_EN_RST 0x00000001 /* R-I-V */ #define NV_CPWR_RISCV_CG 0x00001398 /* RWI4R */ #define NV_CPWR_RISCV_CG__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_CG__PRIV_LEVEL_MASK 0x00001304 /* */ #define NV_CPWR_RISCV_CG_SLCG 0:0 /* RWIVF */ #define NV_CPWR_RISCV_CG_SLCG_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_CG_SLCG_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_CG_SLCG_DISABLED 0 /* */ #define NV_CPWR_RISCV_CG_SLCG_ENABLED 1 /* */ #define NV_CPWR_RISCV_CG_SLCG__PROD 1 /* */ #define NV_CPWR_RISCV_CG_CORE_SLCG 1:1 /* RWIVF */ #define NV_CPWR_RISCV_CG_CORE_SLCG_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_CG_CORE_SLCG_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_CG_RSVD 31:2 /* R-IVF */ #define NV_CPWR_RISCV_CG_RSVD_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_CYA 0x0000139c /* RWI4R */ #define NV_CPWR_RISCV_CYA__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_CYA__PRIV_LEVEL_MASK 0x00001304 /* */ #define NV_CPWR_RISCV_CYA_RSVD 31:0 /* RWIVF */ #define NV_CPWR_RISCV_CYA_RSVD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL 0x000013c8 /* RW-4R */ #define NV_CPWR_RISCV_DBGCTL__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL__PRIV_LEVEL_MASK 0x00001314 /* */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_RSVD1 2:2 /* R-IVF */ #define NV_CPWR_RISCV_DBGCTL_RSVD1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_J 4:4 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_J_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_J_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_EMASK 5:5 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RREG 6:6 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RREG_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RREG_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WREG 7:7 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WREG_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WREG_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RDM 8:8 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WDM 9:9 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WDM_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WDM_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RSTAT 10:10 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_IBRKPT 11:11 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_IBRKPT_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_IBRKPT_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RCSR 12:12 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RCSR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RCSR_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WCSR 13:13 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WCSR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WCSR_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RPC 14:14 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RPC_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RPC_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RFREG 15:15 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RFREG_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_RFREG_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WFREG 16:16 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WFREG_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_ICD_CMDWL_WFREG_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_RSVD 29:17 /* R-IVF */ #define NV_CPWR_RISCV_DBGCTL_RSVD_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_DBGCTL_START_IN_ICD 30:30 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_START_IN_ICD_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_START_IN_ICD_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_SINGLE_STEP_MODE 31:31 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_SINGLE_STEP_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_SINGLE_STEP_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK 0x000013cc /* RW-4R */ #define NV_CPWR_RISCV_DBGCTL_LOCK__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_DBGCTL_LOCK__PRIV_LEVEL_MASK 0x00001314 /* */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_RSVD1 2:2 /* R-IVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_RSVD1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_J 4:4 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_J_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_J_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK 5:5 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG 6:6 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG 7:7 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM 8:8 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM 9:9 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT 10:10 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT 11:11 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR 12:12 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR 13:13 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC 14:14 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG 15:15 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG 16:16 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_RSVD 30:17 /* R-IVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_RSVD_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE 31:31 /* RWIVF */ #define NV_CPWR_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD 0x000013d0 /* RW-4R */ #define NV_CPWR_RISCV_ICD_CMD__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_ICD_CMD_OPC 4:0 /* RWIVF */ #define NV_CPWR_RISCV_ICD_CMD_OPC_STOP 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_J 0x00000006 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_RCSR 0x00000010 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_WCSR 0x00000011 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_RPC 0x00000012 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_RFREG 0x00000013 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_OPC_WFREG 0x00000014 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_SZ 7:6 /* RWIVF */ #define NV_CPWR_RISCV_ICD_CMD_SZ_B 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_ICD_CMD_SZ_HW 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_SZ_W 0x00000002 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_SZ_DW 0x00000003 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX 12:8 /* RWIVF */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG0 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG16 0x00000010 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG17 0x00000011 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG18 0x00000012 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG19 0x00000013 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG20 0x00000014 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG21 0x00000015 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG22 0x00000016 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG23 0x00000017 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG24 0x00000018 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG25 0x00000019 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG26 0x0000001a /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG27 0x0000001b /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG28 0x0000001c /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG29 0x0000001e /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG30 0x0000001e /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_REG31 0x0000001f /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */ #define NV_CPWR_RISCV_ICD_CMD_ERROR 14:14 /* R-IVF */ #define NV_CPWR_RISCV_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_CMD_ERROR_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_ICD_CMD_BUSY 15:15 /* R-IVF */ #define NV_CPWR_RISCV_ICD_CMD_BUSY_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_ICD_CMD_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_CMD_PARM 31:16 /* RWIVF */ #define NV_CPWR_RISCV_ICD_CMD_PARM_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_ICD_ADDR0 0x000013d4 /* RW-4R */ #define NV_CPWR_RISCV_ICD_ADDR0__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_ICD_ADDR0_ADDR 31:0 /* RWIVF */ #define NV_CPWR_RISCV_ICD_ADDR0_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_ICD_ADDR1 0x000013d8 /* RW-4R */ #define NV_CPWR_RISCV_ICD_ADDR1__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_ICD_ADDR1_ADDR 31:0 /* RWIVF */ #define NV_CPWR_RISCV_ICD_ADDR1_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_ICD_WDATA0 0x000013dc /* RW-4R */ #define NV_CPWR_RISCV_ICD_WDATA0__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_ICD_WDATA0_DATA 31:0 /* RWIVF */ #define NV_CPWR_RISCV_ICD_WDATA0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_ICD_WDATA1 0x000013e0 /* RW-4R */ #define NV_CPWR_RISCV_ICD_WDATA1__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_ICD_WDATA1_DATA 31:0 /* RWIVF */ #define NV_CPWR_RISCV_ICD_WDATA1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_ICD_RDATA0 0x000013e4 /* R--4R */ #define NV_CPWR_RISCV_ICD_RDATA0__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_ICD_RDATA0_DATA 31:0 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_ROB_FULL 0:0 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_IFU_INSTBUF_FULL 1:1 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_IFU_LINEFILL_FULL 2:2 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_STB_FULL 3:3 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_MEM_WACK_FULL 4:4 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_IO_WACK_FULL 5:5 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_LINEFILL_FULL 6:6 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_VICBUF_FULL 7:7 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_CB_FULL 8:8 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_ALU_RS_FULL 9:9 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_IMD_RS_FULL 10:10 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_FPU_RS_FULL 11:11 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_IOWR_INFLIGHT 23:16 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT0_MEMWR_INFLIGHT 31:24 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_SSINT 1:1 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_SSINT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_SSINT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MSINT 3:3 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MSINT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MSINT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_STINT 5:5 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_STINT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_STINT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MTINT 7:7 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MTINT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MTINT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_SEINT 9:9 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_SEINT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_SEINT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MEINT 11:11 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MEINT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT3_MEINT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE 1:0 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_ACTIVE 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_INACTIVE 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_ICD 0x00000002 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_RS0 3:2 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_RS0_VALUE 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_TRIGGER_HIT_INDEX 10:4 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_RS1 31:11 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA0_RSTAT4_RS1_VALUE 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1 0x000013e8 /* R--4R */ #define NV_CPWR_RISCV_ICD_RDATA1__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_ICD_RDATA1_DATA 31:0 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IAMA 0:0 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IAMA_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IAMA_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IFAULT 1:1 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IFAULT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IFAULT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_ILL 2:2 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_ILL_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_ILL_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_BKPT 3:3 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_BKPT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_BKPT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LAMA 4:4 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LAMA_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LAMA_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LFAULT 5:5 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LFAULT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LFAULT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SAMA 6:6 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SAMA_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SAMA_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SFAULT 7:7 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SFAULT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SFAULT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_UCALL 8:8 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_UCALL_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_UCALL_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SCALL 9:9 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SCALL_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SCALL_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_MCALL 11:11 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_MCALL_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_MCALL_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IPFAULT 12:12 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IPFAULT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_IPFAULT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LPFAULT 13:13 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LPFAULT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_LPFAULT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SPFAULT 15:15 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SPFAULT_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_SPFAULT_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP 28:28 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP 29:29 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP_ENTER_ICD 0x00000001 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP_EXPT 0x00000000 /* R---V */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT4_RS 31:0 /* R--VF */ #define NV_CPWR_RISCV_ICD_RDATA1_RSTAT4_RS_VALUE 0x00000000 /* R---V */ #define NV_CPWR_RISCV_RPC 0x000013ec /* R--4R */ #define NV_CPWR_RISCV_RPC__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_RPC_PC_LO 31:0 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0 0x000013f0 /* R--4R */ #define NV_CPWR_RISCV_RSTAT0__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_RSTAT0_ROB_FULL 0:0 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_IFU_INSTBUF_FULL 1:1 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_IFU_LINEFILL_FULL 2:2 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_LSU_STB_FULL 3:3 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_LSU_MEM_WACK_FULL 4:4 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_LSU_IO_WACK_FULL 5:5 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_LSU_LINEFILL_FULL 6:6 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_LSU_VICBUF_FULL 7:7 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_LSU_CB_FULL 8:8 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_ALU_RS_FULL 9:9 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_IMD_RS_FULL 10:10 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_FPU_RS_FULL 11:11 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_IOWR_INFLIGHT 23:16 /* R--VF */ #define NV_CPWR_RISCV_RSTAT0_MEMWR_INFLIGHT 31:24 /* R--VF */ #define NV_CPWR_RISCV_TRACECTL 0x00001400 /* RW-4R */ #define NV_CPWR_RISCV_TRACECTL__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_TRACECTL__PRIV_LEVEL_MASK 0x00001318 /* */ #define NV_CPWR_RISCV_TRACECTL_LOW_THSHD 7:0 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_LOW_THSHD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_HIGH_THSHD 15:8 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_HIGH_THSHD_INIT 0x000000ff /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_UMODE_ENABLE 20:20 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_UMODE_ENABLE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_UMODE_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_TRACECTL_SMODE_ENABLE 21:21 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_SMODE_ENABLE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_SMODE_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_TRACECTL_MMODE_ENABLE 23:23 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_MMODE_ENABLE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_MMODE_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_TRACECTL_MODE 25:24 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_MODE_FULL 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_MODE_REDUCED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_TRACECTL_MODE_STACK 0x00000002 /* RW--V */ #define NV_CPWR_RISCV_TRACECTL_BELOW_LO 27:27 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_BELOW_LO_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_ABOVE_HI 28:28 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_ABOVE_HI_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_INTR_ENABLE 29:29 /* R-IVF */ #define NV_CPWR_RISCV_TRACECTL_INTR_ENABLE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_TRACECTL_INTR_ENABLE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_RISCV_TRACECTL_FULL 30:30 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_FULL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACECTL_EMPTY 31:31 /* RWIVF */ #define NV_CPWR_RISCV_TRACECTL_EMPTY_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACE_RDIDX 0x00001404 /* RW-4R */ #define NV_CPWR_RISCV_TRACE_RDIDX__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_TRACE_RDIDX__PRIV_LEVEL_MASK 0x00001318 /* */ #define NV_CPWR_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */ #define NV_CPWR_RISCV_TRACE_RDIDX_RDIDX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACE_RDIDX_RSVD0 15:8 /* R-IVF */ #define NV_CPWR_RISCV_TRACE_RDIDX_RSVD0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */ #define NV_CPWR_RISCV_TRACE_RDIDX_MAXIDX_INIT 0x0000003f /* R-I-V */ #define NV_CPWR_RISCV_TRACE_RDIDX_RSVD1 31:24 /* R-IVF */ #define NV_CPWR_RISCV_TRACE_RDIDX_RSVD1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_TRACE_WTIDX 0x00001408 /* RW-4R */ #define NV_CPWR_RISCV_TRACE_WTIDX__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_TRACE_WTIDX__PRIV_LEVEL_MASK 0x00001318 /* */ #define NV_CPWR_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */ #define NV_CPWR_RISCV_TRACE_WTIDX_WTIDX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACE_WTIDX_RSVD1 23:0 /* R-IVF */ #define NV_CPWR_RISCV_TRACE_WTIDX_RSVD1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_TRACEPC_HI 0x00001410 /* RW-4R */ #define NV_CPWR_RISCV_TRACEPC_HI__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_TRACEPC_HI__PRIV_LEVEL_MASK 0x00001318 /* */ #define NV_CPWR_RISCV_TRACEPC_HI_PC 31:0 /* RWIVF */ #define NV_CPWR_RISCV_TRACEPC_HI_PC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_TRACEPC_LO 0x0000140c /* RW-4R */ #define NV_CPWR_RISCV_TRACEPC_LO__DEVICE_MAP 0x00000009 /* */ #define NV_CPWR_RISCV_TRACEPC_LO__PRIV_LEVEL_MASK 0x00001318 /* */ #define NV_CPWR_RISCV_TRACEPC_LO_PC 31:0 /* RWIVF */ #define NV_CPWR_RISCV_TRACEPC_LO_PC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_MTIMECMP_HI 0x000013c4 /* RWI4R */ #define NV_CPWR_RISCV_MTIMECMP_HI__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_MTIMECMP_HI__PRIV_LEVEL_MASK 0x00001300 /* */ #define NV_CPWR_RISCV_MTIMECMP_HI_VALUE 31:0 /* RWIVF */ #define NV_CPWR_RISCV_MTIMECMP_HI_VALUE_INIT 0xffffffff /* RWI-V */ #define NV_CPWR_RISCV_MTIMECMP_LO 0x000013c0 /* RWI4R */ #define NV_CPWR_RISCV_MTIMECMP_LO__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_MTIMECMP_LO__PRIV_LEVEL_MASK 0x00001300 /* */ #define NV_CPWR_RISCV_MTIMECMP_LO_VALUE 31:0 /* RWIVF */ #define NV_CPWR_RISCV_MTIMECMP_LO_VALUE_INIT 0xffffffff /* RWI-V */ #define NV_CPWR_RISCV_INTR_STATUS 0x00001394 /* R-I4R */ #define NV_CPWR_RISCV_INTR_STATUS__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_INTR_STATUS__PRIV_LEVEL_MASK 0x00001300 /* */ #define NV_CPWR_RISCV_INTR_STATUS_S_SOFTWARE_INTR 5:5 /* R-IVF */ #define NV_CPWR_RISCV_INTR_STATUS_S_SOFTWARE_INTR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_INTR_STATUS_S_EXTERNAL_INTR 4:4 /* R-IVF */ #define NV_CPWR_RISCV_INTR_STATUS_S_EXTERNAL_INTR_INT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_INTR_STATUS_S_TIMER_INTR 3:3 /* R-IVF */ #define NV_CPWR_RISCV_INTR_STATUS_S_TIMER_INTR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_INTR_STATUS_SOFTWARE_INTR 2:2 /* R-IVF */ #define NV_CPWR_RISCV_INTR_STATUS_SOFTWARE_INTR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_INTR_STATUS_M_SOFTWARE_INTR 2:2 /* */ #define NV_CPWR_RISCV_INTR_STATUS_M_SOFTWARE_INTR_INIT 0 /* */ #define NV_CPWR_RISCV_INTR_STATUS_EXTERNAL_INTR 1:1 /* R-IVF */ #define NV_CPWR_RISCV_INTR_STATUS_EXTERNAL_INTR_INT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_INTR_STATUS_M_EXTERNAL_INTR 1:1 /* */ #define NV_CPWR_RISCV_INTR_STATUS_M_EXTERNAL_INTR_INT 0 /* */ #define NV_CPWR_RISCV_INTR_STATUS_TIMER_INTR 0:0 /* R-IVF */ #define NV_CPWR_RISCV_INTR_STATUS_TIMER_INTR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_INTR_STATUS_M_TIMER_INTR 0:0 /* */ #define NV_CPWR_RISCV_INTR_STATUS_M_TIMER_INTR_INIT 0 /* */ #define NV_CPWR_RISCV_MSIP 0x0000138c /* RWI4R */ #define NV_CPWR_RISCV_MSIP__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_MSIP__PRIV_LEVEL_MASK 0x0000131c /* */ #define NV_CPWR_RISCV_MSIP_VLD 0:0 /* RWIVF */ #define NV_CPWR_RISCV_MSIP_VLD_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_MSIP_VLD_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_PRIV_ERR_STAT 0x00001500 /* RWI4R */ #define NV_CPWR_RISCV_PRIV_ERR_STAT__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_PRIV_ERR_STAT__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_RISCV_PRIV_ERR_STAT_VALID 31:31 /* RWIVF */ #define NV_CPWR_RISCV_PRIV_ERR_STAT_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_PRIV_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_PRIV_ERR_STAT_RESERVED 30:0 /* R-IVF */ #define NV_CPWR_RISCV_PRIV_ERR_STAT_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_PRIV_ERR_INFO 0x00001504 /* R-I4R */ #define NV_CPWR_RISCV_PRIV_ERR_INFO__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_PRIV_ERR_INFO__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_RISCV_PRIV_ERR_INFO_ERROR_INFO 31:0 /* R-IVF */ #define NV_CPWR_RISCV_PRIV_ERR_INFO_ERROR_INFO_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR 0x00001508 /* R-I4R */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR_ADDR 31:0 /* R-IVF */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR_ADDR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR_HI 0x0000150c /* R-I4R */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR_HI__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR_HI_ADDR 31:0 /* R-IVF */ #define NV_CPWR_RISCV_PRIV_ERR_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_HUB_ERR_STAT 0x00001510 /* RWI4R */ #define NV_CPWR_RISCV_HUB_ERR_STAT__DEVICE_MAP 0x00000002 /* */ #define NV_CPWR_RISCV_HUB_ERR_STAT__PRIV_LEVEL_MASK 0x0000028c /* */ #define NV_CPWR_RISCV_HUB_ERR_STAT_VALID 31:31 /* RWIVF */ #define NV_CPWR_RISCV_HUB_ERR_STAT_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_HUB_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_HUB_ERR_STAT_RESERVED 30:0 /* RWIVF */ #define NV_CPWR_RISCV_HUB_ERR_STAT_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_INDEX 0x00001590 /* RWI4R */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_INDEX__DEVICE_MAP 0x0000000d /* */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_INDEX_INDEX 4:0 /* RWIVF */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_INDEX_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID 0x00001594 /* RWI4R */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID__DEVICE_MAP 0x0000000d /* */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID_ADDR 17:0 /* RWIVF */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID_VALID 31:31 /* RWIVF */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID_VALID_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_DATA 0x00001598 /* RWI4R */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_DATA__DEVICE_MAP 0x0000000d /* */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_DATA_DATA 15:0 /* RWIVF */ #define NV_CPWR_RISCV_IROM_PATCH_CAM_DATA_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IROM_PATCH_SECURE 0x0000159c /* RWI4R */ #define NV_CPWR_RISCV_IROM_PATCH_SECURE__DEVICE_MAP 0x0000000d /* */ #define NV_CPWR_RISCV_IROM_PATCH_SECURE_IPATCH_LOCK 0:0 /* RWIVF */ #define NV_CPWR_RISCV_IROM_PATCH_SECURE_IPATCH_LOCK_INIT 0x00000001 /* R-I-V */ #define NV_CPWR_RISCV_IOPMP_INDEX 0x000015b0 /* RWI4R */ #define NV_CPWR_RISCV_IOPMP_INDEX__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_INDEX__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_INDEX_VAL 4:0 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_INDEX_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_CFG 0x000015b4 /* RWI4R */ #define NV_CPWR_RISCV_IOPMP_CFG__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_CFG__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_READ 0:0 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_CFG_READ_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IOPMP_CFG_READ_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_CFG_WRITE 1:1 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_CFG_WRITE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IOPMP_CFG_WRITE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER 15:4 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_ALL_MASTERS_ENABLED 0x00000ff7 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_FBDMA 4:4 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_FBDMA_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_FBDMA_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_CPDMA 5:5 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_CPDMA_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_CPDMA_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_SHA 6:6 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_SHA_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_SHA_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_PMB(i) (8+(i)):(8+(i)) /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_PMB__SIZE_1 8 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_PMB_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_MASTER_PMB_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IOPMP_CFG_LOCK 31:31 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_CFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_CFG_LOCK_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IOPMP_ADDR_HI 0x000015bc /* RWI4R */ #define NV_CPWR_RISCV_IOPMP_ADDR_HI__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_ADDR_HI__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_ADDR_HI_VAL 28:0 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_ADDR_HI_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_ADDR_LO 0x000015b8 /* RWI4R */ #define NV_CPWR_RISCV_IOPMP_ADDR_LO__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_ADDR_LO__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_ADDR_LO_VAL 31:0 /* */ #define NV_CPWR_RISCV_IOPMP_ADDR_LO_ABOVE1K 31:7 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_ADDR_LO_ABOVE1K_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_ADDR_LO_1K 6:0 /* R-IVF */ #define NV_CPWR_RISCV_IOPMP_ADDR_LO_1K_INIT 0x0000007f /* R-I-V */ #define NV_CPWR_RISCV_IOPMP_MODE(i) (0x000015c0+(i)*4) /* RWI4A */ #define NV_CPWR_RISCV_IOPMP_MODE__SIZE_1 2 /* */ #define NV_CPWR_RISCV_IOPMP_MODE__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_MODE__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_MODE_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_MODE_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_MODE_VAL_ENTRY(i) (1+2*(i)):(2*(i)) /* */ #define NV_CPWR_RISCV_IOPMP_MODE_VAL_ENTRY__SIZE_1 16 /* */ #define NV_CPWR_RISCV_IOPMP_MODE_VAL_ENTRY_OFF 0x00000000 /* */ #define NV_CPWR_RISCV_IOPMP_MODE_VAL_ENTRY_NAPOT 0x00000003 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_STAT 0x000015e0 /* RWI4R */ #define NV_CPWR_RISCV_IOPMP_ERR_STAT__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_ERR_STAT__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_STAT_VALID 31:31 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_ERR_STAT_VALID_TURE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_IOPMP_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO 0x000015e4 /* R-I4R */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER 3:0 /* R-IVF */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_FBDMA 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_CPDMA 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_SHA 0x00000002 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB0 0x00000004 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB1 0x00000005 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB2 0x00000006 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB3 0x00000007 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB4 0x00000008 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB5 0x00000009 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB6 0x0000000a /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB7 0x0000000b /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_READ 4:4 /* R-IVF */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_READ_TRUE 0x00000001 /* R---V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_READ_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_ENTRY 21:16 /* R-IVF */ #define NV_CPWR_RISCV_IOPMP_ERR_INFO_ENTRY_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_HI 0x000015ec /* R-I4R */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_HI__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_HI_ADDR 31:0 /* R-IVF */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_LO 0x000015e8 /* R-I4R */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_LO__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_LO__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_LO_ADDR 31:0 /* R-IVF */ #define NV_CPWR_RISCV_IOPMP_ERR_ADDR_LO_ADDR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN 0x000015f0 /* RWI4R */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN__DEVICE_MAP 0x0000000e /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER 11:0 /* RWIVF */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_ALL_MASTERS_ENABLED 0x00000fff /* RWI-V */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA 0:0 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA 1:1 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA 2:2 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB(i) (4+(i)):(4+(i)) /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB__SIZE_1 8 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_SCPDMATRFMOFFS 0x00001570 /* RWI4R */ #define NV_CPWR_RISCV_SCPDMATRFMOFFS__DEVICE_MAP 0x00000010 /* */ #define NV_CPWR_RISCV_SCPDMATRFMOFFS__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_SCPDMATRFMOFFS_OFFS 31:0 /* RWIVF */ #define NV_CPWR_RISCV_SCPDMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCPDMATRFCMD 0x00001574 /* RWI4R */ #define NV_CPWR_RISCV_SCPDMATRFCMD__DEVICE_MAP 0x00000010 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SUPPRESS 2:2 /* RWIVF */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SUPPRESS_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SHORTCUT 3:3 /* RWIVF */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SHORTCUT_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SHORTCUT_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_IMEM 4:4 /* RWIVF */ #define NV_CPWR_RISCV_SCPDMATRFCMD_IMEM_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_WRITE 5:5 /* RWIVF */ #define NV_CPWR_RISCV_SCPDMATRFCMD_WRITE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_GPR 8:6 /* RWIVF */ #define NV_CPWR_RISCV_SCPDMATRFCMD_GPR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SIZE 8:6 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SIZE_16B 2 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SIZE_32B 3 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SIZE_64B 4 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SIZE_128B 5 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_SIZE_256B 6 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_CCI_EX 15:15 /* RWIVF */ #define NV_CPWR_RISCV_SCPDMATRFCMD_CCI_EX_SCPDMA 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_CCI_EX_CCI 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_CCI_CMD 31:16 /* RWIVF */ #define NV_CPWR_RISCV_SCPDMATRFCMD_CCI_CMD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCPDMATRFCMD_RY 19:16 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_RX_OR_IMM 25:20 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE 31:26 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_NOP 0 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_MOV 1 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_PUSH 2 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_FETCH 3 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_RAND 4 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_LOAD_TRACE0 5 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_LOOP_TRACE0 6 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_LOAD_TRACE1 7 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_LOOP_TRACE1 8 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_CHMOD 10 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_XOR 11 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_ADD 12 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_AND 13 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_BSWAP 14 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_CMAC_SK 15 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_SECRET 16 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_KEY 17 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_RKEY10 18 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_RKEY1 19 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_ENCRYPT 20 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_DECRYPT 21 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_COMPARE_SIG 22 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_ENCRYPT_SIG 23 /* */ #define NV_CPWR_RISCV_SCPDMATRFCMD_OPCODE_FORGET_SIG 24 /* */ #define NV_CPWR_RISCV_SCPDMAPOLL 0x00001578 /* RWI4R */ #define NV_CPWR_RISCV_SCPDMAPOLL__DEVICE_MAP 0x00000010 /* */ #define NV_CPWR_RISCV_SCPDMAPOLL__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_SCPDMAPOLL_DMA_ACTIVE 0:0 /* R-IVF */ #define NV_CPWR_RISCV_SCPDMAPOLL_DMA_ACTIVE_IDLE 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_SCPDMAPOLL_DMA_ACTIVE_ACTIVE 0x00000001 /* R---V */ #define NV_CPWR_RISCV_SCPDMAPOLL_ERROR_CLR 4:4 /* -WXVF */ #define NV_CPWR_RISCV_SCPDMAPOLL_ERROR_CODE 9:8 /* R-IVF */ #define NV_CPWR_RISCV_SCPDMAPOLL_ERROR_CODE_NO_ERROR 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_SCPDMAPOLL_ERROR_CODE_NOT_SIZE_ALIGNED 0x00000001 /* R---V */ #define NV_CPWR_RISCV_SCPDMAPOLL_ERROR_CODE_SECRET_NOT_ALLOWED 0x00000002 /* R---V */ #define NV_CPWR_RISCV_SCPDMAPOLL_WCOUNT 19:16 /* R-IVF */ #define NV_CPWR_RISCV_SCPDMAPOLL_WCOUNT_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_SCPDMAPOLL_RCOUNT 23:20 /* R-IVF */ #define NV_CPWR_RISCV_SCPDMAPOLL_RCOUNT_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_SCPDMAPOLL_REQQ_NUM 27:24 /* R-IVF */ #define NV_CPWR_RISCV_SCPDMAPOLL_REQQ_NUM_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_SCPDMAPOLL_REQQ_DEPTH 31:28 /* R-XVF */ #define NV_CPWR_RISCV_SCP_SECRET_MASK(i) (0x00001580+(i)*4) /* RWI4A */ #define NV_CPWR_RISCV_SCP_SECRET_MASK__SIZE_1 2 /* */ #define NV_CPWR_RISCV_SCP_SECRET_MASK__DEVICE_MAP 0x00000008 /* */ #define NV_CPWR_RISCV_SCP_SECRET_MASK__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_SCP_SECRET_MASK_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_SCP_SECRET_MASK_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_SCP_SECRET_MASK_LOCK(i) (0x00001588+(i)*4) /* RWI4A */ #define NV_CPWR_RISCV_SCP_SECRET_MASK_LOCK__SIZE_1 2 /* */ #define NV_CPWR_RISCV_SCP_SECRET_MASK_LOCK__DEVICE_MAP 0x00000008 /* */ #define NV_CPWR_RISCV_SCP_SECRET_MASK_LOCK__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_SCP_SECRET_MASK_LOCK_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_SCP_SECRET_MASK_LOCK_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BR_RETCODE 0x0000165c /* RWI4R */ #define NV_CPWR_RISCV_BR_RETCODE_RESULT 1:0 /* RWIVF */ #define NV_CPWR_RISCV_BR_RETCODE_RESULT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BR_RETCODE_RESULT_RUNNING 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_RESULT_FAIL 0x00000002 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_RESULT_PASS 0x00000003 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE 7:2 /* RWIVF */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_ENTRY 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_INIT_DEVICE 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_LOAD_PUBLIC_KEY 0x00000002 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_LOAD_PKC_BOOT_PARAM 0x00000003 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_SHA_MANIFEST 0x00000004 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_VERIFY_MANIFEST_SIGNATURE 0x00000005 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_DECRYPT_MANIFEST 0x00000006 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_SANITIZE_MANIFEST 0x00000007 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_LOAD_FMC 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_VERIFY_FMC_DIGEST 0x00000009 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_DECRYPT_FMC 0x0000000a /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_DECRYPT_FUSEKEY 0x0000000b /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_REVOKE_RESOURCE 0x0000000c /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_PHASE_CONFIGURE_FMC_ENV 0x0000000d /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME 17:8 /* RWIVF */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_DMA_FB_ADDRESS_ERROR 0x00000020 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_DMA_NACK_ERROR 0x00000021 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_SHA_ACQUIRE_MUTEX_ERROR 0x00000040 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_SHA_EXECUTION_ERROR 0x00000041 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_DIO_READ_ERROR 0x00000060 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_DIO_WRITE_ERROR 0x00000061 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_SE_PDI_INVALID_ERROR 0x00000080 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_SE_PKEYHASH_INVALID_ERROR 0x00000081 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_SW_PKEY_DIGEST_ERROR 0x00000082 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_SE_PKA_RETURN_CODE_ERROR 0x00000083 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_SCP_LOAD_SECRET_ERROR 0x000000a0 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_SCP_TRAPPED_DMA_NOT_ALIGNED_ERROR 0x000000a1 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_CODE_SIZE_ERROR 0x000000c0 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_CORE_PMP_RESERVATION_ERROR 0x000000c1 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_DATA_SIZE_ERROR 0x000000c2 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_DEVICEMAP_BR_UNLOCK_ERROR 0x000000c3 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_FAMILY_ID_ERROR 0x000000c4 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_MSPM_VALUE_ERROR 0x000000c5 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_PAD_INFO_MASK_ERROR 0x000000c6 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_REG_PAIR_ADDRESS_ERROR 0x000000c7 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_REG_PAIR_ENTRY_NUM_ERROR 0x000000c8 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SECRET_MASK_ERROR 0x000000c9 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SECRET_MASK_LOCK_ERROR 0x000000ca /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SIGNATURE_ERROR 0x000000cb /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_UCODE_ID_ERROR 0x000000cc /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_UCODE_VERSION_ERROR 0x000000cd /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_FMC_DIGEST_ERROR 0x000000e0 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_BAD_HEADER_ERROR 0x00000100 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_KEYGLOB_INVALID_ERROR 0x00000101 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_PROTECT_INFO_ERROR 0x00000102 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_SIGNATURE_ERROR 0x00000103 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_DISPOSE_KSLOT_ERROR 0x00000120 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_KEY_SLOT_K3_ERROR 0x00000121 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_LOAD_KSLOT2SCP_ERROR 0x00000122 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_READ_ERROR 0x00000123 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_WRITE_ERROR 0x00000124 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_IOPMP_ERROR 0x00000141 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_MMIO_ERROR 0x00000142 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_SYNDROME_OK 0x000003ff /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO 31:18 /* RWIVF */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_DMA_WAIT_FOR_IDLE_HANG 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_SHA_HANG 0x00000002 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_DIO_READ_HANG 0x00000004 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_DIO_WAIT_FREE_ENTRY_HANG 0x00000008 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_DIO_WRITE_HANG 0x00000010 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_SE_ACQUIRE_MUTEX_HANG 0x00000020 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_SE_PDI_LOAD_HANG 0x00000040 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_SE_PKEYHASH_LOAD_HANG 0x00000080 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_PKA_POLL_RESULT_HANG 0x00000100 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_SCP_PIPELINE_RESET_HANG 0x00000200 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_TRAPPED_DMA_HANG 0x00000400 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_FUSEKEY_KEYGLOB_LOAD_HANG 0x00000800 /* RW--V */ #define NV_CPWR_RISCV_BR_RETCODE_INFO_KMEM_CMD_EXECUTE_HANG 0x00001000 /* RW--V */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN 0x00001660 /* RWI4R */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN__DEVICE_MAP 0x00000000 /* */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN__PRIV_LEVEL_MASK 0x000001b8 /* */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK 0:0 /* RW-VF */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_UNLOCKED 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_FALSE_CORESELECT_FALSE 0x00000000 /* */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_FALSE_CORESELECT_TRUE 0x00000001 /* */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_TRUE_CORESELECT_FALSE 0x00000001 /* */ #define NV_CPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_TRUE_CORESELECT_TRUE 0x00000001 /* */ #define NV_CPWR_RISCV_BCR_CTRL 0x00001668 /* RWI4R */ #define NV_CPWR_RISCV_BCR_CTRL__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_CTRL__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */ #define NV_CPWR_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */ #define NV_CPWR_RISCV_BCR_CTRL_VALID_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_RISCV_BCR_CTRL_CORE_SELECT 4:4 /* RWIVF */ #define NV_CPWR_RISCV_BCR_CTRL_CORE_SELECT_FALCON 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_CTRL_CORE_SELECT_RISCV 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_BCR_CTRL_BRFETCH 8:8 /* RWIVF */ #define NV_CPWR_RISCV_BCR_CTRL_BRFETCH_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_RISCV_BCR_CTRL_BRFETCH_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG 0x0000166c /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMACFG__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMACFG__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_TARGET 1:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_TARGET_LOCAL_FB 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_TARGET_COHERENT_SYSMEM 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_LOCK 31:31 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMACFG_LOCK_LOCKED 0x00000001 /* RW--V */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC 0x00001694 /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC__PRIV_LEVEL_MASK 0x00001690 /* */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_WPRID 1:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMACFG_SEC_WPRID_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO 0x00001670 /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI 0x00001674 /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL 6:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_LO 0x00001678 /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_LO__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_LO__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_HI 0x0000167c /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_HI__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_HI__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL 6:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_LO 0x00001680 /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_LO__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_LO__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_HI 0x00001684 /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_HI__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_HI__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL 6:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_LO 0x00001688 /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_LO__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_LO__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_LO_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_LO_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_HI 0x0000168c /* RWI4R */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_HI__DEVICE_MAP 0x0000000c /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_HI__PRIV_LEVEL_MASK 0x00001664 /* */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_HI_VAL 6:0 /* RWIVF */ #define NV_CPWR_RISCV_BCR_DMAADDR_PUBKEY_HI_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE(i) (0x00001610+(i)*8) /* RWI4A */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE__SIZE_1 4 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_VAL_INIT 0x33333333 /* RWI-V */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_READ(i) (0+4*(i)):(0+4*(i)) /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_READ__SIZE_1 8 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_READ_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_READ_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_WRITE(i) (1+4*(i)):(1+4*(i)) /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_WRITE__SIZE_1 8 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_WRITE_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_WRITE_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_LOCK(i) (3+4*(i)):(3+4*(i)) /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_LOCK__SIZE_1 8 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_LOCK_LOCKED 0x00000001 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVMMODE_LOCK_UNLOCKED 0x00000000 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE(i) (0x00001614+(i)*8) /* RWI4A */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE__SIZE_1 4 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_VAL 31:0 /* RWIVF */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_VAL_INIT 0x33333333 /* RWI-V */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_READ(i) (0+4*(i)):(0+4*(i)) /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_READ__SIZE_1 8 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_READ_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_READ_DISABLE 0x00000000 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE(i) (1+4*(i)):(1+4*(i)) /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE__SIZE_1 8 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE_ENABLE 0x00000001 /* */ #define NV_CPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK 0x00000e70 /* RWI4R */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_PLM /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK 0x00000e88 /* RWI4R */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_PLM /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG(i) (0x00000e00+(i)*4) /* RW-4A */ #define NV_CPWR_FBIF_TRANSCFG__SIZE_1 8 /* */ #define NV_CPWR_FBIF_TRANSCFG__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_MMODE /* */ #define NV_CPWR_FBIF_TRANSCFG__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */ #define NV_CPWR_FBIF_TRANSCFG_TARGET_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */ #define NV_CPWR_FBIF_TRANSCFG_MEM_TYPE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x00000000 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */ #define NV_CPWR_FBIF_TRANSCFG_L2C_WR_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x00000000 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x00000001 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x00000002 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */ #define NV_CPWR_FBIF_TRANSCFG_L2C_RD_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x00000000 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x00000001 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x00000002 /* R---V */ #define NV_CPWR_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */ #define NV_CPWR_FBIF_TRANSCFG_WACHK0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG_WACHK0_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_TRANSCFG_WACHK0_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */ #define NV_CPWR_FBIF_TRANSCFG_WACHK1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG_WACHK1_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_TRANSCFG_WACHK1_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */ #define NV_CPWR_FBIF_TRANSCFG_RACHK0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG_RACHK0_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_TRANSCFG_RACHK0_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */ #define NV_CPWR_FBIF_TRANSCFG_RACHK1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_TRANSCFG_RACHK1_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_TRANSCFG_RACHK1_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_INSTBLK 0x00000e20 /* R--4R */ #define NV_CPWR_FBIF_INSTBLK__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_INSTBLK_PTR 27:0 /* R--VF */ #define NV_CPWR_FBIF_INSTBLK_TARGET 29:28 /* R--VF */ #define NV_CPWR_FBIF_INSTBLK_TARGET_LOCAL_FB 0x00000000 /* R---V */ #define NV_CPWR_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */ #define NV_CPWR_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO 0x00000e90 /* R--4R */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_GPC 0:0 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_GPC_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB 1:1 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_TARGET 3:2 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_TARGET_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_ADR_LO 31:4 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_ADR_LO_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI 0x00000e94 /* R--4R */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_PDB_ADR_HI 6:0 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_PDB_ADR_HI_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_PAGE_TABLE_LEVEL 9:7 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_PAGE_TABLE_LEVEL_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_TARGET_AVA 10:10 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_TARGET_AVA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_MMU_REPLAY 13:11 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_MMU_REPLAY_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_CLIENT_UNIT_ID 20:14 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_CLIENT_UNIT_ID_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_GPC_ID 23:21 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_GPC_ID_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_SYS_MEMBAR 24:24 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_SYS_MEMBAR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_ACK_TYPE 26:25 /* R-IVF */ #define NV_CPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_ACK_TYPE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_FBIF_CTL 0x00000e24 /* RW-4R */ #define NV_CPWR_FBIF_CTL__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_CTL_FLUSH 0:0 /* RW-VF */ #define NV_CPWR_FBIF_CTL_FLUSH_SET 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_CTL_FLUSH_CLEAR 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */ #define NV_CPWR_FBIF_CTL_INVAL_CONTEXT_SET 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */ #define NV_CPWR_FBIF_CTL_CLR_BWCOUNT_SET 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL_ENABLE 4:4 /* RWIVF */ #define NV_CPWR_FBIF_CTL_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_CTL_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_CTL_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */ #define NV_CPWR_FBIF_CTL_CLR_IDLEWDERR_SET 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL_RESET 6:6 /* RW-VF */ #define NV_CPWR_FBIF_CTL_RESET_SET 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_CTL_RESET_CLEAR 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */ #define NV_CPWR_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_CTL_IDLE 8:8 /* R--VF */ #define NV_CPWR_FBIF_CTL_IDLE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FBIF_CTL_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */ #define NV_CPWR_FBIF_CTL_IDLEWDERR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FBIF_CTL_IDLEWDERR_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_CTL_SRTOUT 10:10 /* R--VF */ #define NV_CPWR_FBIF_CTL_SRTOUT_TRUE 0x00000001 /* R---V */ #define NV_CPWR_FBIF_CTL_SRTOUT_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */ #define NV_CPWR_FBIF_CTL_CLR_SRTOUT_SET 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_CTL_CLR_SRTOUT_CLEAR 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */ #define NV_CPWR_FBIF_CTL_SRTOVAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_CTL2 0x00000e84 /* RW-4R */ #define NV_CPWR_FBIF_CTL2__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_CTL2__PRIV_LEVEL_MASK 0x00000e88 /* */ #define NV_CPWR_FBIF_CTL2_NACK_MODE 0:0 /* RWIVF */ #define NV_CPWR_FBIF_CTL2_NACK_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_CTL2_NACK_MODE_NACK_AS_ACK 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_THROTTLE 0x00000e2c /* RW-4R */ #define NV_CPWR_FBIF_THROTTLE__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */ #define NV_CPWR_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x00000064 /* RWI-V */ #define NV_CPWR_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */ #define NV_CPWR_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */ #define NV_CPWR_FBIF_THROTTLE_LEAK_SIZE_16B 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_THROTTLE_LEAK_SIZE_32B 0x00000001 /* RW--V */ #define NV_CPWR_FBIF_THROTTLE_LEAK_SIZE_64B 0x00000002 /* RWI-V */ #define NV_CPWR_FBIF_THROTTLE_LEAK_SIZE_128B 0x00000003 /* RW--V */ #define NV_CPWR_FBIF_REGIONCFG 0x00000e6c /* RW-4R */ #define NV_CPWR_FBIF_REGIONCFG__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_MMODE /* */ #define NV_CPWR_FBIF_REGIONCFG__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_REGIONCFG_T0 3:0 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_T0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_T1 7:4 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_T1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_T2 11:8 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_T2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_T3 15:12 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_T3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_T4 19:16 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_T4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_T5 23:20 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_T5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_T6 27:24 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_T6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_REGIONCFG_T7 31:28 /* RWIVF */ #define NV_CPWR_FBIF_REGIONCFG_T7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_FBIF_CG1 0x00000e74 /* RW-4R */ #define NV_CPWR_FBIF_CG1__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_MMODE /* */ #define NV_CPWR_FBIF_CG1_SLCG 3:0 /* */ #define NV_CPWR_FBIF_CG1_SLCG_ENABLED 0 /* */ #define NV_CPWR_FBIF_CG1_SLCG_DISABLED 0xF /* */ #define NV_CPWR_FBIF_CG1_SLCG__PROD 0x0 /* */ #define NV_CPWR_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */ #define NV_CPWR_FBIF_CG1_SLCG_MSD0_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CG1_SLCG_MSD0_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */ #define NV_CPWR_FBIF_CG1_SLCG_MSD1_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CG1_SLCG_MSD1_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */ #define NV_CPWR_FBIF_CG1_SLCG_FB0_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CG1_SLCG_FB0_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */ #define NV_CPWR_FBIF_CG1_SLCG_FB1_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_FBIF_CG1_SLCG_FB1_DISABLED 0x00000001 /* RWI-V */ #define NV_CPWR_FBIF_ACHK_BLK(i) (0x00000e30+(i)*8) /* RW-4A */ #define NV_CPWR_FBIF_ACHK_BLK__SIZE_1 2 /* */ #define NV_CPWR_FBIF_ACHK_BLK__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */ #define NV_CPWR_FBIF_ACHK_CTL(i) (0x00000e34+(i)*8) /* RW-4A */ #define NV_CPWR_FBIF_ACHK_CTL__SIZE_1 2 /* */ #define NV_CPWR_FBIF_ACHK_CTL__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */ #define NV_CPWR_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */ #define NV_CPWR_FBIF_ACHK_CTL_TYPE_INSIDE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x00000001 /* R---V */ #define NV_CPWR_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */ #define NV_CPWR_FBIF_ACHK_CTL_STATE_DISABLE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_ACHK_CTL_STATE_ENABLE 0x00000001 /* R---V */ #define NV_CPWR_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */ #define NV_CPWR_FBIF_DBG_STAT0 0x00000e40 /* R--4R */ #define NV_CPWR_FBIF_DBG_STAT0__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_DBG_STAT0__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE 3:0 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_IDLE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_CHECK 0x00000001 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_ALLOC 0x00000002 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_ISSUE 0x00000003 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_WDAT 0x00000004 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_FLT_FLUSH 0x00000005 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_HALT 0x00000006 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_INST 0x00000007 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_INST_ACK 0x00000008 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_OBJ 0x00000009 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_DSP_STATE_FLUSH 0x0000000a /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_INST_VLD 4:4 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_INST_BOUND 5:5 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_RICF_HAS_DATA 6:6 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_ARQ_HAS_DATA 7:7 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_MRQ_HAS_DATA 8:8 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_FAULT_OR_HALT 9:9 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_ORQ_NOT_FULL 10:10 /* R-IUF */ #define NV_CPWR_FBIF_DBG_STAT0_ORQ_NOT_FULL_TRUE 0x00000001 /* R-I-V */ #define NV_CPWR_FBIF_DBG_STAT0_ORQ_NOT_FULL_FLASE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_FLUSH_OUTSTANDING 11:11 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_DISPATCH_IDLE 12:12 /* R-IUF */ #define NV_CPWR_FBIF_DBG_STAT0_DISPATCH_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CPWR_FBIF_DBG_STAT0_DISPATCH_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_MWF_FSM_STATE 17:16 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_MWF_FSM_STATE_IDLE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_MWF_FSM_STATE_COMMIT 0x00000001 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_MWF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT0_MWF_HAS_DATA 18:18 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_MWF_COMMIT_COUNT 24:19 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_STALL_RQQ_FULL 25:25 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_STALL_WDF_FULL 26:26 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_STALL_FB_BUSY 27:27 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_STALL_ORQ_FULL 28:28 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_STALL_RDM_ALLOC 29:29 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_STALL_RDM_PORTQ 30:30 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT0_STALL_RDM_CLIENT 31:31 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1 0x00000e44 /* R--4R */ #define NV_CPWR_FBIF_DBG_STAT1__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_DBG_STAT1__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_DBG_STAT1_FLT_STATE 1:0 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_FLT_FAULTED 2:2 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_FLT_BUSY 3:3 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_ACKF_HAS_DATA 4:4 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_ORQ_HAS_DATA 5:5 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_ALL_READS_DONE 6:6 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_FBR_IDLE 8:8 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_FBR_FAULTED 9:9 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_FBR_FB_BUSY 10:10 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_FBR_PKT2FB_VLD 11:11 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_FBR_RCV_DATA_VALID 12:12 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_FBR_RCV_DATA_TYPE 15:14 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_WDF_FSM_STATE 17:16 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_WDF_FSM_STATE_IDLE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT1_WDF_FSM_STATE_COMMIT 0x00000001 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT1_WDF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT1_WDF_HAS_DATA 18:18 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_WDF_COMMIT_COUNT 23:19 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_RDM_STATE 25:24 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_RDM_STATE_IDLE 0x00000000 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT1_RDM_STATE_WAITBUF 0x00000001 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT1_RDM_STATE_SAVEBUF 0x00000002 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT1_RDM_ANY_READY 26:26 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_RDM_DAQ_HAS_DATA 27:27 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_RDM_DEALLOC_COUNT 30:28 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT1_RDATA_WAIT 31:31 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT2 0x00000e48 /* R--4R */ #define NV_CPWR_FBIF_DBG_STAT2__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_DBG_STAT2__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_DBG_STAT2_FAULTED_PORTID 5:0 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT2_FAULTED_SUBID 12:6 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT2_FAULTED_SRCQ 13:13 /* R--UF */ #define NV_CPWR_FBIF_DBG_STAT2_FAULTED_SRCQ_ARQ 0x00000001 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT2_FAULTED_SRCQ_MRQ 0x00000000 /* R---V */ #define NV_CPWR_FBIF_DBG_STAT2_FAULTED_VLD 14:14 /* R--UF */ #define NV_CPWR_FBIF_DBG_RDCOUNT_LO 0x00000e50 /* R--4R */ #define NV_CPWR_FBIF_DBG_RDCOUNT_LO__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_DBG_RDCOUNT_LO_DATA 31:0 /* R--UF */ #define NV_CPWR_FBIF_DBG_RDCOUNT_HI 0x00000e54 /* R--4R */ #define NV_CPWR_FBIF_DBG_RDCOUNT_HI__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_DBG_RDCOUNT_HI_DATA 31:0 /* R--UF */ #define NV_CPWR_FBIF_DBG_WRCOUNT_LO 0x00000e58 /* R--4R */ #define NV_CPWR_FBIF_DBG_WRCOUNT_LO__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_DBG_WRCOUNT_LO_DATA 31:0 /* R--UF */ #define NV_CPWR_FBIF_DBG_WRCOUNT_HI 0x00000e5c /* R--4R */ #define NV_CPWR_FBIF_DBG_WRCOUNT_HI__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK 0x00000e70 /* */ #define NV_CPWR_FBIF_DBG_WRCOUNT_HI_DATA 31:0 /* R--UF */ #define NV_CPWR_FBIF_BW_ALLOC 0x00000e4c /* RW-4R */ #define NV_CPWR_FBIF_BW_ALLOC__DEVICE_MAP NV_CPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */ #define NV_CPWR_FBIF_BW_ALLOC_VAL 31:0 /* */ #define NV_CPWR_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */ #define NV_CPWR_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */ #define NV_CPWR_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */ #define NV_CPWR_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK 0x00000b60 /* RW-4R */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_rst" /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK 0x00000b18 /* RW-4R */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_ENABLED 0x00000048 /* RWI-V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK 0x00000b0c /* RW-4R */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_idle_count" /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK 0x00000b10 /* RW-4R */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpc_deglitch_cfg" /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK 0x0000087c /* RW-4R */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_intr_1" /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK 0x00000878 /* RW-4R */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_intr_0" /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK 0x0000053c /* RW-4R */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpio_output" /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK 0x00000538 /* RW-4R */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpio_general" /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK 0x00000400 /* RW-4R */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_cmd_head_intr" /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK(i) (0x00001d00+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK__SIZE_1 8 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK(i) (0x00001d20+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK__SIZE_1 8 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK 0x00001f78 /* RW-4R */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK 0x00001f7c /* RW-4R */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK 0x00000b1c /* RW-4R */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_reset_ctrl" /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK 0x0000065c /* RW-4R */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_ctrl" /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK 0x000005e0 /* RW-4R */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_interlock" /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK 0x000005e4 /* RW-4R */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_interlock" /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK 0x000005e8 /* RW-4R */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_gpc_pri_err" /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK 0x000005ec /* RW-4R */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_gpc_pri_err" /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK 0x00000788 /* RW-4R */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK 0x000007dc /* RW-4R */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0 0x00000b38 /* RW-4R */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION__FUSE_SIGNAL "pmu_sw_client" /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1 0x00000b3c /* RW-4R */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION__FUSE_SIGNAL "pmu_sw_client" /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2 0x00000b40 /* RW-4R */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION__FUSE_SIGNAL "pmu_sw_client" /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3 0x00000b44 /* RW-4R */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4 0x00000b48 /* RW-4R */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5 0x00000b4c /* RW-4R */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6 0x00000b50 /* RW-4R */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7 0x00000b54 /* RW-4R */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK 0x00000a78 /* RW-4R */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg_dbg" /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK 0x000007fc /* RW-4R */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK 0x00000b80 /* RW-4R */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_CPWR_PMU_RESET_COUNTER 0x00000404 /* RW-4R */ #define NV_CPWR_PMU_RESET_COUNTER__PRIV_LEVEL_MASK 0x00000b60 /* */ #define NV_CPWR_PMU_RESET_COUNTER_VAL 31:0 /* RWIVF */ #define NV_CPWR_PMU_RESET_COUNTER_VAL_INIT 0x0000ffff /* RWI-V */ #define NV_CPWR_PMU_RESET_PMU 0x00000408 /* RW-4R */ #define NV_CPWR_PMU_RESET_PMU__PRIV_LEVEL_MASK 0x00000b60 /* */ #define NV_CPWR_PMU_RESET_PMU_EN 0:0 /* RWIVF */ #define NV_CPWR_PMU_RESET_PMU_EN_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_RESET_PMU_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_RESET_THERM 0x00000410 /* RW-4R */ #define NV_CPWR_PMU_RESET_THERM__PRIV_LEVEL_MASK 0x00000b18 /* */ #define NV_CPWR_PMU_RESET_THERM_EN 0:0 /* RWIVF */ #define NV_CPWR_PMU_RESET_THERM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_RESET_THERM_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PMU2BSI_RDY4TRANS 0x0000040c /* RW-4R */ #define NV_CPWR_PMU_PMU2BSI_RDY4TRANS_STATUS 0:0 /* RWIVF */ #define NV_CPWR_PMU_PMU2BSI_RDY4TRANS_STATUS_EN 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_PMU2BSI_RDY4TRANS_STATUS_DIS 0x00000000 /* RW--V */ #define NV_CPWR_PMU_FORCE_BUSY 0x00000420 /* RW-4R */ #define NV_CPWR_PMU_FORCE_BUSY_STATE 0:0 /* RWIUF */ #define NV_CPWR_PMU_FORCE_BUSY_STATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_FORCE_BUSY_STATE_IDLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_FORCE_BUSY_STATE_BUSY 0x00000001 /* RW--V */ #define NV_CPWR_PMU_NEW_INSTBLK 0x00000480 /* RW-4R */ #define NV_CPWR_PMU_NEW_INSTBLK_PTR 27:0 /* RWIUF */ #define NV_CPWR_PMU_NEW_INSTBLK_PTR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_NEW_INSTBLK_TARGET 29:28 /* RWIVF */ #define NV_CPWR_PMU_NEW_INSTBLK_TARGET_FB 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 0x00000002 /* RW--V */ #define NV_CPWR_PMU_NEW_INSTBLK_TARGET_SYS_NONCOH 0x00000003 /* RW--V */ #define NV_CPWR_PMU_NEW_INSTBLK_VALID 30:30 /* RWIVF */ #define NV_CPWR_PMU_NEW_INSTBLK_VALID_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_NEW_INSTBLK_STATUS 31:31 /* R-IVF */ #define NV_CPWR_PMU_NEW_INSTBLK_STATUS_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_NEW_INSTBLK_STATUS_NOT_DONE 0x00000001 /* R---V */ #define NV_CPWR_PMU_FALCON_ICD_CTRL 0x00000424 /* RW-4R */ #define NV_CPWR_PMU_FALCON_ICD_CTRL_MODE 0:0 /* RWIUF */ #define NV_CPWR_PMU_FALCON_ICD_CTRL_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_FALCON_ICD_CTRL_MODE_JTAG 0x00000000 /* RW--V */ #define NV_CPWR_PMU_FALCON_ICD_CTRL_MODE_UART 0x00000001 /* RW--V */ #define NV_CPWR_PMU_ECO 0x00000428 /* RW-4R */ #define NV_CPWR_PMU_ECO_BIT0 0:0 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_ECO_CFG_ERR_CYA 0:0 /* RWIVF */ #define NV_CPWR_PMU_ECO_CFG_ERR_CYA_EN 0x00000000 /* --I-V */ #define NV_CPWR_PMU_ECO_CFG_ERR_CYA_DIS 0x00000001 /* ----V */ #define NV_CPWR_PMU_ECO_BIT1 1:1 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_ECO_IDLE_SNAP_CYA 1:1 /* RWIVF */ #define NV_CPWR_PMU_ECO_IDLE_SNAP_CYA_EN 0x00000000 /* --I-V */ #define NV_CPWR_PMU_ECO_IDLE_SNAP_CYA_DIS 0x00000001 /* ----V */ #define NV_CPWR_PMU_ECO_BIT2 2:2 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT3 3:3 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT4 4:4 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT5 5:5 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT6 6:6 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT7 7:7 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT8 8:8 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT8_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT9 9:9 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT9_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT10 10:10 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT10_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT11 11:11 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT11_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT12 12:12 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT12_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT13 13:13 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT13_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT14 14:14 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT14_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_ECO_BIT15 15:15 /* RWIVF */ #define NV_CPWR_PMU_ECO_BIT15_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG 0x00000434 /* RW-4R */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG__PRIV_LEVEL_MASK 0x00000b10 /* */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_LOW_BOUNDARY 9:0 /* RWIUF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_LOW_BOUNDARY_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_HIGH_BOUNDARY 19:10 /* RWIUF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_HIGH_BOUNDARY_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_MAX 29:20 /* RWIUF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_MAX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_CNT_EN 31:31 /* RWIUF */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_CNT_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_CNT_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPC_DEGLITCH_CFG_CNT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG 0x00000438 /* RW-4R */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_LOW_BOUNDARY 9:0 /* RWIUF */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_LOW_BOUNDARY_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_HIGH_BOUNDARY 19:10 /* RWIUF */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_HIGH_BOUNDARY_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_MAX 29:20 /* RWIUF */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_MAX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_CNT_EN 31:31 /* RWIUF */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_CNT_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_CNT_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_TPC_DEGLITCH_CFG_CNT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS 0x0000043c /* R--4R */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC0 0:0 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC0_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC0_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC1 1:1 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC1_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC1_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC2 2:2 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC2_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC2_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC3 3:3 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC3_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC3_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC4 4:4 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC4_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC4_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC5 5:5 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC5_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC5_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC6 6:6 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC6_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC6_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC7 7:7 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC7_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC7_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC 7:0 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC0 8:8 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC0_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC0_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC1 9:9 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC1_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC1_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC2 10:10 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC2_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC2_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC3 11:11 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC3_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC3_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC4 12:12 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC4_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC4_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC5 13:13 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC5_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC5_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC6 14:14 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC6_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC6_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC7 15:15 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC7_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC7_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC 15:8 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GR 16:16 /* R--VF */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GR_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GR_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC(i) (i):(i) /* */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC_BUSY 0 /* */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC_IDLE 1 /* */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC(i) (8+(i)):(8+(i)) /* */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC_BUSY 0 /* */ #define NV_CPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC_IDLE 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0 0x00000440 /* RW-4R */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0 0:0 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1 1:1 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2 2:2 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3 3:3 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4 4:4 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5 5:5 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6 6:6 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7 7:7 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING 7:0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0 8:8 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1 9:9 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2 10:10 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3 11:11 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4 12:12 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5 13:13 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6 14:14 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7 15:15 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING 15:8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0 16:16 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1 17:17 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2 18:18 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3 19:19 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4 20:20 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5 21:21 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6 22:22 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7 23:23 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING 23:16 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0 24:24 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1 25:25 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2 26:26 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3 27:27 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4 28:28 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5 29:29 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6 30:30 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7 31:31 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING 31:24 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC(i) (i):(i) /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC_INIT 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC_PENDING 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC_CLEAR 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC(i) (8+(i)):(8+(i)) /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC_INIT 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC_PENDING 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC_CLEAR 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC(i) (16+(i)):(16+(i)) /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC_INIT 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC_PENDING 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC_CLEAR 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC(i) (24+(i)):(24+(i)) /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC_INIT 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC_PENDING 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC_CLEAR 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1 0x00000444 /* RW-4R */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING 0:0 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING 1:1 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0 0x00000448 /* RW-4R */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC0 0:0 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC0_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC1 1:1 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC2 2:2 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC2_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC3 3:3 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC3_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC4 4:4 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC4_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC5 5:5 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC5_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC6 6:6 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC6_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC7 7:7 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC7_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING 7:0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC0 8:8 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC0_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC1 9:9 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC2 10:10 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC2_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC3 11:11 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC3_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC4 12:12 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC4_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC5 13:13 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC5_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC6 14:14 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC6_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC7 15:15 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC7_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING 15:8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC0 16:16 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC0_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC1 17:17 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC2 18:18 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC2_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC3 19:19 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC3_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC4 20:20 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC4_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC5 21:21 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC5_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC6 22:22 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC6_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC7 23:23 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC7_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING 23:16 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC0 24:24 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC0_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC1 25:25 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC2 26:26 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC2_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC3 27:27 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC3_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC4 28:28 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC4_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC5 29:29 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC5_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC6 30:30 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC6_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC7 31:31 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC7_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING 31:24 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC(i) (i):(i) /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC_INIT 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC_DISABLED 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC_ENABLED 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC(i) (8+(i)):(8+(i)) /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC_INIT 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC_DISABLED 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC_ENABLED 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC(i) (16+(i)):(16+(i)) /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC_INIT 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC_DISABLED 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC_ENABLED 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC(i) (24+(i)):(24+(i)) /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC_INIT 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC_DISABLED 0 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC_ENABLED 1 /* */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1 0x0000044c /* RW-4R */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_RISING 0:0 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_RISING_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_RISING_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_RISING_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_FALLING 1:1 /* RWIUF */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_FALLING_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_FALLING_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_FALLING_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_MUTEX_ID 0x00000488 /* R--4R */ #define NV_CPWR_PMU_MUTEX_ID_VALUE 7:0 /* R-IUF */ #define NV_CPWR_PMU_MUTEX_ID_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0x000000ff /* R---V */ #define NV_CPWR_PMU_MUTEX_ID_RELEASE 0x0000048c /* RW-4R */ #define NV_CPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 /* RWIUF */ #define NV_CPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_MUTEX(i) (0x00000580+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_MUTEX__SIZE_1 16 /* */ #define NV_CPWR_PMU_MUTEX_VALUE 7:0 /* RWIUF */ #define NV_CPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_PM 0x000004f0 /* RW-4R */ #define NV_CPWR_PMU_PM_SELECT 5:0 /* RWIVF */ #define NV_CPWR_PMU_PM_SELECT_INTR 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_PM_SELECT_BAR0 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_CSBREG 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_GPIO 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_TPRIV 0x00000004 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ENG_EN_DIS 0x00000005 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_FB_STOP 0x00000006 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_CLK_GATE 0x00000007 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SLOWDOWN 0x00000008 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ELPG_0_1 0x00000009 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_INTR_SC 0x00000010 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_BAR0_SC 0x00000011 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_CSBREG_SC 0x00000012 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_GPIO_SC 0x00000013 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_TPRIV_SC 0x00000014 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ENG_EN_DIS_SC 0x00000015 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_FB_STOP_SC 0x00000016 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_CLK_GATE_SC 0x00000017 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SLOWDOWN_SC 0x00000018 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ELPG_0_1_SC 0x00000019 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SLOWDOWN_GPCCLK 0x0000000a /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SLOWDOWN_GPCCLK_SC 0x0000000b /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ELPG_2_3 0x0000000c /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ELPG_2_3_SC 0x0000000d /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_WSP_0 0x0000000e /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_WSP_0_SC 0x0000000f /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_WSP_1 0x0000001a /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_WSP_1_SC 0x0000001b /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SOFT_PM_0 0x0000001c /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SOFT_PM_0_SC 0x0000001d /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SOFT_PM_1 0x0000001e /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SOFT_PM_1_SC 0x0000001f /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ENG_EN_DIS_CE 0x00000020 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ENG_EN_DIS_CE_SC 0x00000021 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_GR_VD_INTR 0x00000022 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_GR_VD_INTR_SC 0x00000023 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_CPM_SUM 0x00000024 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_CPM_SUM_SC 0x00000025 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SCP 0x00000026 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_SCP_SC 0x00000027 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ELPG_4 0x00000030 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_ELPG_4_SC 0x00000031 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_DI_INTR 0x00000032 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_DI_INTR_SC 0x00000033 /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_STATIC_PATTERN_5555_16_GROUP 0x0000002a /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_STATIC_PATTERN_5555_16_GROUP_SC 0x0000002b /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_STATIC_PATTERN_AAAA_16_GROUP 0x0000002c /* RW--V */ #define NV_CPWR_PMU_PM_SELECT_STATIC_PATTERN_AAAA_16_GROUP_SC 0x0000002d /* RW--V */ #define NV_CPWR_PMU_PM_FIFO_OVERRUN 28:28 /* RWIVF */ #define NV_CPWR_PMU_PM_FIFO_OVERRUN_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_PM_FIFO_OVERRUN_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_PM_FIFO_OVERRUN_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PM_CTRL_ENABLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_PM_CTRL_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_PM_CTRL_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SOFT_PM 0x000005fc /* RW-4R */ #define NV_CPWR_PMU_SOFT_PM_VALUE 31:0 /* RWIVF */ #define NV_CPWR_PMU_SOFT_PM_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CRC_UPDATE 0x00000490 /* RW-4R */ #define NV_CPWR_PMU_CRC_UPDATE_DATA 31:0 /* RWIVF */ #define NV_CPWR_PMU_CRC_UPDATE_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CRC_VALUE 0x00000494 /* RW-4R */ #define NV_CPWR_PMU_CRC_VALUE_DATA 31:0 /* RWIVF */ #define NV_CPWR_PMU_CRC_VALUE_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_HEAD(i) (0x00000800+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_QUEUE_HEAD__SIZE_1 8 /* */ #define NV_CPWR_PMU_QUEUE_HEAD__PRIV_LEVEL_MASK NV_CPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK /* */ #define NV_CPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_QUEUE_TAIL(i) (0x00000820+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_QUEUE_TAIL__SIZE_1 8 /* */ #define NV_CPWR_PMU_QUEUE_TAIL__PRIV_LEVEL_MASK NV_CPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK /* */ #define NV_CPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */ #define NV_CPWR_PMU_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT 0x000004c0 /* RW-4R */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT__PRIV_LEVEL_MASK 0x00000400 /* */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_0 0:0 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_0_UPDATED 0x00000001 /* R---V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_1 1:1 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_1_UPDATED 0x00000001 /* R---V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_2 2:2 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_2_UPDATED 0x00000001 /* R---V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_3 3:3 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_3_UPDATED 0x00000001 /* R---V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_4 4:4 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_4_UPDATED 0x00000001 /* R---V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_5 5:5 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_5_UPDATED 0x00000001 /* R---V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_6 6:6 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_6_UPDATED 0x00000001 /* R---V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_7 7:7 /* RWIVF */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_7_UPDATED 0x00000001 /* R---V */ #define NV_CPWR_PMU_CMD_HEAD_INTRSTAT_7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CMD_INTREN 0x000004c4 /* RW-4R */ #define NV_CPWR_PMU_CMD_INTREN__PRIV_LEVEL_MASK 0x00000400 /* */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_0_UPDATE 0:0 /* RWIVF */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_0_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_0_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_0_UPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_1_UPDATE 1:1 /* RWIVF */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_1_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_1_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_1_UPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_2_UPDATE 2:2 /* RWIVF */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_2_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_2_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_2_UPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_3_UPDATE 3:3 /* RWIVF */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_3_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_3_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_3_UPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_4_UPDATE 4:4 /* RWIVF */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_4_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_4_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_4_UPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_5_UPDATE 5:5 /* RWIVF */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_5_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_5_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_5_UPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_6_UPDATE 6:6 /* RWIVF */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_6_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_6_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_6_UPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_7_UPDATE 7:7 /* RWIVF */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_7_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_7_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CMD_INTREN_HEAD_7_UPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_MSGQ_HEAD 0x000004c8 /* RW-4R */ #define NV_CPWR_PMU_MSGQ_HEAD__PRIV_LEVEL_MASK 0x00001f78 /* */ #define NV_CPWR_PMU_MSGQ_HEAD_VAL 31:0 /* RWIUF */ #define NV_CPWR_PMU_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_MSGQ_TAIL 0x000004cc /* RW-4R */ #define NV_CPWR_PMU_MSGQ_TAIL__PRIV_LEVEL_MASK 0x00001f7c /* */ #define NV_CPWR_PMU_MSGQ_TAIL_VAL 31:0 /* RWIUF */ #define NV_CPWR_PMU_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TIMER_0_INTERVAL 0x000004e0 /* RW-4R */ #define NV_CPWR_PMU_TIMER_0_INTERVAL_VALUE 31:0 /* RWIVF */ #define NV_CPWR_PMU_TIMER_0_INTERVAL_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TIMER_0_COUNT 0x000004e4 /* R--4R */ #define NV_CPWR_PMU_TIMER_0_COUNT_VALUE 31:0 /* R--VF */ #define NV_CPWR_PMU_TIMER_0_COUNT_VALUE_INIT 0xffffffff /* R---V */ #define NV_CPWR_PMU_TIMER_CTRL 0x000004e8 /* RW-4R */ #define NV_CPWR_PMU_TIMER_CTRL_GATE 0:0 /* RWIVF */ #define NV_CPWR_PMU_TIMER_CTRL_GATE_STOP 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TIMER_CTRL_GATE_RUN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_TIMER_CTRL_SOURCE 4:4 /* RWIVF */ #define NV_CPWR_PMU_TIMER_CTRL_SOURCE_PMU_CLK 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TIMER_CTRL_SOURCE_PTIMER_1US 0x00000001 /* RW--V */ #define NV_CPWR_PMU_TIMER_CTRL_MODE 8:8 /* RWIVF */ #define NV_CPWR_PMU_TIMER_CTRL_MODE_ONE_SHOT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TIMER_CTRL_MODE_CONTINUOUS 0x00000001 /* RW--V */ #define NV_CPWR_PMU_TIMER_CTRL_RESET 12:12 /* RWIVF */ #define NV_CPWR_PMU_TIMER_CTRL_RESET_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_TIMER_CTRL_RESET_NOT_DONE 0x00000001 /* R---V */ #define NV_CPWR_PMU_TIMER_CTRL_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_DP1_SEL0 0x000005d0 /* RW-4R */ #define NV_CPWR_PMU_DP1_SEL0_BIT_0 7:0 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL0_BIT_0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL0_BIT_1 15:8 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL0_BIT_1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL0_BIT_2 23:16 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL0_BIT_2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL0_BIT_3 31:24 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL0_BIT_3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL1 0x000005d4 /* RW-4R */ #define NV_CPWR_PMU_DP1_SEL1_BIT_4 7:0 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL1_BIT_4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL1_BIT_5 15:8 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL1_BIT_5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL1_BIT_6 23:16 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL1_BIT_6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL1_BIT_7 31:24 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL1_BIT_7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL2 0x000005d8 /* RW-4R */ #define NV_CPWR_PMU_DP1_SEL2_BIT_8 7:0 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL2_BIT_8_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL2_BIT_9 15:8 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL2_BIT_9_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL2_BIT_10 23:16 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL2_BIT_10_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL2_BIT_11 31:24 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL2_BIT_11_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL3 0x000005dc /* RW-4R */ #define NV_CPWR_PMU_DP1_SEL3_BIT_12 7:0 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL3_BIT_12_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL3_BIT_13 15:8 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL3_BIT_13_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL3_BIT_14 23:16 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL3_BIT_14_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DP1_SEL3_BIT_15 31:24 /* RWIVF */ #define NV_CPWR_PMU_DP1_SEL3_BIT_15_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPCRG_CONTROL 0x00000414 /* RW-4R */ #define NV_CPWR_PMU_GPCRG_CONTROL__PRIV_LEVEL_MASK 0x0000065c /* */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_CLAMP 0:0 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_CLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_CLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_CLK_CLAMP 1:1 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_CLK_CLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_CLK_CLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMP 2:2 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMPVAL 3:3 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMPVAL_ZERO 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMPVAL_ONE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET 4:4 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_CLAMPVAL 5:5 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_CLAMPVAL_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_CLAMPVAL_ONE 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2ALL_RESET 8:8 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2ALL_RESET_DISABLE 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2ALL_RESET_ENABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2XBAR_RESET 9:9 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2XBAR_RESET_DISABLE 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2XBAR_RESET_ENABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2PERFMON_RESET 10:10 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2PERFMON_RESET_DISABLE 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2PERFMON_RESET_ENABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_RESET2CLK_DIRECT_RESET 12:12 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_RESET2CLK_DIRECT_RESET_DISABLE 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_RESET2CLK_DIRECT_RESET_ENABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2CLK_RESET 13:13 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2CLK_RESET_DISABLE 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2CLK_RESET_ENABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_CYA_XV2CLK_RESET 14:14 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_CYA_XV2CLK_RESET_DISABLE 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_CYA_XV2CLK_RESET_ENABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL 0x0000054c /* RW-4R */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL__PRIV_LEVEL_MASK 0x000005e0 /* */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_RESET 0:0 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_RESET_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_RESET_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PGOOD 4:4 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PGOOD_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PGOOD_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_MTHD_INTERLOCK 8:8 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_MTHD_INTERLOCK_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_MTHD_INTERLOCK_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PRI_INTERLOCK 12:12 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PRI_INTERLOCK_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PRI_INTERLOCK_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_GPC_PRI_ERR 0x00000540 /* RW-4R */ #define NV_CPWR_PMU_GPCRG_GPC_PRI_ERR__PRIV_LEVEL_MASK 0x000005e8 /* */ #define NV_CPWR_PMU_GPCRG_GPC_PRI_ERR_SW 0:0 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_GPC_PRI_ERR_SW_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_GPC_PRI_ERR_SW_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_MTHD_LOCK 0x00000544 /* RW-4R */ #define NV_CPWR_PMU_GPCRG_MTHD_LOCK__PRIV_LEVEL_MASK 0x000005ec /* */ #define NV_CPWR_PMU_GPCRG_MTHD_LOCK_SW 0:0 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_MTHD_LOCK_SW_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_MTHD_LOCK_SW_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK 0x00000548 /* RW-4R */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK__PRIV_LEVEL_MASK 0x000005e4 /* */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_MTHD_HW 30:30 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_MTHD_HW_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_MTHD_HW_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_PRI_HW 31:31 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_PRI_HW_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_INTERLOCK_PRI_HW_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CTRL 0x00000b30 /* RW-4R */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CTRL__PRIV_LEVEL_MASK 0x00000b1c /* */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CTRL_RESET 0:0 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CTRL_RESET_DIS 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CTRL_RESET_EN 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CTRL_CLAMP_RST_COUPLER_DIS_CYA 4:4 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CTRL_CLAMP_RST_COUPLER_DIS_CYA_EN 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CTRL_CLAMP_RST_COUPLER_DIS_CYA_DIS 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CNT 0x00000b14 /* RW-4R */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CNT__PRIV_LEVEL_MASK 0x00000b1c /* */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CNT_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CNT_VALUE_INIT 0x0000021c /* RWE-V */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CLAMP_CNT 0x00000b58 /* RW-4R */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CLAMP_CNT__PRIV_LEVEL_MASK 0x00000b1c /* */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CLAMP_CNT_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_GPCRG_SECURE_RESET_CLAMP_CNT_VALUE_INIT 0x0000021c /* RWE-V */ #define NV_CPWR_PMU_ELPG_SEQ_CG 0x00000b34 /* RW-4R */ #define NV_CPWR_PMU_ELPG_SEQ_CG_EN 0:0 /* RWEUF */ #define NV_CPWR_PMU_ELPG_SEQ_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_ELPG_SEQ_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_ELPG_SEQ_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA 0x00000970 /* R--4R */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_0 0:0 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_0_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_0_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_1 1:1 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_1_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_1_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_2 2:2 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_2_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_2_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_3 3:3 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_3_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_3_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_4 4:4 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_4_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_4_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_5 5:5 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_5_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_5_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_6 6:6 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_6_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_7 7:7 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_7_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_8 8:8 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_8_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_9 9:9 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_9_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_10 10:10 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_10_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_11 11:11 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_11_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_12 12:12 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_12_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_13 13:13 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_13_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_14 14:14 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_14_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_15 15:15 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_15_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_16 16:16 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_16_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_17 17:17 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_17_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_18 18:18 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_18_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_19 19:19 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_19_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_20 20:20 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_20_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_21 21:21 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_21_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_22 22:22 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_22_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_23 23:23 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_23_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_24 24:24 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_24_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_25 25:25 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_25_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_26 26:26 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_26_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_27 27:27 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_27_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_28 28:28 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_28_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_29 29:29 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_29_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_30 30:30 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_30_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_31 31:31 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_31_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS 0x00000500 /* R--4R */ #define NV_CPWR_PMU_IDLE_STATUS_GR_FE 0:0 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_GR_FE_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_GR_FE_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_SYS 1:1 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_SYS_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_SYS_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_GPC 2:2 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_GPC_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_GPC_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE 2:1 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_NOT_USED_3 3:3 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_NOT_USED_3_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_SEC 4:4 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_SEC_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_SEC_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVDEC 5:5 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVDEC_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVDEC_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_NOT_USED_6 6:6 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_NOT_USED_6_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_FB_NOREQ 7:7 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FB_NOREQ_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FB_NOREQ_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FB_PA 8:8 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FB_PA_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FB_PA_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_ALL 9:9 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_ALL_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_ALL_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_NISO 10:10 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_NISO_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_NISO_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FB_ASR 11:11 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_FB_ASR_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_FB_ASR_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_LTC_IDLE 12:12 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_LTC_IDLE_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_LTC_IDLE_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_AZA_IDLE 13:13 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_AZA_IDLE_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_AZA_IDLE_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED0 14:14 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED0_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED0_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_NOT_USED_15 15:15 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_NOT_USED_15_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_NISO_EX_ISO 16:16 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_NISO_EX_ISO_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HSHUB_NISO_EX_ISO_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVENC0 17:17 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVENC0_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVENC0_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XBAR_IDLE 18:18 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_XBAR_IDLE_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XBAR_IDLE_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_CE_0 19:19 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_CE_0_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_CE_0_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_CE_1 20:20 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_CE_1_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_CE_1_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_CE_2 21:21 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_CE_2_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_CE_2_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_NOT_USED_22 22:22 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_NOT_USED_22_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_XP_L0S 23:23 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_XP_L0S_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XP_L0S_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XP_L1 24:24 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_XP_L1_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XP_L1_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVE_XCLK 25:25 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_XVE_XCLK_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVE_XCLK_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_COMMON 26:26 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_COMMON_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_COMMON_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_DEEP 27:27 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_DEEP_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_DEEP_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_XP 28:28 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_XP_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_XP_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_XVE 29:29 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_XVE_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP_XVE_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_XVXP 29:26 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED1 30:30 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED1_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED1_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED2 31:31 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED2_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_HOST_ESCHED2_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVENC(i) (17+5*(i)):(17+5*(i)) /* */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVENC__SIZE_1 1 /* */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVENC_BUSY 0 /* */ #define NV_CPWR_PMU_IDLE_STATUS_VD_NVENC_IDLE 1 /* */ #define NV_CPWR_PMU_IDLE_STATUS_1 0x000009e4 /* RW-4R */ #define NV_CPWR_PMU_IDLE_STATUS_1_HSHUB_MMU 0:0 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_HSHUB_MMU_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HSHUB_MMU_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_GSP 1:1 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_GSP_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_GSP_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_FBHUB_ALL 2:2 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_FBHUB_ALL_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_FBHUB_ALL_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_FBHUB_NONPMU_INTERFACE 3:3 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_FBHUB_NONPMU_INTERFACE_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_FBHUB_NONPMU_INTERFACE_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_MS_MMU 4:4 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_MS_MMU_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_MS_MMU_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED3 5:5 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED3_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED3_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED4 6:6 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED4_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED4_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED5 7:7 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED5_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED5_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED6 8:8 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED6_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED6_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED7 9:9 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED7_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED7_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED8 10:10 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED8_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_HOST_ESCHED8_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_11 11:11 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_11_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_12 12:12 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_12_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_13 13:13 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_13_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_14 14:14 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_14_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_15 15:15 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_15_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_16 16:16 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_16_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_17 17:17 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_17_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_18 18:18 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_18_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_PMU2FB_TRAFFIC 19:19 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_PMU2FB_TRAFFIC_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_PMU2FB_TRAFFIC_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_CE_3 20:20 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_CE_3_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_CE_3_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_CE_4 21:21 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_CE_4_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_CE_4_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_22 22:22 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_22_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_23 23:23 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_23_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_24 24:24 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_24_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_25 25:25 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_25_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_26 26:26 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_26_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_SEC_FBIF 27:27 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_SEC_FBIF_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_SEC_FBIF_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_28 28:28 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_28_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_29 29:29 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_1_NOT_USED_29_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_1_SW0 30:30 /* RWIVF */ #define NV_CPWR_PMU_IDLE_STATUS_1_SW0_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_STATUS_1_SW0_IDLE 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_IDLE_STATUS_1_SW1 31:31 /* RWIVF */ #define NV_CPWR_PMU_IDLE_STATUS_1_SW1_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_STATUS_1_SW1_IDLE 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_IDLE_STATUS_2 0x0000068c /* RW-4R */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_0 0:0 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_0_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_1 1:1 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_1_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_2 2:2 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_2_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_3 3:3 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_3_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_4 4:4 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_4_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_5 5:5 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_5_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_FB 6:6 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_FB_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_FB_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_7 7:7 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_7_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_VD_NVDEC1 8:8 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_VD_NVDEC1_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_VD_NVDEC1_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_9 9:9 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_9_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_10 10:10 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_10_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_11 11:11 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_11_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_12 12:12 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_12_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_13 13:13 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_13_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_GR 14:14 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_GR_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_GR_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_MS 15:15 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_MS_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_MS_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_GR 16:16 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_GR_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_GR_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_MS 17:17 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_MS_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_MS_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_18 18:18 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_18_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_19 19:19 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_19_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_20 20:20 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_20_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_21 21:21 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_21_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_22 22:22 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_22_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_23 23:23 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_23_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_24 24:24 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_24_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_25 25:25 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_25_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_26 26:26 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_26_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_27 27:27 /* C--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_NOT_USED_27_TIEHIGH 0x00000001 /* C---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_VD_OFA 28:28 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_VD_OFA_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_VD_OFA_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_MS 29:29 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_MS_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_MS_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_GR 30:30 /* R--VF */ #define NV_CPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_GR_BUSY 0x00000000 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_GR_IDLE 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_STATUS_2_SW2 31:31 /* RWIVF */ #define NV_CPWR_PMU_IDLE_STATUS_2_SW2_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_STATUS_2_SW2_IDLE 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK(i) (0x00001e40+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_IDLE_MASK__SIZE_1 16 /* */ #define NV_CPWR_PMU_IDLE_MASK__PRIV_LEVEL_MASK 0x00000b0c /* */ #define NV_CPWR_PMU_IDLE_MASK_GR 0:0 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_GR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_GR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_GR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_GR_SYS 1:1 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_GR_SYS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_GR_SYS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_GR_SYS_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_GR_GPC 2:2 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_GR_GPC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_GR_GPC_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_GR_GPC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_SEC 4:4 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_SEC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_SEC_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_SEC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_VD_NVDEC 5:5 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_VD_NVDEC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_VD_NVDEC_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_VD_NVDEC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_FB_NOREQ 7:7 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_FB_NOREQ_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_FB_NOREQ_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_FB_NOREQ_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_FB_PA 8:8 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_FB_PA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_FB_PA_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_FB_PA_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_ALL 9:9 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_ALL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_ALL_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_ALL_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_NISO 10:10 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_NISO_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_NISO_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_NISO_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_FB_ASR 11:11 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_FB_ASR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_FB_ASR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_FB_ASR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_LTC_IDLE 12:12 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_LTC_IDLE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_LTC_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_LTC_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_AZA_IDLE 13:13 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_AZA_IDLE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_AZA_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_AZA_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED0 14:14 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED0_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_NISO_EX_ISO 16:16 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_NISO_EX_ISO_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_NISO_EX_ISO_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HSHUB_NISO_EX_ISO_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_VD_NVENC0 17:17 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_VD_NVENC0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_VD_NVENC0_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_VD_NVENC0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XBAR_IDLE 18:18 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_XBAR_IDLE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_XBAR_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XBAR_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_CE_0 19:19 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_CE_0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_CE_0_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_CE_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_CE_1 20:20 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_CE_1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_CE_1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_CE_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_CE_2 21:21 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_CE_2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_CE_2_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_CE_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XP_L0S 23:23 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_XP_L0S_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_XP_L0S_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XP_L0S_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XP_L1 24:24 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_XP_L1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_XP_L1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XP_L1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVE_XCLK 25:25 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_XVE_XCLK_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_XVE_XCLK_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVE_XCLK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_COMMON 26:26 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_COMMON_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_COMMON_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_COMMON_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_DEEP 27:27 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_DEEP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_DEEP_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_DEEP_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_XP 28:28 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_XP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_XP_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_XP_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_XVE 29:29 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_XVE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_XVE_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_XVXP_XVE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED1 30:30 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED2 31:31 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED2_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_HOST_ESCHED2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_CE_IDX(i) (19+(i)):(19+(i)) /* */ #define NV_CPWR_PMU_IDLE_MASK_CE_IDX__SIZE_1 3 /* */ #define NV_CPWR_PMU_IDLE_MASK_CE_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_IDLE_MASK_CE_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_IDLE_MASK_1(i) (0x00001e80+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_IDLE_MASK_1__SIZE_1 16 /* */ #define NV_CPWR_PMU_IDLE_MASK_1__PRIV_LEVEL_MASK 0x00000b0c /* */ #define NV_CPWR_PMU_IDLE_MASK_1_HSHUB_MMU 0:0 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_HSHUB_MMU_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_HSHUB_MMU_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HSHUB_MMU_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_GSP 1:1 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_GSP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_GSP_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_GSP_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_FBHUB_ALL 2:2 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_FBHUB_ALL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_FBHUB_ALL_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_FBHUB_ALL_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_FBHUB_HNONPMU_INTERFACE 3:3 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_FBHUB_HNONPMU_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_FBHUB_HNONPMU_INTERFACE_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_FBHUB_HNONPMU_INTERFACE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_MS_MMU 4:4 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_MS_MMU_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_MS_MMU_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_MS_MMU_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED3 5:5 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED3_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED4 6:6 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED4_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED5 7:7 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED5_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED6 8:8 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED6_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED7 9:9 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED7_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED8 10:10 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED8_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED8_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_HOST_ESCHED8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_PMU2FB_TRAFFIC 19:19 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_PMU2FB_TRAFFIC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_PMU2FB_TRAFFIC_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_PMU2FB_TRAFFIC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_CE_3 20:20 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_CE_3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_CE_3_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_CE_3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_CE_4 21:21 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_CE_4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_CE_4_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_CE_4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_SEC_FBIF 27:27 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_SEC_FBIF_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_SEC_FBIF_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_SEC_FBIF_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_SW0 30:30 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_SW0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_SW0_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_SW0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_SW1 31:31 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_SW1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_SW1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_1_SW1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2(i) (0x00001ec0+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_IDLE_MASK_2__SIZE_1 16 /* */ #define NV_CPWR_PMU_IDLE_MASK_2__PRIV_LEVEL_MASK 0x00000b0c /* */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_FB 6:6 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_FB_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_FB_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_FB_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_VD_NVDEC1 8:8 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_VD_NVDEC1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_VD_NVDEC1_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_VD_NVDEC1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_GR 14:14 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_GR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_GR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_GR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_MS 15:15 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_MS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_MS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_MS_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_GR 16:16 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_GR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_GR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_GR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_MS 17:17 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_MS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_MS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_MS_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_VD_OFA 28:28 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_VD_OFA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_VD_OFA_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_VD_OFA_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_MS 29:29 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_MS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_MS_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_MS_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_GR 30:30 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_GR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_GR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_GR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_SW2 31:31 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_SW2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_SW2_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_MASK_2_SW2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_COUNT(i) (0x00001f80+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_IDLE_COUNT__SIZE_1 16 /* */ #define NV_CPWR_PMU_IDLE_COUNT__PRIV_LEVEL_MASK 0x00000b0c /* */ #define NV_CPWR_PMU_IDLE_COUNT_VALUE 30:0 /* R-IVF */ #define NV_CPWR_PMU_IDLE_COUNT_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_COUNT_RESET 31:31 /* RWIVF */ #define NV_CPWR_PMU_IDLE_COUNT_RESET_DONE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_COUNT_RESET_NOT_DONE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_IDLE_COUNT_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_IDLE_CTRL(i) (0x00001fc0+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_IDLE_CTRL__SIZE_1 16 /* */ #define NV_CPWR_PMU_IDLE_CTRL__PRIV_LEVEL_MASK 0x00000b0c /* */ #define NV_CPWR_PMU_IDLE_CTRL_VALUE 1:0 /* RWIVF */ #define NV_CPWR_PMU_IDLE_CTRL_VALUE_NEVER 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_CTRL_VALUE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_CTRL_VALUE_BUSY 0x00000002 /* RW--V */ #define NV_CPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 0x00000003 /* RW--V */ #define NV_CPWR_PMU_IDLE_CTRL_FILTER 2:2 /* RWIVF */ #define NV_CPWR_PMU_IDLE_CTRL_FILTER_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_CTRL_FILTER_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_CTRL_FILTER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_THRESHOLD(i) (0x00001e00+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_IDLE_THRESHOLD__SIZE_1 16 /* */ #define NV_CPWR_PMU_IDLE_THRESHOLD_VALUE 30:0 /* RWIUF */ #define NV_CPWR_PMU_IDLE_THRESHOLD_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_INTR 0x000009e8 /* RW-4R */ #define NV_CPWR_PMU_IDLE_INTR_EN 0:0 /* RWIUF */ #define NV_CPWR_PMU_IDLE_INTR_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_INTR_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_IDLE_INTR_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_INTR_STATUS 0x000009ec /* RW-4R */ #define NV_CPWR_PMU_IDLE_INTR_STATUS_INTR 0:0 /* RWIUF */ #define NV_CPWR_PMU_IDLE_INTR_STATUS_INTR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IDLE_INTR_STATUS_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_IDLE_INTR_STATUS_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_IDLE_MASK_SUPP(i) (0x000009f0+(i)*8) /* RW-4A */ #define NV_CPWR_PMU_IDLE_MASK_SUPP__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_IDX_GR 0 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_IDX_VID 1 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_IDX_HISTOGRAM_0 2 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_IDX_HISTOGRAM_1 3 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_IDX_MS 4 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_IDX_HISTOGRAM_2 5 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_IDX_HISTOGRAM_3 6 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_IDX_DI 7 /* */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_VALUE 31:0 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_SUPP_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_1_SUPP(i) (0x000009f4+(i)*8) /* RW-4A */ #define NV_CPWR_PMU_IDLE_MASK_1_SUPP__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_MASK_1_SUPP_VALUE 31:0 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_1_SUPP_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_MASK_2_SUPP(i) (0x00000690+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_IDLE_MASK_2_SUPP__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_MASK_2_SUPP_VALUE 31:0 /* RWIVF */ #define NV_CPWR_PMU_IDLE_MASK_2_SUPP_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP(i) (0x00000a30+(i)*8) /* RW-4A */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP__SIZE_1 8 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_IDX_GR 0 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_IDX_VID 1 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_IDX_HISTOGRAM_0 2 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_IDX_HISTOGRAM_1 3 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_IDX_MS 4 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_IDX_HISTOGRAM_2 5 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_IDX_HISTOGRAM_3 6 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_IDX_DI 7 /* */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_VALUE 1:0 /* RWIVF */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_VALUE_NEVER 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_VALUE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_VALUE_BUSY 0x00000002 /* RW--V */ #define NV_CPWR_PMU_IDLE_CTRL_SUPP_VALUE_ALWAYS 0x00000003 /* RW--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL(i) (0x000008c0+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_HISTOGRAM_CTRL__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_CTRL__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_START 0:0 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_START_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_START_OFF 0x00000000 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_START_PAUSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_START_ON 0x00000001 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_START_RESUME 0x00000001 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_RESET 4:4 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_RESET_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_RESET_OFF 0x00000000 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_RESET_ON 0x00000001 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_SHIFTWINDOW 12:8 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_SHIFTWINDOW_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_SHIFTWINDOW_MIN 0x00000000 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_SHIFTWINDOW_MAX 0x00000010 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_LOAD 16:16 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_LOAD_INIT 0x00000000 /* --I-V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_LOAD_TRIG 0x00000001 /* -W--T */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_MODE 20:20 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_MODE_FIXED 0x00000000 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_CTRL_MODE_FLOAT 0x00000001 /* -W--V */ #define NV_CPWR_PMU_HISTOGRAM_COUNT(i) (0x000008d0+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_COUNT__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_COUNT_VALUE 31:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_COUNT_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_COUNT_INCR(i) (0x00000960+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_HISTOGRAM_COUNT_INCR__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_COUNT_INCR__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_HISTOGRAM_COUNT_INCR_VALUE 31:0 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_COUNT_INCR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0(i) (0x00000600+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0_00 7:0 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0_00_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0_01 15:8 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0_01_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0_02 23:16 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0_02_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0_03 31:24 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS3TO0_03_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4(i) (0x00000610+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4_04 7:0 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4_04_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4_05 15:8 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4_05_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4_06 23:16 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4_06_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4_07 31:24 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS7TO4_07_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8(i) (0x00000620+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8_08 7:0 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8_08_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8_09 15:8 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8_09_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8_10 23:16 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8_10_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8_11 31:24 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS11TO8_11_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12(i) (0x00000630+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12_12 7:0 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12_12_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12_13 15:8 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12_13_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12_14 23:16 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12_14_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12_15 31:24 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_FLOORS15TO12_15_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS1TO0(i) (0x000008e0+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_BINS1TO0__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS1TO0_00 15:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS1TO0_00_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS1TO0_01 31:16 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS1TO0_01_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS3TO2(i) (0x000008f0+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_BINS3TO2__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS3TO2_02 15:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS3TO2_02_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS3TO2_03 31:16 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS3TO2_03_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS5TO4(i) (0x00000900+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_BINS5TO4__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS5TO4_04 15:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS5TO4_04_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS5TO4_05 31:16 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS5TO4_05_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS7TO6(i) (0x00000910+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_BINS7TO6__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS7TO6_06 15:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS7TO6_06_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS7TO6_07 31:16 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS7TO6_07_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS9TO8(i) (0x00000920+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_BINS9TO8__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS9TO8_08 15:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS9TO8_08_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS9TO8_09 31:16 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS9TO8_09_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS11TO10(i) (0x00000930+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_BINS11TO10__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS11TO10_10 15:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS11TO10_10_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS11TO10_11 31:16 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS11TO10_11_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS13TO12(i) (0x00000940+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_BINS13TO12__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS13TO12_12 15:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS13TO12_12_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS13TO12_13 31:16 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS13TO12_13_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS15TO14(i) (0x00000950+(i)*4) /* R--4A */ #define NV_CPWR_PMU_HISTOGRAM_BINS15TO14__SIZE_1 4 /* */ #define NV_CPWR_PMU_HISTOGRAM_BINS15TO14_14 15:0 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS15TO14_14_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_BINS15TO14_15 31:16 /* R-IUF */ #define NV_CPWR_PMU_HISTOGRAM_BINS15TO14_15_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_HISTOGRAM_SCALING 0x000009e0 /* RW-4R */ #define NV_CPWR_PMU_HISTOGRAM_SCALING__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_HISTOGRAM_SCALING_EN 0:0 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_SCALING_EN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_SCALING_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_HISTOGRAM_SCALING_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_HISTOGRAM_SCALING_X 11:8 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_SCALING_X_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_HISTOGRAM_SCALING_Y 15:12 /* RWIUF */ #define NV_CPWR_PMU_HISTOGRAM_SCALING_Y_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_IP_VER 0x00000430 /* R--4R */ #define NV_CPWR_PMU_IP_VER_DEV 7:0 /* R-IVF */ #define NV_CPWR_PMU_IP_VER_DEV_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IP_VER_ECO 15:8 /* R-IVF */ #define NV_CPWR_PMU_IP_VER_ECO_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_IP_VER_MINOR 23:16 /* R-IVF */ #define NV_CPWR_PMU_IP_VER_MINOR_INIT 0x00000002 /* R-I-V */ #define NV_CPWR_PMU_IP_VER_MINOR_GF119 0x00000000 /* R---V */ #define NV_CPWR_PMU_IP_VER_MINOR_GF117 0x00000001 /* R---V */ #define NV_CPWR_PMU_IP_VER_MINOR_GK104 0x00000000 /* R---V */ #define NV_CPWR_PMU_IP_VER_MINOR_GK110 0x00000001 /* R---V */ #define NV_CPWR_PMU_IP_VER_MINOR_GK208 0x00000002 /* R---V */ #define NV_CPWR_PMU_IP_VER_MINOR_GK20A 0x00000000 /* R---V */ #define NV_CPWR_PMU_IP_VER_MAJOR 31:24 /* R-IVF */ #define NV_CPWR_PMU_IP_VER_MAJOR_INIT 0x00000002 /* R-I-V */ #define NV_CPWR_PMU_IP_VER_MAJOR_GF119 0x00000001 /* R---V */ #define NV_CPWR_PMU_IP_VER_MAJOR_GF117 0x00000001 /* R---V */ #define NV_CPWR_PMU_IP_VER_MAJOR_GK104 0x00000002 /* R---V */ #define NV_CPWR_PMU_IP_VER_MAJOR_GK110 0x00000002 /* R---V */ #define NV_CPWR_PMU_IP_VER_MAJOR_GK208 0x00000002 /* R---V */ #define NV_CPWR_PMU_IP_VER_MAJOR_GK20A 0x00000003 /* R---V */ #define NV_CPWR_PMU_DEBUG(i) (0x000005c0+(i)*4) /* R--4A */ #define NV_CPWR_PMU_DEBUG__SIZE_1 4 /* */ #define NV_CPWR_PMU_DEBUG_VAL 31:0 /* R-IVF */ #define NV_CPWR_PMU_DEBUG_VAL_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_MAILBOX(i) (0x00000450+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_MAILBOX__SIZE_1 12 /* */ #define NV_CPWR_PMU_MAILBOX_VAL 31:0 /* RWIVF */ #define NV_CPWR_PMU_MAILBOX_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_DEBUG_TAG 0x000005f0 /* RW-4R */ #define NV_CPWR_PMU_DEBUG_TAG_VAL 31:0 /* RWIVF */ #define NV_CPWR_PMU_DEBUG_TAG_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_TPRIV_WRBE 0x000005f4 /* RW-4R */ #define NV_CPWR_PMU_TPRIV_WRBE_VAL 3:0 /* RWIVF */ #define NV_CPWR_PMU_TPRIV_WRBE_VAL_INIT 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_WSP_GP_MSGBOX 0x000005f8 /* RW-4R */ #define NV_CPWR_PMU_WSP_GP_MSGBOX_VAL 31:0 /* RWIVF */ #define NV_CPWR_PMU_WSP_GP_MSGBOX_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_WSP_GP_MSGBOX_1 0x00000b78 /* RW-4R */ #define NV_CPWR_PMU_WSP_GP_MSGBOX_1_VAL 31:0 /* RWIVF */ #define NV_CPWR_PMU_WSP_GP_MSGBOX_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_WSP_GP_MSGBOX_2 0x00000b7c /* RW-4R */ #define NV_CPWR_PMU_WSP_GP_MSGBOX_2_VAL 31:0 /* RWIVF */ #define NV_CPWR_PMU_WSP_GP_MSGBOX_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT 0x000007c0 /* R--4R */ #define NV_CPWR_PMU_GPIO_OUTPUT_PMU_2_FECS_REQ 0:0 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_PMU_2_FECS_REQ_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PMU_2_FECS_REQ_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_PMU_2_FECS_REQ_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_FECS_2_PMU_ACK 1:1 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_FECS_2_PMU_ACK_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_FECS_2_PMU_ACK_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_FECS_2_PMU_ACK_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_FB_STOP_REQ 2:2 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_FB_STOP_REQ_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_FB_STOP_REQ_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_FB_STOP_REQ_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLK(i) (3+(i)):(3+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLK__SIZE_1 3 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLK_INIT 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLK_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLK_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS 3:3 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS1 4:4 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS1_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS1_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS2 5:5 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS2_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_STOPCLOCKS2_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL0 10:10 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL0_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL0_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL1 11:11 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL1_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL1_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL2 12:12 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL2_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL2_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL3 13:13 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL3_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL3_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL4 14:14 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL4_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL4_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL5 15:15 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL5_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL5_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL6 16:16 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL6_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL6_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL7 17:17 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL7_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL7_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL8 18:18 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL8_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL8_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL8_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL9 19:19 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL9_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL9_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL9_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL 19:10 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA0 20:20 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA0_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA0_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA1 21:21 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA1_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA1_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA2 22:22 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA2_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA2_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA3 23:23 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA3_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA3_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA4 24:24 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA4_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA4_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA5 25:25 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA5_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA5_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA6 26:26 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA6_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA6_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA7 27:27 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA7_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA7_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA8 28:28 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA8_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA8_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA8_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA9 29:29 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA9_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA9_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA9_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA 29:20 /* R-IVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL_IDX_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SCL_IDX_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA_IDX_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_I2C_SDA_IDX_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_INPUT 0x000007c4 /* R--4R */ #define NV_CPWR_PMU_GPIO_INPUT_PMU_2_FECS_ACK 0:0 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_PMU_2_FECS_ACK_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_PMU_2_FECS_ACK_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_PMU_2_FECS_ACK_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_FECS_2_PMU_REQ 1:1 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_FECS_2_PMU_REQ_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_FECS_2_PMU_REQ_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_FECS_2_PMU_REQ_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_FB_STOP_ACK 2:2 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_FB_STOP_ACK_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_FB_STOP_ACK_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_FB_STOP_ACK_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_XVE_INTR 3:3 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_XVE_INTR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_XVE_INTR_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_XVE_INTR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_PMGR_INTR 8:8 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_PMGR_INTR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_PMGR_INTR_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_PMGR_INTR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL0 10:10 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL0_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL0_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL1 11:11 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL1_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL1_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL2 12:12 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL2_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL2_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL3 13:13 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL3_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL3_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL4 14:14 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL4_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL4_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL5 15:15 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL5_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL5_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL6 16:16 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL6_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL6_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL7 17:17 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL7_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL7_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL8 18:18 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL8_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL8_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL8_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL9 19:19 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL9_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL9_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL9_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL 19:10 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA0 20:20 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA0_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA0_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA1 21:21 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA1_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA1_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA2 22:22 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA2_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA2_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA3 23:23 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA3_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA3_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA4 24:24 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA4_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA4_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA5 25:25 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA5_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA5_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA5_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA6 26:26 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA6_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA6_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA6_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA7 27:27 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA7_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA7_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA7_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA8 28:28 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA8_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA8_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA8_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA9 29:29 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA9_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA9_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA9_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA 29:20 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_DISP_2PMU_INTR 30:30 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_DISP_2PMU_INTR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_DISP_2PMU_INTR_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_DISP_2PMU_INTR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_XVXP_DEEP_IDLE 31:31 /* R-IVF */ #define NV_CPWR_PMU_GPIO_INPUT_XVXP_DEEP_IDLE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INPUT_XVXP_DEEP_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_XVXP_DEEP_IDLE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL_IDX_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SCL_IDX_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA_IDX_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_INPUT_I2C_SDA_IDX_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_1_INPUT 0x000007e8 /* R--4R */ #define NV_CPWR_PMU_GPIO_1_INPUT_FBH_DWCF 1:1 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_FBH_DWCF_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_FBH_DWCF_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_FBH_DWCF_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_IHUB_OK_TO_SWITCH 3:3 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_IHUB_OK_TO_SWITCH_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_IHUB_OK_TO_SWITCH_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_IHUB_OK_TO_SWITCH_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_HSHUB1_FB_BLOCKER 11:11 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_HSHUB1_FB_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_HSHUB1_FB_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_HSHUB1_FB_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_HSHUB_FB_BLOCKER 12:12 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_HSHUB_FB_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_HSHUB_FB_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_HSHUB_FB_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_MEMPOOL_DRAINING 13:13 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_MEMPOOL_DRAINING_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_MEMPOOL_DRAINING_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_MEMPOOL_DRAINING_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_MSPG_WAKE 14:14 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_MSPG_WAKE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_MSPG_WAKE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_MSPG_WAKE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XVE_BAR_GR_BLOCKER 15:15 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_XVE_BAR_GR_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XVE_BAR_GR_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XVE_BAR_GR_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XVE_BAR_BLOCKER 16:16 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_XVE_BAR_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XVE_BAR_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XVE_BAR_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_PERF_FB_BLOCKER 17:17 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_PERF_FB_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_PERF_FB_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_PERF_FB_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_SEC_FB_BLOCKER 19:19 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_SEC_FB_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_SEC_FB_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_SEC_FB_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_ISO_FB_BLOCKER 20:20 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_ISO_FB_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_ISO_FB_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_ISO_FB_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_DNISO_FB_BLOCKER 21:21 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_DNISO_FB_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_DNISO_FB_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_DNISO_FB_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_1 23:23 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_1_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_1_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_2 24:24 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_2_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_2_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_SEC_PRIV_BLOCKER 25:25 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_SEC_PRIV_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_SEC_PRIV_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_SEC_PRIV_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_GSP_FB_BLOCKER 26:26 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_GSP_FB_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_GSP_FB_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_GSP_FB_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_GSP_PRIV_BLOCKER 27:27 /* R-IVF */ #define NV_CPWR_PMU_GPIO_1_INPUT_GSP_PRIV_BLOCKER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INPUT_GSP_PRIV_BLOCKER_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INPUT_GSP_PRIV_BLOCKER_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_BYPASS 0x000007c8 /* RW-4R */ #define NV_CPWR_PMU_GPIO_BYPASS__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_BYPASS_FECS_2_PMU 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_FECS_2_PMU_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_FECS_2_PMU_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SCL_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_BYPASS_I2C_SDA_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING 0x000007cc /* RW-4R */ #define NV_CPWR_PMU_GPIO_INTR_RISING__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_PMU_2_FECS_ACK 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_PMU_2_FECS_ACK_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_PMU_2_FECS_ACK_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_PMU_2_FECS_ACK_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_FECS_2_PMU_REQ 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_FECS_2_PMU_REQ_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_FECS_2_PMU_REQ_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_FECS_2_PMU_REQ_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_FB_STOP_ACK 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_FB_STOP_ACK_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_FB_STOP_ACK_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_FB_STOP_ACK_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_XVE_INTR 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_XVE_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_XVE_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_XVE_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_PMGR_INTR 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_PMGR_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_PMGR_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_PMGR_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_DISP_2PMU_INTR 30:30 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_DISP_2PMU_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_DISP_2PMU_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_DISP_2PMU_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_XVXP_DEEP_IDLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_XVXP_DEEP_IDLE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_XVXP_DEEP_IDLE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_XVXP_DEEP_IDLE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX_PENDING 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX_PENDING 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING 0x000007ec /* RW-4R */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_FBH_DWCF 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_FBH_DWCF_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_FBH_DWCF_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_FBH_DWCF_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_IHUB_OK_TO_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_IHUB_OK_TO_SWITCH_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_IHUB_OK_TO_SWITCH_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_HSHUB1_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_HSHUB1_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_HSHUB1_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_HSHUB_FB_BLOCKER 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_HSHUB_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_HSHUB_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_HSHUB_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_MEMPOOL_DRAINING 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_MEMPOOL_DRAINING_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_MEMPOOL_DRAINING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_MEMPOOL_DRAINING_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_MSPG_WAKE 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_MSPG_WAKE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_MSPG_WAKE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_MSPG_WAKE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_GR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_GR_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_GR_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_BLOCKER 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_PERF_FB_BLOCKER 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_PERF_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_PERF_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_PERF_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_SEC_FB_BLOCKER 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_SEC_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_SEC_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_SEC_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_ISO_FB_BLOCKER 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_ISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_ISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_ISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_DNISO_FB_BLOCKER 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_DNISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_DNISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_DNISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_SEC_PRIV_BLOCKER 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_SEC_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_SEC_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_SEC_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_GSP_FB_BLOCKER 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_GSP_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_GSP_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_GSP_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_GSP_PRIV_BLOCKER 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_GSP_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_GSP_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_GSP_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING 0x000007d0 /* RW-4R */ #define NV_CPWR_PMU_GPIO_INTR_FALLING__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_PMU_2_FECS_ACK 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_PMU_2_FECS_ACK_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_PMU_2_FECS_ACK_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_PMU_2_FECS_ACK_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_FECS_2_PMU_REQ 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_FECS_2_PMU_REQ_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_FECS_2_PMU_REQ_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_FECS_2_PMU_REQ_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_FB_STOP_ACK 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_FB_STOP_ACK_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_FB_STOP_ACK_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_FB_STOP_ACK_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_XVE_INTR 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_XVE_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_XVE_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_XVE_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_PMGR_INTR 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_PMGR_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_PMGR_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_PMGR_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_DISP_2PMU_INTR 30:30 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_DISP_2PMU_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_DISP_2PMU_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_DISP_2PMU_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_XVXP_DEEP_IDLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_XVXP_DEEP_IDLE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_XVXP_DEEP_IDLE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_XVXP_DEEP_IDLE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX_PENDING 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX_PENDING 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING 0x000007f0 /* RW-4R */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_FBH_DWCF 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_FBH_DWCF_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_FBH_DWCF_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_FBH_DWCF_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_IHUB_OK_TO_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_IHUB_OK_TO_SWITCH_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_IHUB_OK_TO_SWITCH_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_HSHUB1_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_HSHUB1_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_HSHUB1_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_HSHUB_FB_BLOCKER 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_HSHUB_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_HSHUB_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_HSHUB_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_MEMPOOL_DRAINING 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_MEMPOOL_DRAINING_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_MEMPOOL_DRAINING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_MEMPOOL_DRAINING_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_MSPG_WAKE 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_MSPG_WAKE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_MSPG_WAKE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_MSPG_WAKE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_GR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_GR_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_GR_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_BLOCKER 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_PERF_FB_BLOCKER 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_PERF_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_PERF_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_PERF_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_SEC_FB_BLOCKER 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_SEC_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_SEC_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_SEC_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_ISO_FB_BLOCKER 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_ISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_ISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_ISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_DNISO_FB_BLOCKER 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_DNISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_DNISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_DNISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_SEC_PRIV_BLOCKER 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_SEC_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_SEC_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_SEC_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_GSP_FB_BLOCKER 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_GSP_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_GSP_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_GSP_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_GSP_PRIV_BLOCKER 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_GSP_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_GSP_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_GSP_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN 0x000007d4 /* RW-4R */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_PMU_2_FECS_ACK 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_PMU_2_FECS_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_PMU_2_FECS_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_FECS_2_PMU_REQ 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_FECS_2_PMU_REQ_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_FECS_2_PMU_REQ_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_FB_STOP_ACK 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_FB_STOP_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_FB_STOP_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_XVE_INTR 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_XVE_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_XVE_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_PMGR_INTR 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_PMGR_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_PMGR_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_DISP_2PMU_INTR 30:30 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_DISP_2PMU_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_DISP_2PMU_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_XVXP_DEEP_IDLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_XVXP_DEEP_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_XVXP_DEEP_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN 0x000007f4 /* RW-4R */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_FBH_DWCF 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_FBH_DWCF_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_FBH_DWCF_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_IHUB_OK_TO_SWITCH_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_IHUB_OK_TO_SWITCH_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB1_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB1_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB_FB_BLOCKER 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_MEMPOOL_DRAINING 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_MEMPOOL_DRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_MEMPOOL_DRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_MSPG_WAKE 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_MSPG_WAKE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_MSPG_WAKE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_GR_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_GR_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_BLOCKER 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_PERF_FB_BLOCKER 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_PERF_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_PERF_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_FB_BLOCKER 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_ISO_FB_BLOCKER 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_ISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_ISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_DNISO_FB_BLOCKER 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_DNISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_DNISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_PRIV_BLOCKER 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_FB_BLOCKER 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_PRIV_BLOCKER 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN 0x000007d8 /* RW-4R */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_PMU_2_FECS_ACK 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_PMU_2_FECS_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_PMU_2_FECS_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_FECS_2_PMU_REQ 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_FECS_2_PMU_REQ_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_FECS_2_PMU_REQ_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_FB_STOP_ACK 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_FB_STOP_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_FB_STOP_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_XVE_INTR 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_XVE_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_XVE_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_PMGR_INTR 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_PMGR_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_PMGR_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_DISP_2PMU_INTR 30:30 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_DISP_2PMU_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_DISP_2PMU_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_XVXP_DEEP_IDLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_XVXP_DEEP_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_XVXP_DEEP_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN 0x000007f8 /* RW-4R */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_FBH_DWCF 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_FBH_DWCF_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_FBH_DWCF_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_IHUB_OK_TO_SWITCH_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_IHUB_OK_TO_SWITCH_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB1_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB1_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB_FB_BLOCKER 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_MEMPOOL_DRAINING 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_MEMPOOL_DRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_MEMPOOL_DRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_MSPG_WAKE 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_MSPG_WAKE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_MSPG_WAKE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_GR_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_GR_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_BLOCKER 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_PERF_FB_BLOCKER 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_PERF_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_PERF_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_FB_BLOCKER 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_ISO_FB_BLOCKER 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_ISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_ISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_DNISO_FB_BLOCKER 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_DNISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_DNISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_PRIV_BLOCKER 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_FB_BLOCKER 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_PRIV_BLOCKER 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET 0x000007e0 /* RW-4R */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET__PRIV_LEVEL_MASK 0x0000053c /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLK(i) (3+(i)):(3+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLK__SIZE_1 3 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLK_INIT 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLK_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLK_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLK_TRIGGER 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1 4:4 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2 5:5 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL 19:10 /* -WIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA 29:20 /* -WIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX_TRIGGER 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX_TRIGGER 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR 0x000007e4 /* RW-4R */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR__PRIV_LEVEL_MASK 0x0000053c /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK(i) (3+(i)):(3+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK__SIZE_1 3 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK_INIT 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1 4:4 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2 5:5 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL 19:10 /* -WIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9_INIT 0x00000000 /* -WI-V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9_FALSE 0x00000000 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9_TRUE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA 29:20 /* -WIVF */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX_FALSE 0 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX_TRUE 1 /* */ #define NV_CPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH 0x00000550 /* RW-4R */ #define NV_CPWR_PMU_GPIO_INTR_HIGH__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_PMU_2_FECS_ACK 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_PMU_2_FECS_ACK_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_PMU_2_FECS_ACK_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_PMU_2_FECS_ACK_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_FECS_2_PMU_REQ 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_FECS_2_PMU_REQ_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_FECS_2_PMU_REQ_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_FECS_2_PMU_REQ_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_FB_STOP_ACK 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_FB_STOP_ACK_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_FB_STOP_ACK_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_FB_STOP_ACK_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_XVE_INTR 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_XVE_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_XVE_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_XVE_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_PMGR_INTR 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_PMGR_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_PMGR_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_PMGR_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_DISP_2PMU_INTR 30:30 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_DISP_2PMU_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_DISP_2PMU_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_DISP_2PMU_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_XVXP_DEEP_IDLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_XVXP_DEEP_IDLE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_XVXP_DEEP_IDLE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_XVXP_DEEP_IDLE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX_PENDING 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX_PENDING 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH 0x00000554 /* RW-4R */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_FBH_DWCF 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_FBH_DWCF_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_FBH_DWCF_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_FBH_DWCF_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_IHUB_OK_TO_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_IHUB_OK_TO_SWITCH_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_IHUB_OK_TO_SWITCH_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_HSHUB1_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_HSHUB1_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_HSHUB1_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_HSHUB_FB_BLOCKER 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_HSHUB_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_HSHUB_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_HSHUB_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_MEMPOOL_DRAINING 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_MEMPOOL_DRAINING_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_MEMPOOL_DRAINING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_MEMPOOL_DRAINING_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_MSPG_WAKE 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_MSPG_WAKE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_MSPG_WAKE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_MSPG_WAKE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_GR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_GR_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_GR_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_BLOCKER 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_PERF_FB_BLOCKER 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_PERF_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_PERF_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_PERF_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_SEC_FB_BLOCKER 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_SEC_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_SEC_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_SEC_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_ISO_FB_BLOCKER 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_ISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_ISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_ISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_DNISO_FB_BLOCKER 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_DNISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_DNISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_DNISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_SEC_PRIV_BLOCKER 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_SEC_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_SEC_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_SEC_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_GSP_FB_BLOCKER 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_GSP_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_GSP_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_GSP_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_GSP_PRIV_BLOCKER 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_GSP_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_GSP_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_GSP_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW 0x00000558 /* RW-4R */ #define NV_CPWR_PMU_GPIO_INTR_LOW__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_PMU_2_FECS_ACK 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_PMU_2_FECS_ACK_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_PMU_2_FECS_ACK_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_PMU_2_FECS_ACK_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_FECS_2_PMU_REQ 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_FECS_2_PMU_REQ_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_FECS_2_PMU_REQ_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_FECS_2_PMU_REQ_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_FB_STOP_ACK 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_FB_STOP_ACK_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_FB_STOP_ACK_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_FB_STOP_ACK_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_XVE_INTR 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_XVE_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_XVE_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_XVE_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_PMGR_INTR 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_PMGR_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_PMGR_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_PMGR_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_DISP_2PMU_INTR 30:30 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_DISP_2PMU_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_DISP_2PMU_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_DISP_2PMU_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_XVXP_DEEP_IDLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_XVXP_DEEP_IDLE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_XVXP_DEEP_IDLE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_XVXP_DEEP_IDLE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX_PENDING 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX_NOT_PENDING 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX_PENDING 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX_CLEAR 1 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW 0x0000055c /* RW-4R */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_FBH_DWCF 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_FBH_DWCF_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_FBH_DWCF_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_FBH_DWCF_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_IHUB_OK_TO_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_IHUB_OK_TO_SWITCH_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_IHUB_OK_TO_SWITCH_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_HSHUB1_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_HSHUB1_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_HSHUB1_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_HSHUB_FB_BLOCKER 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_HSHUB_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_HSHUB_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_HSHUB_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_MEMPOOL_DRAINING 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_MEMPOOL_DRAINING_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_MEMPOOL_DRAINING_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_MEMPOOL_DRAINING_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_MSPG_WAKE 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_MSPG_WAKE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_MSPG_WAKE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_MSPG_WAKE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_GR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_GR_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_GR_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_BLOCKER 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_PERF_FB_BLOCKER 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_PERF_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_PERF_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_PERF_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_SEC_FB_BLOCKER 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_SEC_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_SEC_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_SEC_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_ISO_FB_BLOCKER 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_ISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_ISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_ISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_DNISO_FB_BLOCKER 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_DNISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_DNISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_DNISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_SEC_PRIV_BLOCKER 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_SEC_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_SEC_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_SEC_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_GSP_FB_BLOCKER 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_GSP_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_GSP_FB_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_GSP_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_GSP_PRIV_BLOCKER 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_GSP_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_GSP_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_GSP_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN 0x00000560 /* RW-4R */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_PMU_2_FECS_ACK 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_PMU_2_FECS_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_PMU_2_FECS_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_FECS_2_PMU_REQ 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_FECS_2_PMU_REQ_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_FECS_2_PMU_REQ_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_FB_STOP_ACK 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_FB_STOP_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_FB_STOP_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_XVE_INTR 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_XVE_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_XVE_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_PMGR_INTR 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_PMGR_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_PMGR_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_DISP_2PMU_INTR 30:30 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_DISP_2PMU_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_DISP_2PMU_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_XVXP_DEEP_IDLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_XVXP_DEEP_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_XVXP_DEEP_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN 0x00000564 /* RW-4R */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_FBH_DWCF 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_FBH_DWCF_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_FBH_DWCF_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_IHUB_OK_TO_SWITCH_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_IHUB_OK_TO_SWITCH_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB1_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB1_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB_FB_BLOCKER 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_MEMPOOL_DRAINING 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_MEMPOOL_DRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_MEMPOOL_DRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_MSPG_WAKE 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_MSPG_WAKE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_MSPG_WAKE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_GR_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_GR_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_BLOCKER 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_PERF_FB_BLOCKER 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_PERF_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_PERF_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_FB_BLOCKER 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_ISO_FB_BLOCKER 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_ISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_ISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_DNISO_FB_BLOCKER 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_DNISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_DNISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_PRIV_BLOCKER 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_FB_BLOCKER 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_PRIV_BLOCKER 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN 0x00000568 /* RW-4R */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_PMU_2_FECS_ACK 0:0 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_PMU_2_FECS_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_PMU_2_FECS_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_FECS_2_PMU_REQ 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_FECS_2_PMU_REQ_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_FECS_2_PMU_REQ_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_FB_STOP_ACK 2:2 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_FB_STOP_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_FB_STOP_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_XVE_INTR 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_XVE_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_XVE_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_PMGR_INTR 8:8 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_PMGR_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_PMGR_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL0 10:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL1 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL2 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL3 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL4 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL5 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL6 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL7 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL8 18:18 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL9 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL 19:10 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA0 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA1 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA2 22:22 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA3 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA4 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA5 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA6 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA7 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA8 28:28 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA9 29:29 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA 29:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_DISP_2PMU_INTR 30:30 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_DISP_2PMU_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_DISP_2PMU_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_XVXP_DEEP_IDLE 31:31 /* RWIVF */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_XVXP_DEEP_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_XVXP_DEEP_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA_IDX__SIZE_1 10 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA_IDX_DISABLED 0 /* */ #define NV_CPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA_IDX_ENABLED 1 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN 0x0000056c /* RW-4R */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_FBH_DWCF 1:1 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_FBH_DWCF_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_FBH_DWCF_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_IHUB_OK_TO_SWITCH_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_IHUB_OK_TO_SWITCH_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB1_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB1_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB_FB_BLOCKER 12:12 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_MEMPOOL_DRAINING 13:13 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_MEMPOOL_DRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_MEMPOOL_DRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_MSPG_WAKE 14:14 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_MSPG_WAKE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_MSPG_WAKE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_GR_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_GR_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_BLOCKER 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_PERF_FB_BLOCKER 17:17 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_PERF_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_PERF_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_FB_BLOCKER 19:19 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_ISO_FB_BLOCKER 20:20 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_ISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_ISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_DNISO_FB_BLOCKER 21:21 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_DNISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_DNISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_PRIV_BLOCKER 25:25 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_FB_BLOCKER 26:26 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_PRIV_BLOCKER 27:27 /* RWIVF */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_2_INPUT 0x0000088c /* R--4R */ #define NV_CPWR_PMU_GPIO_2_INPUT_XVE_MARGINING_INTR 16:16 /* R--VF */ #define NV_CPWR_PMU_GPIO_2_INPUT_XVE_MARGINING_INTR_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_GPIO_2_INPUT_XVE_MARGINING_INTR_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING 0x00000890 /* RW-4R */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_XVE_MARGINING_INTR 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_XVE_MARGINING_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_XVE_MARGINING_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_XVE_MARGINING_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING 0x00000894 /* RW-4R */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_XVE_MARGINING_INTR 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_XVE_MARGINING_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_XVE_MARGINING_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_XVE_MARGINING_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_EN 0x00000898 /* RW-4R */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_EN_XVE_MARGINING_INTR 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_EN_XVE_MARGINING_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_2_INTR_RISING_EN_XVE_MARGINING_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_EN 0x0000089c /* RW-4R */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_EN_XVE_MARGINING_INTR 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_EN_XVE_MARGINING_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_2_INTR_FALLING_EN_XVE_MARGINING_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH 0x00000570 /* RW-4R */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_XVE_MARGINING_INTR 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_XVE_MARGINING_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_XVE_MARGINING_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_XVE_MARGINING_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW 0x00000574 /* RW-4R */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_XVE_MARGINING_INTR 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_XVE_MARGINING_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_XVE_MARGINING_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_XVE_MARGINING_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_EN 0x00000578 /* RW-4R */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_EN_XVE_MARGINING_INTR 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_EN_XVE_MARGINING_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_2_INTR_HIGH_EN_XVE_MARGINING_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_EN 0x0000057c /* RW-4R */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_EN__PRIV_LEVEL_MASK 0x00000538 /* */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_EN_XVE_MARGINING_INTR 16:16 /* RWIVF */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_EN_XVE_MARGINING_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_GPIO_2_INTR_LOW_EN_XVE_MARGINING_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CSBMASTER_NULL_REQ 0x00000880 /* RW-4R */ #define NV_CPWR_PMU_CSBMASTER_NULL_REQ_ADDR 15:0 /* RWIVF */ #define NV_CPWR_PMU_CSBMASTER_NULL_REQ_ADDR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CSBMASTER_NULL_REQ_ADDR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CSBMASTER_NULL_REQ_WRITE 16:16 /* RWIVF */ #define NV_CPWR_PMU_CSBMASTER_NULL_REQ_WRITE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CSBMASTER_NULL_REQ_WRITE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_CSBMASTER_INTR_EN 0x00000884 /* RW-4R */ #define NV_CPWR_PMU_CSBMASTER_INTR_EN_NULL_REQ 0:0 /* RWIVF */ #define NV_CPWR_PMU_CSBMASTER_INTR_EN_NULL_REQ_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_CSBMASTER_INTR_EN_NULL_REQ_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_CSBMASTER_INTR_EN_NULL_REQ_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_CSBMASTER_INTR 0x00000888 /* RW-4R */ #define NV_CPWR_PMU_CSBMASTER_INTR_NULL_REQ 0:0 /* RWIVF */ #define NV_CPWR_PMU_CSBMASTER_INTR_NULL_REQ_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_CSBMASTER_INTR_NULL_REQ_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_CSBMASTER_INTR_NULL_REQ_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_0 0x00000680 /* RW-4R */ #define NV_CPWR_PMU_INTR_0__PRIV_LEVEL_MASK 0x00000878 /* */ #define NV_CPWR_PMU_INTR_0_TIMER 8:8 /* RWIUF */ #define NV_CPWR_PMU_INTR_0_TIMER_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_0_TIMER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_0_TIMER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_0_EN 0x00000684 /* RW-4R */ #define NV_CPWR_PMU_INTR_0_EN__PRIV_LEVEL_MASK 0x00000878 /* */ #define NV_CPWR_PMU_INTR_0_EN_TIMER 8:8 /* RWIUF */ #define NV_CPWR_PMU_INTR_0_EN_TIMER_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_INTR_1 0x00000688 /* RW-4R */ #define NV_CPWR_PMU_INTR_1__PRIV_LEVEL_MASK 0x0000087c /* */ #define NV_CPWR_PMU_INTR_1_CMD 1:1 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_CMD_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_CMD_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_CMD_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_ELPG_0 2:2 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_ELPG_0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_ELPG_0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_ELPG_0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_ELPG_1 3:3 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_ELPG_1_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_ELPG_1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_ELPG_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_BAR0 4:4 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_BAR0_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_BAR0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_BAR0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_BAU 7:7 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_BAU_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_BAU_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_BAU_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_UART 8:8 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_UART_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_UART_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_UART_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_ELPG_2 5:5 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_ELPG_2_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_ELPG_2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_ELPG_2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_HOLDOFF 9:9 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_HOLDOFF_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_HOLDOFF_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_HOLDOFF_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_ELPG_3 10:10 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_ELPG_3_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_ELPG_3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_ELPG_3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_CSBM 13:13 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_CSBM_INTT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_CSBM_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_CSBM_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_IDLE 14:14 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_IDLE_INTT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_IDLE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_IDLE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_ELPG_4 15:15 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_ELPG_4_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_ELPG_4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_ELPG_4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_IDLE_EDGE 16:16 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_IDLE_EDGE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_IDLE_EDGE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_IDLE_EDGE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_INTR_1_SCP 17:17 /* RWIUF */ #define NV_CPWR_PMU_INTR_1_SCP_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_INTR_1_SCP_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_INTR_1_SCP_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_UART_TX 0x00000660 /* RW-4R */ #define NV_CPWR_PMU_UART_TX_DATA 7:0 /* RWIVF */ #define NV_CPWR_PMU_UART_TX_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_TX_PUSH 8:8 /* RWIVF */ #define NV_CPWR_PMU_UART_TX_PUSH_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_UART_TX_PUSH_NOT_DONE 0x00000001 /* -W--V */ #define NV_CPWR_PMU_UART_TX_PUSH_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_UART_RX 0x00000664 /* RW-4R */ #define NV_CPWR_PMU_UART_RX_DATA 7:0 /* R--VF */ #define NV_CPWR_PMU_UART_RX_POP 8:8 /* RWIVF */ #define NV_CPWR_PMU_UART_RX_POP_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_UART_RX_POP_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_UART_RX_POP_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_UART_CTL 0x00000668 /* RW-4R */ #define NV_CPWR_PMU_UART_CTL_CONNECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_NONE 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_I2C 0x00000003 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC4 0x00000004 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC5 0x00000005 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC6 0x00000006 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC7 0x00000007 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC8 0x00000008 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CONNECTION_DDC9 0x00000009 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CLIENT 4:4 /* RWIVF */ #define NV_CPWR_PMU_UART_CTL_CLIENT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_CTL_CLIENT_PMU_UCODE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CLIENT_FALCON_ICD 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CLKDIV 20:8 /* RWIUF */ #define NV_CPWR_PMU_UART_CTL_CLKDIV_HZ_115200 0x00000010 /* RWI-V */ #define NV_CPWR_PMU_UART_CTL_CLKDIV_HZ_57600 0x00000021 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CLKDIV_HZ_38400 0x00000032 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CLKDIV_HZ_19200 0x00000065 /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CLKDIV_HZ_9600 0x000000cb /* RW--V */ #define NV_CPWR_PMU_UART_CTL_CLKSRC 24:24 /* RWIVF */ #define NV_CPWR_PMU_UART_CTL_CLKSRC_PTIMER 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_CTL_CLKSRC_PWRCLK 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_THRESHOLD 0x0000066c /* RW-4R */ #define NV_CPWR_PMU_UART_THRESHOLD_VALUE 23:0 /* RWIVF */ #define NV_CPWR_PMU_UART_THRESHOLD_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_INTR 0x00000670 /* RW-4R */ #define NV_CPWR_PMU_UART_INTR_RX_READY 0:0 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_RX_READY_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_UART_INTR_RX_READY_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_UART_INTR_RX_READY_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_UART_INTR_TX_READY 4:4 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_TX_READY_NOT_PENDING 0x00000000 /* R---V */ #define NV_CPWR_PMU_UART_INTR_TX_READY_PENDING 0x00000001 /* R-I-V */ #define NV_CPWR_PMU_UART_INTR_TX_READY_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_UART_INTR_RX_OVERRUN 8:8 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_RX_OVERRUN_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_UART_INTR_RX_OVERRUN_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_UART_INTR_RX_OVERRUN_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_UART_INTR_RX_BAD_START_BIT 16:16 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_RX_BAD_START_BIT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_UART_INTR_RX_BAD_START_BIT_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_UART_INTR_RX_BAD_START_BIT_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_UART_INTR_RX_BAD_STOP_BIT 20:20 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_RX_BAD_STOP_BIT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_UART_INTR_RX_BAD_STOP_BIT_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_UART_INTR_RX_BAD_STOP_BIT_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_UART_INTR_EN 0x00000674 /* RW-4R */ #define NV_CPWR_PMU_UART_INTR_EN_RX_READY 0:0 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_EN_RX_READY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_INTR_EN_RX_READY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_INTR_EN_TX_READY 4:4 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_EN_TX_READY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_INTR_EN_TX_READY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_INTR_EN_RX_OVERRUN 8:8 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_EN_RX_OVERRUN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_INTR_EN_RX_OVERRUN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_INTR_EN_RX_BAD_START_BIT 16:16 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_EN_RX_BAD_START_BIT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_INTR_EN_RX_BAD_START_BIT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_INTR_EN_RX_BAD_STOP_BIT 20:20 /* RWIVF */ #define NV_CPWR_PMU_UART_INTR_EN_RX_BAD_STOP_BIT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_INTR_EN_RX_BAD_STOP_BIT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG 0x00000678 /* R--4R */ #define NV_CPWR_PMU_UART_DEBUG_VALUE 31:0 /* R--VF */ #define NV_CPWR_PMU_UART_DEBUG_CTL 0x0000067c /* RW-4R */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL 3:0 /* RWIVF */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_RX_BUF_31_0 0x00000001 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_RX_BUF_63_32 0x00000002 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_RX_BUF_79_64 0x00000003 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_TX_BUF_31_0 0x00000004 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_TX_BUF_63_32 0x00000005 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_TX_BUF_79_64 0x00000006 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_RX_BUF_ERR 0x00000007 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_UART_CTRL 0x00000008 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_TX_DAT 0x00000009 /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_FSM 0x0000000a /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_ICDC_STAT_CRTL 0x0000000b /* RW--V */ #define NV_CPWR_PMU_UART_DEBUG_CTL_SEL_ICDC_TIMER 0x0000000c /* RW--V */ #define NV_CPWR_PMU_BAR0_ADDR 0x000007a0 /* RW-4R */ #define NV_CPWR_PMU_BAR0_ADDR_VALUE 25:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_ADDR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_ADDR_BLOCKING 26:26 /* RWIUF */ #define NV_CPWR_PMU_BAR0_ADDR_BLOCKING_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_ADDR_BLOCKING_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_ADDR_TARGET 27:27 /* RWIUF */ #define NV_CPWR_PMU_BAR0_ADDR_TARGET_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_ADDR_TARGET_HOST 0x00000000 /* RW--V */ #define NV_CPWR_PMU_BAR0_ADDR_TARGET_FECS 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_DATA 0x000007a4 /* RW-4R */ #define NV_CPWR_PMU_BAR0_DATA_VALUE 31:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_DATA_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_CTL 0x000007ac /* RW-4R */ #define NV_CPWR_PMU_BAR0_CTL_CMD 1:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_CTL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_CTL_CMD_READ 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_CTL_CMD_WRITE 0x00000002 /* RW--V */ #define NV_CPWR_PMU_BAR0_CTL_CMD_RSVD 0x00000003 /* RW--V */ #define NV_CPWR_PMU_BAR0_CTL_WRBE 7:4 /* RWIUF */ #define NV_CPWR_PMU_BAR0_CTL_WRBE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_CTL_INCR_ADDR 8:8 /* RWIUF */ #define NV_CPWR_PMU_BAR0_CTL_INCR_ADDR_NO 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_CTL_INCR_ADDR_YES 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_CTL_STATUS 14:12 /* R-IUF */ #define NV_CPWR_PMU_BAR0_CTL_STATUS_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_CTL_STATUS_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_CTL_STATUS_TOUT 0x00000002 /* R---V */ #define NV_CPWR_PMU_BAR0_CTL_STATUS_DIS 0x00000003 /* R---V */ #define NV_CPWR_PMU_BAR0_CTL_STATUS_ERROR 0x00000004 /* R---V */ #define NV_CPWR_PMU_BAR0_CTL_TRIG 16:16 /* RWIUF */ #define NV_CPWR_PMU_BAR0_CTL_TRIG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_CTL_TRIG_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_BAR0_CTL_TRIG_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_CTL_BAR0_PRIV_LEVEL 21:20 /* R-IUF */ #define NV_CPWR_PMU_BAR0_CTL_BAR0_PRIV_LEVEL_0 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_CTL_BAR0_PRIV_LEVEL_1 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_CTL_BAR0_PRIV_LEVEL_2 0x00000002 /* R---V */ #define NV_CPWR_PMU_BAR0_TIMEOUT 0x000007a8 /* RW-4R */ #define NV_CPWR_PMU_BAR0_TIMEOUT_VALUE 30:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_TIMEOUT_VALUE_INIT 0x10000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_TIMEOUT_EN 31:31 /* RWIUF */ #define NV_CPWR_PMU_BAR0_TIMEOUT_EN_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS 0x000007b0 /* RW-4R */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_HOST 0:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_HOST_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_HOST_DETECTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_HOST_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_FECS 1:1 /* RWIUF */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_FECS_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_FECS_DETECTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_FECS_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_CMD_HWERR 2:2 /* RWIUF */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_CMD_HWERR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_CMD_HWERR_DETECTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_CMD_HWERR_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_ERROR_CMD 3:3 /* R-IUF */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_ERROR_CMD_READ 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_ERROR_CMD_WRITE 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_ERROR_ADDR 29:4 /* R-IUF */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_ERROR_ADDR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_HOSTERR 30:30 /* RWIVF */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_HOSTERR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_HOSTERR_DETECTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_HOSTERR_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_FECSERR 31:31 /* RWIVF */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_FECSERR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_FECSERR_DETECTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_ERROR_STATUS_FECSERR_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR 0x00000988 /* RW-4R */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA 7:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_REQ 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_RDAT_WAIT 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_HOLD 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_WAIT_ACK 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_SYNC_REQ 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_EXTRA_SYNC_RDAT_WAIT 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE 31:8 /* RWIUF */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_TIMEOUT 0x00badf10 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_DECODE 0x00badf11 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_RESET 0x00badf12 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_FLOORSWEEP 0x00badf13 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_STUCK_ACK 0x00badf14 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_0_EXPECTED_ACK 0x00badf15 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_FENCE_ERROR 0x00badf16 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_ORPHAN 0x00badf20 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_DEAD_RING 0x00badf30 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_TRAP 0x00badf40 /* R---V */ #define NV_CPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_CLIENT_ERR 0x00badf50 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR 0x00000990 /* RW-4R */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_EXTRA 7:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_EXTRA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_EXTRA_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE 31:8 /* RWIUF */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_CLEAR 0x00000001 /* -W--V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_TIMEOUT 0x00badf10 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_DECODE 0x00badf11 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_RESET 0x00badf12 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_FLOORSWEEP 0x00badf13 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_STUCK_ACK 0x00badf14 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_0_EXPECTED_ACK 0x00badf15 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_FENCE_ERROR 0x00badf16 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_ORPHAN 0x00badf20 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_DEAD_RING 0x00badf30 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_TRAP 0x00badf40 /* R---V */ #define NV_CPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_CLIENT_ERR 0x00badf50 /* R---V */ #define NV_CPWR_PMU_BAR0_EXT 0x0000098c /* R--4R */ #define NV_CPWR_PMU_BAR0_EXT_STATUS 1:0 /* R-IUF */ #define NV_CPWR_PMU_BAR0_EXT_STATUS_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_EXT_STATUS_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_EXT_STATUS_DIS 0x00000002 /* R---V */ #define NV_CPWR_PMU_BAR0_INTR 0x000007b4 /* RW-4R */ #define NV_CPWR_PMU_BAR0_INTR_HW_ERR 0:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_INTR_HW_ERR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_INTR_HW_ERR_DETECTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_INTR_HW_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_BAR0_INTEN 0x000007b8 /* RW-4R */ #define NV_CPWR_PMU_BAR0_INTEN_HW_ERR 0:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_INTEN_HW_ERR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_INTEN_HW_ERR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_INTEN_HW_ERR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_BAR0_EN 0x000007bc /* RW-4R */ #define NV_CPWR_PMU_BAR0_EN_CTL 0:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_EN_CTL_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_BAR0_EN_CTL_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_EN_CTL_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_BAR0_EN_AUTO_TRIGGER 1:1 /* RWIUF */ #define NV_CPWR_PMU_BAR0_EN_AUTO_TRIGGER_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_EN_AUTO_TRIGGER_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_CYA 0x00000980 /* RW-4R */ #define NV_CPWR_PMU_BAR0_CYA_BLOCKING_OVERRIDE 1:0 /* RWIUF */ #define NV_CPWR_PMU_BAR0_CYA_BLOCKING_OVERRIDE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_CYA_BLOCKING_OVERRIDE_BLOCK 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_CYA_BLOCKING_OVERRIDE_NONBLOCK 0x00000002 /* RW--V */ #define NV_CPWR_PMU_BAR0_CYA_TARGET_OVERRIDE 3:2 /* RWIUF */ #define NV_CPWR_PMU_BAR0_CYA_TARGET_OVERRIDE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_CYA_TARGET_OVERRIDE_HOST 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_CYA_TARGET_OVERRIDE_FECS 0x00000002 /* RW--V */ #define NV_CPWR_PMU_BAR0_CYA_LOCAL_ORDERING 4:4 /* RWIUF */ #define NV_CPWR_PMU_BAR0_CYA_LOCAL_ORDERING_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_BAR0_CYA_LOCAL_ORDERING_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_BAR0_DBG 0x00000984 /* R--4R */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE 3:0 /* R-IUF */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_NO_TRANSACTION 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_CSB2FECS 0x00000001 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_EXT2FECS 0x00000002 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_CSB2HOST 0x00000003 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_EXT2HOST 0x00000004 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_FECS_BUSY 0x00000005 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_HOST_BUSY 0x00000006 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_TIMEOUT 0x00000007 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_FSM_STATE_ERROR 0x00000008 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_BAR0_DISABLED 4:4 /* R-IUF */ #define NV_CPWR_PMU_BAR0_DBG_BAR0_DISABLED_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_BAR0_DBG_BAR0_DISABLED_NO 0x00000000 /* R---V */ #define NV_CPWR_PMU_BAR0_DBG_BAR0_DISABLED_YES 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_CTRL(i) (0x00000ad0+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_CTRL__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_CTRL__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PG_CTRL_ENG 0:0 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_ENG_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_ENG_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_ENG_TYPE 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_ENG_TYPE_PG 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_ENG_TYPE_LPWR 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_CFG_RDY 4:4 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_CFG_RDY_FALSE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_CFG_RDY_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_SOFT_RST 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_SOFT_RST_FALSE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_SOFT_RST_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_ENG 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_ENG_DONE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_ENG_START 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_REQSRC 7:7 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_REQSRC_RM 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_REQSRC_HOST 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_IDLE_MASK_VALUE 9:8 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_IDLE_MASK_VALUE_NEVER 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_IDLE_MASK_VALUE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_IDLE_MASK_VALUE_BUSY 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_IDLE_MASK_VALUE_ALWAYS 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_AUTO_WAKEUP 12:12 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_AUTO_WAKEUP_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_AUTO_WAKEUP_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_DONE 16:16 /* RWEVF */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_DONE_INVALID 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_CTRL_PGOFF_DONE_VALID 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_WAKEUP_INTERVAL(i) (0x000009c8+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_WAKEUP_INTERVAL__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_WAKEUP_INTERVAL__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PG_WAKEUP_INTERVAL_VAL 23:0 /* RWEVF */ #define NV_CPWR_PMU_PG_WAKEUP_INTERVAL_VAL_INIT 0x004c4b40 /* RWE-V */ #define NV_CPWR_PMU_PWRCLK_FREQ 0x00000b5c /* RW-4R */ #define NV_CPWR_PMU_PWRCLK_FREQ__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PWRCLK_FREQ_VAL 31:0 /* RWEVF */ #define NV_CPWR_PMU_PWRCLK_FREQ_VAL_INIT 0x0000021c /* RWE-V */ #define NV_CPWR_PMU_PG_CLAMP_DELAY(i) (0x00000af8+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_CLAMP_DELAY__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_CLAMP_DELAY_PWRDOWN_VAL 15:0 /* RWEVF */ #define NV_CPWR_PMU_PG_CLAMP_DELAY_PWRDOWN_VAL_INIT 0x000000ff /* RWE-V */ #define NV_CPWR_PMU_PG_CLAMP_DELAY_PWRUP_VAL 31:16 /* RWEVF */ #define NV_CPWR_PMU_PG_CLAMP_DELAY_PWRUP_VAL_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_MISC 0x000004f8 /* RW-4R */ #define NV_CPWR_PMU_PG_MISC__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PG_MISC_IDLE_SNAP_READ 0:0 /* RWEVF */ #define NV_CPWR_PMU_PG_MISC_IDLE_SNAP_READ_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_MISC_IDLE_SNAP_READ_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_MISC_IDLE_SNAP_IDX 3:1 /* RWEVF */ #define NV_CPWR_PMU_PG_MISC_IDLE_SNAP_IDX_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_MISC_IDLE_FLIP_STATUS_IDX 6:4 /* RWEVF */ #define NV_CPWR_PMU_PG_MISC_IDLE_FLIP_STATUS_IDX_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_MISC_SOFT_RST_DBGEN 28:28 /* RWEVF */ #define NV_CPWR_PMU_PG_MISC_SOFT_RST_DBGEN_FALSE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_MISC_SOFT_RST_DBGEN_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_MISC_SOFT_RST_DBG 31:31 /* RWEVF */ #define NV_CPWR_PMU_PG_MISC_SOFT_RST_DBG_FALSE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_MISC_SOFT_RST_DBG_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS 0x0000078c /* RW-4R */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_VALUE_INIT 0xffffffff /* RWE-V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_FE 0:0 /* RWXVF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_FE_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_FE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_SYS 1:1 /* RWXVF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_SYS_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_SYS_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_GPC 2:2 /* RWXVF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_GPC_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_GPC_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE 2:1 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_SEC 4:4 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_SEC_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_SEC_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVDEC 5:5 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVDEC_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVDEC_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_6 6:6 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_6_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_NOREQ 7:7 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_NOREQ_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_NOREQ_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_PA 8:8 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_PA_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_PA_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_ALL 9:9 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_ALL_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_ALL_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO 10:10 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_ASR 11:11 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_ASR_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_FB_ASR_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_LTC_IDLE 12:12 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_LTC_IDLE_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_LTC_IDLE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_AZA_IDLE 13:13 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_AZA_IDLE_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_AZA_IDLE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED0 14:14 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED0_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED0_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_15 15:15 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_15_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_EX_ISO 16:16 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_EX_ISO_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_EX_ISO_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVENC0 17:17 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVENC0_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVENC0_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XBAR_IDLE 18:18 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XBAR_IDLE_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XBAR_IDLE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_0 19:19 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_0_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_0_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_1 20:20 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_1_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_1_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_2 21:21 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_2_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_CE_2_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_22 22:22 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_22_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L0S 23:23 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L0S_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L0S_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L1 24:24 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L1_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L1_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVE_XCLK 25:25 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVE_XCLK_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVE_XCLK_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_COMMON 26:26 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_COMMON_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_COMMON_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_DEEP 27:27 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_DEEP_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_DEEP_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XP 28:28 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XP_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XP_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XVE 29:29 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XVE_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XVE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP 29:26 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED1 30:30 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED1_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED1_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED2 31:31 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED2_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED2_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1 0x00000790 /* RW-4R */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_VALUE_INIT 0xffffffff /* RWE-V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HSHUB_MMU 0:0 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HSHUB_MMU_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HSHUB_MMU_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_GSP 1:1 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_GSP_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_GSP_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_ALL 2:2 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_ALL_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_ALL_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_NONPMU_INTERFACE 3:3 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_NONPMU_INTERFACE_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_NONPMU_INTERFACE_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_MS_MMU 4:4 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_MS_MMU_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_MS_MMU_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED3 5:5 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED3_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED3_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED4 6:6 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED4_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED4_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED5 7:7 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED5_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED5_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED6 8:8 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED6_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED6_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED7 9:9 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED7_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED7_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED8 10:10 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED8_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED8_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_11 11:11 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_11_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_12 12:12 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_12_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_13 13:13 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_13_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_14 14:14 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_14_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_15 15:15 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_15_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_16 16:16 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_16_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_17 17:17 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_17_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_18 18:18 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_18_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_PMU2FB_TRAFFIC 19:19 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_PMU2FB_TRAFFIC_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_PMU2FB_TRAFFIC_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_3 20:20 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_3_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_3_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_4 21:21 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_4_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_4_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_22 22:22 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_22_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_23 23:23 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_23_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_24 24:24 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_24_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_25 25:25 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_25_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_26 26:26 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_26_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SEC_FBIF 27:27 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SEC_FBIF_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SEC_FBIF_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_28 28:28 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_28_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_29 29:29 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_29_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW0 30:30 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW0_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW0_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW1 31:31 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW1_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW1_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2 0x00000794 /* RW-4R */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_VALUE_INIT 0xffffffff /* RWE-V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_0 0:0 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_0_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_1 1:1 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_1_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_2 2:2 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_2_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_3 3:3 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_3_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_4 4:4 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_4_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_5 5:5 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_5_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_FB 6:6 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_FB_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_FB_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_7 7:7 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_7_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_NVDEC1 8:8 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_NVDEC1_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_NVDEC1_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_9 9:9 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_9_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_10 10:10 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_10_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_11 11:11 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_11_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_12 12:12 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_12_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_13 13:13 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_13_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_GR 14:14 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_GR_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_GR_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_MS 15:15 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_MS_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_MS_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_GR 16:16 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_GR_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_GR_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_MS 17:17 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_MS_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_MS_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_18 18:18 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_18_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_19 19:19 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_19_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_20 20:20 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_20_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_21 21:21 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_21_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_22 22:22 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_22_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_23 23:23 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_23_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_24 24:24 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_24_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_25 25:25 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_25_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_26 26:26 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_26_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_27 27:27 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_27_TIEHIGH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_OFA 28:28 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_OFA_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_OFA_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_MS 29:29 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_MS_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_MS_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_GR 30:30 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_GR_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_GR_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SW2 31:31 /* RW-VF */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SW2_BUSY 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_IDLE_FLIP_STATUS_2_SW2_IDLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_IDLEFILTH(i) (0x000006c0+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_IDLEFILTH__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_IDLEFILTH__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_IDLEFILTH_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_PG_IDLEFILTH_VALUE_INIT 0x00001000 /* RWE-V */ #define NV_CPWR_PMU_PG_PPUIDLEFILTH(i) (0x000006e8+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_PPUIDLEFILTH__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_PPUIDLEFILTH__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_PPUIDLEFILTH_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_PG_PPUIDLEFILTH_VALUE_INIT 0x01000000 /* RWE-V */ #define NV_CPWR_PMU_PG_IDLE_CNT(i) (0x00000710+(i)*4) /* R--4A */ #define NV_CPWR_PMU_PG_IDLE_CNT__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_IDLE_CNT_VALUE 31:0 /* R-EVF */ #define NV_CPWR_PMU_PG_IDLE_CNT_VALUE_INIT 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_SWCTRL(i) (0x00000738+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_SWCTRL__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_SWCTRL__PRIV_LEVEL_MASK 0x00000a78 /* */ #define NV_CPWR_PMU_PG_SWCTRL_PWR 0:0 /* RWEVF */ #define NV_CPWR_PMU_PG_SWCTRL_PWR_OFF 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_SWCTRL_PWR_ON 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_OVERWR 3:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SWCTRL_OVERWR_POWERON_ENGIDLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_SWCTRL_OVERWR_POWERINGDOWN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_OVERWR_ACTIVE 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_OVERWR_POWERON_ENGBUSY 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_OVERWR_POWERINGUP 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_OVERWR_PWROFF 0x00000004 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_OVERWR_PWROFF_ACTIVE 0x00000006 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_CLAMPSWITCH 4:4 /* RWEVF */ #define NV_CPWR_PMU_PG_SWCTRL_CLAMPSWITCH_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_SWCTRL_CLAMPSWITCH_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_CLAMPSWITCH_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_CLAMP 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SWCTRL_CLAMP_OFF 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_SWCTRL_CLAMP_ON 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_ENABLE 31:31 /* RWEVF */ #define NV_CPWR_PMU_PG_SWCTRL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_SWCTRL_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_SWCTRL_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN(i) (0x00000760+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_INTREN__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_INTREN__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PG_INTREN_PG_ON 0:0 /* RWEVF */ #define NV_CPWR_PMU_PG_INTREN_PG_ON_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTREN_PG_ON_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_PG_ON_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_PG_ON_DONE 4:4 /* RWEVF */ #define NV_CPWR_PMU_PG_INTREN_PG_ON_DONE_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTREN_PG_ON_DONE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_PG_ON_DONE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_CTX_RESTORE 8:8 /* RWEVF */ #define NV_CPWR_PMU_PG_INTREN_CTX_RESTORE_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTREN_CTX_RESTORE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_CTX_RESTORE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_CFG_ERR 12:12 /* RWEVF */ #define NV_CPWR_PMU_PG_INTREN_CFG_ERR_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTREN_CFG_ERR_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_CFG_ERR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_ENG_RST 16:16 /* RWEVF */ #define NV_CPWR_PMU_PG_INTREN_ENG_RST_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTREN_ENG_RST_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_ENG_RST_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_IDLE_SNAP 20:20 /* RWEVF */ #define NV_CPWR_PMU_PG_INTREN_IDLE_SNAP_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTREN_IDLE_SNAP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_IDLE_SNAP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_WAKEUP 20:20 /* RWEVF */ #define NV_CPWR_PMU_PG_INTREN_WAKEUP_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTREN_WAKEUP_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_INTREN_WAKEUP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_INTRSTAT(i) (0x00000a80+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_INTRSTAT__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_INTRSTAT__PRIV_LEVEL_MASK 0x000007fc /* */ #define NV_CPWR_PMU_PG_INTRSTAT_INTR 0:0 /* RWEVF */ #define NV_CPWR_PMU_PG_INTRSTAT_INTR_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTRSTAT_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PG_INTRSTAT_INTR_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_INTR_RESET 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON 4:4 /* RWEVF */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_RESET 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_DONE 8:8 /* RWEVF */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_DONE_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_DONE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_DONE_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_PG_ON_DONE_RESET 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_CTX_RESTORE 12:12 /* RWEVF */ #define NV_CPWR_PMU_PG_INTRSTAT_CTX_RESTORE_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTRSTAT_CTX_RESTORE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PG_INTRSTAT_CTX_RESTORE_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_CTX_RESTORE_RESET 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_CFG_ERR 16:16 /* RWEVF */ #define NV_CPWR_PMU_PG_INTRSTAT_CFG_ERR_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTRSTAT_CFG_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PG_INTRSTAT_CFG_ERR_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_CFG_ERR_RESET 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_ENG_RST 20:20 /* RWEVF */ #define NV_CPWR_PMU_PG_INTRSTAT_ENG_RST_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTRSTAT_ENG_RST_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PG_INTRSTAT_ENG_RST_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_ENG_RST_RESET 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_IDLE_SNAP 24:24 /* RWEVF */ #define NV_CPWR_PMU_PG_INTRSTAT_IDLE_SNAP_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTRSTAT_IDLE_SNAP_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PG_INTRSTAT_IDLE_SNAP_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_IDLE_SNAP_RESET 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_WAKEUP 24:24 /* RWEVF */ #define NV_CPWR_PMU_PG_INTRSTAT_WAKEUP_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_INTRSTAT_WAKEUP_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_PG_INTRSTAT_WAKEUP_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_INTRSTAT_WAKEUP_RESET 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_STAT(i) (0x00000aa8+(i)*4) /* R--4A */ #define NV_CPWR_PMU_PG_STAT__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_STAT_EST 2:0 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_EST_IDLE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_EST_POWERON_ENGIDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_STAT_EST_POWERINGDOWN 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_EST_ACTIVE 0x00000002 /* R---V */ #define NV_CPWR_PMU_PG_STAT_EST_POWERON_ENGBUSY 0x00000002 /* R---V */ #define NV_CPWR_PMU_PG_STAT_EST_POWERINGUP 0x00000003 /* R---V */ #define NV_CPWR_PMU_PG_STAT_EST_PWROFF 0x00000004 /* R---V */ #define NV_CPWR_PMU_PG_STAT_EST_PWROFF_ACTIVE 0x00000006 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST 6:3 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_PGST_IDLE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_PGST_PG_ON 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_CLAMP_ON 0x00000002 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_CLAMP_ON_DELAY 0x00000003 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_PWROFF_SEQ 0x00000004 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_PG_ON_DONE 0x00000005 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_PWRON_SEQ 0x00000006 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_ENG_RST 0x00000007 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_CLAMP_OFF 0x00000008 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_CLAMP_OFF_DELAY 0x00000009 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_DAT_RESTORE 0x0000000a /* R---V */ #define NV_CPWR_PMU_PG_STAT_PGST_PG_OFF 0x0000000b /* R---V */ #define NV_CPWR_PMU_PG_STAT_AUTO_WAKEUP 8:8 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_AUTO_WAKEUP_DEASSERTED 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_AUTO_WAKEUP_ASSERTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_SW_CLIENT 9:9 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_SW_CLIENT_DEASSERTED 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_SW_CLIENT_ASSERTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED_PWR_OFF 10:10 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED_PWR_OFF_DEASSERTED 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED_PWR_OFF_ASSERTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_THRESHOLD_ERR 15:15 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_THRESHOLD_ERR_CLEAR 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_THRESHOLD_ERR_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_RUNTIME_CFG_ERR 16:16 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_RUNTIME_CFG_ERR_CLEAR 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_RUNTIME_CFG_ERR_SET 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_PPU_IDLE_PERIOD 19:19 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_PPU_IDLE_PERIOD_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_PPU_IDLE_PERIOD_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED 20:20 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED_DEASSERTED 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED_ASSERTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED_NON_PMU 21:21 /* R-EVF */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED_NON_PMU_DEASSERTED 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_STAT_IDLE_FLIPPED_NON_PMU_ASSERTED 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_DBG(i) (0x00000860+(i)*4) /* R--4A */ #define NV_CPWR_PMU_PG_DBG__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_DBG_VALUE 31:0 /* R--VF */ #define NV_CPWR_PMU_PG_DBG_IDX(i) (0x00000b64+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_DBG_IDX__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_DBG_IDX_PT 7:0 /* RWEVF */ #define NV_CPWR_PMU_PG_DBG_IDX_PT_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_DBG_IDX_PT_IDLE_CNT 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_DBG_IDX_PT_CYAEN_BYPASS_CLAMP 0x00000010 /* RW--V */ #define NV_CPWR_PMU_PG_DBG_IDX_PT_STATUS 0x00000020 /* RW--V */ #define NV_CPWR_PMU_PG_DBG_IDX_PT_CFGERR 0x00000030 /* RW--V */ #define NV_CPWR_PMU_PG_DBG_IDX_PT_PT_DBG_RESET 0x000000ff /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT(i) (0x00000bac+(i)*4) /* R--4A */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG0_OFF 0:0 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG0_OFF_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG0_OFF_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG1_OFF 1:1 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG1_OFF_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG1_OFF_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG2_OFF 2:2 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG2_OFF_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG2_OFF_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG3_OFF 3:3 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG3_OFF_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG3_OFF_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG4_OFF 4:4 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG4_OFF_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_ENG4_OFF_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_DEEPL1_ENGAGED 5:5 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_DEEPL1_ENGAGED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_DEEPL1_ENGAGED_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_L1_1_ENGAGED 6:6 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_L1_1_ENGAGED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_L1_1_ENGAGED_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_L1_2_ENGAGED 7:7 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_L1_2_ENGAGED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_L1_2_ENGAGED_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_MSPG_OK 8:8 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_MSPG_OK_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_MSPG_OK_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_TS_PD_READY 10:10 /* R-EVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_TS_PD_READY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_STAT_TS_PD_READY_FALSE 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK(i) (0x00000bc0+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_AND 0:0 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_OR 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP 4:2 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_NONE 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_AND 8:8 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_OR 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP 12:10 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_NONE 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_AND 16:16 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_OR 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP 20:18 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_NONE 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_AND 24:24 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_OR 25:25 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP 28:26 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_NONE 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_AND(i) (8*(i)):(8*(i)) /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_AND__SIZE_1 4 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_OR(i) (1+8*(i)):(1+8*(i)) /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_OR__SIZE_1 4 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_AND_DISABLE 0 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_AND_ENABLE 1 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_OR_DISABLE 0 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_OR_ENABLE 1 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP(i) (4+8*(i)):(2+8*(i)) /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP__SIZE_1 4 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP_0 0 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP_1 1 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP_2 2 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP_3 3 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1(i) (0x00000bd4+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_AND 0:0 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_OR 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP 4:2 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_INIT 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_AND 8:8 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_OR 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP 12:10 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_INIT 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_AND 16:16 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_OR 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP 20:18 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_INIT 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_AND 24:24 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_OR 25:25 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP 28:26 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_INIT 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_AND 0:0 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_OR 1:1 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_AND_DISABLE 0 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_AND_ENABLE 1 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_OR_DISABLE 0 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_OR_ENABLE 1 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP 4:2 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP_0 0 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP_1 1 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP_2 2 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP_3 3 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2(i) (0x00000be8+(i)*4) /* RW-4A */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_AND 0:0 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_OR 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP 4:2 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_INIT 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_AND 16:16 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_AND_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_AND_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_OR 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_OR_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_OR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP 20:18 /* RWEVF */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_INIT 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0 0x00000508 /* RW-4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_0__PRIV_LEVEL_MASK 0x00000b38 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_ST 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_SET 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_CLR 2:2 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_ST 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_SET 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_CLR 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_ST 8:8 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_SET 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_CLR 10:10 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_ST 12:12 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_SET 13:13 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_CLR 14:14 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_ST 16:16 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_SET 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_CLR 18:18 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1 0x0000050c /* RW-4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_1__PRIV_LEVEL_MASK 0x00000b3c /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_ST 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_SET 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_CLR 2:2 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_ST 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_SET 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_CLR 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_ST 8:8 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_SET 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_CLR 10:10 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_ST 12:12 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_SET 13:13 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_CLR 14:14 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_ST 16:16 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_SET 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_CLR 18:18 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2 0x00000510 /* RW-4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_2__PRIV_LEVEL_MASK 0x00000b40 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_ST 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_SET 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_CLR 2:2 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_ST 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_SET 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_CLR 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_ST 8:8 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_SET 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_CLR 10:10 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_ST 12:12 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_SET 13:13 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_CLR 14:14 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_ST 16:16 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_SET 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_CLR 18:18 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3 0x00000514 /* RW-4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_3__PRIV_LEVEL_MASK 0x00000b44 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_ST 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_SET 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_CLR 2:2 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_ST 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_SET 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_CLR 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_ST 8:8 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_SET 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_CLR 10:10 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_ST 12:12 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_SET 13:13 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_CLR 14:14 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_ST 16:16 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_SET 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_CLR 18:18 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4 0x00000518 /* RW-4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_4__PRIV_LEVEL_MASK 0x00000b48 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_ST 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_SET 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_CLR 2:2 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_ST 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_SET 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_CLR 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_ST 8:8 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_SET 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_CLR 10:10 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_ST 12:12 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_SET 13:13 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_CLR 14:14 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_ST 16:16 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_SET 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_CLR 18:18 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5 0x0000051c /* RW-4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_5__PRIV_LEVEL_MASK 0x00000b4c /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_ST 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_SET 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_CLR 2:2 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_ST 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_SET 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_CLR 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_ST 8:8 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_SET 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_CLR 10:10 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_ST 12:12 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_SET 13:13 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_CLR 14:14 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_ST 16:16 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_SET 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_CLR 18:18 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6 0x00000520 /* RW-4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_6__PRIV_LEVEL_MASK 0x00000b50 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_ST 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_SET 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_CLR 2:2 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_ST 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_SET 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_CLR 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_ST 8:8 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_SET 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_CLR 10:10 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_ST 12:12 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_SET 13:13 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_CLR 14:14 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_ST 16:16 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_SET 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_CLR 18:18 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7 0x00000524 /* RW-4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_7__PRIV_LEVEL_MASK 0x00000b54 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_ST 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_SET 1:1 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_CLR 2:2 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_ST 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_SET 5:5 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_CLR 6:6 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_ST 8:8 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_SET 9:9 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_CLR 10:10 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_ST 12:12 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_SET 13:13 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_CLR 14:14 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_ST 16:16 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_ST_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_ST_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_SET 17:17 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_CLR 18:18 /* RWEVF */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */ #define NV_CPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS 0x00000a7c /* R--4R */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG0 0:0 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG0_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG0_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG1 1:1 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG1_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG1_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG2 2:2 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG2_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG2_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG3 3:3 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG3_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG3_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG4 4:4 /* R--VF */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG4_BUSY 0x00000001 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ENG4_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ST_ENG(i) (i):(i) /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ST_ENG__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ST_ENG_BUSY 1 /* */ #define NV_CPWR_PMU_PG_SW_CLIENT_STATUS_ST_ENG_IDLE 0 /* */ #define NV_CPWR_PMU_PG_IDLE_MASK(i) (0x00000f00+(i)*12) /* RW-4A */ #define NV_CPWR_PMU_PG_IDLE_MASK__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_IDLE_MASK__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_IDLE_MASK_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_PG_IDLE_MASK_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_IDLE_MASK_1(i) (0x00000f04+(i)*12) /* RW-4A */ #define NV_CPWR_PMU_PG_IDLE_MASK_1__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_IDLE_MASK_1__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_IDLE_MASK_1_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_PG_IDLE_MASK_1_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_IDLE_MASK_2(i) (0x00000f08+(i)*12) /* RW-4A */ #define NV_CPWR_PMU_PG_IDLE_MASK_2__SIZE_1 5 /* */ #define NV_CPWR_PMU_PG_IDLE_MASK_2__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_IDLE_MASK_2_VALUE 31:0 /* RWEVF */ #define NV_CPWR_PMU_PG_IDLE_MASK_2_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK 0x0000079c /* RW-4R */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK__PRIV_LEVEL_MASK 0x000007dc /* */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0 2:0 /* RWEVF */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG0 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG4 0x00000004 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1 6:4 /* RWEVF */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG1 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG4 0x00000004 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2 10:8 /* RWEVF */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG2 0x00000002 /* RWE-V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG4 0x00000004 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3 14:12 /* RWEVF */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG3 0x00000003 /* RWE-V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG4 0x00000004 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4 18:16 /* RWEVF */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG0 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG1 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG2 0x00000002 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG3 0x00000003 /* RW--V */ #define NV_CPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG4 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK 0x00000974 /* RW-4R */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_gpc_pri_err" /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_PMU_GR_PRI_ERROR 0x00000658 /* RW-4R */ #define NV_CPWR_PMU_GR_PRI_ERROR__PRIV_LEVEL_MASK 0x00000974 /* */ #define NV_CPWR_PMU_GR_PRI_ERROR_CONFIG 0:0 /* RWEVF */ #define NV_CPWR_PMU_GR_PRI_ERROR_CONFIG_DISABLE 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_GR_PRI_ERROR_CONFIG_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_RAM_TARGET 0x00000b8c /* RW-4R */ #define NV_CPWR_PMU_RAM_TARGET__PRIV_LEVEL_MASK 0x00000788 /* */ #define NV_CPWR_PMU_RAM_TARGET_SEQ(i) (4*(i)+3):(4*(i)) /* */ #define NV_CPWR_PMU_RAM_TARGET_SEQ__SIZE_1 2 /* */ #define NV_CPWR_PMU_RAM_TARGET_SEQ_POWER_ON 0x00000000 /* */ #define NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE0 0x00000001 /* */ #define NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE1 0x00000002 /* */ #define NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE2 0x00000004 /* */ #define NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE3 0x00000008 /* */ #define NV_CPWR_PMU_RAM_TARGET_GR 3:0 /* RWEVF */ #define NV_CPWR_PMU_RAM_TARGET_GR_POWER_ON 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_RAM_TARGET_GR_PROFILE0 0x00000001 /* RW--V */ #define NV_CPWR_PMU_RAM_TARGET_GR_PROFILE1 0x00000002 /* RW--V */ #define NV_CPWR_PMU_RAM_TARGET_GR_PROFILE2 0x00000004 /* RW--V */ #define NV_CPWR_PMU_RAM_TARGET_GR_PROFILE3 0x00000008 /* RW--V */ #define NV_CPWR_PMU_RAM_TARGET_MS 7:4 /* RWEVF */ #define NV_CPWR_PMU_RAM_TARGET_MS_POWER_ON 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_RAM_TARGET_MS_PROFILE0 0x00000001 /* RW--V */ #define NV_CPWR_PMU_RAM_TARGET_MS_PROFILE1 0x00000002 /* RW--V */ #define NV_CPWR_PMU_RAM_TARGET_MS_PROFILE2 0x00000004 /* RW--V */ #define NV_CPWR_PMU_RAM_TARGET_MS_PROFILE3 0x00000008 /* RW--V */ #define NV_CPWR_PMU_RAM_STATUS 0x00000b90 /* R--4R */ #define NV_CPWR_PMU_RAM_STATUS__PRIV_LEVEL_MASK 0x00000788 /* */ #define NV_CPWR_PMU_RAM_STATUS_FSM_SEQ(i) (8*(i)+1):(8*(i)) /* */ #define NV_CPWR_PMU_RAM_STATUS_FSM_SEQ__SIZE_1 2 /* */ #define NV_CPWR_PMU_RAM_STATUS_FSM_SEQ_POWER_ON 0 /* */ #define NV_CPWR_PMU_RAM_STATUS_FSM_SEQ_LOW_POWER_ENTERING 1 /* */ #define NV_CPWR_PMU_RAM_STATUS_FSM_SEQ_LOW_POWER 2 /* */ #define NV_CPWR_PMU_RAM_STATUS_FSM_SEQ_LOW_POWER_EXITING 3 /* */ #define NV_CPWR_PMU_RAM_STATUS_PROFILE_SEQ(i) (8*(i)+7):(8*(i)+4) /* */ #define NV_CPWR_PMU_RAM_STATUS_PROFILE_SEQ__SIZE_1 2 /* */ #define NV_CPWR_PMU_RAM_STATUS_PROFILE_SEQ_POWER_ON 0x00000000 /* */ #define NV_CPWR_PMU_RAM_STATUS_PROFILE_SEQ_PROFILE0 0x00000001 /* */ #define NV_CPWR_PMU_RAM_STATUS_PROFILE_SEQ_PROFILE1 0x00000002 /* */ #define NV_CPWR_PMU_RAM_STATUS_PROFILE_SEQ_PROFILE2 0x00000004 /* */ #define NV_CPWR_PMU_RAM_STATUS_PROFILE_SEQ_PROFILE3 0x00000008 /* */ #define NV_CPWR_PMU_RAM_STATUS_GR_FSM 1:0 /* R-EVF */ #define NV_CPWR_PMU_RAM_STATUS_GR_FSM_POWER_ON 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_RAM_STATUS_GR_FSM_LOW_POWER_ENTERING 0x00000001 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_GR_FSM_LOW_POWER 0x00000002 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_GR_FSM_LOW_POWER_EXITING 0x00000003 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_GR_PROFILE 7:4 /* R-EVF */ #define NV_CPWR_PMU_RAM_STATUS_GR_PROFILE_POWER_ON 0x00000000 /* R-E-V */ #define NV_CPWR_PMU_RAM_STATUS_GR_PROFILE_PROFILE0 0x00000001 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_GR_PROFILE_PROFILE1 0x00000002 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_GR_PROFILE_PROFILE2 0x00000004 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_GR_PROFILE_PROFILE3 0x00000008 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_FSM 9:8 /* R--VF */ #define NV_CPWR_PMU_RAM_STATUS_MS_FSM_POWER_ON 0x00000000 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_FSM_LOW_POWER_ENTERING 0x00000001 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_FSM_LOW_POWER 0x00000002 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_FSM_LOW_POWER_EXITING 0x00000003 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_PROFILE 15:12 /* R--VF */ #define NV_CPWR_PMU_RAM_STATUS_MS_PROFILE_POWER_ON 0x00000000 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_PROFILE_PROFILE0 0x00000001 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_PROFILE_PROFILE1 0x00000002 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_PROFILE_PROFILE2 0x00000004 /* R---V */ #define NV_CPWR_PMU_RAM_STATUS_MS_PROFILE_PROFILE3 0x00000008 /* R---V */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG 0x00000b98 /* RW-4R */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK 0x00000b80 /* */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG_ZONE_DELAY 3:0 /* RWEVF */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT 0x00000003 /* RWE-V */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG_FAST_MODE 4:4 /* RWEVF */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG_FAST_MODE_EN 0x00000001 /* RW--V */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG_FAST_MODE_DIS 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG_RET_EN_DELAY 13:8 /* RWEVF */ #define NV_CPWR_PMU_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT 0x00000003 /* RWE-V */ #define NV_CPWR_PMU_GROUP_TOP_ORDER 0x00000b9c /* RW-4R */ #define NV_CPWR_PMU_GROUP_TOP_ORDER__PRIV_LEVEL_MASK 0x00000b80 /* */ #define NV_CPWR_PMU_GROUP_TOP_ORDER_GR_RAM 13:8 /* RWEVF */ #define NV_CPWR_PMU_GROUP_TOP_ORDER_GR_RAM_INIT 0x0000003f /* RWE-V */ #define NV_CPWR_PMU_GROUP_TOP_ORDER_MS_RAM 21:16 /* RWEVF */ #define NV_CPWR_PMU_GROUP_TOP_ORDER_MS_RAM_INIT 0x00000035 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX 0x00000ba0 /* RW-4R */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x00000b80 /* */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX 0:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR 8:8 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION 0x00000ba4 /* RW-4R */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX_OFFSET (0x00000BA0-0x00000BA4) /* */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK 0x00000b80 /* */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ORDER 5:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT 0x0000001f /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT 0x00000003 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX 0x00000528 /* RW-4R */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x00000788 /* */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX 0:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR 8:8 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR 9:9 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1 0x0000052c /* RW-4R */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX_OFFSET (0x00000528-0x0000052C) /* */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK 0x00000788 /* */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0 1:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG 0x00000002 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1 3:2 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG 0x00000002 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2 5:4 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG 0x00000002 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3 7:6 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG 0x00000002 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX 0x00001d40 /* RW-4R */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x00000b80 /* */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX 5:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX 0x00000020 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR 8:8 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION 0x00001d44 /* RW-4R */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX_OFFSET (0x00001D40-0x00001D44) /* */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK 0x00000b80 /* */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ORDER 5:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT 0x00000010 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT 0x0000000e /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT 0x00000003 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT 0x0000000f /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT 0x00000017 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT 0x0000001a /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT 0x00000020 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT 0x00000014 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT 0x0000001e /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT 0x00000015 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT 0x00000016 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT 0x00000021 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT 0x0000001f /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT 0x00000002 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT 0x00000032 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_18_ORDER_INIT 0x00000033 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_19_ORDER_INIT 0x00000034 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_20_ORDER_INIT 0x00000018 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_21_ORDER_INIT 0x0000000d /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_22_ORDER_INIT 0x00000006 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_23_ORDER_INIT 0x00000008 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_24_ORDER_INIT 0x0000001d /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_25_ORDER_INIT 0x00000019 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_26_ORDER_INIT 0x0000000c /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_27_ORDER_INIT 0x00000007 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_28_ORDER_INIT 0x00000009 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_29_ORDER_INIT 0x0000001c /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_30_ORDER_INIT 0x00000013 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_31_ORDER_INIT 0x00000035 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_32_ORDER_INIT 0x0000000b /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX 0x00000530 /* RW-4R */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x00000788 /* */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX 5:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX 0x00000020 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR 8:8 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR 9:9 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1 0x00000534 /* RW-4R */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX_OFFSET (0x00000530-0x00000534) /* */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK 0x00000788 /* */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0 1:0 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG 0x00000002 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1 3:2 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON 0x00000000 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG 0x00000002 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2 5:4 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG 0x00000002 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3 7:6 /* RWEVF */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG 0x00000001 /* RW--V */ #define NV_CPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG 0x00000002 /* RW--V */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE 0x00001d50 /* RW-4R */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK 0x00000b80 /* */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX 2:0 /* RWEVF */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT 0x00000000 /* RWE-V */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX 6:4 /* RWEVF */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT 0x00000001 /* RWE-V */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX 10:8 /* RWEVF */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT 0x00000002 /* RWE-V */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX 14:12 /* RWEVF */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT 0x00000003 /* RWE-V */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX 18:16 /* RWEVF */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT 0x00000004 /* RWE-V */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX 22:20 /* RWEVF */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT 0x00000005 /* RWE-V */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX 26:24 /* RWEVF */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT 0x00000006 /* RWE-V */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX 30:28 /* RWEVF */ #define NV_CPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT 0x00000007 /* RWE-V */ #define NV_CPWR_PMU_PRI_PWR_CG 0x00000a70 /* RWI4R */ #define NV_CPWR_PMU_PRI_PWR_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ #define NV_CPWR_PMU_PRI_PWR_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_PRI_PWR_CG_IDLE_CG_DLY_CNT__PROD 0x00000005 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG_IDLE_CG_EN 6:6 /* RWIVF */ #define NV_CPWR_PMU_PRI_PWR_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_PRI_PWR_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG_STATE_CG_EN 7:7 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_STALL_CG_EN 14:14 /* RWIVF */ #define NV_CPWR_PMU_PRI_PWR_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_PRI_PWR_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */ #define NV_CPWR_PMU_PRI_PWR_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_PRI_PWR_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_CNT 23:20 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_EN 28:28 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_PAUSE_CG_EN 30:30 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_HALT_CG_EN 31:31 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_CPWR_PMU_PRI_PWR_CG1 0x00000a74 /* RWI4R */ #define NV_CPWR_PMU_PRI_PWR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */ #define NV_CPWR_PMU_PRI_PWR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_PRI_PWR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG1_SLCG 14:1 /* RWIVF */ #define NV_CPWR_PMU_PRI_PWR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_PRI_PWR_CG1_SLCG_DISABLED 0x00003fff /* RWI-V */ #define NV_CPWR_PMU_PRI_PWR_CG1_SLCG__PROD 0x00003225 /* RW--V */ #define NV_CPWR_THERM 0x20fff:0x20000 #define NV_CPWR_THERM_CLK_COUNT 4 /* */ #define NV_CPWR_THERM_PHYS_CLK_COUNT 11 /* */ #define NV_CPWR_THERM_CLK_GPCCLK 0 /* */ #define NV_CPWR_THERM_CLK_SYSCLK 1 /* */ #define NV_CPWR_THERM_CLK_LEGCLK 2 /* */ #define NV_CPWR_THERM_CLK_LTCCLK 3 /* */ #define NV_CPWR_THERM_CLKT_GPCCLK_REM 3 /* */ #define NV_CPWR_THERM_CLKT_GPCCLK_LOC_0 4 /* */ #define NV_CPWR_THERM_CLKT_GPCCLK_LOC_1 5 /* */ #define NV_CPWR_THERM_CLKT_GPCCLK_LOC_2 6 /* */ #define NV_CPWR_THERM_CLKT_GPCCLK_LOC_3 7 /* */ #define NV_CPWR_THERM_CLKT_GPCCLK_LOC_4 8 /* */ #define NV_CPWR_THERM_CLKT_GPCCLK_LOC_5 9 /* */ #define NV_CPWR_THERM_CLKT_GPCCLK_LOC_6 10 /* */ #define NV_CPWR_THERM_CLKT_SYSCLK 0 /* */ #define NV_CPWR_THERM_CLKT_LEGCLK 1 /* */ #define NV_CPWR_THERM_CLKT_LTCCLK 2 /* */ #define NV_CPWR_THERM_BA_WEIGHT_BITS_EXTEND 8 /* */ #define NV_CPWR_THERM_DIV_BY1 0x00000000 /* */ #define NV_CPWR_THERM_DIV_BY2 0x00000001 /* */ #define NV_CPWR_THERM_DIV_BY4 0x00000002 /* */ #define NV_CPWR_THERM_DIV_BY8 0x00000003 /* */ #define NV_CPWR_THERM_DIV_BY16 0x00000004 /* */ #define NV_CPWR_THERM_DIV_BY31 0x00000005 /* */ #define NV_CPWR_THERM_FPDIV_BY1 0x00000000 /* */ #define NV_CPWR_THERM_FPDIV_BY1P5 0x00000001 /* */ #define NV_CPWR_THERM_FPDIV_BY2 0x00000002 /* */ #define NV_CPWR_THERM_FPDIV_BY2P5 0x00000003 /* */ #define NV_CPWR_THERM_FPDIV_BY3 0x00000004 /* */ #define NV_CPWR_THERM_FPDIV_BY3P5 0x00000005 /* */ #define NV_CPWR_THERM_FPDIV_BY4 0x00000006 /* */ #define NV_CPWR_THERM_FPDIV_BY4P5 0x00000007 /* */ #define NV_CPWR_THERM_FPDIV_BY5 0x00000008 /* */ #define NV_CPWR_THERM_FPDIV_BY5P5 0x00000009 /* */ #define NV_CPWR_THERM_FPDIV_BY6 0x0000000a /* */ #define NV_CPWR_THERM_FPDIV_BY6P5 0x0000000b /* */ #define NV_CPWR_THERM_FPDIV_BY7 0x0000000c /* */ #define NV_CPWR_THERM_FPDIV_BY7P5 0x0000000d /* */ #define NV_CPWR_THERM_FPDIV_BY8 0x0000000e /* */ #define NV_CPWR_THERM_FPDIV_BY8P5 0x0000000f /* */ #define NV_CPWR_THERM_FPDIV_BY9 0x00000010 /* */ #define NV_CPWR_THERM_FPDIV_BY9P5 0x00000011 /* */ #define NV_CPWR_THERM_FPDIV_BY10 0x00000012 /* */ #define NV_CPWR_THERM_FPDIV_BY10P5 0x00000013 /* */ #define NV_CPWR_THERM_FPDIV_BY11 0x00000014 /* */ #define NV_CPWR_THERM_FPDIV_BY11P5 0x00000015 /* */ #define NV_CPWR_THERM_FPDIV_BY12 0x00000016 /* */ #define NV_CPWR_THERM_FPDIV_BY12P5 0x00000017 /* */ #define NV_CPWR_THERM_FPDIV_BY13 0x00000018 /* */ #define NV_CPWR_THERM_FPDIV_BY13P5 0x00000019 /* */ #define NV_CPWR_THERM_FPDIV_BY14 0x0000001a /* */ #define NV_CPWR_THERM_FPDIV_BY14P5 0x0000001b /* */ #define NV_CPWR_THERM_FPDIV_BY15 0x0000001c /* */ #define NV_CPWR_THERM_FPDIV_BY15P5 0x0000001d /* */ #define NV_CPWR_THERM_FPDIV_BY16 0x0000001e /* */ #define NV_CPWR_THERM_FPDIV_BY16P5 0x0000001f /* */ #define NV_CPWR_THERM_FPDIV_MAXP5 0x0000001f /* */ #define NV_CPWR_THERM_FPDIV_BY17 0x00000020 /* */ #define NV_CPWR_THERM_FPDIV_BY18 0x00000022 /* */ #define NV_CPWR_THERM_FPDIV_BY19 0x00000024 /* */ #define NV_CPWR_THERM_FPDIV_BY20 0x00000026 /* */ #define NV_CPWR_THERM_FPDIV_BY21 0x00000028 /* */ #define NV_CPWR_THERM_FPDIV_BY22 0x0000002a /* */ #define NV_CPWR_THERM_FPDIV_BY23 0x0000002c /* */ #define NV_CPWR_THERM_FPDIV_BY24 0x0000002e /* */ #define NV_CPWR_THERM_FPDIV_BY25 0x00000030 /* */ #define NV_CPWR_THERM_FPDIV_BY26 0x00000032 /* */ #define NV_CPWR_THERM_FPDIV_BY27 0x00000034 /* */ #define NV_CPWR_THERM_FPDIV_BY28 0x00000036 /* */ #define NV_CPWR_THERM_FPDIV_BY29 0x00000038 /* */ #define NV_CPWR_THERM_FPDIV_BY30 0x0000003a /* */ #define NV_CPWR_THERM_FPDIV_BY31 0x0000003c /* */ #define NV_CPWR_THERM_FPDIV_MAX 0x0000003f /* */ #define NV_CPWR_THERM_ENGINE_GRAPHICS 0 /* */ #define NV_CPWR_THERM_ENGINE_COPY0 1 /* */ #define NV_CPWR_THERM_ENGINE_COPY1 2 /* */ #define NV_CPWR_THERM_ENGINE_COPY2 3 /* */ #define NV_CPWR_THERM_ENGINE_COPY3 4 /* */ #define NV_CPWR_THERM_ENGINE_COPY4 10 /* */ #define NV_CPWR_THERM_ENGINE_NVDEC 5 /* */ #define NV_CPWR_THERM_ENGINE_NVDEC1 6 /* */ #define NV_CPWR_THERM_ENGINE_SEC 7 /* */ #define NV_CPWR_THERM_ENGINE_NVENC0 8 /* */ #define NV_CPWR_THERM_ENGINE_OFA0 9 /* */ #define NV_CPWR_THERM_EVENT_MAX_COUNT 0x0000001F /* */ #define NV_CPWR_THERM_EDPP_EVENT_MAX_COUNT 0x00000002 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_MAX 0x00000003 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_COUNT 0x00000008 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_MASK 0x000000FF /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_GPC_AVG_UNMUNGED 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_ID_GPC_AVG 0x00000001 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_COUNT 2 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC(i) (NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED+((i)*4)) /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_FIXED_POINT 16:3 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_FIXED_POINT_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_FIXED_POINT_MIN 0x00003b00 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_FIXED_POINT_MAX 0x000012c0 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_INTEGER 16:8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_INTEGER_MIN 0x000001d8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_INTEGER_MAX 0x00000096 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_MUNGED 24:24 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_MUNGED_NO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_MUNGED_YES 0x00000001 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_STATE 30:30 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_STATE_INVALID 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_STATE_VALID 0x00000001 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_SOURCE 31:31 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_SOURCE_HW_LOGIC 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_SOURCE_SW_OVERRIDE 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_EXT_OVERT 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_EXT_ALERT 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_EXT_POWER 0x00000002 /* */ #define NV_CPWR_THERM_EVENT_THERMAL_0 0x00000003 /* */ #define NV_CPWR_THERM_EVENT_THERMAL_1 0x00000004 /* */ #define NV_CPWR_THERM_EVENT_THERMAL_2 0x00000005 /* */ #define NV_CPWR_THERM_EVENT_THERMAL_3 0x00000006 /* */ #define NV_CPWR_THERM_EVENT_THERMAL_4 0x00000007 /* */ #define NV_CPWR_THERM_EVENT_THERMAL_5 0x00000008 /* */ #define NV_CPWR_THERM_EVENT_THERMAL_6 0x00000009 /* */ #define NV_CPWR_THERM_EVENT_THERMAL_7 0x0000000a /* */ #define NV_CPWR_THERM_EVENT_THERMAL_8 0x0000000b /* */ #define NV_CPWR_THERM_EVENT_THERMAL_9 0x0000000c /* */ #define NV_CPWR_THERM_EVENT_THERMAL_10 0x0000000d /* */ #define NV_CPWR_THERM_EVENT_THERMAL_11 0x0000000e /* */ #define NV_CPWR_THERM_EVENT_EXT_ALERT_0 0x0000000f /* */ #define NV_CPWR_THERM_EVENT_EXT_ALERT_1 0x00000010 /* */ #define NV_CPWR_THERM_EVENT_BA_W0_T1 0x00000014 /* */ #define NV_CPWR_THERM_EVENT_BA_W0_T2 0x00000015 /* */ #define NV_CPWR_THERM_EVENT_BA_W1_T1 0x00000016 /* */ #define NV_CPWR_THERM_EVENT_BA_W1_T2 0x00000017 /* */ #define NV_CPWR_THERM_EVENT_BA_W2_T1 0x00000018 /* */ #define NV_CPWR_THERM_EVENT_BA_W2_T2 0x00000019 /* */ #define NV_CPWR_THERM_EVENT_VOLTAGE_HW_ADC 0x0000001C /* */ #define NV_CPWR_THERM_EVENT_EDPP_VMIN 0x0000001D /* */ #define NV_CPWR_THERM_EVENT_EDPP_FONLY 0x0000001E /* */ #define NV_CPWR_THERM_EVENT_THERMAL(i) (0x00000003+(i)) #define NV_CPWR_THERM_EVENT_MASK_EXTERNAL 0x00018007 /* */ #define NV_CPWR_THERM_EVENT_MASK_THERMAL 0x00007FF8 /* */ #define NV_CPWR_THERM_EVENT_MASK_BA 0x03F00000 /* */ #define NV_CPWR_THERM_EVENT_MASK_HW_ADC 0x10000000 /* */ #define NV_CPWR_THERM_EVENT_MASK_EDPP 0x60000000 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM_INPUT_NO_CH 0x000000FF /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM_INPUT_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM_INPUT_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM_INPUT_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM_INPUT_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_EVENT_MASK_HW_FAILSAFE (0x00018007|0x00007FF8|0x03F00000|0x10000000|0x60000000) /* */ #define NV_CPWR_THERM_EVENT_MASK_INTERRUPT (0x00018007|0x00007FF8|0x03F00000|0x10000000|0x60000000) /* */ #define NV_CPWR_THERM_EVENT_MASK_TRIGGER (0x00018007|0x00007FF8|0x03F00000|0x10000000|0x60000000) /* */ #define NV_CPWR_THERM_EVT_SETTINGS(i) (NV_CPWR_THERM_EVT_EXT_OVERT +((i)*4)) /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_THRESHOLD 16:3 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_THRESHOLD_MIN 0x00002000 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_THRESHOLD_MAX 0x00001fff /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID 23:20 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID_MAX 0x00000003 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_SLOW_FACTOR 29:24 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_SLOW_FACTOR_DISABLED 0x00000000 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_SLOW_LEGACY_FACTOR 26:24 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_MODE 31:30 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_MODE_NORMAL 0x00000000 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_MODE_INVERTED 0x00000001 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_MODE_FORCED 0x00000002 /* */ #define NV_CPWR_THERM_EVT_SETTINGS_MODE_CLEARED 0x00000003 /* */ #define NV_CPWR_THERM_TEMP_SENSOR(i) (NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE+((i)*4)) /* */ #define NV_CPWR_THERM_TEMP_SENSOR_FIXED_POINT 16:3 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_FIXED_POINT_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_FIXED_POINT_MIN 0x00003b00 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_FIXED_POINT_MAX 0x000012c0 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_INTEGER 16:8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_INTEGER_MIN 0x000001d8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_INTEGER_MAX 0x00000096 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_MUNGED 24:24 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_MUNGED_NO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_MUNGED_YES 0x00000001 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_STATE 30:30 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_STATE_INVALID 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_STATE_VALID 0x00000001 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_SOURCE 31:31 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_SOURCE_HW_LOGIC 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_SOURCE_SW_OVERRIDE 0x00000001 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA(i) (0x00000528 + (i)*20) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA__SIZE_1 4 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA_VALUE 31:0 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA_VALUE_INIT 0x00000000 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE(i) (0x0000052C + (i)*20) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE__SIZE_1 4 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE 31:30 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE_SET_NACK 0x00000000 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE_SET_RO 0x00000001 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE_SET_RW 0x00000002 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE_SET_NONE 0x00000003 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE_NACK 0x00000000 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE_RO 0x00000001 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE_RW 0x00000002 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE_STATE_NONE 0x00000003 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX(i) (0x00000524+(i)*20) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX__SIZE_1 4 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_VALUE 8:0 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_VALUE_INIT 0x00000000 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_VALUE_MIN 0x00000000 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_VALUE_MAX 0x000001FF /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_READINCR 16:16 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_READINCR_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_READINCR_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_WRITEINCR 17:17 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_WRITEINCR_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX_WRITEINCR_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PEAKPOWER_NVVDD_ADC_IIR_ADC_OUTPUT_WIDTH 0x00000007 /* */ #define NV_CPWR_THERM_PEAKPOWER_NVVDD_ADC_IIR_LUT_INDEX_WIDTH 0x00000004 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW 0x00020320 /* RW-4R */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION__FUSE_SIGNAL "therm_thermal_low" /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_LOW_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0 0x00020324 /* RW-4R */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION__FUSE_SIGNAL "therm_thermal_med_high_0" /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1 0x00020328 /* RW-4R */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION__FUSE_SIGNAL "therm_thermal_med_high_1" /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_THERMAL_PRIV_LEVEL_MASK_MED_HIGH_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK 0x0002032c /* RW-4R */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_vidctrl" /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_VIDCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0 0x00020380 /* RW-4R */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION__FUSE_SIGNAL "therm_smartfan_0" /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1 0x00020384 /* RW-4R */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION__FUSE_SIGNAL "therm_smartfan_1" /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_SMARTFAN_PRIV_LEVEL_MASK_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK 0x00020388 /* RW-4R */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_fantach" /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_FANTACH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK 0x0002038c /* RW-4R */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_i2cslave" /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_I2CSLAVE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK 0x00020390 /* RW-4R */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_intrupt" /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_INTRUPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK 0x00020398 /* RW-4R */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_pp" /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_PP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0 0x0002039c /* RW-4R */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION__FUSE_SIGNAL "therm_pwrgate_0" /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1 0x000203a0 /* RW-4R */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION__FUSE_SIGNAL "therm_pwrgate_1" /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_PWRGATE_PRIV_LEVEL_MASK_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0 0x000203a8 /* RW-4R */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION__FUSE_SIGNAL "therm_slowdown_0" /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1 0x000203b0 /* RW-4R */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION__FUSE_SIGNAL "therm_slowdown_1" /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PRIV_LEVEL_MASK_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK 0x000203b4 /* RW-4R */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "adcs" /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_ADC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK 0x000206c0 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "tsense" /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK 0x00020880 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "therm_dlppe" /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RW--V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_EVENT_LATCH 0x000207e0 /* RW-4R */ #define NV_CPWR_THERM_EVENT_LATCH__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_OVERT_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_OVERT_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_OVERT_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_POWER_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_POWER_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_POWER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_0_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_0_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_1_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_2_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_2_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_3_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_3_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_4_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_4_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_5_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_5_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_6_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_6_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_7_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_7_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_8_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_8_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_9_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_9_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_10_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_10_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_10_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_11_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_11_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_THERMAL_11_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_0_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_0_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_1_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_EXT_ALERT_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W0_T1_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W0_T1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W0_T1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W0_T2_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W0_T2_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W0_T2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W1_T1_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W1_T1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W1_T1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W1_T2_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W1_T2_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W1_T2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W2_T1_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W2_T1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W2_T1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W2_T2_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W2_T2_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_BA_W2_T2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_VOLTAGE_HW_ADC_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_VOLTAGE_HW_ADC_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_VOLTAGE_HW_ADC_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_EDPP_VMIN_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_EDPP_VMIN_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_EDPP_VMIN_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_EVENT_LATCH_EDPP_FONLY_NORMAL 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_LATCH_EDPP_FONLY_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_LATCH_EDPP_FONLY_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_LATCH_STATE(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_LATCH_STATE__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_LATCH_STATE_NORMAL 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_LATCH_STATE_TRIGGERED 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_LATCH_STATE_CLEAR 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_SELECT 0x000207e4 /* RW-4R */ #define NV_CPWR_THERM_EVENT_SELECT__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_OVERT_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_OVERT_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_POWER_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_POWER_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_0_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_0_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_1_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_1_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_2_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_2_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_3_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_3_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_4_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_4_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_5_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_5_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_6_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_6_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_7_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_7_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_8_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_8_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_9_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_9_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_10_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_10_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_11_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_THERMAL_11_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT_0_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT_0_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT_1_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_EXT_ALERT_1_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W0_T1_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W0_T1_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W0_T2_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W0_T2_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W1_T1_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W1_T1_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W1_T2_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W1_T2_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W2_T1_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W2_T1_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W2_T2_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_BA_W2_T2_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_VOLTAGE_HW_ADC_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_VOLTAGE_HW_ADC_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_EDPP_VMIN_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_EDPP_VMIN_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_EVENT_SELECT_EDPP_FONLY_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_SELECT_EDPP_FONLY_LATCH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_SELECT_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_SELECT_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_SELECT_CTRL_NORMAL 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_SELECT_CTRL_LATCH 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_TRIGGER 0x00020780 /* R--4R */ #define NV_CPWR_THERM_EVENT_TRIGGER__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_OVERT 0:0 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_OVERT_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_OVERT_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT 1:1 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_POWER 2:2 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_POWER_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_POWER_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_0 3:3 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_0_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_0_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_1 4:4 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_1_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_2 5:5 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_2_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_2_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_3 6:6 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_3_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_3_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_4 7:7 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_4_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_4_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_5 8:8 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_5_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_5_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_6 9:9 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_6_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_6_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_7 10:10 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_7_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_7_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_8 11:11 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_8_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_8_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_9 12:12 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_9_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_9_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_10 13:13 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_10_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_10_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_11 14:14 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_11_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_THERMAL_11_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT_0 15:15 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT_0_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT_0_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT_1 16:16 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT_1_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EXT_ALERT_1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W0_T1 20:20 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W0_T1_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W0_T1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W0_T2 21:21 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W0_T2_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W0_T2_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W1_T1 22:22 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W1_T1_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W1_T1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W1_T2 23:23 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W1_T2_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W1_T2_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W2_T1 24:24 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W2_T1_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W2_T1_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W2_T2 25:25 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W2_T2_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_BA_W2_T2_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_VOLTAGE_HW_ADC 28:28 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_VOLTAGE_HW_ADC_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_VOLTAGE_HW_ADC_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EDPP_VMIN 29:29 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_EDPP_VMIN_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EDPP_VMIN_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EDPP_FONLY 30:30 /* R--VF */ #define NV_CPWR_THERM_EVENT_TRIGGER_EDPP_FONLY_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_EDPP_FONLY_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_TRIGGER_STATE(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_TRIGGER_STATE__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_TRIGGER_STATE_NORMAL 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_TRIGGER_STATE_TRIGGERED 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_INTR_TYPE 0x000207e8 /* RW-4R */ #define NV_CPWR_THERM_EVENT_INTR_TYPE__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_OVERT_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_OVERT_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_POWER_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_POWER_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_0_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_0_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_1_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_1_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_2_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_2_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_3_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_3_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_4_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_4_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_5_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_5_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_6_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_6_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_7_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_7_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_8_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_8_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_9_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_9_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_10_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_10_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_11_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_THERMAL_11_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT_0_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT_0_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT_1_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EXT_ALERT_1_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W0_T1_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W0_T1_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W0_T2_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W0_T2_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W1_T1_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W1_T1_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W1_T2_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W1_T2_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W2_T1_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W2_T1_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W2_T2_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_BA_W2_T2_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_VOLTAGE_HW_ADC_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_VOLTAGE_HW_ADC_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EDPP_VMIN_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EDPP_VMIN_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EDPP_FONLY_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_EDPP_FONLY_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_CTRL_EDGE 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_INTR_TYPE_CTRL_LEVEL 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED 0x00020784 /* RW-4R */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_OVERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_OVERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_POWER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_POWER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_10_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_10_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_11_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_THERMAL_11_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W0_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W1_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_BA_W2_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_CTRL_DISABLED 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_TRIGGERED_CTRL_ENABLED 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL 0x00020788 /* RW-4R */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_OVERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_OVERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_POWER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_POWER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_10_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_10_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_11_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_THERMAL_11_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W0_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W1_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_BA_W2_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_CTRL_DISABLED 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_INTR_ON_NORMAL_CTRL_ENABLED 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_INTR_PENDING 0x0002078c /* RW-4R */ #define NV_CPWR_THERM_EVENT_INTR_PENDING__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_OVERT_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_OVERT_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_OVERT_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_POWER_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_POWER_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_POWER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_0_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_0_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_1_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_1_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_2_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_2_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_3_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_3_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_3_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_4_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_4_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_4_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_5_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_5_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_5_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_6_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_6_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_6_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_7_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_7_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_7_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_8_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_8_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_8_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_9_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_9_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_9_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_10_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_10_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_10_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_11_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_11_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_THERMAL_11_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_0_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_0_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_1_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_1_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EXT_ALERT_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W0_T1_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W0_T1_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W0_T1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W0_T2_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W0_T2_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W0_T2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W1_T1_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W1_T1_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W1_T1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W1_T2_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W1_T2_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W1_T2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W2_T1_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W2_T1_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W2_T1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W2_T2_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W2_T2_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_BA_W2_T2_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_VOLTAGE_HW_ADC_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_VOLTAGE_HW_ADC_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_VOLTAGE_HW_ADC_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EDPP_VMIN_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EDPP_VMIN_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EDPP_VMIN_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EDPP_FONLY_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EDPP_FONLY_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_EDPP_FONLY_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_STATE(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_STATE__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_STATE_NO 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_STATE_YES 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_INTR_PENDING_STATE_CLEAR 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE 0x00020790 /* RW-4R */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_OVERT_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_OVERT_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_POWER_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_POWER_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_0_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_0_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_2_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_2_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_3_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_3_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_4_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_4_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_5_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_5_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_6_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_6_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_7_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_7_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_8_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_8_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_9_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_9_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_10_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_10_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_11_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_THERMAL_11_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT_0_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT_0_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT_1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EXT_ALERT_1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W0_T1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W0_T1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W0_T2_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W0_T2_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W1_T1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W1_T1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W1_T2_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W1_T2_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W2_T1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W2_T1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W2_T2_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_BA_W2_T2_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_VOLTAGE_HW_ADC_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_VOLTAGE_HW_ADC_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EDPP_VMIN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EDPP_VMIN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EDPP_FONLY_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_EDPP_FONLY_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_CTRL_NO 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_INTR_ENABLE_CTRL_YES 0x00000001 /* */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE 0x00020794 /* RW-4R */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_OVERT_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_OVERT_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_POWER_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_POWER_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_0_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_0_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_1_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_1_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_2_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_2_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_3_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_3_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_4_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_4_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_5_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_5_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_6_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_6_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_7_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_7_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_8_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_8_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_9_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_9_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_10_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_10_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_11_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_THERMAL_11_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT_0_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT_0_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT_1_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EXT_ALERT_1_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W0_T1_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W0_T1_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W0_T2_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W0_T2_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W1_T1_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W1_T1_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W1_T2_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W1_T2_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W2_T1_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W2_T1_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W2_T2_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_BA_W2_T2_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_VOLTAGE_HW_ADC_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_VOLTAGE_HW_ADC_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EDPP_VMIN_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EDPP_VMIN_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EDPP_FONLY_TO_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_EDPP_FONLY_TO_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_CTRL_TO_HOST 0x00000000 /* */ #define NV_CPWR_THERM_EVENT_INTR_ROUTE_CTRL_TO_PMU 0x00000001 /* */ #define NV_CPWR_THERM_USE_A 0x00020798 /* RW-4R */ #define NV_CPWR_THERM_USE_A__PRIV_LEVEL_MASK 0x000203b0 /* */ #define NV_CPWR_THERM_USE_A_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_USE_A_EXT_OVERT_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_EXT_OVERT_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_USE_A_EXT_ALERT_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_EXT_ALERT_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_USE_A_EXT_POWER_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_EXT_POWER_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_0_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_0_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_2_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_2_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_3_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_3_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_4_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_4_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_5_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_5_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_6_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_6_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_7_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_7_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_8_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_8_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_9_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_9_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_10_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_10_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_USE_A_THERMAL_11_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_THERMAL_11_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_USE_A_EXT_ALERT_0_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_EXT_ALERT_0_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_USE_A_EXT_ALERT_1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_EXT_ALERT_1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_USE_A_BA_W0_T1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_BA_W0_T1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_USE_A_BA_W0_T2_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_BA_W0_T2_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_USE_A_BA_W1_T1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_BA_W1_T1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_USE_A_BA_W1_T2_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_BA_W1_T2_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_USE_A_BA_W2_T1_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_BA_W2_T1_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_USE_A_BA_W2_T2_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_BA_W2_T2_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_USE_A_VOLTAGE_HW_ADC_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_VOLTAGE_HW_ADC_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_USE_A_EDPP_VMIN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_EDPP_VMIN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_USE_A_EDPP_FONLY_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_A_EDPP_FONLY_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_A_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_USE_A_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_USE_A_CTRL_NO 0x00000000 /* */ #define NV_CPWR_THERM_USE_A_CTRL_YES 0x00000001 /* */ #define NV_CPWR_THERM_USE_B 0x0002079c /* RW-4R */ #define NV_CPWR_THERM_USE_B__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_USE_B_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_USE_B_EXT_OVERT_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_EXT_OVERT_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_USE_B_EXT_ALERT_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_EXT_ALERT_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_USE_B_EXT_POWER_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_EXT_POWER_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_0_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_0_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_1_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_1_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_2_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_2_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_3_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_3_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_4_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_4_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_5_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_5_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_6_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_6_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_7_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_7_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_8_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_8_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_9_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_9_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_10_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_10_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_USE_B_THERMAL_11_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_THERMAL_11_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_USE_B_EXT_ALERT_0_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_EXT_ALERT_0_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_USE_B_EXT_ALERT_1_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_EXT_ALERT_1_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_USE_B_BA_W0_T1_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_BA_W0_T1_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_USE_B_BA_W0_T2_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_BA_W0_T2_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_USE_B_BA_W1_T1_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_BA_W1_T1_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_USE_B_BA_W1_T2_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_BA_W1_T2_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_USE_B_BA_W2_T1_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_BA_W2_T1_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_USE_B_BA_W2_T2_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_USE_B_BA_W2_T2_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_USE_B_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_USE_B_VOLTAGE_HW_ADC_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_B_VOLTAGE_HW_ADC_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_B_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_USE_B_EDPP_VMIN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_B_EDPP_VMIN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_B_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_USE_B_EDPP_FONLY_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_USE_B_EDPP_FONLY_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_USE_B_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_USE_B_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_USE_B_CTRL_NO 0x00000000 /* */ #define NV_CPWR_THERM_USE_B_CTRL_YES 0x00000001 /* */ #define NV_CPWR_THERM_EVT_EXT_OVERT 0x00020700 /* RW-4R */ #define NV_CPWR_THERM_EVT_EXT_OVERT__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_EXT_OVERT_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_OVERT_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_OVERT_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_OVERT_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_OVERT_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_OVERT_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_OVERT_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_OVERT_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT 0x00020704 /* RW-4R */ #define NV_CPWR_THERM_EVT_EXT_ALERT__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_EXT_ALERT_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_ALERT_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_ALERT_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_POWER 0x00020708 /* RW-4R */ #define NV_CPWR_THERM_EVT_EXT_POWER__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_EXT_POWER_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_POWER_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_POWER_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_POWER_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_POWER_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_POWER_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_POWER_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_POWER_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0 0x0002070c /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_0__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_0_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_0_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_0_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_0_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_0_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_0_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_0_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1 0x00020710 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_1__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_1_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_1_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_1_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_1_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_1_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_1_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2 0x00020714 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_2__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_2_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_2_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_2_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_2_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_2_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_2_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_2_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3 0x00020718 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_3__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_3_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_3_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_3_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_3_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_3_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_3_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_3_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4 0x0002071c /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_4__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_4_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_4_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_4_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_4_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_4_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_4_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_4_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5 0x00020720 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_5__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_5_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_5_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_5_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_5_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_5_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_5_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_5_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6 0x00020724 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_6__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_6_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_6_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_6_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_6_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_6_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_6_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_6_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7 0x00020728 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_7__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_7_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_7_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_7_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_7_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_7_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_7_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_7_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8 0x0002072c /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_8__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_8_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_8_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_8_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_8_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_8_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_8_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_8_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9 0x00020730 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_9__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_9_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_9_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_9_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_9_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_9_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_9_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_9_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10 0x00020734 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_10__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_10_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_10_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_10_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_10_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_10_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_10_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_10_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11 0x00020738 /* RW-4R */ #define NV_CPWR_THERM_EVT_THERMAL_11__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_THRESHOLD_0C 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_THRESHOLD_MAX 0x00001fff /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID 23:20 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_11_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_11_SLOW_LEGACY_FACTOR 26:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_11_SLOW_LEGACY_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_11_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_THERMAL_11_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_THERMAL_11_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_THERMAL_11_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0 0x0002073c /* RW-4R */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_0_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1 0x00020740 /* RW-4R */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_EXT_ALERT_1_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W0_T1 0x00020750 /* RW-4R */ #define NV_CPWR_THERM_EVT_BA_W0_T1__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_BA_W0_T1_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W0_T1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W0_T1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W0_T1_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W0_T1_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W0_T1_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W0_T1_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W0_T1_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W0_T2 0x00020754 /* RW-4R */ #define NV_CPWR_THERM_EVT_BA_W0_T2__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_BA_W0_T2_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W0_T2_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W0_T2_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W0_T2_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W0_T2_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W0_T2_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W0_T2_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W0_T2_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W1_T1 0x00020758 /* RW-4R */ #define NV_CPWR_THERM_EVT_BA_W1_T1__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_BA_W1_T1_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W1_T1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W1_T1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W1_T1_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W1_T1_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W1_T1_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W1_T1_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W1_T1_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W1_T2 0x0002075c /* RW-4R */ #define NV_CPWR_THERM_EVT_BA_W1_T2__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_BA_W1_T2_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W1_T2_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W1_T2_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W1_T2_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W1_T2_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W1_T2_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W1_T2_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W1_T2_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W2_T1 0x00020760 /* RW-4R */ #define NV_CPWR_THERM_EVT_BA_W2_T1__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_BA_W2_T1_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W2_T1_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W2_T1_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W2_T1_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W2_T1_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W2_T1_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W2_T1_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W2_T1_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W2_T2 0x00020764 /* RW-4R */ #define NV_CPWR_THERM_EVT_BA_W2_T2__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_BA_W2_T2_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W2_T2_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W2_T2_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W2_T2_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_BA_W2_T2_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_BA_W2_T2_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W2_T2_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_BA_W2_T2_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC 0x00020770 /* RW-4R */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_VOLTAGE_HW_ADC_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_EDPP_VMIN 0x00020774 /* RW-4R */ #define NV_CPWR_THERM_EVT_EDPP_VMIN__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_EDPP_VMIN_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_EDPP_VMIN_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_EDPP_VMIN_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EDPP_VMIN_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_EDPP_VMIN_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EDPP_VMIN_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_EDPP_VMIN_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_EDPP_VMIN_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_EDPP_FONLY 0x00020778 /* RW-4R */ #define NV_CPWR_THERM_EVT_EDPP_FONLY__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_EVT_EDPP_FONLY_SLOW_FACTOR 29:24 /* RWIUF */ #define NV_CPWR_THERM_EVT_EDPP_FONLY_SLOW_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_EDPP_FONLY_SLOW_FACTOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EDPP_FONLY_MODE 31:30 /* RWIUF */ #define NV_CPWR_THERM_EVT_EDPP_FONLY_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_EVT_EDPP_FONLY_MODE_INVERTED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_EDPP_FONLY_MODE_FORCED 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_EDPP_FONLY_MODE_CLEARED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN 0x000204a8 /* RW-4R */ #define NV_CPWR_THERM_OVERT_EN__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_OVERT_EN_EXT_OVERT 0:0 /* C--VF */ #define NV_CPWR_THERM_OVERT_EN_EXT_OVERT_DISABLED 0x00000000 /* C---V */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_EXT_POWER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_EXT_POWER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_10_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_10_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_11_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_THERMAL_11_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_BA_W0_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_BA_W0_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_BA_W1_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_BA_W1_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_BA_W2_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_BA_W2_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_OVERT_EN_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_EN_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_EN_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_OVERT_EN_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_OVERT_EN_CTRL_DISABLED 0x00000000 /* */ #define NV_CPWR_THERM_OVERT_EN_CTRL_ENABLED 0x00000001 /* */ #define NV_CPWR_THERM_ALERT_EN 0x000204ac /* RW-4R */ #define NV_CPWR_THERM_ALERT_EN__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_ALERT_EN_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_EXT_OVERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_EXT_OVERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_EXT_POWER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_EXT_POWER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_10_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_10_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_11_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_THERMAL_11_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_BA_W0_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_BA_W0_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_BA_W1_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_BA_W1_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_BA_W2_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_BA_W2_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_ALERT_EN_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ALERT_EN_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ALERT_EN_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_ALERT_EN_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_ALERT_EN_CTRL_DISABLED 0x00000000 /* */ #define NV_CPWR_THERM_ALERT_EN_CTRL_ENABLED 0x00000001 /* */ #define NV_CPWR_THERM_MAXFAN_EN 0x000204b0 /* RW-4R */ #define NV_CPWR_THERM_MAXFAN_EN__PRIV_LEVEL_MASK 0x00020380 /* */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_OVERT 0:0 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_OVERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_OVERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT 1:1 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_POWER 2:2 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_POWER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_POWER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_0 3:3 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_1 4:4 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_2 5:5 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_3 6:6 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_4 7:7 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_5 8:8 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_6 9:9 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_7 10:10 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_8 11:11 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_9 12:12 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_10 13:13 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_10_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_10_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_11 14:14 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_11_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_THERMAL_11_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT_0 15:15 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT_0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT_0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT_1 16:16 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT_1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_EXT_ALERT_1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W0_T1 20:20 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W0_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W0_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W0_T2 21:21 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W0_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W0_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W1_T1 22:22 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W1_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W1_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W1_T2 23:23 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W1_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W1_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W2_T1 24:24 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W2_T1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W2_T1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W2_T2 25:25 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W2_T2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_BA_W2_T2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_VOLTAGE_HW_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_VOLTAGE_HW_ADC_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_VOLTAGE_HW_ADC_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_EDPP_VMIN 29:29 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_EDPP_VMIN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_EDPP_VMIN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_EDPP_FONLY 30:30 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_EN_EDPP_FONLY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MAXFAN_EN_EDPP_FONLY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MAXFAN_EN_CTRL(i) (i):(i) /* */ #define NV_CPWR_THERM_MAXFAN_EN_CTRL__SIZE_1 32 /* */ #define NV_CPWR_THERM_MAXFAN_EN_CTRL_DISABLED 0x00000000 /* */ #define NV_CPWR_THERM_MAXFAN_EN_CTRL_ENABLED 0x00000001 /* */ #define NV_CPWR_THERM_MAXFAN 0x000204b4 /* RW-4R */ #define NV_CPWR_THERM_MAXFAN__PRIV_LEVEL_MASK 0x00020380 /* */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_THERM 0:0 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_THERM_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_THERM_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_THERM_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_SCI_0 1:1 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_SCI_0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_SCI_0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_SCI_0_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_SCI_1 2:2 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_SCI_1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_SCI_1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_MAXFAN_STATUS_SMARTFAN_SCI_1_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_MAXFAN_FORCE 31:31 /* RWIVF */ #define NV_CPWR_THERM_MAXFAN_FORCE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_MAXFAN_FORCE_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_MAXFAN_FORCE_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_CTRL_2 0x00020108 /* RW-4R */ #define NV_CPWR_THERM_CTRL_2__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT 13:12 /* RWIVF */ #define NV_CPWR_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT_RISING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT_FALLING 0x00000002 /* RW--V */ #define NV_CPWR_THERM_CTRL_2_CLK_SLOWDOWN_INTERRUPT_BOTH 0x00000003 /* RW--V */ #define NV_CPWR_THERM_CTRL_2_CLK_SLOWDOWN 22:22 /* R--VF */ #define NV_CPWR_THERM_CTRL_2_CLK_SLOWDOWN_NORMAL 0x00000000 /* R---V */ #define NV_CPWR_THERM_CTRL_2_CLK_SLOWDOWN_TRIGGERED 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0 0x00020100 /* RW-4R */ #define NV_CPWR_THERM_INTR_0__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_INTR_0_FMON_ERROR_INTR 2:2 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_FMON_ERROR_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_FMON_ERROR_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_FMON_ERROR_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_I2C_SCRATCH_INTR_STATE 4:4 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_I2C_SCRATCH_INTR_STATE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_I2C_SCRATCH_INTR_STATE_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_I2C_SCRATCH_INTR_STATE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_ISENSE_BEACON1_INTR 5:5 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_ISENSE_BEACON1_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_ISENSE_BEACON1_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_ISENSE_BEACON1_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_ISENSE_BEACON2_INTR 6:6 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_ISENSE_BEACON2_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_ISENSE_BEACON2_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_ISENSE_BEACON2_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_DLPPE_INTR 7:7 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_DLPPE_INTR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_DLPPE_INTR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_DLPPE_INTR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_PEAKPOWER 8:8 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_PEAKPOWER_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_PEAKPOWER_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_PEAKPOWER_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_CLK_SLOWDOWN 15:15 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_CLK_SLOWDOWN_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_CLK_SLOWDOWN_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_CLK_SLOWDOWN_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_SMBUS_MSGBOX 16:16 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_SMBUS_MSGBOX_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_SMBUS_MSGBOX_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_SMBUS_MSGBOX_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_CFG_ERR 18:18 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_CFG_ERR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_CFG_ERR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_CFG_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_TEMPAVG_OFLOW 24:24 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_TEMPAVG_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_TEMPAVG_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_THERMAL_TRIGGER_TEMPAVG_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_SM_PIPELINE_STALLED_ENTRY 28:28 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_SM_PIPELINE_STALLED_ENTRY_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_SM_PIPELINE_STALLED_ENTRY_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_SM_PIPELINE_STALLED_ENTRY_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_SM_PIPELINE_STALLED_EXIT 29:29 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_SM_PIPELINE_STALLED_EXIT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_0_SM_PIPELINE_STALLED_EXIT_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_INTR_0_SM_PIPELINE_STALLED_EXIT_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_INTR_0_SPARE 31:31 /* RWIVF */ #define NV_CPWR_THERM_INTR_0_SPARE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_EN_0 0x00020134 /* RW-4R */ #define NV_CPWR_THERM_INTR_EN_0__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_INTR_EN_0_FMON_ERROR_INTR 2:2 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_FMON_ERROR_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_FMON_ERROR_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_I2C_SCRATCH_INTR_STATE 4:4 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_I2C_SCRATCH_INTR_STATE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_I2C_SCRATCH_INTR_STATE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_ISENSE_BEACON1_INTR 5:5 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_ISENSE_BEACON1_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_ISENSE_BEACON1_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_ISENSE_BEACON2_INTR 6:6 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_ISENSE_BEACON2_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_ISENSE_BEACON2_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_DLPPE_INTR 7:7 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_DLPPE_INTR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_DLPPE_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_PEAKPOWER 8:8 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_PEAKPOWER_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_PEAKPOWER_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_CLK_SLOWDOWN 15:15 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_CLK_SLOWDOWN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_CLK_SLOWDOWN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_SMBUS_MSGBOX 16:16 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_SMBUS_MSGBOX_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_SMBUS_MSGBOX_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_CFG_ERR 18:18 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_CFG_ERR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_CFG_ERR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_TEMPAVG_OFLOW 24:24 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_TEMPAVG_OFLOW_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_TEMPAVG_OFLOW_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_SM_PIPELINE_STALLED_ENTRY 28:28 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_SM_PIPELINE_STALLED_ENTRY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_SM_PIPELINE_STALLED_ENTRY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_EN_0_SM_PIPELINE_STALLED_EXIT 29:29 /* RWIVF */ #define NV_CPWR_THERM_INTR_EN_0_SM_PIPELINE_STALLED_EXIT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_EN_0_SM_PIPELINE_STALLED_EXIT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE 0x000200fc /* RW-4R */ #define NV_CPWR_THERM_INTR_ROUTE__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_INTR_ROUTE_FMON_ERROR_INTR 2:2 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_FMON_ERROR_INTR_HOST 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_FMON_ERROR_INTR_PMU 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_I2C_SCRATCH_INTR_STATE 4:4 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_I2C_SCRATCH_INTR_STATE_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_I2C_SCRATCH_INTR_STATE_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_ISENSE_BEACON1_INTR 5:5 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_ISENSE_BEACON1_INTR_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_ISENSE_BEACON1_INTR_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_ISENSE_BEACON2_INTR 6:6 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_ISENSE_BEACON2_INTR_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_ISENSE_BEACON2_INTR_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_DLPPE_INTR 7:7 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_DLPPE_INTR_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_DLPPE_INTR_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_PEAKPOWER 8:8 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_PEAKPOWER_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_PEAKPOWER_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_CLK_SLOWDOWN 15:15 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_CLK_SLOWDOWN_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_CLK_SLOWDOWN_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_SMBUS_MSGBOX 16:16 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_SMBUS_MSGBOX_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_SMBUS_MSGBOX_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_CFG_ERR 18:18 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_CFG_ERR_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_CFG_ERR_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_TEMPAVG_OFLOW 24:24 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_TEMPAVG_OFLOW_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_THERMAL_TRIGGER_TEMPAVG_OFLOW_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_ENTRY 28:28 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_ENTRY_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_ENTRY_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_EXIT 29:29 /* RWIVF */ #define NV_CPWR_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_EXIT_HOST 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_ROUTE_SM_PIPELINE_STALLED_EXIT_PMU 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL(i) (0x000207a0+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL__SIZE_1 8 /* */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE 5:0 /* RWIVF */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_NONE 0x0000003f /* RWI-V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_OVERT 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_ALERT 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_POWER 0x00000002 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_0 0x00000003 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_1 0x00000004 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_2 0x00000005 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_3 0x00000006 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_4 0x00000007 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_5 0x00000008 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_6 0x00000009 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_7 0x0000000a /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_8 0x0000000b /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_9 0x0000000c /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_10 0x0000000d /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_11 0x0000000e /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_ALERT_0 0x0000000f /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_EXT_ALERT_1 0x00000010 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_BEACON1 0x00000011 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_BEACON2 0x00000012 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_VOLTAGE_HW_ADC 0x00000013 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W0_T1 0x00000014 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W0_T2 0x00000015 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W1_T1 0x00000016 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W1_T2 0x00000017 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W2_T1 0x00000018 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_BA_W2_T2 0x00000019 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC 0x0000001a /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC0 0x0000001b /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC1 0x0000001c /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC2 0x0000001d /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ADC_IPC3 0x0000001e /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_EDPP_VMIN 0x0000001f /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_EDPP_FONLY 0x00000020 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_THERMAL_TRIGGER_SLOWDOWN 0x00000021 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_TEMPAVG_OFLOW 0x00000022 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_SM_PIPELINE_STALLED 0x00000023 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_DVCO_SLOWPATH_ACTIVE 0x00000024 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_IDLE_SLOWDOWN 0x00000027 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_GR 0x00000028 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_NVENC0 0x00000029 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_NVDEC 0x0000002c /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_NVDEC1 0x00000039 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_SEC 0x0000002d /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE0 0x0000002e /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE1 0x0000002f /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE2 0x00000030 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE3 0x00000031 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_CE4 0x00000032 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_VR 0x00000034 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_SOURCE_ELCG_OFA0 0x00000035 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_POLARITY 28:28 /* RWIVF */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_POLARITY_LOW_ACTIVE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_POLARITY_HIGH_ACTIVE 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_TYPE 29:29 /* RWIVF */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_TYPE_EDGE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_TYPE_LEVEL 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_CLEAR 30:30 /* RWIVF */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_CLEAR_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_CLEAR_NOT_DONE 0x00000000 /* R---V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_CLEAR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_EN 31:31 /* RWIVF */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_INTR_MONITOR_CTRL_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_INTR_MONITOR_STATE(i) (0x000207c0+(i)*4) /* R--4A */ #define NV_CPWR_THERM_INTR_MONITOR_STATE__SIZE_1 8 /* */ #define NV_CPWR_THERM_INTR_MONITOR_STATE_VALUE 30:0 /* R-IVF */ #define NV_CPWR_THERM_INTR_MONITOR_STATE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_MONITOR_STATE_OVERFLOW 31:31 /* R-IVF */ #define NV_CPWR_THERM_INTR_MONITOR_STATE_OVERFLOW_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_INTR_MONITOR_STATE_OVERFLOW_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_CTRL_1 0x00020004 /* RW-4R */ #define NV_CPWR_THERM_CTRL_1__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_GPCCLK 24:24 /* RWIVF */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_GPCCLK_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_GPCCLK_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_SYSCLK 25:25 /* RWIVF */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_SYSCLK_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_SYSCLK_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_LTCCLK 27:27 /* RWIVF */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_LTCCLK_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CTRL_1_CLK_SLOWDOWN_INTR_LTCCLK_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_CTRL 0x0002005c /* RW-4R */ #define NV_CPWR_THERM_OVERT_CTRL__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_OVERT_CTRL_OUTPUT_DRIVE_MODE 1:0 /* RWIVF */ #define NV_CPWR_THERM_OVERT_CTRL_OUTPUT_DRIVE_MODE_FULL 0x00000000 /* RW--V */ #define NV_CPWR_THERM_OVERT_CTRL_OUTPUT_DRIVE_MODE_OPEN_DRAIN 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_OVERT_CTRL_OUTPUT_DRIVE_MODE_OFF 0x00000002 /* RW--V */ #define NV_CPWR_THERM_OVERT_CTRL_INPUT_DRIVE_MODE 2:2 /* RWIVF */ #define NV_CPWR_THERM_OVERT_CTRL_INPUT_DRIVE_MODE_OFF 0x00000000 /* RW--V */ #define NV_CPWR_THERM_OVERT_CTRL_INPUT_DRIVE_MODE_ON 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_OVERT_CTRL_PAD_INPUT_RCV 3:3 /* RWIVF */ #define NV_CPWR_THERM_OVERT_CTRL_PAD_INPUT_RCV_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_OVERT_CTRL_PAD_INPUT_RCV_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_OVERT_CTRL_POLARITY 8:8 /* RWIVF */ #define NV_CPWR_THERM_OVERT_CTRL_POLARITY_ACTIVE_HIGH 0x00000000 /* RW--V */ #define NV_CPWR_THERM_OVERT_CTRL_POLARITY_ACTIVE_LOW 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_OVERT_CTRL_INT_OVERT_ASSERTED 15:15 /* R--VF */ #define NV_CPWR_THERM_OVERT_CTRL_INT_OVERT_ASSERTED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_OVERT_CTRL_INT_OVERT_ASSERTED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_OVERT_CTRL_EXT_OVERT_ASSERTED 16:16 /* R--VF */ #define NV_CPWR_THERM_OVERT_CTRL_EXT_OVERT_ASSERTED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_OVERT_CTRL_EXT_OVERT_ASSERTED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_OVERT_CTRL_SEL 17:17 /* RWIVF */ #define NV_CPWR_THERM_OVERT_CTRL_SEL_LOCAL_LATCH 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_CTRL_SEL_OVERT_PAD 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_CTRL_OTOB_DISABLE 28:28 /* RWIVF */ #define NV_CPWR_THERM_OVERT_CTRL_OTOB_DISABLE_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_CTRL_OTOB_DISABLE_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_OVERT_CTRL_OTOB_ENABLE 29:29 /* RWIVF */ #define NV_CPWR_THERM_OVERT_CTRL_OTOB_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_OVERT_CTRL_OTOB_ENABLE_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT 0x00020054 /* RW-4R */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_THRESHOLD 16:3 /* RWISF */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_THRESHOLD_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_THRESHOLD_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_THRESHOLD_110C 0x00000dc0 /* RWI-V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_THRESHOLD_MAX 0x00001fff /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE 19:18 /* RWIVF */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE_16US 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE_256US 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE_4096US 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_SCALE_65536US 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID 23:20 /* RWIVF */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_SYS_TSENSE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_RSVD 0x00000002 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_GPU_OFFSET_MAX 0x00000006 /* RWI-V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_TEMP_SENSOR_ID_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_PERIOD 31:24 /* RWIVF */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_PERIOD_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_PERIOD_EIGHT 0x00000008 /* RWI-V */ #define NV_CPWR_THERM_EVT_DEDICATED_OVERT_FILTER_PERIOD_MAX 0x000000ff /* RW--V */ #define NV_CPWR_THERM_SENSOR_0 0x00020008 /* R--4R */ #define NV_CPWR_THERM_SENSOR_0__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_SENSOR_0_TEMP_CODE 13:0 /* R--VF */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE 0x00020028 /* RW-4R */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_RSVD 14:0 /* C--VF */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_TEMP_SELECT 15:15 /* RWIVF */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_TEMP_SELECT_REAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_TEMP_SELECT_OVERRIDE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_TEMP_VALUE 29:16 /* RWISF */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_TEMP_VALUE_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_TEMP_INTEGER 29:21 /* */ #define NV_CPWR_THERM_SYS_TSENSE_OVERRIDE_TEMP_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_SENSOR_1 0x0002000c /* RW-4R */ #define NV_CPWR_THERM_SENSOR_1__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_SENSOR_1_SELECT_SW_A 0:0 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_1_SELECT_SW_A_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_1_SELECT_SW_A_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SENSOR_1_SELECT_SW_B 1:1 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_1_SELECT_SW_B_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_1_SELECT_SW_B_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SENSOR_1_TS_STABLE_CNT 21:2 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_1_TS_STABLE_CNT_INIT 0x00000834 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_1_TS_STABLE_CNT_RST 31:31 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_1_TS_STABLE_CNT_RST_CNT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_1_TS_STABLE_CNT_RST_RST 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SENSOR_2 0x00020010 /* RW-4R */ #define NV_CPWR_THERM_SENSOR_2__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_SENSOR_2_SW_A 9:0 /* RWIUF */ #define NV_CPWR_THERM_SENSOR_2_SW_A_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_2_SW_A_40NM 0x000003ac /* RW--V */ #define NV_CPWR_THERM_SENSOR_2_SW_B 26:16 /* RWIUF */ #define NV_CPWR_THERM_SENSOR_2_SW_B_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_2_SW_B_40NM 0x000005ef /* RW--V */ #define NV_CPWR_THERM_SENSOR_3 0x00020014 /* R--4R */ #define NV_CPWR_THERM_SENSOR_3__PRIV_LEVEL_MASK 0x00020320 /* */ #define NV_CPWR_THERM_SENSOR_3_HW_A 9:0 /* R--UF */ #define NV_CPWR_THERM_SENSOR_3_HW_B 26:16 /* R--UF */ #define NV_CPWR_THERM_SENSOR_4 0x0002001c /* R--4R */ #define NV_CPWR_THERM_SENSOR_4__PRIV_LEVEL_MASK 0x00020320 /* */ #define NV_CPWR_THERM_SENSOR_4_HW_A_NOMINAL 9:0 /* C--UF */ #define NV_CPWR_THERM_SENSOR_4_HW_A_NOMINAL_DEF 0x00000226 /* C---V */ #define NV_CPWR_THERM_SENSOR_4_HW_B_NOMINAL 26:16 /* C--UF */ #define NV_CPWR_THERM_SENSOR_4_HW_B_NOMINAL_DEF 0x0000028e /* C---V */ #define NV_CPWR_THERM_SENSOR_6 0x000200f0 /* RW-4R */ #define NV_CPWR_THERM_SENSOR_6__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_SENSOR_6_POWER 0:0 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_6_POWER_ON 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_6_POWER_OFF 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_6_XTAL_GATE_INVALIDATE_TEMP 1:1 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_6_XTAL_GATE_INVALIDATE_TEMP_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_6_XTAL_GATE_INVALIDATE_TEMP_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_6_XTAL_GATE_STATUS 2:2 /* R--VF */ #define NV_CPWR_THERM_SENSOR_6_XTAL_GATE_STATUS_GATED 0x00000001 /* R---V */ #define NV_CPWR_THERM_SENSOR_6_XTAL_GATE_STATUS_RUNNING 0x00000000 /* R---V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_PERIOD 23:16 /* RWIUF */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_PERIOD_NONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_PERIOD_MAX 0x000000ff /* RW--V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_SCALE 25:24 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_SCALE_16US 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_SCALE_256US 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_SCALE_4096US 0x00000002 /* RW--V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_SCALE_65536US 0x00000003 /* RW--V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_STATUS 31:31 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_STATUS_VALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_STATUS_ERROR 0x00000001 /* R---V */ #define NV_CPWR_THERM_SENSOR_6_POLLING_INTERVAL_STATUS_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_SENSOR_7 0x000200f4 /* RW-4R */ #define NV_CPWR_THERM_SENSOR_7__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_SENSOR_7_DEBUG_TS_ADC_OUT 13:0 /* RWIUF */ #define NV_CPWR_THERM_SENSOR_7_DEBUG_TS_ADC_OUT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_7_DEBUG_TS_ADC_OVERRIDE 15:15 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_7_DEBUG_TS_ADC_OVERRIDE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_7_DEBUG_TS_ADC_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SENSOR_7_DEBUG_TS_POWER_DOWN 16:16 /* R-IVF */ #define NV_CPWR_THERM_SENSOR_7_DEBUG_TS_POWER_DOWN_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_SENSOR_7_DEBUG_TS_POWER_DOWN_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE 0x00020460 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE__PRIV_LEVEL_MASK 0x00020320 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_INTEGER 16:8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_INTEGER_MIN 0x000001d8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_INTEGER_MAX 0x00000096 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_STATE 30:30 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_STATE_INVALID 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SOURCE 31:31 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE 0x00020464 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE__PRIV_LEVEL_MASK 0x00020320 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_INTEGER 16:8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_INTEGER_MIN 0x000001d8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_INTEGER_MAX 0x00000096 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_STATE 30:30 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_STATE_INVALID 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SOURCE 31:31 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT 0x00020468 /* RW-4R */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_FIXED_POINT 16:3 /* RWISF */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_FIXED_POINT_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_FIXED_POINT_MIN 0x00002000 /* RW--V */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_FIXED_POINT_MAX 0x00001fff /* RW--V */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_INTEGER 16:8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_INTEGER_MIN 0x00000100 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_INTEGER_MAX 0x000000ff /* */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_MUNGED 24:24 /* RWIVF */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_MUNGED_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_MUNGED_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_STATE 30:30 /* RWIVF */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_STATE_INVALID 0x00000000 /* RW--V */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_STATE_VALID 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_SOURCE 31:31 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_CONSTANT_SOURCE_SW_OVERRIDE 0x00000001 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX 0x0002046c /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX__PRIV_LEVEL_MASK 0x00020320 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_FIXED_POINT_MIN 0x00002000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_FIXED_POINT_MAX 0x00001fff /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_INTEGER 16:8 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_INTEGER_MIN 0x00000100 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_INTEGER_MAX 0x000000ff /* */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_STATE 30:30 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_STATE_INVALID 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_SOURCE 31:31 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_SOURCE_HW_LOGIC 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_MAX_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX 0x00020470 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT_INIT 0x00002000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_INTEGER_INIT 0x00000100 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG 0x00020474 /* RW-4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_FORMULA 25:25 /* RWIVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_FORMULA_0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_FORMULA_1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX 0x00020478 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT_INIT 0x00002000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER_INIT 0x00000100 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG 0x0002047c /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_SYS_TSENSE_HS_OFFSET 0x000204a0 /* RW-4R */ #define NV_CPWR_THERM_SYS_TSENSE_HS_OFFSET__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_SYS_TSENSE_HS_OFFSET_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_SYS_TSENSE_HS_OFFSET_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_SYS_TSENSE_HS_OFFSET_FIXED_POINT 16:3 /* RWISF */ #define NV_CPWR_THERM_SYS_TSENSE_HS_OFFSET_FIXED_POINT_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SYS_TSENSE_HS_OFFSET_INTEGER 16:8 /* */ #define NV_CPWR_THERM_SENSOR_9 0x000204a4 /* RW-4R */ #define NV_CPWR_THERM_SENSOR_9__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_SENSOR_9_MAX_SYS_TSENSE 0:0 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_9_MAX_SYS_TSENSE_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_MAX_SYS_TSENSE_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_9_MAX_OFFSET_SYS_TSENSE 1:1 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_9_MAX_OFFSET_SYS_TSENSE_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_MAX_OFFSET_SYS_TSENSE_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_9_MAX_CONSTANT 2:2 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_9_MAX_CONSTANT_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_MAX_CONSTANT_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_MAX 4:4 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_MAX_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_MAX_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_AVG 5:5 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_AVG_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_AVG_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_OFFSET_MAX 6:6 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_OFFSET_MAX_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_OFFSET_MAX_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_OFFSET_AVG 7:7 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_OFFSET_AVG_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_MAX_GPU_OFFSET_AVG_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_9_MAX_SOURCE(i) (i):(i) /* */ #define NV_CPWR_THERM_SENSOR_9_MAX_SOURCE__SIZE_1 10 /* */ #define NV_CPWR_THERM_SENSOR_9_MAX_SOURCE_NO 0x00000000 /* */ #define NV_CPWR_THERM_SENSOR_9_MAX_SOURCE_YES 0x00000001 /* */ #define NV_CPWR_THERM_SENSOR_9_I2CS 31:28 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_9_I2CS_SYS_TSENSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_9_I2CS_OFFSET_SYS_TSENSE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_I2CS_CONSTANT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_I2CS_MAX 0x00000003 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_I2CS_GPU_MAX 0x00000004 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_I2CS_GPU_AVG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_I2CS_GPU_OFFSET_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_SENSOR_9_I2CS_GPU_OFFSET_AVG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX 0x00020448 /* RW-4R */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_SYS_TSENSE 0:0 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_SYS_TSENSE_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_SYS_TSENSE_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_OFFSET_SYS_TSENSE 1:1 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_OFFSET_SYS_TSENSE_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_OFFSET_SYS_TSENSE_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_MAX 4:4 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_MAX_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_MAX_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_AVG 5:5 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_AVG_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_AVG_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_MAX 6:6 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_MAX_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_MAX_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_AVG 7:7 /* RWIVF */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_AVG_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_SEL_GPU_OFFSET_AVG_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_FIXED_POINT 30:17 /* R--SF */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_INTEGER 30:22 /* */ #define NV_CPWR_THERM_SENSOR_DEDICATED_OVERT_MAX_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_WEIGHT_1 0x00020024 /* RW-4R */ #define NV_CPWR_THERM_WEIGHT_1__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_WEIGHT_1_XBAR 7:0 /* RWIUF */ #define NV_CPWR_THERM_WEIGHT_1_XBAR_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1(i) (0x00020154+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_STEP_SIZE 4:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_STEP_SIZE_MAX 0x00000015 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_STEP_SIZE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_WINDOW_SIZE 11:5 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_WINDOW_SIZE_MAX 0x00000040 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_WINDOW_SIZE_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_NVVDD_FACTOR_A_LUT_EN 12:12 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_NVVDD_FACTOR_A_LUT_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_NVVDD_FACTOR_A_LUT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_NVVDD_LEAKAGE_C_LUT_EN 13:13 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_NVVDD_LEAKAGE_C_LUT_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_NVVDD_LEAKAGE_C_LUT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_MSVDD_FACTOR_A_LUT_EN 14:14 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_MSVDD_FACTOR_A_LUT_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_MSVDD_FACTOR_A_LUT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_MSVDD_LEAKAGE_C_LUT_EN 15:15 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_MSVDD_LEAKAGE_C_LUT_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_MSVDD_LEAKAGE_C_LUT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_NVVDD 17:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_NVVDD_SYS_ADC 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_NVVDD_GPC_ADC_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_NVVDD_GPC_ADC_AVG 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_MSVDD 19:18 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_MSVDD_SYS_ADC 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_MSVDD_GPC_ADC_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_LUT_ADC_SEL_MSVDD_GPC_ADC_AVG 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_T1_HW_ADC_MODE 20:20 /* RWIVF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_T1_HW_ADC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_T1_HW_ADC_MODE_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_T1_HW_ADC_MODE_ADC 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_T2_HW_ADC_MODE 21:21 /* RWIVF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_T2_HW_ADC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_T2_HW_ADC_MODE_NORMAL 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_T2_HW_ADC_MODE_ADC 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_GPC 22:22 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_GPC_NVVDD 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_GPC_MSVDD 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_FBP 23:23 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_FBP_NVVDD 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_FBP_MSVDD 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_XBAR 24:24 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_XBAR_NVVDD 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_POWER_DOMAIN_XBAR_MSVDD 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_PEAK_EN 25:25 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_PEAK_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_PEAK_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_SRC_NVVDD 27:27 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_SRC_NVVDD_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_SRC_NVVDD_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_SRC_MSVDD 28:28 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_SRC_MSVDD_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_BA_SRC_MSVDD_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_WINDOW_RST 30:30 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_WINDOW_RST_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_WINDOW_RST_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_WINDOW_RST_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_WINDOW_EN 31:31 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_WINDOW_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG1_WINDOW_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG2(i) (0x00020170+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG2__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG2__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_VAL 19:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_EN 31:31 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG2_BA_THRESHOLD_1H_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG3(i) (0x00020190+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG3__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG3__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_VAL 19:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_EN 31:31 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG3_BA_THRESHOLD_2H_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG4(i) (0x000201c0+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG4__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG4__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_VAL 19:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_EN 31:31 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG4_BA_THRESHOLD_1L_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG5(i) (0x000201f0+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG5__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG5__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_VAL 19:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_EN 31:31 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG5_BA_THRESHOLD_2L_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6(i) (0x00020680+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_FACTOR_A 9:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_FACTOR_A_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT 20:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R3 0x00000003 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R5 0x00000005 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R6 0x00000006 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R7 0x00000007 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R8 0x00000008 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R9 0x00000009 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R10 0x0000000a /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R11 0x0000000b /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R12 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R13 0x0000000d /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R14 0x0000000e /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_R15 0x0000000f /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L16 0x00000010 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L15 0x00000011 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L14 0x00000012 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L13 0x00000013 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L12 0x00000014 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L11 0x00000015 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L10 0x00000016 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L9 0x00000017 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L8 0x00000018 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L7 0x00000019 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L6 0x0000001a /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L5 0x0000001b /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L4 0x0000001c /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L3 0x0000001d /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L2 0x0000001e /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG6_NVVDD_BA_SUM_SHIFT_L1 0x0000001f /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG7(i) (0x000206f0+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG7__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG7__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG7_NVVDD_LEAKAGE_C 19:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG7_NVVDD_LEAKAGE_C_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8(i) (0x000202e8+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_FACTOR_A 9:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_FACTOR_A_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT 20:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R3 0x00000003 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R5 0x00000005 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R6 0x00000006 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R7 0x00000007 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R8 0x00000008 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R9 0x00000009 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R10 0x0000000a /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R11 0x0000000b /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R12 0x0000000c /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R13 0x0000000d /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R14 0x0000000e /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_R15 0x0000000f /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L16 0x00000010 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L15 0x00000011 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L14 0x00000012 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L13 0x00000013 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L12 0x00000014 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L11 0x00000015 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L10 0x00000016 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L9 0x00000017 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L8 0x00000018 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L7 0x00000019 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L6 0x0000001a /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L5 0x0000001b /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L4 0x0000001c /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L3 0x0000001d /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L2 0x0000001e /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG8_MSVDD_BA_SUM_SHIFT_L1 0x0000001f /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG9(i) (0x000202f4+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG9__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG9__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG9_MSVDD_LEAKAGE_C 19:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG9_MSVDD_LEAKAGE_C_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG10(i) (0x00020330+(i)*4) /* R--4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG10__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG10__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG10_WIN_SUM_VALUE 19:0 /* R-IUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG10_WIN_SUM_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11(i) (0x00020358+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_SIGNIFICAND 8:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_SIGNIFICAND_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT 14:12 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R3 0x00000003 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R5 0x00000005 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R6 0x00000006 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C0_RSHIFT_R7 0x00000007 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_SIGNIFICAND 24:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_SIGNIFICAND_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT 30:28 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R3 0x00000003 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R5 0x00000005 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R6 0x00000006 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG11_C1_RSHIFT_R7 0x00000007 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12(i) (0x00020364+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_SIGNIFICAND 8:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_SIGNIFICAND_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT 14:12 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R3 0x00000003 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R5 0x00000005 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R6 0x00000006 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_C2_RSHIFT_R7 0x00000007 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD 19:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_MAX 0x00000008 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_256 0x00000008 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_128 0x00000007 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_64 0x00000006 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_32 0x00000005 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_16 0x00000004 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_8 0x00000003 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_4 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_2 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_1 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG12_DBA_PERIOD_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG13(i) (0x00020370+(i)*4) /* R--4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG13__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG13__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG13_DP_PREDICT_BA_VALUE 19:0 /* R-IUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG13_DP_PREDICT_BA_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14(i) (0x000203f0+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_DATA 19:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_INDEX 26:20 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_WRITE_EN 29:29 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_WRITE_EN_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_WRITE_EN_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_WRITE_EN_WRITE 0x00000001 /* -W--T */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_SEL 31:30 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_SEL_NVVDD_FACTOR_A 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_SEL_NVVDD_LEAKAGE_C 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_SEL_MSVDD_FACTOR_A 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_CONFIG14_LUT_SEL_MSVDD_LEAKAGE_C 0x00000003 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT 0x000200c0 /* RW-4R */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_STEP_OFLOW 12:12 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_STEP_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_STEP_OFLOW 13:13 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_STEP_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_STEP_OFLOW 14:14 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_STEP_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_PEAK_OFLOW 15:15 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_PEAK_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_PEAK_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_PEAK_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_PEAK_OFLOW 16:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_PEAK_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_PEAK_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_PEAK_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_PEAK_OFLOW 17:17 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_PEAK_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_PEAK_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_PEAK_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBA_OFLOW 18:18 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBA_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBA_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBA_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBA_OFLOW 19:19 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBA_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBA_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBA_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBA_OFLOW 20:20 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBA_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBA_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBA_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBG3_STEP_OFLOW 21:21 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBG3_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBG3_STEP_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W0_DBG3_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBG3_STEP_OFLOW 22:22 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBG3_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBG3_STEP_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W1_DBG3_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBG3_STEP_OFLOW 23:23 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBG3_STEP_OFLOW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBG3_STEP_OFLOW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_TRIGGER_STAT_W2_DBG3_STEP_OFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0 0x000200d0 /* RW-4R */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX 2:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX_0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX_1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_WINDOW_IDX_2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SELECT 17:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_INIT 0x00000003 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_DYNAMIC 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_LEAKAGE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_TOTAL 0x00000002 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SELECT_RESERVED 0x00000003 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SHIFT 22:18 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SHIFT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SHIFT_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_DEBUG0_DP2_SHIFT_MAX 0x00000010 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL(i) (0x00020110+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_LOGGING 0:0 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_LOGGING_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_LOGGING_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_LOGGING_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_RST 2:2 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_RST_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_RST_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_RST_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_WHEN_OVERFLOW 3:3 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_WHEN_OVERFLOW_SATURATE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_WHEN_OVERFLOW_ROLLOVER 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT 4:4 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_DIRECT_READ 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP_MODE 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP 5:5 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_PEAKPOWER_ACC_CTRL_BA_RESULT_SNAP_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_PEAKPOWER_ACC_PWR(i) (0x000201d0+(i)*4) /* R--4A */ #define NV_CPWR_THERM_PEAKPOWER_ACC_PWR__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_PWR__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_PWR_TOTAL_POWER 31:0 /* R-XVF */ #define NV_CPWR_THERM_PEAKPOWER_ACC_LKG(i) (0x000201b0+(i)*4) /* R--4A */ #define NV_CPWR_THERM_PEAKPOWER_ACC_LKG__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_LKG__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_LKG_LEAKAGE_POWER 31:0 /* R-XVF */ #define NV_CPWR_THERM_PEAKPOWER_ACC_STEPS(i) (0x000202b0+(i)*4) /* R--4A */ #define NV_CPWR_THERM_PEAKPOWER_ACC_STEPS__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_STEPS__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_STEPS_STEPS_CNT 31:0 /* R-XVF */ #define NV_CPWR_THERM_PEAKPOWER_ACC_BA(i) (0x00020310+(i)*4) /* R--4A */ #define NV_CPWR_THERM_PEAKPOWER_ACC_BA__SIZE_1 3 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_BA__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_ACC_BA_TOTAL_BA 31:0 /* R-XVF */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR 0x0002031c /* RW-4R */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR_ADC_OUT 6:0 /* R-XVF */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR_LENGTH 19:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR_LENGTH_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_BYPASS_DATA 30:24 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_BYPASS_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_SEL 31:31 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_SEL_IIR 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_SYS_ADC_IIR_OUTPUT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR 0x0002037c /* RW-4R */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_ADC_OUT 6:0 /* R-XVF */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_ADC_IDX 11:8 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_ADC_IDX_GPC0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_LENGTH 19:16 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_LENGTH_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_BYPASS_DATA 30:24 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_BYPASS_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_SEL 31:31 /* RWIUF */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_SEL_IIR 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PEAKPOWER_GPC_ADC_IIR_OUTPUT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_NAFLL_ADC_DISABLE 0x000202bc /* RW-4R */ #define NV_CPWR_THERM_GPC_NAFLL_ADC_DISABLE__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_GPC_NAFLL_ADC_DISABLE_MASK 7:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_NAFLL_ADC_DISABLE_MASK_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL 0x00020600 /* RW-4R */ #define NV_CPWR_THERM_BA_TRAINING_CTRL__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_PRIV_POLLING_MODE 0:0 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_PRIV_POLLING_MODE_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_PRIV_POLLING_MODE_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_MODE 1:1 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_MODE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_MODE_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_MODE_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MTRAIN_SWITCH 2:2 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MTRAIN_SWITCH_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MTRAIN_SWITCH_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_RESET 3:3 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_RESET_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_RESET_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_TRANSCFG_IDX 6:4 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_TRANSCFG_IDX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_MODE_VBIOS_SET 7:7 /* RWIVF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_MODE_VBIOS_SET_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_MODE_VBIOS_SET_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_DMA_MODE_VBIOS_SET_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE 11:8 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_4KB 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_8KB 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_16KB 0x00000002 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_32KB 0x00000003 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_64KB 0x00000004 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_128KB 0x00000005 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_256KB 0x00000006 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_512KB 0x00000007 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_1MB 0x00000008 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_2MB 0x00000009 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_4MB 0x0000000a /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_8MB 0x0000000b /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_16MB 0x0000000c /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_32MB 0x0000000d /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_64MB 0x0000000e /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFFER_SIZE_128MB 0x0000000f /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_FST_GPIO_P_W 16:12 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_FST_GPIO_P_W_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_MODE 20:20 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_MODE_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_MODE_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_RESET 21:21 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_RESET_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_RESET_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_DMA 22:22 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_DMA_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_DMA_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_SNAP 23:23 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_SNAP_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_SNAP_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_SNAP_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFRAM_0_STATUS 24:24 /* R--VF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFRAM_0_STATUS_IDLE 0x00000000 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFRAM_0_STATUS_BUSY 0x00000001 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFRAM_1_STATUS 25:25 /* R--VF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFRAM_1_STATUS_IDLE 0x00000000 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_BUFRAM_1_STATUS_BUSY 0x00000001 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MTRAIN_DBUF 26:26 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MTRAIN_DBUF_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MTRAIN_DBUF_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_ERR_STATUS 27:27 /* RWIVF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_ERR_STATUS_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_ERR_STATUS_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SW_TRIGGER_ERR_STATUS_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD 30:28 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_1US 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_2US 0x00000002 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_4US 0x00000003 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_8US 0x00000004 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_16US 0x00000005 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_32US 0x00000006 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_MIN_FLUSH_PERIOD_64US 0x00000007 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SKIP_HW_FLUSH 31:31 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SKIP_HW_FLUSH_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_CTRL_SKIP_HW_FLUSH_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_TIMING 0x00020604 /* RW-4R */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_TIMING__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_TIMING_TRUN_PERIOD 15:0 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_TIMING_TRUN_PERIOD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_DMABASE_LOW 0x00020608 /* RW-4R */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_DMABASE_LOW__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_DMABASE_LOW_BASE_ADDR 31:0 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_DMABASE_LOW_BASE_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_DMABASE_HIGH 0x0002060c /* RW-4R */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_DMABASE_HIGH__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_DMABASE_HIGH_BASE_ADDR 8:0 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_ATRAIN_DMABASE_HIGH_BASE_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL 0x00020610 /* RW-4R */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_INDEX 9:0 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_LOW_RD_INCR 20:20 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_LOW_RD_INCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_LOW_RD_INCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_HIGH_RD_INCR 21:21 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_HIGH_RD_INCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_HIGH_RD_INCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_BUFRAM_SEL 23:22 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_BUFRAM_SEL_0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_BUFRAM_SEL_1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_BUFRAM_SEL_SHADOW 0x00000002 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_SEL_1R_MODE 24:24 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_SEL_1R_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_SEL_1R_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_SNAP 31:31 /* RWIUF */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_SNAP_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_SNAP_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_BA_TRAINING_SNAP_CTRL_SNAP_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_BA_TRAINING_DATA_LOW 0x00020614 /* R--4R */ #define NV_CPWR_THERM_BA_TRAINING_DATA_LOW_DATA 31:0 /* R--UF */ #define NV_CPWR_THERM_BA_TRAINING_DATA_HIGH 0x00020618 /* R--4R */ #define NV_CPWR_THERM_BA_TRAINING_DATA_HIGH_DATA 31:0 /* R--UF */ #define NV_CPWR_THERM_BA_TRAINING_SW_TRIGGER_COUNT 0x000206bc /* R--4R */ #define NV_CPWR_THERM_BA_TRAINING_SW_TRIGGER_COUNT_VALUE 31:0 /* R--UF */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC 0x000200d4 /* RW-4R */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_VALUE 6:0 /* RWIVF */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_EN 7:7 /* RWIVF */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_EN_DIS 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_LOW_EN_EN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_VALUE 14:8 /* RWIVF */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_EN 15:15 /* RWIVF */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_EN_DIS 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_THRESHOLD_HIGH_EN_EN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_HYS_VALUE 27:16 /* RWIVF */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_HYS_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_SEL_ADC 28:28 /* RWIVF */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_SEL_ADC_SYS_ADC 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VOLTAGE_HW_ADC_SEL_ADC_GPC_ADC_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX 0x00020038 /* RW-4R */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX 4:0 /* RWIVF */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_MAX 0x0000000a /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_GR 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_NVENC0 0x00000008 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_NVDEC 0x00000005 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_NVDEC1 0x00000006 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_CE0 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_CE1 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_CE2 0x00000003 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_CE3 0x00000004 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_CE4 0x0000000a /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_OFA0 0x00000009 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_INDEX_INDEX_SEC 0x00000007 /* RW--V */ #define NV_CPWR_THERM_ELCG_DBG_DATA 0x0002003c /* R--4R */ #define NV_CPWR_THERM_ELCG_DBG_DATA__APERTURE_INDEX_OFFSET (0x00000038-0x0000003C) /* */ #define NV_CPWR_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST 2:0 /* R-IVF */ #define NV_CPWR_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_ENABLED 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_IDLE_FILTER 0x00000001 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_DISABLE_WAIT4ACK 0x00000002 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_DISABLED 0x00000003 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_ENABLE_WAIT2ACK 0x00000004 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_ENDIS_SERVER_ST_ENABLE_WAIT4NREQ 0x00000005 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_CG_ST 7:4 /* R-IVF */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_CG_ST_ENG_ENABLED 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_CG_ST_ENG_DISABLING_WAIT2 0x00000001 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_CG_ST_ENG_DISABLED 0x00000002 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_CG_ST_ENG_ENABLING 0x00000003 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST 7:4 /* R--VF */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_ENABLED 0x00000000 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_IDLE_FILT 0x00000001 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_DISABLING 0x00000002 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_DISABLING_WAIT1 0x00000003 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_DISABLING_WAIT2 0x00000004 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_DISABLED 0x00000005 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_CHK_CLK 0x00000006 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_ENABLING 0x00000007 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CTL_GR_CG_ST_ENG_ACK_CLEAR 0x00000008 /* R---V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CLK_DISABLE 31:31 /* R-IVF */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CLK_DISABLE_DEASSERTED 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ELCG_DBG_DATA_CLK_DISABLE_ASSERTED 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_0 0x00020044 /* R--4R */ #define NV_CPWR_THERM_DBG_0__PRIV_LEVEL_MASK 0x00020320 /* */ #define NV_CPWR_THERM_DBG_0_FUSE_A_ERR 31:31 /* R-XVF */ #define NV_CPWR_THERM_DBG_3 0x00020040 /* R--4R */ #define NV_CPWR_THERM_DBG_3__PRIV_LEVEL_MASK 0x0002039c /* */ #define NV_CPWR_THERM_DBG_3_GPC_CLK_FORCE 30:29 /* R-XVF */ #define NV_CPWR_THERM_DBG_3_GPC_CLK_FORCE_CLK_RUN 0x00000000 /* R---V */ #define NV_CPWR_THERM_DBG_3_GPC_CLK_FORCE_CLK_AUTO 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_3_GPC_CLK_FORCE_CLK_STOP 0x00000002 /* R---V */ #define NV_CPWR_THERM_DBG_3_GPC_GATEABLE 31:31 /* R-XVF */ #define NV_CPWR_THERM_DBG_3_GPC_GATEABLE_DEASSERTED 0x00000000 /* R---V */ #define NV_CPWR_THERM_DBG_3_GPC_GATEABLE_ASSERTED 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_4 0x00020298 /* R--4R */ #define NV_CPWR_THERM_DBG_4__PRIV_LEVEL_MASK 0x0002039c /* */ #define NV_CPWR_THERM_DBG_4_THERMALCTL_HW_SLOW_COND 19:19 /* R-XVF */ #define NV_CPWR_THERM_DBG_4_THERMALCTL_HW_SLOW_COND_DISABLED 0x00000000 /* R---V */ #define NV_CPWR_THERM_DBG_4_THERMALCTL_HW_SLOW_COND_ENABLED 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_FECS_ST 24:22 /* R-XVF */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_FECS_ST_ON_BUSY 0x00000000 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_FECS_ST_ON_IDLE 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_FECS_ST_WAIT_DREQ_ACK 0x00000002 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_FECS_ST_OFF 0x00000003 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_FECS_ST_WAKEUP 0x00000004 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_FECS_ST_WAIT_EN_ACK 0x00000005 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST 27:25 /* R-XVF */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_ON_BUSY 0x00000000 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_ON_IDLE 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_WAIT_DREQ_ACK 0x00000002 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_OFF 0x00000003 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_WAKEUP 0x00000004 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_GTCTL_HUBMMU_ST_WAIT_EN_ACK 0x00000005 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE 29:28 /* R-XVF */ #define NV_CPWR_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE_AUTO 0x00000000 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE_SLOW 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE_FORCE_ON 0x00000002 /* R---V */ #define NV_CPWR_THERM_DBG_4_ELCG_CTL_GR_PWR_MODE_FORCE_POWER 0x00000003 /* R---V */ #define NV_CPWR_THERM_DBG_6 0x00020304 /* R--4R */ #define NV_CPWR_THERM_DBG_6_ELCG_GTCTL_FECSC_ST 5:3 /* R-IVF */ #define NV_CPWR_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_ON_BUSY 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_ON_IDLE 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_WAIT_DREQ_ACK 0x00000002 /* R---V */ #define NV_CPWR_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_OFF 0x00000003 /* R---V */ #define NV_CPWR_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_WAKEUP 0x00000004 /* R---V */ #define NV_CPWR_THERM_DBG_6_ELCG_GTCTL_FECSC_ST_WAIT_EN_ACK 0x00000005 /* R---V */ #define NV_CPWR_THERM_DBG_6_SPARE 31:6 /* C--VF */ #define NV_CPWR_THERM_DBG_6_SPARE_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_CONFIG1 0x00020050 /* RW-4R */ #define NV_CPWR_THERM_CONFIG1__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_CONFIG1_BA_ENABLE 20:20 /* RWIVF */ #define NV_CPWR_THERM_CONFIG1_BA_ENABLE_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CONFIG1_BA_ENABLE_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CONFIG2 0x00020130 /* RW-4R */ #define NV_CPWR_THERM_CONFIG2__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION 11:8 /* RWIUF */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_128K 0x0000000f /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_512 0x00000007 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_256 0x00000006 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_128 0x00000005 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_64 0x00000004 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_32 0x00000003 /* RWI-V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_16 0x00000002 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_8 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_4 0x00000000 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE 15:12 /* RWIUF */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_GRAD_STEP_DURATION_CYCLE_8 0x00000008 /* RW--V */ #define NV_CPWR_THERM_CONFIG2_SLOWDOWN_FACTOR_EXTENDED 24:24 /* RWIUF */ #define NV_CPWR_THERM_CONFIG2_SLOWDOWN_FACTOR_EXTENDED_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CONFIG2_GRAD_ENABLE 31:31 /* RWIUF */ #define NV_CPWR_THERM_CONFIG2_GRAD_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0 0x00020060 /* RW-4R */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0_PERIOD 24:0 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0_PERIOD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0_PERIOD_MAX 0x00ffffff /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0_EN 31:31 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PWM_0_EN__PROD 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SLOWDOWN_PWM_1 0x00020064 /* RW-4R */ #define NV_CPWR_THERM_SLOWDOWN_PWM_1__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_SLOWDOWN_PWM_1_HI 24:0 /* RWIVF */ #define NV_CPWR_THERM_SLOWDOWN_PWM_1_HI_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SLOWDOWN_PWM_1_HI_MAX 0x00ffffff /* RW--V */ #define NV_CPWR_THERM_GRAD_STEPPING0 0x000202c0 /* RW-4R */ #define NV_CPWR_THERM_GRAD_STEPPING0__PRIV_LEVEL_MASK 0x000203b0 /* */ #define NV_CPWR_THERM_GRAD_STEPPING0_FEATURE 0:0 /* RWIVF */ #define NV_CPWR_THERM_GRAD_STEPPING0_FEATURE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING0_FEATURE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GRAD_STEPPING0_MODE 2:2 /* RWIVF */ #define NV_CPWR_THERM_GRAD_STEPPING0_MODE_SYMMETRIC 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING0_MODE_ASYMMETRIC 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GRAD_STEPPING0_DVCO_FEATURE 4:4 /* RWIVF */ #define NV_CPWR_THERM_GRAD_STEPPING0_DVCO_FEATURE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING0_DVCO_FEATURE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GRAD_STEPPING1 0x000202c4 /* RW-4R */ #define NV_CPWR_THERM_GRAD_STEPPING1__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_GRAD_STEPPING1_PDIV_DURATION 16:0 /* RWIUF */ #define NV_CPWR_THERM_GRAD_STEPPING1_PDIV_DURATION_IMMEDIATE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING1_PDIV_DURATION_MAX 0x0001ffff /* RW--V */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE(i) (0x000202c8+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE__SIZE_1 2 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0 5:0 /* RWIVF */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR1 11:6 /* RWIVF */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR1_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR2 17:12 /* RWIVF */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR2_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR3 23:18 /* RWIVF */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR3_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR4 29:24 /* RWIVF */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR4_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR(i) (5+(i)*6):((i)*6) /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR__SIZE_1 5 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY1 0x00000000 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY1P5 0x00000001 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY2 0x00000002 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY2P5 0x00000003 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY3 0x00000004 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY3P5 0x00000005 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY4 0x00000006 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY4P5 0x00000007 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY5 0x00000008 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY5P5 0x00000009 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY6 0x0000000a /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY6P5 0x0000000b /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY7 0x0000000c /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY7P5 0x0000000d /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY8 0x0000000e /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY8P5 0x0000000f /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY9 0x00000010 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY9P5 0x00000011 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY10 0x00000012 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY10P5 0x00000013 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY11 0x00000014 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY11P5 0x00000015 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY12 0x00000016 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY12P5 0x00000017 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY13 0x00000018 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY13P5 0x00000019 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY14 0x0000001a /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY14P5 0x0000001b /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY15 0x0000001c /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY15P5 0x0000001d /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY16 0x0000001e /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY16P5 0x0000001f /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY17 0x00000020 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY18 0x00000022 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY19 0x00000024 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY20 0x00000026 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY21 0x00000028 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY22 0x0000002a /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY23 0x0000002c /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY24 0x0000002e /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY25 0x00000030 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY26 0x00000032 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY27 0x00000034 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY28 0x00000036 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY29 0x00000038 /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY30 0x0000003a /* */ #define NV_CPWR_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR_FPDIV_BY31 0x0000003c /* */ #define NV_CPWR_THERM_CONFIG3 0x00020140 /* RW-4R */ #define NV_CPWR_THERM_CONFIG3__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_CONFIG3_BA_METER_SHIFT 3:0 /* RWIUF */ #define NV_CPWR_THERM_CONFIG3_BA_METER_SHIFT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CONFIG3_BA_SELECT 30:30 /* RWIUF */ #define NV_CPWR_THERM_CONFIG3_BA_SELECT_ACC_PWR 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CONFIG3_BA_SELECT_ACC_BA 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CONFIG3_BA_METER_ENABLE 31:31 /* RWIUF */ #define NV_CPWR_THERM_CONFIG3_BA_METER_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_METER_PULSE_WIDTH 0x00020148 /* RW-4R */ #define NV_CPWR_THERM_BA_METER_PULSE_WIDTH__PRIV_LEVEL_MASK 0x00020398 /* */ #define NV_CPWR_THERM_BA_METER_PULSE_WIDTH_MIN 15:0 /* RWIUF */ #define NV_CPWR_THERM_BA_METER_PULSE_WIDTH_MIN_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_BA_METER_PULSE_WIDTH_MAX 31:16 /* RWIUF */ #define NV_CPWR_THERM_BA_METER_PULSE_WIDTH_MAX_INIT 0x0000ff00 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SCRATCH 0x000200bc /* RW-4R */ #define NV_CPWR_THERM_I2CS_SCRATCH__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0(i) (0x00020160+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0__SIZE_1 4 /* */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0__PRIV_LEVEL_MASK 0x000203b0 /* */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR 5:0 /* RWIUF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DIV2 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DIV4 0x00000002 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DIV8 0x00000003 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_FACTOR_DIV16 0x00000004 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_USE_LOCAL 7:7 /* RWIVF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_USE_LOCAL_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_HW_FAILSAFE_USE_LOCAL_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 /* RWIUF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DIV2 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DIV4 0x00000002 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DIV8 0x00000003 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR_DIV16 0x00000004 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1(i) (0x00020180+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1__SIZE_1 4 /* */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1__PRIV_LEVEL_MASK 0x000203b0 /* */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR 5:0 /* RWIUF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DIV2 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DIV4 0x00000002 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DIV8 0x00000003 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_FACTOR_DIV16 0x00000004 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_TRIGGER 7:7 /* RWIUF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_TRIGGER_UNSET 0x00000000 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_1_SW_THERM_TRIGGER_SET 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2(i) (0x000201a0+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2__SIZE_1 4 /* */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2__PRIV_LEVEL_MASK 0x000203b0 /* */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_SELECT 3:0 /* RWIVF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE 6:4 /* RWIVF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_ENG 0x00000000 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_PMU 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_SLOW 0x00000002 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_ALWAYS 0x00000003 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_A_TYPE_NEVER 0x00000004 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_SELECT 11:8 /* RWIVF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE 14:12 /* RWIVF */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_ENG 0x00000000 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_PMU 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_SLOW 0x00000002 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_ALWAYS 0x00000003 /* RW--V */ #define NV_CPWR_THERM_CLK_SLOWDOWN_2_IDLE_CONDITION_B_TYPE_NEVER 0x00000004 /* RWI-V */ #define NV_CPWR_THERM_CLK_TIMING_0(i) (0x000203c0+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_CLK_TIMING_0__SIZE_1 11 /* */ #define NV_CPWR_THERM_CLK_TIMING_0__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_CLK_TIMING_0_GRAD_SLOWDOWN 16:16 /* RWIVF */ #define NV_CPWR_THERM_CLK_TIMING_0_GRAD_SLOWDOWN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_CLK_TIMING_0_GRAD_SLOWDOWN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CLK_STATUS(i) (0x000201e0+(i)*4) /* R--4A */ #define NV_CPWR_THERM_CLK_STATUS__SIZE_1 4 /* */ #define NV_CPWR_THERM_CLK_STATUS__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_CLK_STATUS_SLOWDOWN_FACTOR 5:0 /* R--UF */ #define NV_CPWR_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DISABLED 0x00000000 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DIV2 0x00000001 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DIV4 0x00000002 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DIV8 0x00000003 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SLOWDOWN_FACTOR_DIV16 0x00000004 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SW_THERM 17:17 /* R--VF */ #define NV_CPWR_THERM_CLK_STATUS_SW_THERM_INACTIVE 0x00000000 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SW_THERM_ACTIVE 0x00000001 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_IDLE_SLOW 18:18 /* R--VF */ #define NV_CPWR_THERM_CLK_STATUS_IDLE_SLOW_INACTIVE 0x00000000 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_IDLE_SLOW_ACTIVE 0x00000001 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_HW_FAILSAFE 19:19 /* R--VF */ #define NV_CPWR_THERM_CLK_STATUS_HW_FAILSAFE_INACTIVE 0x00000000 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_HW_FAILSAFE_ACTIVE 0x00000001 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_IDLE_SLOW_COND 20:20 /* R--VF */ #define NV_CPWR_THERM_CLK_STATUS_IDLE_SLOW_COND_NOT_SATISFY 0x00000000 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_IDLE_SLOW_COND_SATISFY 0x00000001 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SWITCHING 31:30 /* R--VF */ #define NV_CPWR_THERM_CLK_STATUS_SWITCHING_STATIC 0x00000000 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SWITCHING_TRANSITION 0x00000001 /* R---V */ #define NV_CPWR_THERM_CLK_STATUS_SWITCHING_UNAVAILABLE 0x00000003 /* R---V */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR 0x00020128 /* RW-4R */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR__PRIV_LEVEL_MASK 0x000203a8 /* */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_HW_FAILSAFE_FORCE_DISABLE 0:0 /* RWIVF */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_HW_FAILSAFE_FORCE_DISABLE_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_HW_FAILSAFE_FORCE_DISABLE_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_IDLE_FORCE_DISABLE 1:1 /* RWIVF */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_IDLE_FORCE_DISABLE_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_IDLE_FORCE_DISABLE_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_SW_FORCE_DISABLE 2:2 /* RWIVF */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_SW_FORCE_DISABLE_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_SLOWDOWN_FACTOR_SW_FORCE_DISABLE_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWER_6 0x00020078 /* RW-4R */ #define NV_CPWR_THERM_POWER_6__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_PERIOD 23:16 /* RWIVF */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_PERIOD_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_PERIOD_EIGHT 0x00000008 /* RWI-V */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_PERIOD_MAX 0x000000ff /* RW--V */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_SCALE 25:24 /* RWIVF */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_SCALE_16US 0x00000000 /* RW--V */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_SCALE_256US 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_SCALE_4096US 0x00000002 /* RW--V */ #define NV_CPWR_THERM_POWER_6_THERMAL_FILTER_SCALE_65536US 0x00000003 /* RW--V */ #define NV_CPWR_THERM_POWER_7 0x00020094 /* RW-4R */ #define NV_CPWR_THERM_POWER_7__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_POWER_7_EXTOVERT_FILTER_PERIOD 23:16 /* RWIVF */ #define NV_CPWR_THERM_POWER_7_EXTOVERT_FILTER_PERIOD_NONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_7_EXTOVERT_FILTER_PERIOD_MAX 0x000000ff /* RW--V */ #define NV_CPWR_THERM_POWER_7_EXTOVERT_FILTER_SCALE 25:24 /* RWIVF */ #define NV_CPWR_THERM_POWER_7_EXTOVERT_FILTER_SCALE_16US 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_7_EXTOVERT_FILTER_SCALE_256US 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWER_7_EXTOVERT_FILTER_SCALE_4096US 0x00000002 /* RW--V */ #define NV_CPWR_THERM_POWER_7_EXTOVERT_FILTER_SCALE_65536US 0x00000003 /* RW--V */ #define NV_CPWR_THERM_POWER_8 0x00020098 /* RW-4R */ #define NV_CPWR_THERM_POWER_8__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_POWER_8_EXTALERT_FILTER_PERIOD 23:16 /* RWIVF */ #define NV_CPWR_THERM_POWER_8_EXTALERT_FILTER_PERIOD_NONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_8_EXTALERT_FILTER_PERIOD_MAX 0x000000ff /* RW--V */ #define NV_CPWR_THERM_POWER_8_EXTALERT_FILTER_SCALE 25:24 /* RWIVF */ #define NV_CPWR_THERM_POWER_8_EXTALERT_FILTER_SCALE_16US 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_8_EXTALERT_FILTER_SCALE_256US 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWER_8_EXTALERT_FILTER_SCALE_4096US 0x00000002 /* RW--V */ #define NV_CPWR_THERM_POWER_8_EXTALERT_FILTER_SCALE_65536US 0x00000003 /* RW--V */ #define NV_CPWR_THERM_POWER_9 0x0002009c /* RW-4R */ #define NV_CPWR_THERM_POWER_9__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_POWER_9_EXTPOWER_FILTER_PERIOD 23:16 /* RWIVF */ #define NV_CPWR_THERM_POWER_9_EXTPOWER_FILTER_PERIOD_NONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_9_EXTPOWER_FILTER_PERIOD_MAX 0x000000ff /* RW--V */ #define NV_CPWR_THERM_POWER_9_EXTPOWER_FILTER_SCALE 25:24 /* RWIVF */ #define NV_CPWR_THERM_POWER_9_EXTPOWER_FILTER_SCALE_16US 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_9_EXTPOWER_FILTER_SCALE_256US 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWER_9_EXTPOWER_FILTER_SCALE_4096US 0x00000002 /* RW--V */ #define NV_CPWR_THERM_POWER_9_EXTPOWER_FILTER_SCALE_65536US 0x00000003 /* RW--V */ #define NV_CPWR_THERM_POWER_10 0x000200f8 /* RW-4R */ #define NV_CPWR_THERM_POWER_10__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_POWER_10_EXT_ALERT_FILTER_PERIOD 23:16 /* RWIVF */ #define NV_CPWR_THERM_POWER_10_EXT_ALERT_FILTER_PERIOD_NONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_10_EXT_ALERT_FILTER_PERIOD_MAX 0x000000ff /* RW--V */ #define NV_CPWR_THERM_POWER_10_EXT_ALERT_FILTER_SCALE 25:24 /* RWIVF */ #define NV_CPWR_THERM_POWER_10_EXT_ALERT_FILTER_SCALE_16US 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWER_10_EXT_ALERT_FILTER_SCALE_256US 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWER_10_EXT_ALERT_FILTER_SCALE_4096US 0x00000002 /* RW--V */ #define NV_CPWR_THERM_POWER_10_EXT_ALERT_FILTER_SCALE_65536US 0x00000003 /* RW--V */ #define NV_CPWR_THERM_I2C_ADDR 0x00020018 /* RW-4R */ #define NV_CPWR_THERM_I2C_ADDR__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_ADDR_0 7:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_ADDR_0_INIT 0x0000009e /* RWI-V */ #define NV_CPWR_THERM_I2C_ADDR_1 15:8 /* RWIVF */ #define NV_CPWR_THERM_I2C_ADDR_1_INIT 0x0000009c /* RWI-V */ #define NV_CPWR_THERM_I2C_ADDR_2 23:16 /* RWIVF */ #define NV_CPWR_THERM_I2C_ADDR_2_INIT 0x0000009a /* RWI-V */ #define NV_CPWR_THERM_I2C_ADDR_3 31:24 /* RWIVF */ #define NV_CPWR_THERM_I2C_ADDR_3_INIT 0x00000098 /* RWI-V */ #define NV_CPWR_THERM_STRAP_CTRL 0x00020034 /* RW-4R */ #define NV_CPWR_THERM_STRAP_CTRL__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_STRAP_CTRL_SMB_ALT_ADDR 1:0 /* RWIVF */ #define NV_CPWR_THERM_STRAP_CTRL_SMB_ALT_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_STRAP_CTRL_SMB_ALT_ADDR_STRAP 0x00000000 /* RW--V */ #define NV_CPWR_THERM_STRAP_CTRL_SMB_ALT_ADDR_HIGH 0x00000003 /* RW--V */ #define NV_CPWR_THERM_STRAP_CTRL_SMB_ALT_ADDR_LOW 0x00000002 /* RW--V */ #define NV_CPWR_THERM_I2C_CFG 0x00020080 /* RW-4R */ #define NV_CPWR_THERM_I2C_CFG__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_CFG_TIMEOUT 7:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_CFG_TIMEOUT_INIT 0x0000001b /* RWI-V */ #define NV_CPWR_THERM_I2C_CFG_SPIKE 10:8 /* RWIVF */ #define NV_CPWR_THERM_I2C_CFG_SPIKE_INIT 0x00000004 /* RWI-V */ #define NV_CPWR_THERM_I2C_CFG_HOLD 19:16 /* RWIVF */ #define NV_CPWR_THERM_I2C_CFG_HOLD_INIT 0x00000006 /* RWI-V */ #define NV_CPWR_THERM_I2C_CFG_SETUP 23:20 /* RWIVF */ #define NV_CPWR_THERM_I2C_CFG_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_CFG_PRIV_ENABLE 24:24 /* RWIVF */ #define NV_CPWR_THERM_I2C_CFG_PRIV_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_CFG_SPARE 31:25 /* RWIVF */ #define NV_CPWR_THERM_I2C_CFG_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_CLK_DIV 0x000200b8 /* RW-4R */ #define NV_CPWR_THERM_I2C_CLK_DIV__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_CLK_DIV_VAL 2:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_CLK_DIV_VAL_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ARP_CFG 0x000200a0 /* RW-4R */ #define NV_CPWR_THERM_ARP_CFG__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_ARP_CFG_ENABLE 24:24 /* RWIVF */ #define NV_CPWR_THERM_ARP_CFG_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ARP_CFG_OVERRIDE_RAND 16:16 /* RWIVF */ #define NV_CPWR_THERM_ARP_CFG_OVERRIDE_RAND_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_CFG_OVERRIDE_FLAG 8:8 /* RWIVF */ #define NV_CPWR_THERM_ARP_CFG_OVERRIDE_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_CFG_RSVD_COMMAND_CHECK 4:4 /* RWIVF */ #define NV_CPWR_THERM_ARP_CFG_RSVD_COMMAND_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ARP_CFG_RSVD_COMMAND_CHECK_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ARP_CFG_RSVD_DEV_ADDR_CHECK 3:3 /* RWIVF */ #define NV_CPWR_THERM_ARP_CFG_RSVD_DEV_ADDR_CHECK_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_CFG_RSVD_DEV_ADDR_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ARP_CFG_AV_FLAG 1:1 /* RWIVF */ #define NV_CPWR_THERM_ARP_CFG_AV_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_CFG_AR_FLAG 0:0 /* RWIVF */ #define NV_CPWR_THERM_ARP_CFG_AR_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_STATUS 0x000200a4 /* R--4R */ #define NV_CPWR_THERM_ARP_STATUS__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_ARP_STATUS_ARP_ADR 31:25 /* R-IVF */ #define NV_CPWR_THERM_ARP_STATUS_ARP_ADR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ARP_STATUS_AV_FLAG 24:24 /* R-IUF */ #define NV_CPWR_THERM_ARP_STATUS_AV_FLAG_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ARP_STATUS_AR_FLAG 16:16 /* R-IUF */ #define NV_CPWR_THERM_ARP_STATUS_AR_FLAG_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ARP_STATUS_RANDOM 15:0 /* R-IUF */ #define NV_CPWR_THERM_ARP_STATUS_RANDOM_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ARP_UDID_3 0x000200a8 /* RW-4R */ #define NV_CPWR_THERM_ARP_UDID_3__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_ARP_UDID_3_DCAP 31:24 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_3_DCAP_INIT 0x000000c1 /* RWI-V */ #define NV_CPWR_THERM_ARP_UDID_3_VER_REV 23:16 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_3_VER_REV_INIT 0x00000009 /* RWI-V */ #define NV_CPWR_THERM_ARP_UDID_3_VENDOR_ID 15:0 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_3_VENDOR_ID_INIT 0x000010de /* RWI-V */ #define NV_CPWR_THERM_ARP_UDID_2 0x000200ac /* RW-4R */ #define NV_CPWR_THERM_ARP_UDID_2__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_ARP_UDID_2_DEV_ID 31:16 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_2_DEV_ID_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_UDID_2_INTERFACE 15:0 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_2_INTERFACE_INIT 0x00000004 /* RWI-V */ #define NV_CPWR_THERM_ARP_UDID_1 0x000200b0 /* RW-4R */ #define NV_CPWR_THERM_ARP_UDID_1__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_ARP_UDID_1_SUB_VENDOR 31:16 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_1_SUB_VENDOR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_UDID_1_SUB_DEVICE 15:0 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_1_SUB_DEVICE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_UDID_0 0x000200b4 /* RW-4R */ #define NV_CPWR_THERM_ARP_UDID_0__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_ARP_UDID_0_VENDOR_SPEC 31:16 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_0_VENDOR_SPEC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ARP_UDID_0_VENDOR_RAND 15:0 /* RWIVF */ #define NV_CPWR_THERM_ARP_UDID_0_VENDOR_RAND_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_STATE 0x00020084 /* R--4R */ #define NV_CPWR_THERM_I2CS_STATE__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_STATE_VALUE 31:0 /* R-IUF */ #define NV_CPWR_THERM_I2CS_STATE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2CS_STATE_VALUE_SLAVE_ADR 6:0 /* */ #define NV_CPWR_THERM_I2CS_STATE_VALUE_SLAVE_IDLE 7:7 /* */ #define NV_CPWR_THERM_I2CS_STATE_VALUE_COMMAND 15:8 /* */ #define NV_CPWR_THERM_I2CS_STATE_VALUE_DATA_IN 23:16 /* */ #define NV_CPWR_THERM_I2CS_STATE_VALUE_PEC 31:24 /* */ #define NV_CPWR_THERM_I2CS_PRIV_ADDR 0x00020088 /* R--4R */ #define NV_CPWR_THERM_I2CS_PRIV_ADDR__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_PRIV_ADDR_VALUE 31:0 /* R-IUF */ #define NV_CPWR_THERM_I2CS_PRIV_ADDR_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2CS_PRIV_RDATA 0x0002008c /* R--4R */ #define NV_CPWR_THERM_I2CS_PRIV_RDATA__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_PRIV_RDATA_VALUE 31:0 /* R-IUF */ #define NV_CPWR_THERM_I2CS_PRIV_RDATA_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2CS_PRIV_WDATA 0x00020090 /* R--4R */ #define NV_CPWR_THERM_I2CS_PRIV_WDATA__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_PRIV_WDATA_VALUE 31:0 /* R-IUF */ #define NV_CPWR_THERM_I2CS_PRIV_WDATA_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TSENSE_0 0x00020124 /* RW-4R */ #define NV_CPWR_THERM_TSENSE_0__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_TSENSE_0_CALI_SRC 9:9 /* RWIVF */ #define NV_CPWR_THERM_TSENSE_0_CALI_SRC_FUSE 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_TSENSE_0_CALI_SRC_REG 0x00000000 /* RW--V */ #define NV_CPWR_THERM_TSENSE_0_TC_SRC 10:10 /* RWIVF */ #define NV_CPWR_THERM_TSENSE_0_TC_SRC_FUSE 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_TSENSE_0_TC_SRC_REG 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWM0 0x000200d8 /* RW-4R */ #define NV_CPWR_THERM_PWM0__PRIV_LEVEL_MASK 0x00020384 /* */ #define NV_CPWR_THERM_PWM0_PERIOD 12:0 /* RWIVF */ #define NV_CPWR_THERM_PWM0_PERIOD_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PWM0_PERIOD_125KHZ 0x000000d8 /* RWI-V */ #define NV_CPWR_THERM_PWM0_PERIOD_MAX 0x00001fff /* RW--V */ #define NV_CPWR_THERM_PWM0_SHARING 24:24 /* RWIVF */ #define NV_CPWR_THERM_PWM0_SHARING_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_PWM0_SHARING_ENABLE 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_PWM_TEMP_ALERT 0x000200cc /* RW-4R */ #define NV_CPWR_THERM_PWM_TEMP_ALERT__PRIV_LEVEL_MASK 0x00020384 /* */ #define NV_CPWR_THERM_PWM_TEMP_ALERT_HI 12:0 /* RWIVF */ #define NV_CPWR_THERM_PWM_TEMP_ALERT_HI_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PWM_TEMP_ALERT_OVERRIDE 24:24 /* RWIVF */ #define NV_CPWR_THERM_PWM_TEMP_ALERT_OVERRIDE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PWM_TEMP_ALERT_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PWM_TEMP_ALERT_FAKE 25:25 /* RWIVF */ #define NV_CPWR_THERM_PWM_TEMP_ALERT_FAKE_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PWM_TEMP_ALERT_FAKE_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_PWM1 0x000200dc /* RW-4R */ #define NV_CPWR_THERM_PWM1__PRIV_LEVEL_MASK 0x00020384 /* */ #define NV_CPWR_THERM_PWM1_HI 12:0 /* RWIVF */ #define NV_CPWR_THERM_PWM1_HI_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_PWM1_NEW_REQUEST 30:30 /* RWIVF */ #define NV_CPWR_THERM_PWM1_NEW_REQUEST_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PWM1_NEW_REQUEST_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_PWM1_SETTING_NEW 31:31 /* R-IVF */ #define NV_CPWR_THERM_PWM1_SETTING_NEW_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PWM1_SETTING_NEW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_PWM_ACT0 0x000200c4 /* RW-4R */ #define NV_CPWR_THERM_PWM_ACT0__PRIV_LEVEL_MASK 0x00020380 /* */ #define NV_CPWR_THERM_PWM_ACT0_PERIOD 18:0 /* R-IUF */ #define NV_CPWR_THERM_PWM_ACT0_PERIOD_125KHZ 0x000000d8 /* R-I-V */ #define NV_CPWR_THERM_PWM_ACT0_PERIOD_MAX 0x0007ffff /* R---V */ #define NV_CPWR_THERM_PWM_ACT0_OVERFLOW 24:24 /* RWIVF */ #define NV_CPWR_THERM_PWM_ACT0_OVERFLOW_NONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PWM_ACT0_OVERFLOW_DETECTED 0x00000001 /* R---V */ #define NV_CPWR_THERM_PWM_ACT0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_PWM_ACT1 0x000200c8 /* R--4R */ #define NV_CPWR_THERM_PWM_ACT1__PRIV_LEVEL_MASK 0x00020380 /* */ #define NV_CPWR_THERM_PWM_ACT1_HI 18:0 /* R-IUF */ #define NV_CPWR_THERM_PWM_ACT1_HI_OFF 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_PWM_ACT1_HI_MAX 0x0007ffff /* R---V */ #define NV_CPWR_THERM_VID0_PWM(i) (0x00020340+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_VID0_PWM__SIZE_1 4 /* */ #define NV_CPWR_THERM_VID0_PWM__PRIV_LEVEL_MASK 0x0002032c /* */ #define NV_CPWR_THERM_VID0_PWM_PERIOD 11:0 /* RWIVF */ #define NV_CPWR_THERM_VID0_PWM_PERIOD_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_VID0_PWM_PERIOD_125KHZ 0x00000360 /* RWI-V */ #define NV_CPWR_THERM_VID0_PWM_PERIOD_MAX 0x00000fff /* RW--V */ #define NV_CPWR_THERM_VID0_PWM_SAFE_VOLTAGE_EN 12:12 /* RWIVF */ #define NV_CPWR_THERM_VID0_PWM_SAFE_VOLTAGE_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID0_PWM_SAFE_VOLTAGE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_VID0_PWM_IPC_HI_OFFSET_UPDATE 13:13 /* RWIVF */ #define NV_CPWR_THERM_VID0_PWM_IPC_HI_OFFSET_UPDATE_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID0_PWM_IPC_HI_OFFSET_UPDATE_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_VID0_PWM_USE_IPC 14:14 /* RWIVF */ #define NV_CPWR_THERM_VID0_PWM_USE_IPC_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID0_PWM_USE_IPC_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_VID0_PWM_USE_FIXED_SLEWRATE 15:15 /* RWIVF */ #define NV_CPWR_THERM_VID0_PWM_USE_FIXED_SLEWRATE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID0_PWM_USE_FIXED_SLEWRATE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_VID0_PWM_DELAY_PERIOD 23:16 /* RWIVF */ #define NV_CPWR_THERM_VID0_PWM_DELAY_PERIOD_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID0_PWM_BIT_SPREAD 24:24 /* RWIVF */ #define NV_CPWR_THERM_VID0_PWM_BIT_SPREAD_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID0_PWM_BIT_SPREAD_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_VID0_PWM_MIN_SPREAD 30:25 /* RWIUF */ #define NV_CPWR_THERM_VID0_PWM_MIN_SPREAD_SHORTEST 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID1_PWM(i) (0x00020414+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_VID1_PWM__SIZE_1 4 /* */ #define NV_CPWR_THERM_VID1_PWM__PRIV_LEVEL_MASK 0x0002032c /* */ #define NV_CPWR_THERM_VID1_PWM_HI 11:0 /* RWIVF */ #define NV_CPWR_THERM_VID1_PWM_HI_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID2_PWM(i) (0x000202d0+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_VID2_PWM__SIZE_1 4 /* */ #define NV_CPWR_THERM_VID2_PWM__PRIV_LEVEL_MASK 0x0002032c /* */ #define NV_CPWR_THERM_VID2_PWM_IPC_HI_MIN 11:0 /* RWIVF */ #define NV_CPWR_THERM_VID2_PWM_IPC_HI_MIN_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID3_PWM(i) (0x0002042c+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_VID3_PWM__SIZE_1 4 /* */ #define NV_CPWR_THERM_VID3_PWM__PRIV_LEVEL_MASK 0x0002032c /* */ #define NV_CPWR_THERM_VID3_PWM_RISING 11:0 /* RWIVF */ #define NV_CPWR_THERM_VID3_PWM_RISING_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID3_PWM_FALLING 23:12 /* RWIVF */ #define NV_CPWR_THERM_VID3_PWM_FALLING_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID3_PWM_REPEAT 27:24 /* RWIVF */ #define NV_CPWR_THERM_VID3_PWM_REPEAT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID3_PWM_STEP 31:28 /* RWIVF */ #define NV_CPWR_THERM_VID3_PWM_STEP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID4_PWM(i) (0x000208e8+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_VID4_PWM__SIZE_1 4 /* */ #define NV_CPWR_THERM_VID4_PWM__PRIV_LEVEL_MASK 0x0002032c /* */ #define NV_CPWR_THERM_VID4_PWM_SAFE_VOLTAGE_HI 11:0 /* RWIVF */ #define NV_CPWR_THERM_VID4_PWM_SAFE_VOLTAGE_HI_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK 0x0002033c /* RW-4R */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK__PRIV_LEVEL_MASK 0x0002032c /* */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW(i) (i):(i) /* */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW__SIZE_1 4 /* */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW_DONE 0x00000000 /* */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW_PENDING 0x00000001 /* */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_SETTING_NEW_TRIGGER 0x00000001 /* */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_0_SETTING_NEW 0:0 /* RWIVF */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_0_SETTING_NEW_DONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_0_SETTING_NEW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_0_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_1_SETTING_NEW 1:1 /* RWIVF */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_1_SETTING_NEW_DONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_1_SETTING_NEW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_1_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_2_SETTING_NEW 2:2 /* RWIVF */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_2_SETTING_NEW_DONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_2_SETTING_NEW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_2_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_3_SETTING_NEW 3:3 /* RWIVF */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_3_SETTING_NEW_DONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_3_SETTING_NEW_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_VID_PWM_TRIGGER_MASK_3_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_FAN_TACHA(i) (0x000204e0+(i)*8) /* RW-4A */ #define NV_CPWR_THERM_FAN_TACHA__SIZE_1 2 /* */ #define NV_CPWR_THERM_FAN_TACHA__PRIV_LEVEL_MASK 0x00020388 /* */ #define NV_CPWR_THERM_FAN_TACHA_PERIOD 18:0 /* R-IUF */ #define NV_CPWR_THERM_FAN_TACHA_PERIOD_MIN 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_FAN_TACHA_PERIOD_MAX 0x0007ffff /* R---V */ #define NV_CPWR_THERM_FAN_TACHA_OVERFLOW 24:24 /* RWIVF */ #define NV_CPWR_THERM_FAN_TACHA_OVERFLOW_NONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_FAN_TACHA_OVERFLOW_DETECTED 0x00000001 /* R---V */ #define NV_CPWR_THERM_FAN_TACHA_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_FAN_TACHA_WIN_LENGTH 26:25 /* RWIVF */ #define NV_CPWR_THERM_FAN_TACHA_WIN_LENGTH_ONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_FAN_TACHA_WIN_LENGTH_TWO 0x00000001 /* RW--V */ #define NV_CPWR_THERM_FAN_TACHA_WIN_LENGTH_FOUR 0x00000002 /* RW--V */ #define NV_CPWR_THERM_FAN_TACHA_WIN_LENGTH_EIGHT 0x00000003 /* RW--V */ #define NV_CPWR_THERM_FAN_TACHB(i) (0x000204e4+(i)*8) /* R--4A */ #define NV_CPWR_THERM_FAN_TACHB__SIZE_1 2 /* */ #define NV_CPWR_THERM_FAN_TACHB__PRIV_LEVEL_MASK 0x00020388 /* */ #define NV_CPWR_THERM_FAN_TACHB_HI 18:0 /* R-IUF */ #define NV_CPWR_THERM_FAN_TACHB_HI_OFF 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_FAN_TACHB_HI_MAX 0x0007ffff /* R---V */ #define NV_CPWR_THERM_MSGBOX_COMMAND 0x000200e0 /* RW-4R */ #define NV_CPWR_THERM_MSGBOX_COMMAND__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_MSGBOX_COMMAND_DATA 30:0 /* RWIVF */ #define NV_CPWR_THERM_MSGBOX_COMMAND_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MSGBOX_COMMAND_INTR 31:31 /* RWIVF */ #define NV_CPWR_THERM_MSGBOX_COMMAND_INTR_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MSGBOX_COMMAND_INTR_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_MSGBOX_DATA_IN 0x000200e4 /* RW-4R */ #define NV_CPWR_THERM_MSGBOX_DATA_IN__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_MSGBOX_DATA_IN_DATA 31:0 /* RWIVF */ #define NV_CPWR_THERM_MSGBOX_DATA_IN_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MSGBOX_DATA_OUT 0x000200e8 /* RW-4R */ #define NV_CPWR_THERM_MSGBOX_DATA_OUT__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_MSGBOX_DATA_OUT_DATA 31:0 /* RWIVF */ #define NV_CPWR_THERM_MSGBOX_DATA_OUT_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_MSGBOX_MUTEX 0x000200ec /* RW-4R */ #define NV_CPWR_THERM_MSGBOX_MUTEX__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_MSGBOX_MUTEX_CLIENT 7:0 /* RWIVF */ #define NV_CPWR_THERM_MSGBOX_MUTEX_CLIENT_NONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_I2CS_ENABLE 0x000203fc /* RW-4R */ #define NV_CPWR_THERM_THERMAL_I2CS_ENABLE__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_THERMAL_I2CS_ENABLE_WRITE 0:0 /* RWIUF */ #define NV_CPWR_THERM_THERMAL_I2CS_ENABLE_WRITE_DIS 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_I2CS_ENABLE_WRITE_EN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_THERMAL_I2CS_ENABLE_READ 1:1 /* RWIUF */ #define NV_CPWR_THERM_THERMAL_I2CS_ENABLE_READ_DIS 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_THERMAL_I2CS_ENABLE_READ_EN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_00 0x00020400 /* R--4R */ #define NV_CPWR_THERM_I2CS_SENSOR_00__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_00_RLTS 7:0 /* R-IUF */ #define NV_CPWR_THERM_I2CS_SENSOR_00_RLTS_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01 0x00020404 /* RW-4R */ #define NV_CPWR_THERM_I2CS_SENSOR_01__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_0 0:0 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_0_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_0_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_1 1:1 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_1_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_1_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_2 2:2 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_2_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_2_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_3 3:3 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_3_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_3_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_4 4:4 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_4_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_4_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_5 5:5 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_5_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_5_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_6 6:6 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_6_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_6_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_7 7:7 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_7_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_01_RSL_THERMAL_7_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_02 0x00020408 /* RW-4R */ #define NV_CPWR_THERM_I2CS_SENSOR_02__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_8 0:0 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_8_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_8_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_9 1:1 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_9_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_9_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_10 2:2 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_10_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_10_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_11 3:3 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_11_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_02_RSL_THERMAL_11_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_03 0x0002040c /* RW-4R */ #define NV_CPWR_THERM_I2CS_SENSOR_03__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_0_EN 0:0 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_0_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_0_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_1_EN 1:1 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_1_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_1_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_2_EN 2:2 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_2_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_2_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_3_EN 3:3 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_3_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_3_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_4_EN 4:4 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_4_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_4_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_5_EN 5:5 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_5_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_5_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_6_EN 6:6 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_6_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_6_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_7_EN 7:7 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_7_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_03_RCL_THERMAL_7_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_04 0x00020410 /* RW-4R */ #define NV_CPWR_THERM_I2CS_SENSOR_04__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_8_EN 0:0 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_8_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_8_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_9_EN 1:1 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_9_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_9_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_10_EN 2:2 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_10_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_10_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_11_EN 3:3 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_11_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_04_RCL_THERMAL_11_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_11 0x00020444 /* R--4R */ #define NV_CPWR_THERM_I2CS_SENSOR_11__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_11_RIET 7:0 /* R-IUF */ #define NV_CPWR_THERM_I2CS_SENSOR_11_RIET_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2CS_SENSOR_13 0x0002044c /* R--4R */ #define NV_CPWR_THERM_I2CS_SENSOR_13__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_13_UNCLAMPED_TEMP 7:0 /* R-ISF */ #define NV_CPWR_THERM_I2CS_SENSOR_13_UNCLAMPED_TEMP_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2CS_SENSOR_14 0x00020450 /* R--4R */ #define NV_CPWR_THERM_I2CS_SENSOR_14__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_14_NEG_TEMP_OFFSET 7:0 /* C--UF */ #define NV_CPWR_THERM_I2CS_SENSOR_14_NEG_TEMP_OFFSET_INIT 0x00000040 /* C---V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG 0x000204c8 /* RW-4R */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_VOLT 7:0 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_VOLT_INIT 0x00000040 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_TEMP_COEF 10:8 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_TEMP_COEF_INIT 0x00000002 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_MODE 11:11 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_MODE_AVG 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_MODE_NO_AVG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_VPTAT_BIAS_CURRENT 13:12 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_VPTAT_BIAS_CURRENT_INIT 0x00000003 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_BYPASS 14:14 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_BYPASS_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_BYPASS_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_STARTUP_BIAS_CURRENT 15:15 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BANDGAP_STARTUP_BIAS_CURRENT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT 19:16 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_TRISTATE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_GND 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VBG 0x00000002 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VPTAT 0x00000003 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_SELA_2 0x00000004 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_IB0 0x00000006 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_IPTAT 0x00000008 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_IBG 0x00000009 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VDD 0x0000000c /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VMOD 0x0000000d /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_VDD1V8_IN 0x0000000e /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_TS_VREF_OUTPUT_PLL_ADC_TEST_IN 0x0000000f /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_PTAT_BIPOLAR_SWAP 20:20 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_PTAT_BIPOLAR_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_PTAT_BIPOLAR_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_PTAT_OPAMP_SWAP 21:21 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_PTAT_OPAMP_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_PTAT_OPAMP_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_PTAT_SOURCE 25:22 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_PTAT_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_STOP_SWAP 26:26 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_STOP_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_STOP_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BYPASS_PTAT 27:27 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BYPASS_PTAT_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_BYPASS_PTAT_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_SEND_VBG 28:28 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_SEND_VBG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_AVERAGE_VBG 29:29 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_AVERAGE_VBG_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_AVERAGE_VBG_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_START_BANDGAP 30:30 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_START_BANDGAP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_STOP_SWAPPING_BJT 31:31 /* RWIUF */ #define NV_CPWR_THERM_I2CS_SENSOR_TSCFG_STOP_SWAPPING_BJT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_FE 0x000207f8 /* RW-4R */ #define NV_CPWR_THERM_I2CS_SENSOR_FE__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_FE_VENDOR_ID 15:0 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_FE_VENDOR_ID_INIT 0x000010de /* RWI-V */ #define NV_CPWR_THERM_I2CS_SENSOR_FF 0x000207fc /* RW-4R */ #define NV_CPWR_THERM_I2CS_SENSOR_FF__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2CS_SENSOR_FF_REV_ID 7:0 /* RWIVF */ #define NV_CPWR_THERM_I2CS_SENSOR_FF_REV_ID_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GLOBAL_OVERRIDES 0x00020280 /* RW-4R */ #define NV_CPWR_THERM_GLOBAL_OVERRIDES__PRIV_LEVEL_MASK 0x000203a0 /* */ #define NV_CPWR_THERM_GLOBAL_OVERRIDES_NONHOST_BLK_CLK 0:0 /* RWIVF */ #define NV_CPWR_THERM_GLOBAL_OVERRIDES_NONHOST_BLK_CLK_RUN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GLOBAL_OVERRIDES_NONHOST_BLK_CLK_AUTO 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL(i) (0x00020200+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_GATE_CTRL__SIZE_1 11 /* */ #define NV_CPWR_THERM_GATE_CTRL__PRIV_LEVEL_MASK 0x000203a0 /* */ #define NV_CPWR_THERM_GATE_CTRL_ENG_CLK 1:0 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_ENG_CLK_RUN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_CLK_AUTO 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_CLK_STOP 0x00000002 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_CLK 3:2 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_BLK_CLK_RUN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_CLK_AUTO 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_IDLE_HOLDOFF 4:4 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_IDLE_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_IDLE_HOLDOFF_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_PWR 7:6 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_BLK_PWR_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_PWR_AUTO 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP_MAX 0x0000001f /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP__PROD 0x00000002 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT_MAX 0x00000007 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT__PROD 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_BEFORE 19:16 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_BEFORE_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_BEFORE_INIT 0x00000008 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_BEFORE_MAX 0x0000000f /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_BEFORE__PROD 0x00000008 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_AFTER_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_AFTER_INIT 0x00000005 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_AFTER_MAX 0x0000000f /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_ENG_DELAY_AFTER__PROD 0x00000005 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_OVR_DELAY_BEFORE 27:24 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_BLK_OVR_DELAY_BEFORE_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_OVR_DELAY_BEFORE_INIT 0x00000002 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_OVR_DELAY_BEFORE_MAX 0x0000000f /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_OVR_DELAY_AFTER 31:28 /* RWIVF */ #define NV_CPWR_THERM_GATE_CTRL_BLK_OVR_DELAY_AFTER_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_OVR_DELAY_AFTER_INIT 0x00000002 /* RWI-V */ #define NV_CPWR_THERM_GATE_CTRL_BLK_OVR_DELAY_AFTER_MAX 0x0000000f /* RW--V */ #define NV_CPWR_THERM_FECS_IDLE_FILTER 0x00020288 /* RW-4R */ #define NV_CPWR_THERM_FECS_IDLE_FILTER__PRIV_LEVEL_MASK 0x0002039c /* */ #define NV_CPWR_THERM_FECS_IDLE_FILTER_VALUE 31:0 /* RWIVF */ #define NV_CPWR_THERM_FECS_IDLE_FILTER_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_FECS_IDLE_FILTER_VALUE_MAX 0xffffffff /* RW--V */ #define NV_CPWR_THERM_FECS_IDLE_FILTER_VALUE__PROD 0x00000000 /* RW--V */ #define NV_CPWR_THERM_HUBMMU_IDLE_FILTER 0x0002028c /* RW-4R */ #define NV_CPWR_THERM_HUBMMU_IDLE_FILTER__PRIV_LEVEL_MASK 0x0002039c /* */ #define NV_CPWR_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 /* RWIVF */ #define NV_CPWR_THERM_HUBMMU_IDLE_FILTER_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_HUBMMU_IDLE_FILTER_VALUE_MAX 0xffffffff /* RW--V */ #define NV_CPWR_THERM_HUBMMU_IDLE_FILTER_VALUE__PROD 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF 0x00020290 /* RW-4R */ #define NV_CPWR_THERM_ENG_HOLDOFF__PRIV_LEVEL_MASK 0x000203a0 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG0 0:0 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG0_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG0_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG1 1:1 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG1_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG1_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG2 2:2 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG2_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG2_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG3 3:3 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG3_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG3_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG4 4:4 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG4_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG4_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG5 5:5 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG5_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG5_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG6 6:6 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG6_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG6_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG7 7:7 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG7_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG7_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG8 8:8 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG8_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG8_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG9 9:9 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG9_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG9_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG10 10:10 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG10_NOTBLOCKED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG10_BLOCKED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG_HW_SIZE 26 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG(i) (0+(i)):(0+(i)) /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG__SIZE_1 11 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG_NOTBLOCKED 0x00000000 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENG_BLOCKED 0x00000001 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS 0x00020294 /* R--4R */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS__PRIV_LEVEL_MASK 0x0002039c /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG0 0:0 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG0_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG1 1:1 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG1_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG2 2:2 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG2_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG2_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG3 3:3 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG3_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG3_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG4 4:4 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG4_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG4_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG5 5:5 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG5_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG5_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG6 6:6 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG6_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG6_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG7 7:7 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG7_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG7_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG8 8:8 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG8_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG8_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG9 9:9 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG9_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG9_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG10 10:10 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG10_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG10_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG(i) (0+(i)):(0+(i)) /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG__SIZE_1 11 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG_NOTBLOCKED 0x00000000 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_STATUS_ENG_BLOCKED 0x00000001 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER 0x0002030c /* R--4R */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER__PRIV_LEVEL_MASK 0x0002039c /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG0 0:0 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG0_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG0_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG1 1:1 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG1_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG1_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG2 2:2 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG2_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG2_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG3 3:3 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG3_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG3_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG4 4:4 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG4_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG4_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG5 5:5 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG5_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG5_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG6 6:6 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG6_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG6_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG7 7:7 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG7_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG7_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG8 8:8 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG8_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG8_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG9 9:9 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG9_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG9_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG10 10:10 /* R-IVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG10_NOT_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG10_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG(i) (0+(i)):(0+(i)) /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG__SIZE_1 11 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG_NOTDONE 0x00000000 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_ENTER_ENG_DONE 0x00000001 /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN 0x00020308 /* RW-4R */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN__PRIV_LEVEL_MASK 0x0002039c /* */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG0 0:0 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG0_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG0_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG1 1:1 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG1_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG1_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG2 2:2 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG2_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG2_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG3 3:3 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG3_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG3_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG4 4:4 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG4_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG4_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG5 5:5 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG5_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG5_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG6 6:6 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG6_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG6_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG7 7:7 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG7_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG7_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG8 8:8 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG8_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG8_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG9 9:9 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG9_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG9_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG10 10:10 /* RWIVF */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG10_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ENG_HOLDOFF_INTR_EN_ENG10_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWERCTRL_0 0x0002029c /* RW-4R */ #define NV_CPWR_THERM_POWERCTRL_0__PRIV_LEVEL_MASK 0x00020320 /* */ #define NV_CPWR_THERM_POWERCTRL_0_FULLP_PULLDOWN 21:21 /* RWIVF */ #define NV_CPWR_THERM_POWERCTRL_0_FULLP_PULLDOWN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWERCTRL_0_FULLP_PULLDOWN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_POWERCTRL_0_PADS_WEAKPULL 22:22 /* RWIVF */ #define NV_CPWR_THERM_POWERCTRL_0_PADS_WEAKPULL_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_POWERCTRL_0_PADS_WEAKPULL_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DBG_2 0x0002007c /* RW-4R */ #define NV_CPWR_THERM_DBG_2__PRIV_LEVEL_MASK 0x0002039c /* */ #define NV_CPWR_THERM_DBG_2_CFG_ERR_REASON 23:16 /* R-IVF */ #define NV_CPWR_THERM_DBG_2_CFG_ERR_REASON_NONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_DBG_2_FAST_TIMER_MODE 24:24 /* RWIVF */ #define NV_CPWR_THERM_DBG_2_FAST_TIMER_MODE_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DBG_2_FAST_TIMER_MODE_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DBG_2_ENG_SM 25:25 /* RWIVF */ #define NV_CPWR_THERM_DBG_2_ENG_SM_DEFAULT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DBG_2_ENG_SM_RUN_ALWAYS 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DBG_2_FBP_CLK_FORCE 30:29 /* R-XVF */ #define NV_CPWR_THERM_DBG_2_FBP_CLK_FORCE_CLK_RUN 0x00000000 /* R---V */ #define NV_CPWR_THERM_DBG_2_FBP_CLK_FORCE_CLK_AUTO 0x00000001 /* R---V */ #define NV_CPWR_THERM_DBG_2_FBP_CLK_FORCE_CLK_STOP 0x00000002 /* R---V */ #define NV_CPWR_THERM_DBG_2_FBP_GATEABLE 31:31 /* R-XVF */ #define NV_CPWR_THERM_DBG_2_FBP_GATEABLE_DEASSERTED 0x00000000 /* R---V */ #define NV_CPWR_THERM_DBG_2_FBP_GATEABLE_ASSERTED 0x00000001 /* R---V */ #define NV_CPWR_THERM_ECO 0x0002050c /* RW-4R */ #define NV_CPWR_THERM_ECO_BIT0 0:0 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT0_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT1 1:1 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT2 2:2 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT3 3:3 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT4 4:4 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT5 5:5 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT5_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT6 6:6 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT6_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT7 7:7 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT7_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT8 8:8 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT8_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT9 9:9 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT9_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT10 10:10 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT10_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT11 11:11 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT11_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT12 12:12 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT12_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT13 13:13 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT13_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT14 14:14 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT14_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_ECO_BIT15 15:15 /* RWIVF */ #define NV_CPWR_THERM_ECO_BIT15_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_STATISTICS_BA_MAX 0x00020500 /* RW-4R */ #define NV_CPWR_THERM_STATISTICS_BA_MAX_DATA 19:0 /* R-IUF */ #define NV_CPWR_THERM_STATISTICS_BA_MAX_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_STATISTICS_BA_MAX_RESET 31:31 /* RWIVF */ #define NV_CPWR_THERM_STATISTICS_BA_MAX_RESET_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_STATISTICS_BA_MAX_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_STATISTICS_BA_MIN 0x00020504 /* RW-4R */ #define NV_CPWR_THERM_STATISTICS_BA_MIN_DATA 19:0 /* R-IUF */ #define NV_CPWR_THERM_STATISTICS_BA_MIN_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_STATISTICS_BA_MIN_RESET 31:31 /* RWIVF */ #define NV_CPWR_THERM_STATISTICS_BA_MIN_RESET_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_STATISTICS_BA_MIN_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_STATISTICS_BA_MAXDBA 0x00020508 /* RW-4R */ #define NV_CPWR_THERM_STATISTICS_BA_MAXDBA_DATA 19:0 /* R-IUF */ #define NV_CPWR_THERM_STATISTICS_BA_MAXDBA_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_STATISTICS_BA_MAXDBA_RESET 31:31 /* RWIVF */ #define NV_CPWR_THERM_STATISTICS_BA_MAXDBA_RESET_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_STATISTICS_BA_MAXDBA_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_STATISTICS_TEMP_AVG 0x00020510 /* RW-4R */ #define NV_CPWR_THERM_STATISTICS_TEMP_AVG_DATA 7:0 /* R-IUF */ #define NV_CPWR_THERM_STATISTICS_TEMP_AVG_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_STATISTICS_TEMP_AVG_RESET 8:8 /* RWIVF */ #define NV_CPWR_THERM_STATISTICS_TEMP_AVG_RESET_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_STATISTICS_TEMP_AVG_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_STATISTICS_CTRL 0x00020514 /* RW-4R */ #define NV_CPWR_THERM_STATISTICS_CTRL_BA 0:0 /* RWIVF */ #define NV_CPWR_THERM_STATISTICS_CTRL_BA_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_STATISTICS_CTRL_BA_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_STATISTICS_CTRL_TEMP 1:1 /* RWIVF */ #define NV_CPWR_THERM_STATISTICS_CTRL_TEMP_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_STATISTICS_CTRL_TEMP_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH0_ADDR 0x0002051c /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH0_ADDR__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH0_ADDR_VALUE 7:1 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH0_ADDR_VALUE_INIT 0x0000004a /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH0_ADDR_READY 31:31 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH0_ADDR_READY_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH0_ADDR_READY_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH1_ADDR 0x00020520 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH1_ADDR__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH1_ADDR_VALUE 7:1 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH1_ADDR_VALUE_INIT 0x0000004b /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH1_ADDR_READY 31:31 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH1_ADDR_READY_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH1_ADDR_READY_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0 0x00020524 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_INDEX 8:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_INDEX_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_INDEX_MAX 0x000001ff /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_READINCR 16:16 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_READINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_READINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_WRITEINCR 17:17 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_WRITEINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX0_WRITEINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1 0x00020538 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_INDEX 8:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_INDEX_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_INDEX_MAX 0x000001ff /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_READINCR 16:16 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_READINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_READINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_WRITEINCR 17:17 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_WRITEINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX1_WRITEINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2 0x0002054c /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_INDEX 8:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_INDEX_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_INDEX_MAX 0x000001ff /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_READINCR 16:16 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_READINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_READINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_WRITEINCR 17:17 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_WRITEINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX2_WRITEINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3 0x00020560 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_INDEX 8:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_INDEX_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_INDEX_MAX 0x000001ff /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_READINCR 16:16 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_READINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_READINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_WRITEINCR 17:17 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_WRITEINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INDEX3_WRITEINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA0 0x00020528 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA0__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA0__APERTURE_INDEX_OFFSET (0x00000524-0x00000528) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA0_VALUE 31:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA0_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA1 0x0002053c /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA1__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA1__APERTURE_INDEX_OFFSET (0x00000538-0x0000053C) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA1_VALUE 31:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA1_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA2 0x00020550 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA2__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA2__APERTURE_INDEX_OFFSET (0x0000054C-0x00000550) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA2_VALUE 31:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA2_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA3 0x00020564 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA3__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA3__APERTURE_INDEX_OFFSET (0x00000560-0x00000564) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA3_VALUE 31:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_DATA3_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0 0x0002052c /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0__APERTURE_INDEX_OFFSET (0x00000524-0x0000052C) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE 31:30 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE_SET_NACK 0x00000000 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE_SET_RO 0x00000001 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE_SET_RW 0x00000002 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE_SET_NONE 0x00000003 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE_NACK 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE_RO 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE_RW 0x00000002 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE0_STATE_NONE 0x00000003 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1 0x00020540 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1__APERTURE_INDEX_OFFSET (0x00000538-0x00000540) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE 31:30 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE_SET_NACK 0x00000000 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE_SET_RO 0x00000001 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE_SET_RW 0x00000002 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE_SET_NONE 0x00000003 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE_NACK 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE_RO 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE_RW 0x00000002 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE1_STATE_NONE 0x00000003 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2 0x00020554 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2__APERTURE_INDEX_OFFSET (0x0000054C-0x00000554) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE 31:30 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE_SET_NACK 0x00000000 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE_SET_RO 0x00000001 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE_SET_RW 0x00000002 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE_SET_NONE 0x00000003 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE_NACK 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE_RO 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE_RW 0x00000002 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE2_STATE_NONE 0x00000003 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3 0x00020568 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3__APERTURE_INDEX_OFFSET (0x00000560-0x00000568) /* */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE 31:30 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE_SET_NACK 0x00000000 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE_SET_RO 0x00000001 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE_SET_RW 0x00000002 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE_SET_NONE 0x00000003 /* -W--V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE_NACK 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE_RO 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE_RW 0x00000002 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_STATE3_STATE_NONE 0x00000003 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_CTRL(i) (0x00020530+(i)*20) /* RW-4A */ #define NV_CPWR_THERM_I2C_SCRATCH_CTRL__SIZE_1 4 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_CTRL__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE 31:30 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE_INVALID 0x00000000 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE_RO 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE_RW 0x00000002 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_CTRL_SET_STATE_ON_WRITE_NONE 0x00000003 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_MUTEX(i) (0x00020534+(i)*20) /* RW-4A */ #define NV_CPWR_THERM_I2C_SCRATCH_MUTEX__SIZE_1 4 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_MUTEX__PRIV_LEVEL_MASK 0x0002038c /* */ #define NV_CPWR_THERM_I2C_SCRATCH_MUTEX_CLIENT 7:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_MUTEX_CLIENT_NONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE 0x00020588 /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR63 0:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR63_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR63_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR63_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR127 1:1 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR127_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR127_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR127_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR191 2:2 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR191_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR191_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR191_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR255 3:3 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR255_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR255_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR255_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR319 4:4 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR319_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR319_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR319_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR383 5:5 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR383_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR383_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR383_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR447 6:6 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR447_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR447_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR447_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR511 7:7 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR511_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR511_PENDING 0x00000001 /* R---V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_STATE_ADDR511_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN 0x0002058c /* RW-4R */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN__PRIV_LEVEL_MASK 0x00020390 /* */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR63 0:0 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR63_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR63_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR127 1:1 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR127_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR127_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR191 2:2 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR191_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR191_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR255 3:3 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR255_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR255_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR319 4:4 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR319_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR319_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR383 5:5 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR383_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR383_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR447 6:6 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR447_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR447_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR511 7:7 /* RWIVF */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR511_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_I2C_SCRATCH_INTR_EN_ADDR511_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_CG1 0x000206b8 /* RW-4R */ #define NV_CPWR_THERM_CG1_SLCG 3:0 /* RWIVF */ #define NV_CPWR_THERM_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_CG1_SLCG_DISABLED 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_CG1_SLCG__PROD 0x00000009 /* RW--V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK(i) (0x00020800+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK__SIZE_1 8 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK(i) (0x00020820+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK__SIZE_1 8 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_3_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK_3_SOURCE_ENABLE_IFF_GSP_PMU_ENABLED 0x0008004a /* RWI-V */ #define NV_CPWR_THERM_SCRATCH(i) (0x00020598+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_SCRATCH__SIZE_1 8 /* */ #define NV_CPWR_THERM_SCRATCH_VAL 31:0 /* RWIUF */ #define NV_CPWR_THERM_SCRATCH_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SECURE_SCRATCH(i) (0x000205b8+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_SECURE_SCRATCH__SIZE_1 8 /* */ #define NV_CPWR_THERM_SECURE_SCRATCH__PRIV_LEVEL_MASK NV_CPWR_THERM_SECURE_SCRATCH_PRIV_LEVEL_MASK /* */ #define NV_CPWR_THERM_SECURE_SCRATCH_VAL 31:0 /* RWIUF */ #define NV_CPWR_THERM_SECURE_SCRATCH_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SECURE_WR_SCRATCH(i) (0x000205d8+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_SECURE_WR_SCRATCH__SIZE_1 8 /* */ #define NV_CPWR_THERM_SECURE_WR_SCRATCH__PRIV_LEVEL_MASK NV_CPWR_THERM_SECURE_WRITE_SCRATCH_PRIV_LEVEL_MASK /* */ #define NV_CPWR_THERM_SECURE_WR_SCRATCH_VAL 31:0 /* RWIUF */ #define NV_CPWR_THERM_SECURE_WR_SCRATCH_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DUMMY 0x0002004c /* RW-4R */ #define NV_CPWR_THERM_DUMMY__PRIV_LEVEL_MASK 0x00020324 /* */ #define NV_CPWR_THERM_DUMMY_VALUE 0:0 /* RWIUF */ #define NV_CPWR_THERM_DUMMY_VALUE_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX 0x00020874 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX__PRIV_LEVEL_MASK 0x000203a0 /* */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_INDEX 2:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_INDEX_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_READINCR 8:8 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_WRITEINCR 9:9 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY 0x00020878 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY__APERTURE_INDEX_OFFSET (0x00000874-0x00000878) /* */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY__PRIV_LEVEL_MASK 0x000203a0 /* */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_NEW_SETTING 31:31 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_NEW_SETTING_NO_CMD 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_CONFIG_COPY_NEW_SETTING_SEND 0x00000001 /* RW--T */ #define NV_CPWR_THERM_GPC_INDEX 0x00020860 /* RW-4R */ #define NV_CPWR_THERM_GPC_INDEX__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_INDEX_INDEX 2:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_INDEX_INDEX_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_GPC_INDEX_READINCR 8:8 /* RWIVF */ #define NV_CPWR_THERM_GPC_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_INDEX_WRITEINCR 9:9 /* RWIVF */ #define NV_CPWR_THERM_GPC_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE 0x00020864 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE__APERTURE_INDEX_OFFSET (0x00000860-0x00000864) /* */ #define NV_CPWR_THERM_GPC_TSENSE__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_TSENSE_TS_ADC_OUT 13:0 /* R--VF */ #define NV_CPWR_THERM_GPC_TSENSE_STREAM_RAW_CODE 16:16 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_STREAM_RAW_CODE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_STREAM_RAW_CODE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_TS_BJT_SEL 23:20 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_TS_BJT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_TS_PD 24:24 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_TS_PD_DEASSERT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_TS_PD_ASSERT 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_CONTROL_SRC 28:28 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_CONTROL_SRC_LOGIC 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_CONTROL_SRC_REG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_CALI_SRC 29:29 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_CALI_SRC_FUSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_CALI_SRC_REG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_TC_SRC 30:30 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_TC_SRC_FUSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_TC_SRC_REG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ 0x00020868 /* RW-4R */ #define NV_CPWR_THERM_GPC_TS_ADJ__APERTURE_INDEX_OFFSET (0x00000860-0x00000868) /* */ #define NV_CPWR_THERM_GPC_TS_ADJ__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_TS_ADJ_VALUE 31:0 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_VALUE_INIT 0x00007240 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_VOLT 7:0 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_VOLT_INIT 0x00000040 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_TEMP_COEF 10:8 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_TEMP_COEF_INIT 0x00000002 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_MODE 11:11 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_MODE_AVG 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_MODE_NO_AVG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_VPTAT_BIAS_CURRENT 13:12 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_VPTAT_BIAS_CURRENT_INIT 0x00000003 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_BYPASS 14:14 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_BYPASS_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_BYPASS_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_STARTUP_BIAS_CURRENT 15:15 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_BANDGAP_STARTUP_BIAS_CURRENT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT 19:16 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_TRISTATE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_GND 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VBG 0x00000002 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VPTAT 0x00000003 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_SELA_2 0x00000004 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_IB0 0x00000006 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_IPTAT 0x00000008 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_IBG 0x00000009 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VDD 0x0000000c /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VMID 0x0000000d /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_VDD1V8_IN 0x0000000e /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_TS_VREF_OUTPUT_PLL_ADC_TEST_IN 0x0000000f /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_PTAT_BIPOLAR_SWAP 20:20 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_PTAT_BIPOLAR_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_PTAT_BIPOLAR_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_PTAT_OPAMP_SWAP 21:21 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_PTAT_OPAMP_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_PTAT_OPAMP_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_PTAT_SOURCE 25:22 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_PTAT_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_STOP_SWAP 26:26 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_STOP_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_STOP_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BYPASS_PTAT 27:27 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_BYPASS_PTAT_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_BYPASS_PTAT_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_SEND_VBG 28:28 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_SEND_VBG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_AVERAGE_VBG 29:29 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_AVERAGE_VBG_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_AVERAGE_VBG_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_ADJ_START_BANDGAP 30:30 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_START_BANDGAP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_ADJ_STOP_SWAPPING_BJT 31:31 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_ADJ_STOP_SWAPPING_BJT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_RAWCODE_OVERRIDE 0x0002086c /* RW-4R */ #define NV_CPWR_THERM_GPC_RAWCODE_OVERRIDE__APERTURE_INDEX_OFFSET (0x00000860-0x0000086C) /* */ #define NV_CPWR_THERM_GPC_RAWCODE_OVERRIDE__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_RAWCODE_OVERRIDE_VALUE 13:0 /* RWIUF */ #define NV_CPWR_THERM_GPC_RAWCODE_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_RAWCODE_OVERRIDE_EN 16:16 /* RWIUF */ #define NV_CPWR_THERM_GPC_RAWCODE_OVERRIDE_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_RAWCODE_OVERRIDE_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL 0x00020870 /* RW-4R */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL__APERTURE_INDEX_OFFSET (0x00000860-0x00000870) /* */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL_SAMPLE_DELAY 13:0 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL_SAMPLE_DELAY_INIT 0x00000834 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL_AUTO_POLLING 15:15 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL_AUTO_POLLING_OFF 0x00000000 /* RW--V */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL_AUTO_POLLING_ON 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL_POLLING_INTERVAL 31:16 /* RWIUF */ #define NV_CPWR_THERM_GPC_TS_AUTO_CONTROL_POLLING_INTERVAL_INIT 0x0000005a /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX 0x000206d4 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_GPC_BJT_INDEX 3:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_GPC_BJT_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_GPC_BJT_INDEX_MAX 0x00000002 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_GPC_INDEX 19:16 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_GPC_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_GPC_INDEX_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_READINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_RAW_CODE 0x000206ec /* R--4R */ #define NV_CPWR_THERM_GPC_TSENSE_RAW_CODE_VALUE 13:0 /* R--VF */ #define NV_CPWR_THERM_GPC_TSENSE_RAW_CODE_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_GPC_TSENSE_RAW_CODE_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_GPC_TSENSE_RAW_CODE_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_GPC_TSENSE_RAW_CODE_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_GPC_TSENSE_RAW_CODE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_GPC_TSENSE_RAW_CODE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED 0x000204b8 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_FIXED_POINT_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_INTEGER_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED 0x000204bc /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_FIXED_POINT_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_INTEGER_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE 0x000204c0 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_INTEGER_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE 0x000204c4 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_INTEGER_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX 0x000206d0 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_BJT_INDEX 3:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_BJT_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_BJT_INDEX_MAX 0x00000002 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_INDEX 19:16 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_GPC_INDEX_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_READINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_WRITEINCR 31:31 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE 0x000206d8 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_RSVD 14:0 /* C--VF */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_TEMP_SELECT 15:15 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_TEMP_SELECT_REAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_TEMP_SELECT_OVERRIDE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_TEMP_VALUE 29:16 /* RWISF */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_TEMP_VALUE_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_TEMP_INTEGER 29:21 /* */ #define NV_CPWR_THERM_GPC_TSENSE_OVERRIDE_TEMP_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_TSENSE_GLOBAL_OVERRIDE 0x000206dc /* RW-4R */ #define NV_CPWR_THERM_TSENSE_GLOBAL_OVERRIDE__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_TSENSE_GLOBAL_OVERRIDE_VALUE 13:0 /* RWISF */ #define NV_CPWR_THERM_TSENSE_GLOBAL_OVERRIDE_VALUE_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_TSENSE_GLOBAL_OVERRIDE_EN 16:16 /* RWIVF */ #define NV_CPWR_THERM_TSENSE_GLOBAL_OVERRIDE_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_TSENSE_GLOBAL_OVERRIDE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX 0x000206cc /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_BJT_INDEX 3:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_BJT_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_BJT_INDEX_MAX 0x00000002 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_INDEX 19:16 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_GPC_INDEX_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_READINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_WRITEINCR 31:31 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET 0x000206e4 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_FIXED_POINT 16:3 /* RWISF */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_FIXED_POINT_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_HS_OFFSET_INTEGER 16:8 /* */ #define NV_CPWR_THERM_ADC_RAW_CORRECTION 0x0002061c /* RW-4R */ #define NV_CPWR_THERM_ADC_RAW_CORRECTION__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_RAW_CORRECTION_VALUE 10:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_RAW_CORRECTION_VALUE_INIT 0x00000040 /* RWI-V */ #define NV_CPWR_THERM_ADC_RAW_CORRECTION_FLIP_POLARITY 16:16 /* RWIUF */ #define NV_CPWR_THERM_ADC_RAW_CORRECTION_FLIP_POLARITY_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_RAW_CORRECTION_FLIP_POLARITY_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL 0x00020620 /* RW-4R */ #define NV_CPWR_THERM_ADC_CTRL__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_CTRL_ADC_SENSING 0:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL_ADC_SENSING_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL_ADC_SENSING_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL_ADC_ACC 1:1 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL_ADC_ACC_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL_ADC_ACC_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL_SNAP 2:2 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL_SNAP_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ADC_CTRL_SNAP_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_ADC_CTRL_SNAP_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_ADC_CTRL_DEVICE_MODE 3:3 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL_DEVICE_MODE_NON_ALT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL_DEVICE_MODE_ALT 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL_ACTIVE_CHANNELS_NUM 8:4 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL_ACTIVE_CHANNELS_NUM_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL_ACTIVE_CHANNELS_NUM_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL_ACTIVE_CHANNELS_NUM_MAX 0x00000010 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL_ADC_IIR_LENGTH 15:12 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL_ADC_IIR_LENGTH_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL_SAMPLE_DELAY 31:24 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL_SAMPLE_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL2 0x000206c4 /* RW-4R */ #define NV_CPWR_THERM_ADC_CTRL2__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON1 4:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON1_NONE 0x00000010 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON1_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON1_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON1_CH2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET1 12:8 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET1_NONE 0x00000010 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET1_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET1_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET1_CH2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON2 20:16 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON2_NONE 0x00000010 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON2_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON2_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON2_CH2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET2 28:24 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET2_NONE 0x00000010 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET2_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET2_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET2_CH2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON(i) ((i)*16+4):((i)*16) /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON__SIZE_1 2 /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET(i) ((i)*16+12):((i)*16+8) /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET__SIZE_1 2 /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON_NONE 0x00000010 /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON_CH(i) 0x00000000+(i) /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET_NONE 0x00000010 /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET_CH(i) 0x00000000+(i) /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON1_CH(i) 0x00000000+(i) /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON1_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON2_CH(i) 0x00000000+(i) /* */ #define NV_CPWR_THERM_ADC_CTRL2_BEACON2_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET1_CH(i) 0x00000000+(i) /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET1_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET2_CH(i) 0x00000000+(i) /* */ #define NV_CPWR_THERM_ADC_CTRL2_OFFSET2_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_CTRL3 0x000206c8 /* RW-4R */ #define NV_CPWR_THERM_ADC_CTRL3__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON1_THRESH 10:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON1_THRESH_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON1_COMP 11:11 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON1_COMP_GT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON1_COMP_LT 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON2_THRESH 26:16 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON2_THRESH_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON2_COMP 27:27 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON2_COMP_GT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON2_COMP_LT 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON_THRESH(i) ((i)*16+10):((i)*16) /* */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON_THRESH__SIZE_1 2 /* */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON_COMP(i) ((i)*16+11):((i)*16+11) /* */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON_COMP__SIZE_1 2 /* */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON_COMP_GT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_CTRL3_BEACON_COMP_LT 0x00000001 /* */ #define NV_CPWR_THERM_ADC_CTRL4 0x00020590 /* RW-4R */ #define NV_CPWR_THERM_ADC_CTRL4__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_CTRL4_NEG2POS_BIAS 10:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_CTRL4_NEG2POS_BIAS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP 0x00020594 /* RW-4R */ #define NV_CPWR_THERM_ADC_OFFSET_MAP__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH0 1:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH0_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH0_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH0_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH1 3:2 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH1_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH1_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH1_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH2 5:4 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH2_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH2_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH2_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH3 7:6 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH3_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH3_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH3_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH4 9:8 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH4_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH4_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH4_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH5 11:10 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH5_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH5_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH5_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH6 13:12 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH6_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH6_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH6_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH7 15:14 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH7_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH7_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH7_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH8 17:16 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH8_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH8_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH8_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH9 19:18 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH9_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH9_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH9_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH10 21:20 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH10_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH10_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH10_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH11 23:22 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH11_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH11_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH11_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH12 25:24 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH12_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH12_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH12_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH13 27:26 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH13_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH13_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH13_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH14 29:28 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH14_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH14_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH14_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH15 31:30 /* RWIUF */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH15_NO_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH15_OFFSET1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH15_OFFSET2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH(i) ((i)*2+1):((i)*2) /* */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH_NO_OFFSET 0x00000000 /* */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH_OFFSET(i) ((i)+1) /* */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH_OFFSET__SIZE_1 2 /* */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH_OFFSET1 0x00000001 /* */ #define NV_CPWR_THERM_ADC_OFFSET_MAP_CH_OFFSET2 0x00000002 /* */ #define NV_CPWR_THERM_ADC_PWM 0x00020624 /* RW-4R */ #define NV_CPWR_THERM_ADC_PWM__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_PWM_HI 11:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_PWM_HI_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ADC_PWM_PERIOD 27:16 /* RWIUF */ #define NV_CPWR_THERM_ADC_PWM_PERIOD_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ADC_SW_RESET 0x00020628 /* RW-4R */ #define NV_CPWR_THERM_ADC_SW_RESET__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_SW_RESET_RST 0:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_SW_RESET_RST_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ADC_SW_RESET_RST_CLEARED 0x00000000 /* R---V */ #define NV_CPWR_THERM_ADC_SW_RESET_RST_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_ADC_SW_RESET_LENGTH 15:8 /* RWIUF */ #define NV_CPWR_THERM_ADC_SW_RESET_LENGTH_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX 0x0002062c /* RW-4R */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX 2:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_MAX 0x00000007 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP0_CFG 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP1_CFG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP2_CFG 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP3_CFG 0x00000003 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP4_CFG 0x00000004 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP5_CFG 0x00000005 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP6_CFG 0x00000006 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP7_CFG 0x00000007 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_READINCR 8:8 /* RWIUF */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_WRITEINCR 9:9 /* RWIUF */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP(i) (i) /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_INDEX_INDEX_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA 0x00020630 /* RW-4R */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA__APERTURE_INDEX_OFFSET (NV_THERM_ADC_MUL_CTRL_INDEX-NV_THERM_ADC_MUL_CTRL_DATA) /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE 31:0 /* RWIVF */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_OP1 3:0 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_OP2 19:16 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_ENABLE 31:31 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_ENABLE_OFF 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP_CFG_ENABLE_ON 0x00000001 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP0_CFG_INIT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP0_CFG_OP1 3:0 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP0_CFG_OP2 19:16 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP0_CFG_ENABLE 31:31 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP1_CFG_INIT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP1_CFG_OP1 3:0 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP1_CFG_OP2 19:16 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP1_CFG_ENABLE 31:31 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP2_CFG_INIT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP2_CFG_OP1 3:0 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP2_CFG_OP2 19:16 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP2_CFG_ENABLE 31:31 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP3_CFG_INIT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP3_CFG_OP1 3:0 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP3_CFG_OP2 19:16 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP3_CFG_ENABLE 31:31 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP4_CFG_INIT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP4_CFG_OP1 3:0 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP4_CFG_OP2 19:16 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP4_CFG_ENABLE 31:31 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP5_CFG_INIT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP5_CFG_OP1 3:0 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP5_CFG_OP2 19:16 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP5_CFG_ENABLE 31:31 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP6_CFG_INIT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP6_CFG_OP1 3:0 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP6_CFG_OP2 19:16 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP6_CFG_ENABLE 31:31 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP7_CFG_INIT 0x00000000 /* */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP7_CFG_OP1 3:0 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP7_CFG_OP2 19:16 /* RW--F */ #define NV_CPWR_THERM_ADC_MUL_CTRL_DATA_VALUE_CHP7_CFG_ENABLE 31:31 /* RW--F */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX 0x00020634 /* RW-4R */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX 3:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_MAX 0x0000000f /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH3 0x00000003 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH5 0x00000005 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH6 0x00000006 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH7 0x00000007 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH8 0x00000008 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH9 0x00000009 /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH10 0x0000000a /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH11 0x0000000b /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH12 0x0000000c /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH13 0x0000000d /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH14 0x0000000e /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH15 0x0000000f /* RW--V */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH(i) (i) /* */ #define NV_CPWR_THERM_ADC_IIR_VALUE_INDEX_INDEX_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_IIR_VALUE_DATA 0x00020638 /* R--4R */ #define NV_CPWR_THERM_ADC_IIR_VALUE_DATA_VALUE 31:0 /* R--VF */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX 0x0002063c /* RW-4R */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX 5:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_MAX 0x0000002f /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH0_LB 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH0_UB 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH0_SMPCNT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH1_LB 0x00000003 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH1_UB 0x00000004 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH1_SMPCNT 0x00000005 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH2_LB 0x00000006 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH2_UB 0x00000007 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH2_SMPCNT 0x00000008 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH3_LB 0x00000009 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH3_UB 0x0000000a /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH3_SMPCNT 0x0000000b /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH4_LB 0x0000000c /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH4_UB 0x0000000d /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH4_SMPCNT 0x0000000e /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH5_LB 0x0000000f /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH5_UB 0x00000010 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH5_SMPCNT 0x00000011 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH6_LB 0x00000012 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH6_UB 0x00000013 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH6_SMPCNT 0x00000014 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH7_LB 0x00000015 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH7_UB 0x00000016 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH7_SMPCNT 0x00000017 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH8_LB 0x00000018 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH8_UB 0x00000019 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH8_SMPCNT 0x0000001a /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH9_LB 0x0000001b /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH9_UB 0x0000001c /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH9_SMPCNT 0x0000001d /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH10_LB 0x0000001e /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH10_UB 0x0000001f /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH10_SMPCNT 0x00000020 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH11_LB 0x00000021 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH11_UB 0x00000022 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH11_SMPCNT 0x00000023 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH12_LB 0x00000024 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH12_UB 0x00000025 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH12_SMPCNT 0x00000026 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH13_LB 0x00000027 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH13_UB 0x00000028 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH13_SMPCNT 0x00000029 /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH14_LB 0x0000002a /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH14_UB 0x0000002b /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH14_SMPCNT 0x0000002c /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH15_LB 0x0000002d /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH15_UB 0x0000002e /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_CH15_SMPCNT 0x0000002f /* RW--V */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_LB_CH(i) ((i)*3) /* */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_LB_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_UB_CH(i) ((i)*3+1) /* */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_UB_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_SMPCNT_CH(i) ((i)*3+2) /* */ #define NV_CPWR_THERM_ADC_ACC_VALUE_INDEX_INDEX_SMPCNT_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_ADC_ACC_VALUE_DATA 0x00020640 /* R--4R */ #define NV_CPWR_THERM_ADC_ACC_VALUE_DATA_VALUE 31:0 /* R--VF */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX 0x00020644 /* RW-4R */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX 2:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_MAX 0x00000007 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP3 0x00000003 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP5 0x00000005 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP6 0x00000006 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP7 0x00000007 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP(i) (i) /* */ #define NV_CPWR_THERM_ADC_MUL_VALUE_INDEX_INDEX_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_ADC_MUL_VALUE_DATA 0x00020648 /* R--4R */ #define NV_CPWR_THERM_ADC_MUL_VALUE_DATA_VALUE 31:0 /* R--VF */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX 0x0002064c /* RW-4R */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX 4:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_MAX 0x00000017 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP0_LB 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP0_UB 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP0_SMPCNT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP1_LB 0x00000003 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP1_UB 0x00000004 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP1_SMPCNT 0x00000005 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP2_LB 0x00000006 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP2_UB 0x00000007 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP2_SMPCNT 0x00000008 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP3_LB 0x00000009 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP3_UB 0x0000000a /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP3_SMPCNT 0x0000000b /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP4_LB 0x0000000c /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP4_UB 0x0000000d /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP4_SMPCNT 0x0000000e /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP5_LB 0x0000000f /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP5_UB 0x00000010 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP5_SMPCNT 0x00000011 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP6_LB 0x00000012 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP6_UB 0x00000013 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP6_SMPCNT 0x00000014 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP7_LB 0x00000015 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP7_UB 0x00000016 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_CHP7_SMPCNT 0x00000017 /* RW--V */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_LB_CHP(i) ((i)*3) /* */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_LB_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_UB_CHP(i) ((i)*3+1) /* */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_UB_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_SMPCNT_CHP(i) ((i)*3+2) /* */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_INDEX_INDEX_SMPCNT_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_DATA 0x00020650 /* R--4R */ #define NV_CPWR_THERM_ADC_MUL_ACC_VALUE_DATA_VALUE 31:0 /* R--VF */ #define NV_CPWR_THERM_IPC_CTRL(i) (0x00020654+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_IPC_CTRL__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_OP 5:0 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH0 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH2 0x00000002 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH3 0x00000003 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH4 0x00000004 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH5 0x00000005 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH6 0x00000006 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH7 0x00000007 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH8 0x00000008 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH9 0x00000009 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH10 0x0000000a /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH11 0x0000000b /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH12 0x0000000c /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH13 0x0000000d /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH14 0x0000000e /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH15 0x0000000f /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP1 0x00000011 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP2 0x00000012 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP3 0x00000013 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP4 0x00000014 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP5 0x00000015 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP6 0x00000016 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP7 0x00000017 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_OP_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP(i) 16+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_OP_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_OP_BA_W(i) (24+(i)) /* */ #define NV_CPWR_THERM_IPC_CTRL_OP_BA_W__SIZE_1 3 /* */ #define NV_CPWR_THERM_IPC_CTRL_OP_SUM(i) (27+(i)) /* */ #define NV_CPWR_THERM_IPC_CTRL_OP_SUM__SIZE_1 2 /* */ #define NV_CPWR_THERM_IPC_CTRL_OP_BA_W0 0x00000018 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_BA_W1 0x00000019 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_BA_W2 0x0000001a /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_SUM1 0x0000001b /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_OP_SUM2 0x0000001c /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_EN 31:31 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_EN_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_EN_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_INDEX 0x000204f8 /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX 7:0 /* RWIVF */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_HEADER 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_MAX 0x00000043 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_RAUTOINCR 8:8 /* RWIVF */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_RAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_WAUTOINCR 9:9 /* RWIVF */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_WAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_AX0_AY_DS_IPC(i) ((i)*17) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_AX0_AY_DS_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_AX1_AX2_IPC(i) ((i)*17+1) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_AX1_AX2_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_AY1_AY2_IPC(i) ((i)*17+2) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_AY1_AY2_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_A_FLOOR_IPC(i) ((i)*17+3) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_A_FLOOR_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_A_CEIL_IPC(i) ((i)*17+4) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_A_CEIL_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_BX0_BY_DS_IPC(i) ((i)*17+5) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_BX0_BY_DS_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_BX1_BX2_IPC(i) ((i)*17+6) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_BX1_BX2_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_BY1_BY2_IPC(i) ((i)*17+7) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_BY1_BY2_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_B_FLOOR_IPC(i) ((i)*17+8) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_B_FLOOR_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_B_CEIL_IPC(i) ((i)*17+9) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_B_CEIL_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_CX0_CY_DS_IPC_DS_IPC(i) ((i)*17+10) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_CX0_CY_DS_IPC_DS_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_CX1_CX2_IPC(i) ((i)*17+11) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_CX1_CX2_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_CY1_CY2_IPC(i) ((i)*17+12) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_CY1_CY2_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_C_FLOOR_IPC(i) ((i)*17+13) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_C_FLOOR_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_C_CEIL_IPC(i) ((i)*17+14) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_C_CEIL_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_LAST_FLOOR_C_TARGET_IPC(i) ((i)*17+15) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_LAST_FLOOR_C_TARGET_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_LAST_CEIL_INTEGRATOR_IPC(i) ((i)*17+16) /* */ #define NV_CPWR_THERM_IPC_CTRL_INDEX_INDEX_LAST_CEIL_INTEGRATOR_IPC__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA 0x000204fc /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_DATA__APERTURE_INDEX_OFFSET (0x000004F8-0x000004FC) /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE 23:0 /* RWIVF */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE__INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_AX0 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_AY_DS 15:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_AX1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_AX2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_AY1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_AY2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_A_FLOOR 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_A_CEIL 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_BX0 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_BY_DS 15:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_BX1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_BX2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_BY1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_BY2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_B_FLOOR 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_B_CEIL 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_CX0 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_CY_DS 15:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_IPC_DS 20:16 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_CX1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_CX2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_CY1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_CY2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_C_FLOOR 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_C_CEIL 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_LAST_FLOOR 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_C_TARGET 20:20 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_C_TARGET_PRE 0x00000000 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_C_TARGET_POST 0x00000001 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_LAST_CEIL 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_LAST_INTEGRATOR 20:20 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_LAST_INTEGRATOR_DIS 0x00000000 /* */ #define NV_CPWR_THERM_IPC_CTRL_DATA_VALUE_LAST_INTEGRATOR_EN 0x00000001 /* */ #define NV_CPWR_THERM_IPC_REF(i) (0x00020664+(i)*4) /* RW-4A */ #define NV_CPWR_THERM_IPC_REF__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_REF__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_REF_VALUE 31:0 /* RWIUF */ #define NV_CPWR_THERM_IPC_REF_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT 0x00020574 /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1 7:0 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_NO_CH 0x000000ff /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT1_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2 15:8 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_NO_CH 0x000000ff /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT2_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3 23:16 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_NO_CH 0x000000ff /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT3_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4 31:24 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_NO_CH 0x000000ff /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT4_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT(i) ((i)*8+7):((i)*8) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_INPUT__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_NO_CH 0x000000FF /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_INPUT_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT 0x00020578 /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1 7:0 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_NO_CH 0x000000ff /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT1_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2 15:8 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_NO_CH 0x000000ff /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT2_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3 23:16 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_NO_CH 0x000000ff /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT3_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4 31:24 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_NO_CH 0x000000ff /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CH0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CH1 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CHP0 0x00000010 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT4_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT(i) ((i)*8+7):((i)*8) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_INPUT__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_NO_CH 0x000000FF /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_CH(i) (i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_CH__SIZE_1 16 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_CHP(i) 0x00000010+(i) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_INPUT_CHP__SIZE_1 8 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF 0x0002057c /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF1 7:0 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF2 15:8 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF3 23:16 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF4 31:24 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF(i) ((i)*8+7):((i)*8) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM1_SF_SF__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF 0x00020580 /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF1 7:0 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF2 15:8 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF2_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF3 23:16 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF3_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF4 31:24 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF4_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF(i) ((i)*8+7):((i)*8) /* */ #define NV_CPWR_THERM_IPC_CTRL_SUM2_SF_SF__SIZE_1 4 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX 0x00020480 /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX 5:0 /* RWIVF */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_HEADER 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_MAX 0x00000009 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_SEED_UPPER 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_SEED_LOWER 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_SEED_VALUE_REPEAT 0x00000002 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_AX0_AY_DS 0x00000003 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_AX1_AX2 0x00000004 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_AY1_AY2 0x00000005 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_BX0_BY_DS 0x00000006 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_BX1_BX2 0x00000007 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_BY1_BY2 0x00000008 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_INDEX_VID_DOWNSHIFT 0x00000009 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_RAUTOINCR 6:6 /* RWIVF */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_RAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_WAUTOINCR 7:7 /* RWIVF */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_INDEX_WAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA 0x00020484 /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA__APERTURE_INDEX_OFFSET (0x00000480-0x00000484) /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE 31:0 /* RWIVF */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE__INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_SEED_UPPER 31:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_SEED_LOWER 31:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_SEED_VALUE 19:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_SEED_REPEAT 31:20 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_AX0 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_AY_DS 15:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_AX1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_AX2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_AY1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_AY2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_BX0 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_BY_DS 15:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_BX1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_BX2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_BY1 11:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_BY2 23:12 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_DATA_VALUE_VID_DOWNSHIFT 4:0 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA 0x00020584 /* RW-4R */ #define NV_CPWR_THERM_IPC_CTRL_FA__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_SNAP 27:27 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_SNAP_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_SNAP_NOT_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_SNAP_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_MODE 28:28 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_MODE_CONTINUOUS 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_MODE_SNAP 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_CLEAR 29:29 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_CLEAR_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_CLEAR_DONE 0x00000000 /* R---V */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_CLEAR_NOT_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_IPC_CTRL_FA_ACC_CLEAR_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_IPC_CTRL_FA_GEN_UPDATE 30:30 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_FA_GEN_UPDATE_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_GEN_UPDATE_NOT_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_IPC_CTRL_FA_GEN_UPDATE_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_IPC_CTRL_FA_EN 31:31 /* RWIUF */ #define NV_CPWR_THERM_IPC_CTRL_FA_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_CTRL_FA_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX 0x000205f8 /* RW-4R */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX 5:0 /* RWIUF */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_MAX 0x00000008 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_PRE_S1_UB 0x00000000 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_PRE_S1_LB 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_PRE_S2_UB 0x00000002 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_PRE_S2_LB 0x00000003 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_POST_S1_UB 0x00000004 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_POST_S1_LB 0x00000005 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_POST_S2_UB 0x00000006 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_POST_S2_LB 0x00000007 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_INDEX_INDEX_COUNT 0x00000008 /* RW--V */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA 0x000205fc /* R--4R */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA__APERTURE_INDEX_OFFSET (0x000005F8-0x000005FC) /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE 31:0 /* R--VF */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_COUNT 31:0 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_PRE_S1_UB 31:0 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_PRE_S1_LB 31:0 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_PRE_S2_UB 31:0 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_PRE_S2_LB 31:0 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_POST_S1_UB 31:0 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_POST_S1_LB 31:0 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_POST_S2_UB 31:0 /* */ #define NV_CPWR_THERM_IPC_FA_ACC_VALUE_DATA_VALUE_POST_S2_LB 31:0 /* */ #define NV_CPWR_THERM_IPC_DEBUG 0x00020690 /* RW-4R */ #define NV_CPWR_THERM_IPC_DEBUG__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_IPC_DEBUG_IPC_HI_OFFSET_OVERRIDE 12:0 /* RWIUF */ #define NV_CPWR_THERM_IPC_DEBUG_IPC_HI_OFFSET_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_DEBUG_IPC_OVERRIDE_EN 13:13 /* RWIUF */ #define NV_CPWR_THERM_IPC_DEBUG_IPC_OVERRIDE_EN_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_DEBUG_IPC_OVERRIDE_EN_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_DEBUG_SEL_IDX 16:14 /* RWIUF */ #define NV_CPWR_THERM_IPC_DEBUG_SEL_IDX_HI_OFFSET 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_DEBUG_SEL_IDX_PWM0_HI_ACTIVE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_IPC_DEBUG_SEL_IDX_PWM1_HI_ACTIVE 0x00000002 /* RW--V */ #define NV_CPWR_THERM_IPC_DEBUG_SEL_IDX_PWM2_HI_ACTIVE 0x00000003 /* RW--V */ #define NV_CPWR_THERM_IPC_DEBUG_SEL_IDX_PWM3_HI_ACTIVE 0x00000004 /* RW--V */ #define NV_CPWR_THERM_IPC_DEBUG_SEL_VAL 29:17 /* R--UF */ #define NV_CPWR_THERM_IPC_DEBUG_SNAP 30:30 /* RWIUF */ #define NV_CPWR_THERM_IPC_DEBUG_SNAP_DONE 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_IPC_DEBUG_SNAP_NOT_DONE 0x00000001 /* R---V */ #define NV_CPWR_THERM_IPC_DEBUG_SNAP_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_IPC_DEBUG_MODE_CTRL 31:31 /* RWIUF */ #define NV_CPWR_THERM_IPC_DEBUG_MODE_CTRL_CONTINUOUS 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_IPC_DEBUG_MODE_CTRL_SNAP 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_DEBUG 0x00020694 /* RW-4R */ #define NV_CPWR_THERM_ADC_DEBUG__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_DEBUG_MIN_ADC 10:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_DEBUG_MIN_ADC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_DEBUG_MAX_ADC 21:11 /* RWIUF */ #define NV_CPWR_THERM_ADC_DEBUG_MAX_ADC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_DEBUG_STEP_PERIOD 26:23 /* RWIUF */ #define NV_CPWR_THERM_ADC_DEBUG_STEP_PERIOD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_DEBUG_MODE 31:29 /* RWIUF */ #define NV_CPWR_THERM_ADC_DEBUG_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_ADC_DEBUG_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_ADC_DEBUG_MODE_INC 0x00000001 /* RW--V */ #define NV_CPWR_THERM_ADC_DEBUG_MODE_DEC 0x00000002 /* RW--V */ #define NV_CPWR_THERM_ADC_DEBUG_MODE_CMOV 0x00000003 /* RW--V */ #define NV_CPWR_THERM_ADC_DEBUG_MODE_SW_OVERRIDE 0x00000004 /* RW--V */ #define NV_CPWR_THERM_ADC_DEBUG2 0x000206fc /* RW-4R */ #define NV_CPWR_THERM_ADC_DEBUG2__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_ADC_DEBUG2_SW_FORCED_ADC 10:0 /* RWIUF */ #define NV_CPWR_THERM_ADC_DEBUG2_SW_FORCED_ADC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL 0x00020698 /* RW-4R */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SM_CNT_THRESHOLD 7:0 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SM_CNT_THRESHOLD_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SM_CNT_THRESHOLD_1 15:8 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SM_CNT_THRESHOLD_1_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT 16:16 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_1 17:17 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_1_OFF 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_FORCE_HIGH_POWER_EVENT_1_ON 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SEL_ADC 20:20 /* RWIVF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SEL_ADC_SYS_ADC 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SEL_ADC_GPC_ADC_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_IIR_LENGTH 27:24 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_IIR_LENGTH_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_IIR_LENGTH_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_IIR_LENGTH_MAX 0x00000009 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_MODE_SEL 29:28 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_MODE_SEL_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_MODE_SEL_VIDPWM_DLY 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_MODE_SEL_NAFLL_ADC 0x00000002 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_MODE_SEL_SW 0x00000003 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SW_ISSUE_OK 30:30 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SW_ISSUE_OK_LOW 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_SW_ISSUE_OK_HIGH 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_IGNORE_SM_CNT_THRESHOLD 31:31 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_IGNORE_SM_CNT_THRESHOLD_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_CTRL_IGNORE_SM_CNT_THRESHOLD_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_SM_HIGH_POWER_HYSTERESIS 0x0002069c /* RW-4R */ #define NV_CPWR_THERM_SM_HIGH_POWER_HYSTERESIS__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_SM_HIGH_POWER_HYSTERESIS_CNT 31:0 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_HYSTERESIS_CNT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SM_HIGH_POWER_HYSTERESIS_1 0x000206b0 /* RW-4R */ #define NV_CPWR_THERM_SM_HIGH_POWER_HYSTERESIS_1__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_SM_HIGH_POWER_HYSTERESIS_1_CNT 31:0 /* RWIUF */ #define NV_CPWR_THERM_SM_HIGH_POWER_HYSTERESIS_1_CNT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SAFE_VOLTAGE_CFG 0x000206a0 /* RW-4R */ #define NV_CPWR_THERM_SAFE_VOLTAGE_CFG__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_SAFE_VOLTAGE_CFG_NAFLL_ADC 15:0 /* RWIUF */ #define NV_CPWR_THERM_SAFE_VOLTAGE_CFG_NAFLL_ADC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SAFE_VOLTAGE_CFG_DELAY 31:16 /* RWIUF */ #define NV_CPWR_THERM_SAFE_VOLTAGE_CFG_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_SAFE_VOLTAGE_DEBUG 0x000206a8 /* R--4R */ #define NV_CPWR_THERM_SAFE_VOLTAGE_DEBUG__PRIV_LEVEL_MASK 0x000203b4 /* */ #define NV_CPWR_THERM_SAFE_VOLTAGE_DEBUG_NAFLL_ADC_IIR 15:0 /* R--VF */ #define NV_CPWR_THERM_SAFE_VOLTAGE_DEBUG_NAFLL_ADC_RAW 22:16 /* R--VF */ #define NV_CPWR_THERM_DLPPE_NNET 0x00020884 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_NNET__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ 2:0 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_DONE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_0_IN_PROG 0x00000001 /* R---V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_1_IN_PROG 0x00000002 /* R---V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_2_IN_PROG 0x00000003 /* R---V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_3_IN_PROG 0x00000004 /* R---V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_4_IN_PROG 0x00000005 /* R---V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_5_IN_PROG 0x00000006 /* R---V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_6_IN_PROG 0x00000007 /* R---V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_0_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_1_TRIGGER 0x00000002 /* -W--T */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_2_TRIGGER 0x00000003 /* -W--T */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_3_TRIGGER 0x00000004 /* -W--T */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_4_TRIGGER 0x00000005 /* -W--T */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_5_TRIGGER 0x00000006 /* -W--T */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK_6_TRIGGER 0x00000007 /* -W--T */ #define NV_CPWR_THERM_DLPPE_NNET_LOOP_START 12:8 /* RWIUF */ #define NV_CPWR_THERM_DLPPE_NNET_LOOP_START_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_NNET_LOOP_START_MAX 0x0000001f /* RW--V */ #define NV_CPWR_THERM_DLPPE_NNET_LOOP_END 20:16 /* RWIUF */ #define NV_CPWR_THERM_DLPPE_NNET_LOOP_END_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_NNET_LOOP_END_MAX 0x0000001f /* RW--V */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK(i) ((i)+1) /* */ #define NV_CPWR_THERM_DLPPE_NNET_ID_REQ_NETWORK__SIZE_1 7 /* */ #define NV_CPWR_THERM_DLPPE_CFG 0x00020888 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_CFG__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_CFG_ROUNDING_MODE 2:0 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_CFG_ROUNDING_MODE_TO_NEAREST_EVEN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_CFG_ROUNDING_MODE_TOWARDS_ZERO 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_CFG_ROUNDING_MODE_TOWARDS_POSITIVE_INFINITY 0x00000002 /* RW--V */ #define NV_CPWR_THERM_DLPPE_CFG_ROUNDING_MODE_TOWARDS_NEGATIVE_INFINITY 0x00000003 /* RW--V */ #define NV_CPWR_THERM_DLPPE_CFG_ROUNDING_MODE_TO_NEAREST_UP 0x00000004 /* RW--V */ #define NV_CPWR_THERM_DLPPE_CFG_ROUNDING_MODE_AWAY_FROM_ZERO 0x00000005 /* RW--V */ #define NV_CPWR_THERM_DLPPE_CFG_CLAMP_INFINITY_TO_NORMAL 3:3 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_CFG_CLAMP_INFINITY_TO_NORMAL_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_CFG_CLAMP_INFINITY_TO_NORMAL_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR 0x000208a0 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_ADDR 8:0 /* RWIUF */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_ADDR_HEADER 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_ADDR_MAX 0x000001fc /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_RAUTOINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_RAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_WAUTOINCR 31:31 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_DSCR_ADDR_RAM_WAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA 0x000208a4 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_RAM_DATA 31:0 /* RWXUF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_HEADER_NUM_NETWORKS 7:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_HEADER_NUM_NETWORKS_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_HEADER_NUM_NETWORKS_MAX 0x00000007 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_HEADER_VERSION 31:28 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_NUM_LAYERS 7:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_NUM_LAYERS_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_NUM_LAYERS_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_NUM_LAYERS_MAX 0x0000001f /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_LOOP_MAX 15:8 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_LOOP_MAX_INDEX_0 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_LOOP_MAX_INDEX_MAX 0x0000001f /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_STATUS_OFFSET 31:16 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_NETWORK_HEADER_STATUS_OFFSET_MAX 0x000007fc /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_NEURONS 15:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_NEURONS_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_NEURONS_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_NEURONS_MAX 0x0000007f /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_INPUTS 31:16 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_INPUTS_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_INPUTS_MIN 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D0_NUM_INPUTS_MAX 0x000000ff /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D1_SWIZZLE_OFFSET 15:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D1_SWIZZLE_OFFSET_MAX 0x000007fc /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D1_WEIGHT_OFFSET 31:16 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D1_WEIGHT_OFFSET_MAX 0x00007ffe /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D2_OUTPUT_OFFSET 15:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D2_OUTPUT_OFFSET_MAX 0x000007fc /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D2_ACTIVATION_OFFSET 31:16 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D2_ACTIVATION_OFFSET_MAX 0x00007ffe /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_OUTPUT_STRIDE 0:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_OUTPUT_STRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_OUTPUT_STRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_STRIDE 1:1 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_STRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_STRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_FORMAT 2:2 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_FORMAT_FP32 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_WEIGHT_FORMAT_FP16 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL 19:16 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL_IDENTITY 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL_RELU 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_DSCR_DATA_LAYER_D3_ACTIVATION_SEL_LEAKY_RELU 0x00000002 /* RW--V */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR 0x000208a8 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_ADDR 10:0 /* RWIUF */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_ADDR_MAX 0x000007fc /* RW--V */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_RAUTOINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_RAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_WAUTOINCR 31:31 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_SWZL_ADDR_RAM_WAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_SWZL_DATA 0x000208ac /* RW-4R */ #define NV_CPWR_THERM_DLPPE_SWZL_DATA__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_SWZL_DATA_INPUT_POINTER 10:0 /* RWXUF */ #define NV_CPWR_THERM_DLPPE_SWZL_DATA_INPUT_POINTER_MIN 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_SWZL_DATA_INPUT_POINTER_MAX 0x000007fc /* RW--V */ #define NV_CPWR_THERM_DLPPE_SWZL_DATA_INPUT_STRIDE 26:16 /* RWXUF */ #define NV_CPWR_THERM_DLPPE_SWZL_DATA_INPUT_STRIDE_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_SWZL_DATA_INPUT_STRIDE_MAX 0x000007fc /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR 0x000208b0 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_ADDR 10:0 /* RWIUF */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_ADDR_MAX 0x000007fc /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_RAUTOINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_RAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_WAUTOINCR 31:31 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_PARM_ADDR_RAM_WAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA 0x000208b4 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_PARM_DATA__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_RAM_DATA 31:0 /* RWXUF */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP32_DATA 31:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTIONS 3:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTIONS_NONE 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INVALID 0:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INVALID_NOT_PENDING 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INVALID_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_UNDERFLOW 1:1 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_UNDERFLOW_NOT_PENDING 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_UNDERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_OVERFLOW 2:2 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_OVERFLOW_NOT_PENDING 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INEXACT 3:3 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INEXACT_NOT_PENDING 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_PARM_DATA_FP_EXCEPTION_INEXACT_PENDING 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR 0x000208b8 /* RW-4R */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_ADDR 14:0 /* RWIUF */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_ADDR_MAX 0x00007ffc /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_RAUTOINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_RAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_RAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_WAUTOINCR 31:31 /* RWIVF */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_WAUTOINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_ADDR_RAM_WAUTOINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA 0x000208bc /* RW-4R */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA__PRIV_LEVEL_MASK 0x00020880 /* */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_RAM_DATA 31:0 /* RWXUF */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_NEGATIVE_INFINITY 0xff800000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_NEGATIVE_ONE 0xbf800000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_NEGATIVE_ZERO 0x80000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_POSITIVE_ZERO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_POSITIVE_ONE 0x3f800000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_POSITIVE_INFINITY 0x7f800000 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_RAM_DATA_FP32_NAN 0x7f800001 /* RW--V */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_FP16_DATA_0 15:0 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_FP16_DATA_1 31:16 /* RW-UF */ #define NV_CPWR_THERM_DLPPE_WEIGHT_DATA_FP32_DATA 31:0 /* RW-UF */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK 0x000208c0 /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "tsense" /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_CONFIG_COPY 0x000208c4 /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE_CONFIG_COPY__PRIV_LEVEL_MASK 0x000208c0 /* */ #define NV_CPWR_THERM_NVL_TSENSE_CONFIG_COPY_NEW_SETTING 31:31 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_CONFIG_COPY_NEW_SETTING_NO_CMD 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_CONFIG_COPY_NEW_SETTING_SEND 0x00000001 /* RW--T */ #define NV_CPWR_THERM_NVL_TSENSE 0x000208c8 /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE__PRIV_LEVEL_MASK 0x000208c0 /* */ #define NV_CPWR_THERM_NVL_TSENSE_TS_ADC_OUT 13:0 /* R--VF */ #define NV_CPWR_THERM_NVL_TSENSE_STREAM_RAW_CODE 16:16 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_STREAM_RAW_CODE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_STREAM_RAW_CODE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_TS_BJT_SEL 23:20 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_TS_BJT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_TS_PD 24:24 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_TS_PD_DEASSERT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_TS_PD_ASSERT 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_CONTROL_SRC 28:28 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_CONTROL_SRC_LOGIC 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_CONTROL_SRC_REG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_CALI_SRC 29:29 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_CALI_SRC_FUSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_CALI_SRC_REG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_TC_SRC 30:30 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_TC_SRC_FUSE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_TC_SRC_REG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ 0x000208cc /* RW-4R */ #define NV_CPWR_THERM_NVL_TS_ADJ__PRIV_LEVEL_MASK 0x000208c0 /* */ #define NV_CPWR_THERM_NVL_TS_ADJ_VALUE 31:0 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_VALUE_INIT 0x00007240 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_VOLT 7:0 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_VOLT_INIT 0x00000040 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_TEMP_COEF 10:8 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_TEMP_COEF_INIT 0x00000002 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_MODE 11:11 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_MODE_AVG 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_MODE_NO_AVG 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_VPTAT_BIAS_CURRENT 13:12 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_VPTAT_BIAS_CURRENT_INIT 0x00000003 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_BYPASS 14:14 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_BYPASS_NO 0x00000000 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_BYPASS_YES 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_STARTUP_BIAS_CURRENT 15:15 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_BANDGAP_STARTUP_BIAS_CURRENT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT 19:16 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_TRISTATE 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_GND 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VBG 0x00000002 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VPTAT 0x00000003 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_SELA_2 0x00000004 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_IB0 0x00000006 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_IPTAT 0x00000008 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_IBG 0x00000009 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VDD 0x0000000c /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VMID 0x0000000d /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_VDD1V8_IN 0x0000000e /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_TS_VREF_OUTPUT_PLL_ADC_TEST_IN 0x0000000f /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_PTAT_BIPOLAR_SWAP 20:20 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_PTAT_BIPOLAR_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_PTAT_BIPOLAR_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_PTAT_OPAMP_SWAP 21:21 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_PTAT_OPAMP_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_PTAT_OPAMP_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_PTAT_SOURCE 25:22 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_PTAT_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_STOP_SWAP 26:26 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_STOP_SWAP_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_STOP_SWAP_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BYPASS_PTAT 27:27 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_BYPASS_PTAT_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_BYPASS_PTAT_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_SEND_VBG 28:28 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_SEND_VBG_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_AVERAGE_VBG 29:29 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_AVERAGE_VBG_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_AVERAGE_VBG_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_ADJ_START_BANDGAP 30:30 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_START_BANDGAP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_ADJ_STOP_SWAPPING_BJT 31:31 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_ADJ_STOP_SWAPPING_BJT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_RAWCODE_OVERRIDE 0x000208d0 /* RW-4R */ #define NV_CPWR_THERM_NVL_RAWCODE_OVERRIDE__PRIV_LEVEL_MASK 0x000208c0 /* */ #define NV_CPWR_THERM_NVL_RAWCODE_OVERRIDE_VALUE 13:0 /* RWIUF */ #define NV_CPWR_THERM_NVL_RAWCODE_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_RAWCODE_OVERRIDE_EN 16:16 /* RWIUF */ #define NV_CPWR_THERM_NVL_RAWCODE_OVERRIDE_EN_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_RAWCODE_OVERRIDE_EN_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL 0x000208d4 /* RW-4R */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL__PRIV_LEVEL_MASK 0x000208c0 /* */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL_SAMPLE_DELAY 13:0 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL_SAMPLE_DELAY_INIT 0x00000834 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL_AUTO_POLLING 15:15 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL_AUTO_POLLING_OFF 0x00000000 /* RW--V */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL_AUTO_POLLING_ON 0x00000001 /* RWI-V */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL_POLLING_INTERVAL 31:16 /* RWIUF */ #define NV_CPWR_THERM_NVL_TS_AUTO_CONTROL_POLLING_INTERVAL_INIT 0x0000005a /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX 0x000208d8 /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_INDEX 0:0 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_INDEX_MAX 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_READINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE 0x000208dc /* R--4R */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE__APERTURE_INDEX_OFFSET (0x000008D8-0x000008DC) /* */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE_VALUE 13:0 /* R--VF */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_NVL_TSENSE_RAW_CODE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE 0x000208e0 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE__APERTURE_INDEX_OFFSET (0x000008D8-0x000008E0) /* */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE 0x000208e4 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE__APERTURE_INDEX_OFFSET (0x000008D8-0x000008E4) /* */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX 0x0002010c /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_INDEX 0:0 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_INDEX_MAX 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_READINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_WRITEINCR 31:31 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE 0x0002011c /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE__APERTURE_INDEX_OFFSET (0x0000010C-0x0000011C) /* */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE__PRIV_LEVEL_MASK 0x00020328 /* */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_RSVD 14:0 /* C--VF */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_TEMP_SELECT 15:15 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_TEMP_SELECT_REAL 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_TEMP_SELECT_OVERRIDE 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_TEMP_VALUE 29:16 /* RWISF */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_TEMP_VALUE_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_TEMP_INTEGER 29:21 /* */ #define NV_CPWR_THERM_NVL_TSENSE_OVERRIDE_TEMP_INTEGER_ZERO 0x00000000 /* */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX 0x00020030 /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX__PRIV_LEVEL_MASK 0x000208c0 /* */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_INDEX 0:0 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_INDEX_MAX 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_READINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_WRITEINCR 31:31 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_WRITEINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INDEX_WRITEINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET 0x00020048 /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET__APERTURE_INDEX_OFFSET (0x00000030-0x00000048) /* */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET__PRIV_LEVEL_MASK 0x000208c0 /* */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_FIXED_POINT 16:3 /* RWISF */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_FIXED_POINT_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_HS_OFFSET_INTEGER 16:8 /* */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL 0x00020058 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL_TIMEOUT_PERIOD 7:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL_TIMEOUT_PERIOD_INIT 0x0000003c /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL_UPDATE_PERIOD 15:8 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_TIMER_INTERVAL_UPDATE_PERIOD_INIT 0x0000001e /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL 0x000201dc /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL__PRIV_LEVEL_MASK 0x000206c0 /* */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_RAMP_UP_STEP 13:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_RAMP_UP_STEP_INIT 0x000000a0 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_RAMP_DOWN_STEP 27:14 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_RAMP_DOWN_STEP_INIT 0x000000a0 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_AVG_SRC 28:28 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_AVG_SRC_UNMUNGED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_AVG_SRC_MUNGED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_MAX_SRC 29:29 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_MAX_SRC_UNMUNGED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_GPU_MAX_SRC_MUNGED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_ENABLE 31:31 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INTERPOLATION_CTRL_ENABLE_YES 0x00000001 /* RW--V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED 0x000203b8 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG 0x000203bc /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TSENSE_GLOBAL_SNAPSHOT 0x0002085c /* RW-4R */ #define NV_CPWR_THERM_TSENSE_GLOBAL_SNAPSHOT_CMD 0:0 /* RWIVF */ #define NV_CPWR_THERM_TSENSE_GLOBAL_SNAPSHOT_CMD_NO_CMD 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_TSENSE_GLOBAL_SNAPSHOT_CMD_TRIGGER 0x00000001 /* RW--T */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT 0x00020074 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_SYS_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT 0x00020104 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_SYS_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT 0x00020840 /* RW-4R */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_BJT_INDEX 3:0 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_BJT_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_BJT_INDEX_MAX 0x00000002 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_INDEX 19:16 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_GPC_INDEX_MAX 0x00000006 /* RW--V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_READINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_GPC_TSENSE_INDEX_SNAPSHOT_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT 0x00020844 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT 0x00020848 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT 0x0002013c /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT 0x0002014c /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_GPC_TSENSE_UNMUNGED_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT 0x0002084c /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT_INIT 0x00002000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER_INIT 0x00000100 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_MAX_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT 0x00020850 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_AVG_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT 0x00020854 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT 16:3 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT_INIT 0x00002000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER 16:8 /* R-ISF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER_INIT 0x00000100 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_MAX_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT 0x00020858 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPU_OFFSET_AVG_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT 0x0002019c /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_UNMUNGED_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT 0x000201cc /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_MUNGED 24:24 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_MUNGED_NO 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_GPC_AVG_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_SNAPSHOT 0x00020068 /* RW-4R */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_SNAPSHOT_INDEX 0:0 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_SNAPSHOT_INDEX_MIN 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_SNAPSHOT_INDEX_MAX 0x00000001 /* RW--V */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_SNAPSHOT_READINCR 30:30 /* RWIVF */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_SNAPSHOT_READINCR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_THERM_NVL_TSENSE_INDEX_SNAPSHOT_READINCR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT 0x0002006c /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT__APERTURE_INDEX_OFFSET (0x00000068-0x0000006C) /* */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_NVL_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT 0x00020070 /* R--4R */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT__APERTURE_INDEX_OFFSET (0x00000068-0x00000070) /* */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_RSVD 2:0 /* C--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_RSVD_INIT 0x00000000 /* C---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_FIXED_POINT 16:3 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_FIXED_POINT_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_FIXED_POINT_MIN 0x00003b00 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_FIXED_POINT_MAX 0x000012c0 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_INTEGER 16:8 /* R--SF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_INTEGER_ZERO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_INTEGER_MIN 0x000001d8 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_INTEGER_MAX 0x00000096 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_MUNGED 24:24 /* R--VF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_MUNGED_NO 0x00000000 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_MUNGED_YES 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_STATE 30:30 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_STATE_INVALID 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_STATE_VALID 0x00000001 /* R---V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_SOURCE 31:31 /* R-IVF */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_SOURCE_HW_LOGIC 0x00000000 /* R-I-V */ #define NV_CPWR_THERM_TEMP_SENSOR_OFFSET_NVL_TSENSE_SNAPSHOT_SOURCE_SW_OVERRIDE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL0 0x00000c00 /* RW-4R */ #define NV_CPWR_PMU_SCP_CTL0__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_CTL0_CTL_EN 20:20 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL0_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL0_CTL_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL0_SEQ_EN 16:16 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL0_SEQ_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL0_SEQ_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL0_SF_CMD_IFACE_EN 14:14 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL0_SF_CMD_IFACE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL0_SF_CMD_IFACE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL0_SF_PUSH_IFACE_EN 12:12 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL0_SF_PUSH_IFACE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL0_SF_PUSH_IFACE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL0_SF_FETCH_IFACE_EN 10:10 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL0_SF_FETCH_IFACE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL0_SF_FETCH_IFACE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL1 0x00000c04 /* RW-4R */ #define NV_CPWR_PMU_SCP_CTL1__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_CTL1_SF_PUSH_BYPASS 24:24 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL1_SF_PUSH_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL1_SF_PUSH_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL1_SF_FETCH_BYPASS 20:20 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL1_SF_FETCH_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL1_SF_FETCH_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL1_SF_FETCH_AS_ZERO 16:16 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL1_SF_FETCH_AS_ZERO_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL1_SF_FETCH_AS_ZERO_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL1_RNG_EN 12:12 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL1_RNG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL1_RNG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL1_RNG_FAKE_MODE 11:11 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL1_RNG_FAKE_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL1_RNG_FAKE_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL1_PIPE_RESET 8:8 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL1_PIPE_RESET_IDLE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CTL1_PIPE_RESET_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL1_PIPE_RESET_TASK 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_CTL1_SEQ_CLEAR 0:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL1_SEQ_CLEAR_IDLE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CTL1_SEQ_CLEAR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL1_SEQ_CLEAR_TASK 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_CTL_STAT 0x00000c08 /* R--4R */ #define NV_CPWR_PMU_SCP_CTL_STAT__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */ #define NV_CPWR_PMU_SCP_CTL_STAT_DEBUG_MODE_DISABLED 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_STAT_AES_SCC_DIS 2:2 /* R--VF */ #define NV_CPWR_PMU_SCP_CTL_STAT_AES_SCC_DIS_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_STAT_AES_SCC_DIS_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_STAT_HSMODE 1:1 /* R--VF */ #define NV_CPWR_PMU_SCP_CTL_STAT_HSMODE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_STAT_HSMODE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_STAT_SBOOT 0:0 /* R--VF */ #define NV_CPWR_PMU_SCP_CTL_STAT_SBOOT_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_STAT_SBOOT_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_CFG 0x00000c0c /* RW-4R */ #define NV_CPWR_PMU_SCP_CTL_CFG__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN 0:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT 1:1 /* R-IVF */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_PRE 2:2 /* R-IVF */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_PRE_ENABLED 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_PRE_DISABLED 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP 4:4 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_PRE 6:6 /* R-IVF */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_ENABLED 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_DISABLED 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CFG0 0x00000c10 /* RW-4R */ #define NV_CPWR_PMU_SCP_CFG0__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_CFG0_STALL_TIMEOUT 31:16 /* RWIVF */ #define NV_CPWR_PMU_SCP_CFG0_STALL_TIMEOUT_INIT 0x0000ffff /* RWI-V */ #define NV_CPWR_PMU_SCP_CFG0_CARRY_CHAIN 13:12 /* RWIVF */ #define NV_CPWR_PMU_SCP_CFG0_CARRY_CHAIN_32 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CFG0_CARRY_CHAIN_64 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CFG0_CARRY_CHAIN_96 0x00000002 /* RW--V */ #define NV_CPWR_PMU_SCP_CFG0_CARRY_CHAIN_128 0x00000003 /* RW--V */ #define NV_CPWR_PMU_SCP_CFG0_CMD_FLUSH 8:8 /* RWIVF */ #define NV_CPWR_PMU_SCP_CFG0_CMD_FLUSH_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CFG0_CMD_FLUSH_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CFG0_AES_ENDIAN 4:4 /* RWIVF */ #define NV_CPWR_PMU_SCP_CFG0_AES_ENDIAN_BIG 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CFG0_AES_ENDIAN_LITTLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CFG0_PUSH_ENDIAN 3:3 /* RWIVF */ #define NV_CPWR_PMU_SCP_CFG0_PUSH_ENDIAN_BIG 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CFG0_PUSH_ENDIAN_LITTLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CFG0_FETCH_ENDIAN 2:2 /* RWIVF */ #define NV_CPWR_PMU_SCP_CFG0_FETCH_ENDIAN_BIG 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CFG0_FETCH_ENDIAN_LITTLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CFG0_CMAC_ENDIAN 1:1 /* RWIVF */ #define NV_CPWR_PMU_SCP_CFG0_CMAC_ENDIAN_BIG 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CFG0_CMAC_ENDIAN_LITTLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CFG0_ADD_ENDIAN 0:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_CFG0_ADD_ENDIAN_BIG 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_CFG0_ADD_ENDIAN_LITTLE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL_DEBUG 0x00000c1c /* RW-4R */ #define NV_CPWR_PMU_SCP_CTL_DEBUG__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_CYA 4:4 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA 8:8 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0 0x00000c20 /* RW-4R */ #define NV_CPWR_PMU_SCP_DEBUG0__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_DEBUG0_PUSH_SECURE 31:31 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_PUSH_SECURE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_PUSH_SECURE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_PUSH_VALID 30:30 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_PUSH_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_PUSH_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_PUSH_CNT 26:25 /* R-IVF */ #define NV_CPWR_PMU_SCP_DEBUG0_PUSH_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_DEBUG0_FETCH_SECURE 24:24 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_FETCH_SECURE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_FETCH_SECURE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_FETCH_VALID 23:23 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_FETCH_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_FETCH_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_FETCH_CNT 22:19 /* R-IVF */ #define NV_CPWR_PMU_SCP_DEBUG0_FETCH_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_SECURE 18:18 /* R-IVF */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_SECURE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_SECURE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_VALID 17:17 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_PC 16:13 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_PC_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_DEPTH 12:8 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_SEQ_DEPTH_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_TARGET 6:5 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_TARGET_NONE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_TARGET_PUSH 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_TARGET_FETCH 0x00000002 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_TARGET_SEQ 0x00000003 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_INDEX_AUTOINCREMENT 4:4 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_INDEX_AUTOINCREMENT_TRUE 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG0_INDEX_AUTOINCREMENT_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG0_INDEX 3:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG0_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG1 0x00000c24 /* RW-4R */ #define NV_CPWR_PMU_SCP_DEBUG1__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_DEBUG1_DATA 31:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG2 0x00000c28 /* R--4R */ #define NV_CPWR_PMU_SCP_DEBUG2__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_DEBUG2_KU 15:12 /* R-IVF */ #define NV_CPWR_PMU_SCP_DEBUG2_KU_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_DEBUG2_SEQ_CNT 9:4 /* R-IVF */ #define NV_CPWR_PMU_SCP_DEBUG2_SEQ_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_DEBUG2_SEQ_STATE 1:0 /* R-IVF */ #define NV_CPWR_PMU_SCP_DEBUG2_SEQ_STATE_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_DEBUG2_SEQ_STATE_IDLE 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_DEBUG2_SEQ_STATE_LOAD 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_DEBUG2_SEQ_STATE_LOOP 0x00000002 /* R---V */ #define NV_CPWR_PMU_SCP_DEBUG_CMD 0x00000c30 /* RW-4R */ #define NV_CPWR_PMU_SCP_DEBUG_CMD__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_SECURE 31:31 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_SECURE_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_SECURE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_VALID 28:28 /* RWIVF */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_OP 24:20 /* RWXVF */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_RX_IMM 13:8 /* RWXVF */ #define NV_CPWR_PMU_SCP_DEBUG_CMD_RY 3:0 /* RWXVF */ #define NV_CPWR_PMU_SCP_ACL_FETCH 0x00000c40 /* R--4R */ #define NV_CPWR_PMU_SCP_ACL_FETCH__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_ACL_FETCH_SECURE 23:16 /* R--VF */ #define NV_CPWR_PMU_SCP_ACL_FETCH_INSECURE 7:0 /* R--VF */ #define NV_CPWR_PMU_SCP_ACL_KEYABLE 0x00000c44 /* R--4R */ #define NV_CPWR_PMU_SCP_ACL_KEYABLE__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_ACL_KEYABLE_SECURE 23:16 /* R--VF */ #define NV_CPWR_PMU_SCP_ACL_KEYABLE_INSECURE 7:0 /* R--VF */ #define NV_CPWR_PMU_SCP_ACL_WRITE 0x00000c48 /* R--4R */ #define NV_CPWR_PMU_SCP_ACL_WRITE__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_ACL_WRITE_INSECURE 7:0 /* R--VF */ #define NV_CPWR_PMU_SCP_STATUS 0x00000c50 /* R--4R */ #define NV_CPWR_PMU_SCP_STATUS__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_STATUS_SCP_ACTIVE 0:0 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_SCP_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_SCP_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_CMD_ACTIVE 2:2 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_CMD_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_CMD_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_PUSH_ACTIVE 4:4 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_PUSH_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_PUSH_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_SEQ_ACTIVE 6:6 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_SEQ_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_SEQ_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_CTL_ACTIVE 8:8 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_CTL_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_CTL_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_FETCH_ACTIVE 10:10 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_FETCH_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_FETCH_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_AES_ACTIVE 14:14 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_AES_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_AES_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_RNG_ACTIVE 16:16 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_RNG_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_RNG_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_SFK_LOADING_ACTIVE 20:20 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_SFK_LOADING_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_SFK_LOADING_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_SCC_TRNG_ACTIVE 26:26 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_SCC_TRNG_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_SCC_TRNG_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STATUS_SCC_PRNG_ACTIVE 28:28 /* R-IVF */ #define NV_CPWR_PMU_SCP_STATUS_SCC_PRNG_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STATUS_SCC_PRNG_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT0 0x00000c54 /* R--4R */ #define NV_CPWR_PMU_SCP_STAT0__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_STAT0_SF_CMD_VLD 14:14 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT0_SF_CMD_VLD_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_SF_CMD_VLD_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT0_SF_CMD_SECURE 12:12 /* R-XVF */ #define NV_CPWR_PMU_SCP_STAT0_SF_CMD_SECURE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_SF_CMD_SECURE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_SF_PUSH_VLD 10:10 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT0_SF_PUSH_VLD_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_SF_PUSH_VLD_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT0_SF_PUSH_SECURE 8:8 /* R-XVF */ #define NV_CPWR_PMU_SCP_STAT0_SF_PUSH_SECURE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_SF_PUSH_SECURE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_SF_FETCH_RDY 6:6 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT0_SF_FETCH_RDY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_SF_FETCH_RDY_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT0_SF_FETCH_SECURE 4:4 /* R-XVF */ #define NV_CPWR_PMU_SCP_STAT0_SF_FETCH_SECURE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_SF_FETCH_SECURE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_CMP 1:0 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT0_CMP_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT0_CMP_PASS 0x00000003 /* R---V */ #define NV_CPWR_PMU_SCP_STAT0_CMP_FAIL 0x00000002 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1 0x00000c58 /* R--4R */ #define NV_CPWR_PMU_SCP_STAT1__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_STAT1_SEQ_OP 4:0 /* R-XVF */ #define NV_CPWR_PMU_SCP_STAT1_SF_OP 9:5 /* R-XVF */ #define NV_CPWR_PMU_SCP_STAT1_DISPATCH_OP 14:10 /* R-XVF */ #define NV_CPWR_PMU_SCP_STAT1_AES_OP 17:15 /* R-XVF */ #define NV_CPWR_PMU_SCP_STAT1_AES_OP_ENCRYPT 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_AES_OP_DECRYPT 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_AES_OP_RKEY 0x00000002 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_AES_OP_RKEYI 0x00000003 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_HAZARD_STALL 24:24 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT1_HAZARD_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT1_HAZARD_STALL_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_PUSH_STALL 25:25 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT1_PUSH_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT1_PUSH_STALL_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_FETCH_STALL 26:26 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT1_FETCH_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT1_FETCH_STALL_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_RNG_STALL 27:27 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT1_RNG_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT1_RNG_STALL_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_WB_STALL 28:28 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT1_WB_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT1_WB_STALL_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_AES_STALL 29:29 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT1_AES_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT1_AES_STALL_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_STAT1_SECRET_STALL 30:30 /* R-IVF */ #define NV_CPWR_PMU_SCP_STAT1_SECRET_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_STAT1_SECRET_STALL_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_SECRET63_CTL 0x00000c60 /* RW-4R */ #define NV_CPWR_PMU_SCP_SECRET63_CTL__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_SECRET63_CTL_SEL 0:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_SECRET63_CTL_SEL_PKEY 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_SECRET63_CTL_SEL_KMEM 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_RNG_STAT0 0x00000c70 /* RW-4R */ #define NV_CPWR_PMU_SCP_RNG_STAT0__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RAW_RAND_READY 0:0 /* R-IVF */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RAW_RAND_READY_READY 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RAW_RAND_READY_PROCESSING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RAW_RAND_READY_RANDBUF_NOTFULL 0x00000001 /* R-I-V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_AUTOCAL_TAP_A 7:4 /* R-IVF */ #define NV_CPWR_PMU_SCP_RNG_STAT0_AUTOCAL_TAP_A_INIT 0x0000000f /* R-I-V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_AUTOCAL_TAP_B 11:8 /* R-IVF */ #define NV_CPWR_PMU_SCP_RNG_STAT0_AUTOCAL_TAP_B_INIT 0x0000000f /* R-I-V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_A 12:12 /* R-IVF */ #define NV_CPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_A_LEGAL 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_A_ILLEGAL 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_B 13:13 /* R-IVF */ #define NV_CPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_B_LEGAL 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_B_ILLEGAL 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_A 16:16 /* RWIVF */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_A_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_A_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_A_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_B 20:20 /* RWIVF */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_B_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_B_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_B_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_RNG_STAT1 0x00000c74 /* R--4R */ #define NV_CPWR_PMU_SCP_RNG_STAT1__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A 15:0 /* R-IUF */ #define NV_CPWR_PMU_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B 31:16 /* R-IUF */ #define NV_CPWR_PMU_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_INTR 0x00000c80 /* RW-4R */ #define NV_CPWR_PMU_SCP_INTR__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_INTR_RAND_READY 0:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_RAND_READY_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_INTR_RAND_READY_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_INTR_RAND_READY_RESET 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_INTR_ACL_VIO 8:8 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_ACL_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_INTR_ACL_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_INTR_ACL_VIO_RESET 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_INTR_SECURITY_VIO 12:12 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_SECURITY_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_INTR_SECURITY_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_INTR_SECURITY_VIO_RESET 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_INTR_CMD_ERROR 16:16 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_CMD_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_INTR_CMD_ERROR_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_INTR_CMD_ERROR_RESET 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_INTR_STEP 20:20 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_STEP_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_INTR_STEP_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_INTR_STEP_RESET 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_INTR_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_RNDHOLDOFF_REQUESTED_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_INTR_RNDHOLDOFF_REQUESTED_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_INTR_RNDHOLDOFF_REQUESTED_RESET 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_INTR_STALL_TIMEOUT 28:28 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_STALL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_INTR_STALL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_INTR_STALL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_INTR_EN 0x00000c84 /* RW-4R */ #define NV_CPWR_PMU_SCP_INTR_EN__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_INTR_EN_RAND_READY 0:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_EN_RAND_READY_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_INTR_EN_RAND_READY_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_INTR_EN_ACL_VIO 8:8 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_EN_ACL_VIO_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_INTR_EN_ACL_VIO_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_INTR_EN_SECURITY_VIO 12:12 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_EN_SECURITY_VIO_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_INTR_EN_SECURITY_VIO_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_INTR_EN_CMD_ERROR 16:16 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_EN_CMD_ERROR_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_INTR_EN_CMD_ERROR_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_INTR_EN_STEP 20:20 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_EN_STEP_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_INTR_EN_STEP_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_INTR_EN_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_INTR_EN_STALL_TIMEOUT 28:28 /* RWIVF */ #define NV_CPWR_PMU_SCP_INTR_EN_STALL_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_INTR_EN_STALL_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_ACL_VIO 0x00000c90 /* RW-4R */ #define NV_CPWR_PMU_SCP_ACL_VIO__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_ACL_VIO_VIOLATION 31:31 /* R-IVF */ #define NV_CPWR_PMU_SCP_ACL_VIO_VIOLATION_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_ACL_VIO_VIOLATION_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_ACL_VIO_CHMOD_RELAX_VIO 8:8 /* RWIVF */ #define NV_CPWR_PMU_SCP_ACL_VIO_CHMOD_RELAX_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_ACL_VIO_CHMOD_RELAX_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_ACL_VIO_CHMOD_RELAX_VIO_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_ACL_VIO_FETCH_VIO 4:4 /* RWIVF */ #define NV_CPWR_PMU_SCP_ACL_VIO_FETCH_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_ACL_VIO_FETCH_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_ACL_VIO_FETCH_VIO_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_ACL_VIO_WR_VIO 0:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_ACL_VIO_WR_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_ACL_VIO_WR_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_ACL_VIO_WR_VIO_CLEAR 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_SECURITY_VIO 0x00000c94 /* R--4R */ #define NV_CPWR_PMU_SCP_SECURITY_VIO__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_VIOLATION 31:31 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_VIOLATION_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_VIOLATION_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO_SC 26:25 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO 24:24 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC 22:21 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO 20:20 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO_SC 18:17 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO 16:16 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC 6:5 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO 4:4 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC 2:1 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO 0:0 /* R-IVF */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR 0x00000c98 /* RW-4R */ #define NV_CPWR_PMU_SCP_CMD_ERROR__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_CMD_ERROR_UNDEFINED 0:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_CMD_ERROR_UNDEFINED_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_UNDEFINED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_UNDEFINED_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_EMPTY 4:4 /* RWIVF */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_EMPTY_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_EMPTY_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_EMPTY_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_OVERFLOW 8:8 /* RWIVF */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_OVERFLOW_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_OVERFLOW_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING 12:12 /* RWIVF */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SIG_INSECURE 16:16 /* RWIVF */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SIG_INSECURE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SIG_INSECURE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SIG_INSECURE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SIG_INVALID 20:20 /* RWIVF */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SIG_INVALID_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SIG_INVALID_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SIG_INVALID_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_CMD_ERROR_CHMOD_INSECURE 24:24 /* RWIVF */ #define NV_CPWR_PMU_SCP_CMD_ERROR_CHMOD_INSECURE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_CHMOD_INSECURE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_CHMOD_INSECURE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SECRET_INSECURE 28:28 /* RWIVF */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SECRET_INSECURE_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SECRET_INSECURE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CMD_ERROR_SECRET_INSECURE_CLEAR 0x00000001 /* -W--C */ #define NV_CPWR_PMU_SCP_RNDCTL0 0x00000d00 /* RW-4R */ #define NV_CPWR_PMU_SCP_RNDCTL0__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL0_HOLDOFF_INIT_LOWER 31:0 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL0_HOLDOFF_INIT_LOWER_INIT 0x01c9c380 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL1 0x00000d04 /* RW-4R */ #define NV_CPWR_PMU_SCP_RNDCTL1__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL1_HOLDOFF_INIT_UPPER 15:0 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL1_HOLDOFF_INIT_UPPER_ZERO 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL1_HOLDOFF_INTRA_MASK 31:16 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL1_HOLDOFF_INTRA_MASK_INIT 0x0000ffff /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL2 0x00000d08 /* RW-4R */ #define NV_CPWR_PMU_SCP_RNDCTL2__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL2_COMPRESS_CNT 15:0 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL2_COMPRESS_CNT_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL3 0x00000d0c /* RW-4R */ #define NV_CPWR_PMU_SCP_RNDCTL3__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A 12:12 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B 16:16 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_INIT 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_TRIGGER 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_RNDCTL4 0x00000d10 /* -W-4R */ #define NV_CPWR_PMU_SCP_RNDCTL4__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL4_POLYNOMIAL_A 31:0 /* -WIUF */ #define NV_CPWR_PMU_SCP_RNDCTL4_POLYNOMIAL_A_INIT 0x80200003 /* -WI-V */ #define NV_CPWR_PMU_SCP_RNDCTL5 0x00000d14 /* -W-4R */ #define NV_CPWR_PMU_SCP_RNDCTL5__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL5_LFSR_INIT_A 31:0 /* -WIUF */ #define NV_CPWR_PMU_SCP_RNDCTL5_LFSR_INIT_A_INIT 0xdeadbeef /* -WI-V */ #define NV_CPWR_PMU_SCP_RNDCTL6 0x00000d18 /* -W-4R */ #define NV_CPWR_PMU_SCP_RNDCTL6__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL6_POLYNOMIAL_B 31:0 /* -WIUF */ #define NV_CPWR_PMU_SCP_RNDCTL6_POLYNOMIAL_B_INIT 0x80200003 /* -WI-V */ #define NV_CPWR_PMU_SCP_RNDCTL7 0x00000d1c /* -W-4R */ #define NV_CPWR_PMU_SCP_RNDCTL7__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL7_LFSR_INIT_B 31:0 /* -WIUF */ #define NV_CPWR_PMU_SCP_RNDCTL7_LFSR_INIT_B_INIT 0xbeefdead /* -WI-V */ #define NV_CPWR_PMU_SCP_RNDCTL8 0x00000d20 /* RW-4R */ #define NV_CPWR_PMU_SCP_RNDCTL8__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A 15:0 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B 31:16 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL9 0x00000d24 /* RW-4R */ #define NV_CPWR_PMU_SCP_RNDCTL9__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A 15:0 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B 31:16 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL10 0x00000d28 /* RW-4R */ #define NV_CPWR_PMU_SCP_RNDCTL10__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A 15:0 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A_INIT 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B 31:16 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B_INIT 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11 0x00000d2c /* RW-4R */ #define NV_CPWR_PMU_SCP_RNDCTL11__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_ENABLE 0:0 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE 1:1 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_A 2:2 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_A_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_A_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_A_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_B 3:3 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_B_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_B_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_B_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A 5:4 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_OSC 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_AUTOCAL 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_LFSR 0x00000002 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_ZERO 0x00000003 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B 7:6 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_OSC 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_AUTOCAL 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_LFSR 0x00000002 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_ZERO 0x00000003 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A 11:8 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A_INIT 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B 15:12 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B_INIT 0x0000000f /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_MIN_AUTO_TAP 19:16 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_MIN_AUTO_TAP_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY 23:20 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY_INIT 0x00000001 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY 30:24 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_SAFE_MODE 31:31 /* RWIUF */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_CTL_P2PRX 0x00000d30 /* RW-4R */ #define NV_CPWR_PMU_SCP_CTL_P2PRX__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_FALLBACK_MODE 0:0 /* R--VF */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_FALSE 0x00000000 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD 2:2 /* RWIVF */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_IDLE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_PENDING 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_TASK 0x00000001 /* -W--T */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_LOADED 3:3 /* R-IVF */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_LOADED_FALSE 0x00000000 /* R-I-V */ #define NV_CPWR_PMU_SCP_CTL_P2PRX_SFK_LOADED_TRUE 0x00000001 /* R---V */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG0 0x00000d40 /* R--4R */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG0__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT 15:0 /* R-IVF */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT_INIT 0x00000020 /* R-I-V */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA 31:16 /* R-IVF */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA_INIT 0x0000000f /* R-I-V */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG1 0x00000d44 /* R--4R */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG1__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX 31:0 /* R-IVF */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX_INIT 0x00000fff /* R-I-V */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG2 0x00000d48 /* R--4R */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG2__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD 31:0 /* R-IVF */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD_INIT 0x7fffffff /* R-I-V */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_STAT0 0x00000d4c /* R--4R */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_STAT0__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_STAT0_RSEED_TMOUT_CNT 31:0 /* R--VF */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_STAT1 0x00000d50 /* R--4R */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_STAT1__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_SCP /* */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_STAT1_RSEED_BIT_CNT 5:0 /* R--VF */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_STAT1_RSEED_VALID 8:8 /* R--VF */ #define NV_CPWR_PMU_SCP_SCC_DEBUG_STAT1_RSEED_TMOUT 9:9 /* R--VF */ #define NV_CPWR_PMU_SCP_PUBKEYC 0x00000d60 /* RW-4R */ #define NV_CPWR_PMU_SCP_PUBKEYC__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_KEY /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_RSA1_N_OFFS 0x00000000 /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_RSA1_N_SIZE 0x00000180 /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_RSA1_E_OFFS 0x00000180 /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_RSA1_E_SIZE 0x00000020 /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_ECC1_X_OFFS 0x000001a0 /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_ECC1_X_SIZE 0x00000020 /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_ECC1_Y_OFFS 0x000001c0 /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_ECC1_Y_SIZE 0x00000020 /* */ #define NV_CPWR_PMU_SCP_PUBKEYC_OFFS 9:2 /* RWIVF */ #define NV_CPWR_PMU_SCP_PUBKEYC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_PUBKEYC_AINCR 31:31 /* RWIVF */ #define NV_CPWR_PMU_SCP_PUBKEYC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_PUBKEYC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_PUBKEYC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CPWR_PMU_SCP_PUBKEYD 0x00000d64 /* R--4R */ #define NV_CPWR_PMU_SCP_PUBKEYD__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_KEY /* */ #define NV_CPWR_PMU_SCP_PUBKEYD_DATA 31:0 /* R--VF */ #define NV_CPWR_PMU_SCP_PK_ADDR 0x00000d70 /* RWI4R */ #define NV_CPWR_PMU_SCP_PK_ADDR__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_BROM /* */ #define NV_CPWR_PMU_SCP_PK_ADDR_OFFSET 11:0 /* RWIVF */ #define NV_CPWR_PMU_SCP_PK_ADDR_OFFSET_DEFT 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_PK_ADDR_AINCR 31:31 /* RWIVF */ #define NV_CPWR_PMU_SCP_PK_ADDR_AINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CPWR_PMU_SCP_PK_ADDR_AINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CPWR_PMU_SCP_PK_DATA 0x00000d74 /* R--4R */ #define NV_CPWR_PMU_SCP_PK_DATA__DEVICE_MAP NV_CPWR_PMU_DEVICE_MAP_GROUP_BROM /* */ #define NV_CPWR_PMU_SCP_PK_DATA_VAL 31:0 /* R--VF */ #endif // __ga102_dev_pwr_csb_h__