/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2003-2016 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

#ifndef __ga102_dev_imp_h__
#define __ga102_dev_imp_h__
/* This file is autogenerated.  Do not edit */
#define NV_MCLK_MHZ_CUTOFF0                                                 1000
#define NV_MCLK_MHZ_HBM_CUTOFF0                                             1050
#define NV_MCLK_MHZ_CUTOFF__SIZE1                                             2
#define NV_PFB_HBM_RT_LAT_DRAMCLK_COMPONENT_R0                              118
#define NV_PFB_HBM_RT_LAT_NANOSEC_COMPONENT_R0                               68
#define NV_PFB_RT_LAT_LTCCLK_COMPONENT_R0                                   131
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R0                             131
#define NV_PFB_GDDR5X_RT_LAT_LTCCLK_COMPONENT_R0                            131
#define NV_PFB_GDDR5_RT_LAT_LTCCLK_COMPONENT_R0                             131
#define NV_PFB_HBM_RT_LAT_DRAMCLK_COMPONENT_R1                              125
#define NV_PFB_HBM_RT_LAT_NANOSEC_COMPONENT_R1                               68
#define NV_PFB_RT_LAT_LTCCLK_COMPONENT_R1                                  1458
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R1                            1458
#define NV_PFB_GDDR5X_RT_LAT_LTCCLK_COMPONENT_R1                           1158
#define NV_PFB_GDDR5_RT_LAT_LTCCLK_COMPONENT_R1                             866
#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_R0                            486
#define NV_PFB_GDDR5_RT_LAT_NANOSEC_COMPONENT_R0                            564
#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_R0                           682
#define NV_PFB_GDDR5X_RT_LAT_NANOSEC_COMPONENT_R0                           540
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R0                           1434
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R0                             62
#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_R1                            652
#define NV_PFB_GDDR5_RT_LAT_NANOSEC_COMPONENT_R1                            690
#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_R1                           944
#define NV_PFB_GDDR5X_RT_LAT_NANOSEC_COMPONENT_R1                           708
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R1                           1152
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R1                             62
#define NV_PFB_SDDR3_RT_LAT_DRAMCLK_COMPONENT_R0                            488
#define NV_PFB_SDDR3_RT_LAT_NANOSEC_COMPONENT_R0                            634
#define NV_PFB_SDDR3_RT_LAT_DRAMCLK_COMPONENT_R1                            488
#define NV_PFB_SDDR3_RT_LAT_NANOSEC_COMPONENT_R1                            634
#define NV_PFB_HUBCLKS                                                      104
#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE              250 // 250 cycles per CRC replay
#define NV_PFB_GDDR5_MAX_CRC_REPLAYS                                          2 // 2 CRC replays
#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE              250 // 250 cycles per CRC replay
#define NV_PFB_GDDR5X_MAX_CRC_REPLAYS                                          2 // 2 CRC replays
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE              250 // 250 cycles per CRC replay
#define NV_PFB_GDDR6_MAX_CRC_REPLAYS                                          2 // 2 CRC replays
#define NV_PFB_RT_LAT_XBARCLK_COMPONENT                                    159
#define NV_PFB_RT_LAT_SYSCLK_COMPONENT                                      64
#define NV_MCLK_MHZ_CUTOFF0_B                                                  600
#define NV_MCLK_MHZ_CUTOFF1_B                                                 1000
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R0_B                             123
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R0_B                           2139
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R0_B                             62
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R1_B                             123
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R1_B                           2995
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R1_B                             62
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R2_B                             123
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R2_B                           6828
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R2_B                             60
#endif // __ga102_dev_imp_h__