/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_nv_xve_h__ #define __ga102_dev_nv_xve_h__ /* This file is autogenerated. Do not edit */ #define NV_PCFG 0x00088FFF:0x00088000 /* RW--D */ #define NV_XVE 0x00000FFF:0x00000000 /* RW--D */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK 0x00000AB4 /* RW-4R */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK 0x00000EC0 /* RW-4R */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_MISC_CYA_RESET_GPU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK 0x00000EC4 /* RW-4R */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK 0x00000EC8 /* RW-4R */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_LEVEL3_ENABLED 0x0000000C /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_cya_0" /* */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK 0x00000ECC /* RW-4R */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_LEVEL3_ENABLED 0x0000000C /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_priv_xv_1" /* */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_PRIV_XV_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK 0x00000ED0 /* RW-4R */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL2_ENABLED 0x0000000C /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_BAR1_CONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK 0x00000ED4 /* RW-4R */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL2_ENABLED 0x0000000C /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_CYA_5_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK 0x00000ED8 /* RW-4R */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL2_ENABLED 0x0000000C /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_DEBUG_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK 0x00000EDC /* RW-4R */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL2_ENABLED 0x0000000C /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_L1_PM_SUBSTATES_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK 0x00000FE4 /* RW-4R */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_protect_dropoff_cya_grp" /* */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_BAR_BLOCKER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK 0x00000FE8 /* RW-4R */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_protect_dropoff_others" /* */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK 0x00000FEC /* RW-4R */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_protect_dropoff_cya_grp" /* */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK 0x00000FF0 /* RW-4R */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_protect_dropoff_non_cya_grp" /* */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK 0x00000FF4 /* RW-4R */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWC-V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_SW_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK 0x00000FF8 /* RW-4R */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_reset_ctrl" /* */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK 0x00000FFC /* RW-4R */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */ #define NV_XVE_ID 0x00000000 /* R--4R */ #define NV_XVE_ID_VENDOR 15:0 /* C--VF */ #define NV_XVE_ID_VENDOR_NVIDIA 0x000010DE /* C---V */ #define NV_XVE_ID_DEVICE_CHIP 31:16 /* R-CVF */ #define NV_XVE_ID_DEVICE_CHIP_NO_USE 0x00000000 /* R-C-V */ #define NV_XVE_ID_DEVICE_CHIP_NV30 0x00000300 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV31 0x00000320 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV34 0x00000380 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV35 0x000003A0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV40 0x00000040 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV41 0x000000C0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV42 0x00000120 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV43 0x00000140 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV44 0x00000160 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV46 0x000001D0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV47 0x00000090 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G74 0x00000480 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_NV50 0x00000190 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G84 0x00000400 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G82 0x00000410 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G86 0x00000420 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G88 0x00000430 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G92 0x00000600 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G94 0x00000620 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G96 0x00000640 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GT200 0x000005E0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_G98 0x000006E0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_IGT206 0x00000AE0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_IGT209 0x00000B00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GT212 0x00000A00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GT214 0x000006A0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GT216 0x00000A20 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GT218 0x00000A60 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF100 0x000006C0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF102 0x00000D00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF103 0x00000D20 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF104 0x00000E20 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF105 0x00000DA0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF106 0x00000DC0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF108 0x00000DE0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF110D 0x00000CC0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF110F 0x00000CE0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GF117 0x00001140 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GK104 0x00001180 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GK106 0x000011C0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GK107 0x00000FC0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GK110 0x00001000 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GK208 0x00001280 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GM108 0x00001340 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GM107 0x00001380 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GM104 0x00001580 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GM204 0x000013C0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GM206 0x00001400 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GM200 0x000017C0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GP100 0x000015C0 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GP102 0x00001B00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GP104 0x00001B80 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GP106 0x00001C00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GP107 0x00001C80 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GP108 0x00001D00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GV100 0x00001D80 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU102 0x00001E00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU104 0x00001E80 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU106 0x00001F00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU107 0x00001F80 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU117 0x00001F80 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU108 0x00002000 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU116 0x00002180 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA100 0x00002080 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA101 0x00002380 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA102 0x00002200 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA103 0x00002400 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA104 0x00002480 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA106 0x00002500 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA107 0x00002580 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GH202 0x00002600 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA114 0x00002200 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA10B 0x00002200 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU102_START 0x00001E00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU102_END 0x00001E7F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_TU102 0x00001AD6 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_TU102 0x00001AD7 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU104_START 0x00001E80 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU104_END 0x00001EFF /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_TU104 0x00001AD8 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_TU104 0x00001AD9 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU106_START 0x00001F00 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU106_END 0x00001F7F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_TU106 0x00001ADA /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_TU106 0x00001ADB /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU117_START 0x00001F80 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU117_END 0x00001FFF /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_TU117 0x00001ADC /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_TU117 0x00001ADD /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU108_START 0x00002000 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU108_END 0x0000207F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_TU108 0x00001ADE /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_TU108 0x00001ADF /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU101_START 0x00002100 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU101_END 0x0000217F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_TU101 0x00001AE4 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_TU101 0x00001AE5 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU116_START 0x00002180 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_TU116_END 0x000021FF /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_TU116 0x00001AEC /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_TU116 0x00001AED /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA100_START 0x00002080 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA100_END 0x000020FF /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA100 0x00001AE1 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA100 0x00001AE2 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA101_START 0x00002380 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA101_END 0x000023FF /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA101 0x00002286 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA101 0x00002287 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA102_START 0x00002200 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA103_START 0x00002400 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA104_START 0x00002480 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA106_START 0x00002500 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA107_START 0x00002580 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GH202_START 0x00002600 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA114_START 0x00002200 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA10B_START 0x00002200 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA102_END 0x0000227F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA103_END 0x0000247F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA104_END 0x000024FF /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA106_END 0x0000257F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA107_END 0x000025FF /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GH202_END 0x0000267F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA114_END 0x0000227F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_GA10B_END 0x0000227F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA102 0x00002280 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA103 0x00002289 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA104 0x0000228C /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA106 0x0000228F /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA107 0x00002292 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA114 0x00002280 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_XUSB_GA10B 0x00002280 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA102 0x00002281 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA103 0x0000228A /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA104 0x0000228D /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA106 0x00002290 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA107 0x00002293 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA114 0x00002281 /* R---V */ #define NV_XVE_ID_DEVICE_CHIP_I2C_GA10B 0x00002281 /* R---V */ #define NV_XVE_DEV_CTRL 0x00000004 /* RW-4R */ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE 0:0 /* RWIVF */ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEV_CTRL_CMD_IO_SPACE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE 1:1 /* RWIVF */ #define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEV_CTRL_CMD_BUS_MASTER 2:2 /* RWIVF */ #define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEV_CTRL_CMD_SPECIAL_CYCLE 3:3 /* C--VF */ #define NV_XVE_DEV_CTRL_CMD_SPECIAL_CYCLE_DISABLED 0x00000000 /* C---V */ #define NV_XVE_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE 4:4 /* C--VF */ #define NV_XVE_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE_DISABLED 0x00000000 /* C---V */ #define NV_XVE_DEV_CTRL_CMD_VGA_PALETTE_SNOOP 5:5 /* C--VF */ #define NV_XVE_DEV_CTRL_CMD_VGA_PALETTE_SNOOP_DISABLED 0x00000000 /* C---V */ #define NV_XVE_DEV_CTRL_CMD_PERR 6:6 /* RWIVF */ #define NV_XVE_DEV_CTRL_CMD_PERR_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEV_CTRL_CMD_PERR_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEV_CTRL_CMD_IDSEL_STEP 7:7 /* C--VF */ #define NV_XVE_DEV_CTRL_CMD_IDSEL_STEP_DISABLED 0x00000000 /* C---V */ #define NV_XVE_DEV_CTRL_CMD_SERR 8:8 /* RWIVF */ #define NV_XVE_DEV_CTRL_CMD_SERR_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEV_CTRL_CMD_SERR_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEV_CTRL_CMD_FAST_BACK2BACK 9:9 /* C--VF */ #define NV_XVE_DEV_CTRL_CMD_FAST_BACK2BACK_DISABLED 0x00000000 /* C---V */ #define NV_XVE_DEV_CTRL_CMD_INTERRUPT_DISABLE 10:10 /* RWIVF */ #define NV_XVE_DEV_CTRL_CMD_INTERRUPT_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_DEV_CTRL_STAT_INTERRUPT 19:19 /* R-IVF */ #define NV_XVE_DEV_CTRL_STAT_INTERRUPT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_DEV_CTRL_STAT_INTERRUPT_PENDING 0x00000001 /* R---V */ #define NV_XVE_DEV_CTRL_STAT_CAPLIST 20:20 /* C--VF */ #define NV_XVE_DEV_CTRL_STAT_CAPLIST_PRESENT 0x00000001 /* C---V */ #define NV_XVE_DEV_CTRL_STAT_66MHZ 21:21 /* C--VF */ #define NV_XVE_DEV_CTRL_STAT_66MHZ_INCAPABLE 0x00000000 /* C---V */ #define NV_XVE_DEV_CTRL_STAT_FAST_BACK2BACK 23:23 /* C--VF */ #define NV_XVE_DEV_CTRL_STAT_FAST_BACK2BACK_INCAPABLE 0x00000000 /* C---V */ #define NV_XVE_DEV_CTRL_STAT_MASTER_DATA_PERR 24:24 /* RWIVF */ #define NV_XVE_DEV_CTRL_STAT_MASTER_DATA_PERR_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DEV_CTRL_STAT_MASTER_DATA_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */ #define NV_XVE_DEV_CTRL_STAT_MASTER_DATA_PERR_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEV_CTRL_STAT_DEVSEL_TIMING 26:25 /* C--VF */ #define NV_XVE_DEV_CTRL_STAT_DEVSEL_TIMING_FAST 0x00000000 /* C---V */ #define NV_XVE_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT 27:27 /* RWIVF */ #define NV_XVE_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_NO 0x00000000 /* R-I-V */ #define NV_XVE_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_YES 0x00000001 /* R---V */ #define NV_XVE_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT 28:28 /* RWIVF */ #define NV_XVE_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_NO 0x00000000 /* R-I-V */ #define NV_XVE_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_YES 0x00000001 /* R---V */ #define NV_XVE_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT 29:29 /* RWIVF */ #define NV_XVE_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_NO 0x00000000 /* R-I-V */ #define NV_XVE_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_YES 0x00000001 /* R---V */ #define NV_XVE_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEV_CTRL_STAT_SIGNALED_SERR 30:30 /* RWIVF */ #define NV_XVE_DEV_CTRL_STAT_SIGNALED_SERR_NOT_ACTIVE 0x00000000 /* R-I-V */ #define NV_XVE_DEV_CTRL_STAT_SIGNALED_SERR_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DEV_CTRL_STAT_SIGNALED_SERR_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEV_CTRL_STAT_DETECTED_PERR 31:31 /* RWIVF */ #define NV_XVE_DEV_CTRL_STAT_DETECTED_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */ #define NV_XVE_DEV_CTRL_STAT_DETECTED_PERR_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DEV_CTRL_STAT_DETECTED_PERR_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_REV_ID 0x00000008 /* R--4R */ #define NV_XVE_REV_ID_FIB 3:0 /* R-CVF */ #define NV_XVE_REV_ID_FIB_ONE 0x00000001 /* R-C-V */ #define NV_XVE_REV_ID_FIB_TWO 0x00000002 /* R---V */ #define NV_XVE_REV_ID_MASK 7:4 /* R-CVF */ #define NV_XVE_REV_ID_MASK_A 0x0000000A /* R-C-V */ #define NV_XVE_REV_ID_MASK_B 0x0000000B /* ----V */ #define NV_XVE_REV_ID_CLASS_CODE 31:8 /* R-CVF */ #define NV_XVE_REV_ID_CLASS_CODE_VGA 0x00030000 /* R-C-V */ #define NV_XVE_REV_ID_CLASS_CODE_3D 0x00030200 /* ----V */ #define NV_XVE_REV_ID_CLASS_CODE_MULTIMEDIA 0x00048000 /* ----V */ #define NV_XVE_MISC_1 0x0000000C /* RW-4R */ #define NV_XVE_MISC_1_CACHE_LINE_SIZE 7:0 /* RWIVF */ #define NV_XVE_MISC_1_CACHE_LINE_SIZE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_MISC_1_MASTER_LATENCY_TIMER 15:8 /* C--VF */ #define NV_XVE_MISC_1_MASTER_LATENCY_TIMER_0_CLOCKS 0x00000000 /* C---V */ #define NV_XVE_MISC_1_HEADER_TYPE 23:16 /* R-IVF */ #define NV_XVE_MISC_1_HEADER_TYPE_SINGLEFUNC 0x00000000 /* R-I-V */ #define NV_XVE_MISC_1_HEADER_TYPE_MULTIFUNC 0x00000080 /* R---V */ #define NV_XVE_MISC_1_BIST 31:24 /* C--VF */ #define NV_XVE_MISC_1_BIST_NULL 0x00000000 /* C---V */ #define NV_XVE_BAR0 0x00000010 /* RW-4R */ #define NV_XVE_BAR0_SPACE_TYPE 0:0 /* C--VF */ #define NV_XVE_BAR0_SPACE_TYPE_MEMORY 0x00000000 /* C---V */ #define NV_XVE_BAR0_ADDRESS_TYPE 2:1 /* R-IVF */ #define NV_XVE_BAR0_ADDRESS_TYPE_32_BIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR0_ADDRESS_TYPE_64_BIT 0x00000002 /* R---V */ #define NV_XVE_BAR0_PREFETCHABLE 3:3 /* R-IVF */ #define NV_XVE_BAR0_PREFETCHABLE_NOT 0x00000000 /* R-I-V */ #define NV_XVE_BAR0_PREFETCHABLE_MERGABLE 0x00000001 /* R---V */ #define NV_XVE_BAR0_BASE_ADDRESS 31:24 /* RWIVF */ #define NV_XVE_BAR0_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR1_LO 0x00000014 /* RW-4R */ #define NV_XVE_BAR1_LO_SPACE_TYPE 0:0 /* R--VF */ #define NV_XVE_BAR1_LO_SPACE_TYPE_MEMORY 0x00000000 /* R---V */ #define NV_XVE_BAR1_LO_ADDRESS_TYPE 2:1 /* R--VF */ #define NV_XVE_BAR1_LO_ADDRESS_TYPE_64_BIT 0x00000002 /* R---V */ #define NV_XVE_BAR1_LO_PREFETCHABLE 3:3 /* R--VF */ #define NV_XVE_BAR1_LO_PREFETCHABLE_MERGABLE 0x00000001 /* R---V */ #define NV_XVE_BAR1_LO_RSVD 25:4 /* R--VF */ #define NV_XVE_BAR1_LO_RSVD_NULL 0x00000000 /* R---V */ #define NV_XVE_BAR1_LO_BASE_ADDRESS 31:26 /* RWIVF */ #define NV_XVE_BAR1_LO_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR1_HI 0x00000018 /* RW-4R */ #define NV_XVE_BAR1_HI_BASE_ADDRESS 31:0 /* RWIVF */ #define NV_XVE_BAR1_HI_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR2_LO 0x0000001C /* RW-4R */ #define NV_XVE_BAR2_LO_SPACE_TYPE 0:0 /* R--VF */ #define NV_XVE_BAR2_LO_SPACE_TYPE_MEMORY 0x00000000 /* R---V */ #define NV_XVE_BAR2_LO_ADDRESS_TYPE 2:1 /* R--VF */ #define NV_XVE_BAR2_LO_ADDRESS_TYPE_64_BIT 0x00000002 /* R---V */ #define NV_XVE_BAR2_LO_PREFETCHABLE 3:3 /* R--VF */ #define NV_XVE_BAR2_LO_PREFETCHABLE_MERGABLE 0x00000001 /* R---V */ #define NV_XVE_BAR2_LO_RSVD 23:4 /* R--VF */ #define NV_XVE_BAR2_LO_RSVD_NULL 0x00000000 /* R---V */ #define NV_XVE_BAR2_LO_BASE_ADDRESS 31:24 /* RWIVF */ #define NV_XVE_BAR2_LO_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR2_HI 0x00000020 /* RW-4R */ #define NV_XVE_BAR2_HI_BASE_ADDRESS 31:0 /* RWIVF */ #define NV_XVE_BAR2_HI_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR3 0x00000024 /* RW-4R */ #define NV_XVE_BAR3_SPACE_TYPE 0:0 /* R-IVF */ #define NV_XVE_BAR3_SPACE_TYPE_MEMORY 0x00000000 /* ----V */ #define NV_XVE_BAR3_SPACE_TYPE_IO 0x00000001 /* R-I-V */ #define NV_XVE_BAR3_ADDRESS_TYPE 2:1 /* R-IVF */ #define NV_XVE_BAR3_ADDRESS_TYPE_32_BIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR3_ADDRESS_TYPE_20_BIT 0x00000001 /* ----V */ #define NV_XVE_BAR3_ADDRESS_TYPE_64_BIT 0x00000002 /* ----V */ #define NV_XVE_BAR3_PREFETCHABLE 3:3 /* R-IVF */ #define NV_XVE_BAR3_PREFETCHABLE_NOT 0x00000000 /* R-I-V */ #define NV_XVE_BAR3_PREFETCHABLE_MERGABLE 0x00000001 /* ----V */ #define NV_XVE_BAR3_RSVD 6:4 /* R-XVF */ #define NV_XVE_BAR3_RSVD_NULL 0x00000000 /* ----V */ #define NV_XVE_BAR3_BASE_ADDRESS 31:7 /* RWIVF */ #define NV_XVE_BAR3_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_CARDBUS 0x00000028 /* C--4R */ #define NV_XVE_CARDBUS_PTR 31:0 /* C--VF */ #define NV_XVE_CARDBUS_PTR_0 0x00000000 /* C---V */ #define NV_XVE_SUBSYSTEM 0x0000002C /* R--4R */ #define NV_XVE_SUBSYSTEM_VENDOR_ID 15:0 /* R-CVF */ #define NV_XVE_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R-C-V */ #define NV_XVE_SUBSYSTEM_ID_USER 19:16 /* R-CVF */ #define NV_XVE_SUBSYSTEM_ID_USER_NONE 0x00000000 /* R-C-V */ #define NV_XVE_SUBSYSTEM_ID_NON_USER 31:20 /* R-CVF */ #define NV_XVE_SUBSYSTEM_ID_NON_USER_NONE 0x00000000 /* R-C-V */ #define NV_XVE_ROM 0x00000030 /* RW-4R */ #define NV_XVE_ROM_DECODE 0:0 /* RWIVF */ #define NV_XVE_ROM_DECODE_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_ROM_DECODE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ROM_VALIDATION_STATUS 3:1 /* R-CVF */ #define NV_XVE_ROM_VALIDATION_STATUS_INIT 0x00000000 /* R-C-V */ #define NV_XVE_ROM_VALIDATION_DETAILS 7:4 /* R-CVF */ #define NV_XVE_ROM_VALIDATION_DETAILS_INIT 0x00000000 /* R-C-V */ #define NV_XVE_ROM_RSVD 15:11 /* C--VF */ #define NV_XVE_ROM_RSVD_NULL 0x00000000 /* C---V */ #define NV_XVE_ROM_BASE 31:16 /* RWIVF */ #define NV_XVE_ROM_BASE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_CAP_LIST 0x00000034 /* C--4R */ #define NV_XVE_CAP_LIST_CAP_PTR 7:0 /* C--VF */ #define NV_XVE_CAP_LIST_CAP_PTR_POWER_MGMT 0x00000060 /* C---V */ #define NV_XVE_RSVD_0 0x00000038 /* C--4R */ #define NV_XVE_RSVD_0_BITS 31:0 /* C--VF */ #define NV_XVE_RSVD_0_BITS_0 0x00000000 /* C---V */ #define NV_XVE_INTR_GNT 0x0000003C /* RW-4R */ #define NV_XVE_INTR_GNT_INTR_LINE 7:0 /* RWIVF */ #define NV_XVE_INTR_GNT_INTR_LINE_IRQ0 0x00000000 /* RWI-V */ #define NV_XVE_INTR_GNT_INTR_LINE_IRQ1 0x00000001 /* RW--V */ #define NV_XVE_INTR_GNT_INTR_LINE_IRQ15 0x0000000F /* RW--V */ #define NV_XVE_INTR_GNT_INTR_LINE_UNKNOWN 0x000000FF /* RW--V */ #define NV_XVE_INTR_GNT_INTR_PIN 15:8 /* C--VF */ #define NV_XVE_INTR_GNT_INTR_PIN_INTA 0x00000001 /* C---V */ #define NV_XVE_INTR_GNT_MIN_GNT 23:16 /* C--VF */ #define NV_XVE_INTR_GNT_MIN_GNT_NO_REQUIREMENTS 0x00000000 /* C---V */ #define NV_XVE_INTR_GNT_MAX_LAT 31:24 /* C--VF */ #define NV_XVE_INTR_GNT_MAX_LAT_NO_REQUIREMENTS 0x00000000 /* C---V */ #define NV_XVE_SUBSYSTEM_ALIAS 0x00000040 /* RW-4R */ #define NV_XVE_SUBSYSTEM_ALIAS_VENDOR_ID 15:0 /* RWCVF */ #define NV_XVE_SUBSYSTEM_ALIAS_VENDOR_ID_NONE 0x00000000 /* RWC-V */ #define NV_XVE_SUBSYSTEM_ALIAS_ID 31:16 /* RWCVF */ #define NV_XVE_SUBSYSTEM_ALIAS_ID_NONE 0x00000000 /* RWC-V */ #define NV_XVE_ROM_CTRL 0x00000050 /* RW-4R */ #define NV_XVE_ROM_CTRL__PRIV_LEVEL_MASK 0x00000AB4 /* */ #define NV_XVE_ROM_CTRL_ROM_SHADOW 0:0 /* RWIVF */ #define NV_XVE_ROM_CTRL_ROM_SHADOW_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_ROM_CTRL_ROM_SHADOW_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_OVERRIDE 1:1 /* RWCVF */ #define NV_XVE_ROM_CTRL_BASE_SIZE_OVERRIDE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE 7:4 /* RWCVF */ #define NV_XVE_ROM_CTRL_BASE_SIZE_0 0x00000000 /* RWC-V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_64K 0x00000001 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_128K 0x00000002 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_256K 0x00000003 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_512K 0x00000004 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_1M 0x00000005 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_2M 0x00000006 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_4M 0x00000007 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_8M 0x00000008 /* RW--V */ #define NV_XVE_ROM_CTRL_BASE_SIZE_16M 0x00000009 /* RW--V */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS 18:16 /* RWCVF */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS_UNSUPPORTED 0x00000000 /* RWC-V */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS_IN_PROGRESS 0x00000001 /* RW--V */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS_PASS_NO_TRUST 0x00000002 /* RW--V */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS_PASS_TRUSTED 0x00000003 /* RW--V */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS_FAIL 0x00000004 /* RW--V */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS_PASS_UNTRUSTED 0x00000005 /* RW--V */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS_WARN_NO_TRUST 0x00000006 /* RW--V */ #define NV_XVE_ROM_CTRL_VALIDATION_STATUS_WARN_TRUSTED 0x00000007 /* RW--V */ #define NV_XVE_ROM_CTRL_VALIDATION_DETAILS 23:20 /* RWCVF */ #define NV_XVE_ROM_CTRL_VALIDATION_DETAILS_INIT 0x00000000 /* RWC-V */ #define NV_XVE_VGA_MEM_DECODE 0x00000054 /* RW-4R */ #define NV_XVE_VGA_MEM_DECODE_VGA 0:0 /* RWCVF */ #define NV_XVE_VGA_MEM_DECODE_VGA_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_VGA_MEM_DECODE_VGA_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_MISC_3 0x00000058 /* RW-4R */ #define NV_XVE_MISC_3_SCRATCH 23:0 /* RWCVF */ #define NV_XVE_MISC_3_SCRATCH_DEFAULT 0x0023D6CE /* RWC-V */ #define NV_XVE_MISC_3_SWSCRATCH 31:24 /* RWCVF */ #define NV_XVE_MISC_3_SWSCRATCH_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID 0x0000005C /* RW-4R */ #define NV_XVE_OVERRIDE_ID__PRIV_LEVEL_MASK 0x00000AB4 /* */ #define NV_XVE_OVERRIDE_ID_UNUSED 3:0 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_UNUSED_INIT 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_DEV_WRITE 4:4 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_DEV_WRITE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_DEV_WRITE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_OVERRIDE_ID_DEV_READ 5:5 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_DEV_READ_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_DEV_READ_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_OVERRIDE_ID_REV_WRITE 6:6 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_REV_WRITE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_REV_WRITE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_OVERRIDE_ID_REV_READ 7:7 /* RWCVF */ #define NV_XVE_OVERRIDE_ID_REV_READ_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_OVERRIDE_ID_REV_READ_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PWR_MGMT_0 0x00000060 /* R--4R */ #define NV_XVE_PWR_MGMT_0_PME_D3_COLD 31:31 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_PME_D3_COLD_SUPPORTED 0x00000001 /* ----V */ #define NV_XVE_PWR_MGMT_0_PME_D3_COLD_NOT_SUPPORTED 0x00000000 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_PME_D3_HOT 30:30 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_PME_D3_HOT_SUPPORTED 0x00000001 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_PME_D3_HOT_NOT_SUPPORTED 0x00000000 /* ----V */ #define NV_XVE_PWR_MGMT_0_PME_D2 29:29 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_PME_D2_SUPPORTED 0x00000001 /* ----V */ #define NV_XVE_PWR_MGMT_0_PME_D2_NOT_SUPPORTED 0x00000000 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_PME_D1 28:28 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_PME_D1_SUPPORTED 0x00000001 /* ----V */ #define NV_XVE_PWR_MGMT_0_PME_D1_NOT_SUPPORTED 0x00000000 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_PME_D0 27:27 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_PME_D0_SUPPORTED 0x00000001 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_PME_D0_NOT_SUPPORTED 0x00000000 /* ----V */ #define NV_XVE_PWR_MGMT_0_D2 26:26 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_D2_SUPPORTED 0x00000001 /* ----V */ #define NV_XVE_PWR_MGMT_0_D2_NOT_SUPPORTED 0x00000000 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_D1 25:25 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_D1_SUPPORTED 0x00000001 /* ----V */ #define NV_XVE_PWR_MGMT_0_D1_NOT_SUPPORTED 0x00000000 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_AUX_CURRENT 24:22 /* R-CVF */ #define NV_XVE_PWR_MGMT_0_AUX_CURRENT_SELF_POWERED 0x00000000 /* R-C-V */ #define NV_XVE_PWR_MGMT_0_DSI 21:21 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_DSI_NOT_REQUIRED 0x00000000 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_PME_CLOCK 19:19 /* R-IVF */ #define NV_XVE_PWR_MGMT_0_PME_CLOCK_NOT_REQUIRED 0x00000000 /* R-I-V */ #define NV_XVE_PWR_MGMT_0_VERSION 18:16 /* C--VF */ #define NV_XVE_PWR_MGMT_0_VERSION_3 0x00000003 /* C---V */ #define NV_XVE_PWR_MGMT_0_NEXT_PTR 15:8 /* C--VF */ #define NV_XVE_PWR_MGMT_0_NEXT_PTR_MSI 0x00000068 /* C---V */ #define NV_XVE_PWR_MGMT_0_CAP_ID 7:0 /* C--VF */ #define NV_XVE_PWR_MGMT_0_CAP_ID_POWER_MGMT 0x00000001 /* C---V */ #define NV_XVE_PWR_MGMT_1 0x00000064 /* RW-4R */ #define NV_XVE_PWR_MGMT_1_PME_DATA 31:24 /* C--VF */ #define NV_XVE_PWR_MGMT_1_PME_DATA_UNS 0x00000000 /* C---V */ #define NV_XVE_PWR_MGMT_1_PME_BPCC 23:23 /* C--VF */ #define NV_XVE_PWR_MGMT_1_PME_BPCC_UNS 0x00000000 /* C---V */ #define NV_XVE_PWR_MGMT_1_PME_B2B3 22:22 /* C--VF */ #define NV_XVE_PWR_MGMT_1_PME_B2B3_UNS 0x00000000 /* C---V */ #define NV_XVE_PWR_MGMT_1_PME_STATUS 15:15 /* RWCVF */ #define NV_XVE_PWR_MGMT_1_PME_STATUS_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_PWR_MGMT_1_PME_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_PWR_MGMT_1_PME_STATUS_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_PWR_MGMT_1_PME_DATA_SCALE 14:13 /* C--VF */ #define NV_XVE_PWR_MGMT_1_PME_DATA_SCALE_UNS 0x00000000 /* C---V */ #define NV_XVE_PWR_MGMT_1_PME_DATA_SEL 12:9 /* C--VF */ #define NV_XVE_PWR_MGMT_1_PME_DATA_SEL_UNS 0x00000000 /* C---V */ #define NV_XVE_PWR_MGMT_1_PME 8:8 /* RWCVF */ #define NV_XVE_PWR_MGMT_1_PME_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PWR_MGMT_1_PME_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PWR_MGMT_1_NO_SOFT_RESET 3:3 /* R-IVF */ #define NV_XVE_PWR_MGMT_1_NO_SOFT_RESET_ENABLE 0x00000001 /* R-I-V */ #define NV_XVE_PWR_MGMT_1_NO_SOFT_RESET_DISABLE 0x00000000 /* R---V */ #define NV_XVE_PWR_MGMT_1_PWR_STATE 1:0 /* RWIVF */ #define NV_XVE_PWR_MGMT_1_PWR_STATE_D0 0x00000000 /* RWI-V */ #define NV_XVE_PWR_MGMT_1_PWR_STATE_D1 0x00000001 /* RW--V */ #define NV_XVE_PWR_MGMT_1_PWR_STATE_D2 0x00000002 /* RW--V */ #define NV_XVE_PWR_MGMT_1_PWR_STATE_D3HOT 0x00000003 /* RW--V */ #define NV_XVE_MSI_CTRL 0x00000068 /* RW-4R */ #define NV_XVE_MSI_CTRL_RSVD 31:24 /* C--VF */ #define NV_XVE_MSI_CTRL_RSVD_0 0x00000000 /* C---V */ #define NV_XVE_MSI_CTRL_64BIT_CAP 23:23 /* R-IVF */ #define NV_XVE_MSI_CTRL_64BIT_CAP_TRUE 0x00000001 /* R-I-V */ #define NV_XVE_MSI_CTRL_64BIT_CAP_FALSE 0x00000000 /* R---V */ #define NV_XVE_MSI_CTRL_MULT_EN 22:20 /* RWIVF */ #define NV_XVE_MSI_CTRL_MULT_EN_CODE0 0x00000000 /* RWI-V */ #define NV_XVE_MSI_CTRL_MULT_EN_CODE2 0x00000001 /* RW--V */ #define NV_XVE_MSI_CTRL_MULT_EN_CODE4 0x00000002 /* RW--V */ #define NV_XVE_MSI_CTRL_MULT_EN_CODE8 0x00000003 /* RW--V */ #define NV_XVE_MSI_CTRL_MULT_CAP 19:17 /* R-IVF */ #define NV_XVE_MSI_CTRL_MULT_CAP_CODE0 0x00000000 /* R-I-V */ #define NV_XVE_MSI_CTRL_MSI 16:16 /* RWIVF */ #define NV_XVE_MSI_CTRL_MSI_DISABLE 0x00000000 /* RWI-V */ #define NV_XVE_MSI_CTRL_MSI_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MSI_CTRL_NEXT_PTR 15:8 /* C--VF */ #define NV_XVE_MSI_CTRL_NEXT_PTR_PCIEXP 0x00000078 /* C---V */ #define NV_XVE_MSI_CTRL_CAP_ID 7:0 /* R-CVF */ #define NV_XVE_MSI_CTRL_CAP_ID_MSI 0x00000005 /* R-C-V */ #define NV_XVE_MSI_CTRL_CAP_ID_NULL 0x00000000 /* R---V */ #define NV_XVE_MSI_LOW_ADDR 0x0000006C /* RW-4R */ #define NV_XVE_MSI_LOW_ADDR_DWORD 31:2 /* RWIVF */ #define NV_XVE_MSI_LOW_ADDR_DWORD_0 0x00000000 /* RWI-V */ #define NV_XVE_MSI_LOW_ADDR_RSVD 1:0 /* C--VF */ #define NV_XVE_MSI_LOW_ADDR_RSVD_0 0x00000000 /* C---V */ #define NV_XVE_MSI_UPPER_ADDR 0x00000070 /* RW-4R */ #define NV_XVE_MSI_UPPER_ADDR_DWORD 31:0 /* RWIVF */ #define NV_XVE_MSI_UPPER_ADDR_DWORD_0 0x00000000 /* RWI-V */ #define NV_XVE_MSI_DATA 0x00000074 /* RW-4R */ #define NV_XVE_MSI_DATA_RSVD 31:16 /* R-IVF */ #define NV_XVE_MSI_DATA_RSVD_0 0x00000000 /* R-I-V */ #define NV_XVE_MSI_DATA_NON_RSVD 15:0 /* RWIVF */ #define NV_XVE_MSI_DATA_NON_RSVD_0 0x00000000 /* RWI-V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY 0x00000078 /* R--4R */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID 7:0 /* C--VF */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID_INIT 0x00000010 /* C---V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR 15:8 /* R-IVF */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_NULL 0x00000000 /* R-I-V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_MSGBOX 0x000000B4 /* R---V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_MSIX 0x000000C8 /* R---V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_VERSION 19:16 /* R-IVF */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_VERSION_GEN1 0x00000001 /* R---V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_VERSION_GEN2 0x00000002 /* R-I-V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE 23:20 /* R-IVF */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE_INIT 0x00000000 /* R-I-V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE_ENDPOINT 0x00000000 /* R---V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE_LEGACY 0x00000001 /* R---V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED 24:24 /* R-EVF */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED_INIT 0x00000000 /* R-E-V */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER 29:25 /* C--VF */ #define NV_XVE_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITY 0x0000007C /* R--4R */ #define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE 2:0 /* R-IVF */ #define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_INIT 0x00000001 /* R-I-V */ #define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_128B 0x00000000 /* R---V */ #define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_256B 0x00000001 /* R---V */ #define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_512B 0x00000002 /* R---V */ #define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_1024B 0x00000003 /* R---V */ #define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_2048B 0x00000004 /* R---V */ #define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_4096B 0x00000005 /* R---V */ #define NV_XVE_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED 4:3 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE 5:5 /* R-IVF */ #define NV_XVE_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE_INIT 0x00000001 /* R-I-V */ #define NV_XVE_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY 8:6 /* R-XVF */ #define NV_XVE_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY 11:9 /* R-XVF */ #define NV_XVE_DEVICE_CAPABILITY_RSVD 14:12 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITY_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING 15:15 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING_INIT 0x00000001 /* C---V */ #define NV_XVE_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE 25:18 /* R-EVF */ #define NV_XVE_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* R-E-V */ #define NV_XVE_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE 27:26 /* R-EVF */ #define NV_XVE_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* R-E-V */ #define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */ #define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */ #define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_SUPPORTED 0x00000001 /* R---V */ #define NV_XVE_DEVICE_CONTROL_STATUS 0x00000080 /* RW-4R */ #define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE 0:0 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE 1:1 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE 2:2 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE 3:3 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE 7:5 /* RWEVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_128B 0x00000000 /* R---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_256B 0x00000001 /* R---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_512B 0x00000002 /* R---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_1024B 0x00000003 /* R---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_2048B 0x00000004 /* R---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_4096B 0x00000005 /* R---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE 9:9 /* R-IVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT 0x00000000 /* R-I-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE 10:10 /* RWCVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT 0x00000001 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE 14:12 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT 0x00000002 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST 15:15 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST_INIT 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT 0x00000000 /* R-I-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED 20:20 /* R-IVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT 0x00000000 /* R-I-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT 0x00000000 /* R-I-V */ #define NV_XVE_LINK_CAPABILITIES 0x00000084 /* R--4R */ #define NV_XVE_LINK_CAPABILITIES_MAX_LINK_SPEED 3:0 /* R-XVF */ #define NV_XVE_LINK_CAPABILITIES_MAX_LINK_WIDTH 9:4 /* R-XVF */ #define NV_XVE_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT 11:10 /* R-IVF */ #define NV_XVE_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT_INIT 0x00000003 /* R-I-V */ #define NV_XVE_LINK_CAPABILITIES_L0S_EXIT_LATENCY 14:12 /* R-XVF */ #define NV_XVE_LINK_CAPABILITIES_L1_EXIT_LATENCY 17:15 /* R-XVF */ #define NV_XVE_LINK_CAPABILITIES_CLOCK_PM 18:18 /* R-IVF */ #define NV_XVE_LINK_CAPABILITIES_CLOCK_PM_INIT 0x00000000 /* R-I-V */ #define NV_XVE_LINK_CAPABILITIES_CLOCK_PM_DISABLE 0x00000000 /* R---V */ #define NV_XVE_LINK_CAPABILITIES_CLOCK_PM_ENABLE 0x00000001 /* R---V */ #define NV_XVE_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING 19:19 /* C--VF */ #define NV_XVE_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING 20:20 /* C--VF */ #define NV_XVE_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION 21:21 /* C--VF */ #define NV_XVE_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE 22:22 /* R-EVF */ #define NV_XVE_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_SUPPORTED 0x00000001 /* R-E-V */ #define NV_XVE_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_NOT_SUPPORTED 0x00000000 /* R---V */ #define NV_XVE_LINK_CAPABILITIES_PORT_NUMBER 31:24 /* R-XVF */ #define NV_XVE_LINK_CONTROL_STATUS 0x00000088 /* RW-4R */ #define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL 1:0 /* RWEVF */ #define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_INIT 0x00000000 /* RWE-V */ #define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_DISABLE 0x00000002 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_ENABLE 0x00000003 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY 3:3 /* RWEVF */ #define NV_XVE_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_INIT 0x00000000 /* RWE-V */ #define NV_XVE_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_64B 0x00000000 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_128B 0x00000001 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_DISABLE 4:4 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_DISABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_LINK_CONTROL_STATUS_RETRAIN_LINK 5:5 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_RETRAIN_LINK_INIT 0x00000000 /* C---V */ #define NV_XVE_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION 6:6 /* RWEVF */ #define NV_XVE_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION_INIT 0x00000000 /* RWE-V */ #define NV_XVE_LINK_CONTROL_STATUS_EXTENDED_SYNCH 7:7 /* RWEVF */ #define NV_XVE_LINK_CONTROL_STATUS_EXTENDED_SYNCH_INIT 0x00000000 /* RWE-V */ #define NV_XVE_LINK_CONTROL_STATUS_CLOCK_PM 8:8 /* RWEVF */ #define NV_XVE_LINK_CONTROL_STATUS_CLOCK_PM_INIT 0x00000000 /* RWE-V */ #define NV_XVE_LINK_CONTROL_STATUS_HW_AUTO_WIDTH_DISABLE 9:9 /* RWEVF */ #define NV_XVE_LINK_CONTROL_STATUS_HW_AUTO_WIDTH_DISABLE_INIT 0x00000000 /* RWE-V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN 10:10 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN_INIT 0x00000000 /* C---V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN 11:11 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN_INIT 0x00000000 /* C---V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED 19:16 /* R--VF */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 0x00000002 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 0x00000003 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH 25:20 /* R--VF */ #define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X1 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X2 0x00000002 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X4 0x00000004 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X8 0x00000008 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X16 0x00000010 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_RSVD 26:26 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_TRAINING 27:27 /* R-IVF */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_TRAINING_INIT 0x00000000 /* R-I-V */ #define NV_XVE_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON 28:28 /* R-EVF */ #define NV_XVE_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON_INIT 0x00000001 /* R-E-V */ #define NV_XVE_LINK_CONTROL_STATUS_DLL_ACTIVE 29:29 /* R-IVF */ #define NV_XVE_LINK_CONTROL_STATUS_DLL_ACTIVE_INIT 0x00000000 /* R-I-V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT 30:30 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INIT 0x00000000 /* C---V */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH 31:31 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES 0x0000008C /* C--4R */ #define NV_XVE_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT 0:0 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT 1:1 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT 2:2 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT 3:3 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT 4:4 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE 5:5 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE 6:6 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE 14:7 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE 16:15 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT 17:17 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_NO_COMMAND_COMPLETED_SUPPORT 18:18 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_NO_COMMAND_COMPLETED_SUPPORT_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER 31:19 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS 0x00000090 /* C--4R */ #define NV_XVE_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE 0:0 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE 1:1 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE 2:2 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE 3:3 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE 4:4 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE 5:5 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL 7:6 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL 9:8 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL 10:10 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL 11:11 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_ENABLE 12:12 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED 16:16 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED 17:17 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED 18:18 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED 19:19 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_COMMAND_COMPLETED 20:20 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE 21:21 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE 22:22 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATUS 23:23 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATUS_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED 24:24 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2 0x0000009C /* R--4R */ #define NV_XVE_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES 3:0 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_A_AND_B 0x00000003 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE 4:4 /* R-IVF */ #define NV_XVE_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_SUPPORTED 0x00000001 /* R-I-V */ #define NV_XVE_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_ARI_FORWARDING 5:5 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_ARI_FORWARDING_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING 6:6 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT 7:7 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT 8:8 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT 9:9 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING 10:10 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING 11:11 /* R--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING_NOT_SUPPORTED 0x00000000 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING_SUPPORTED 0x00000001 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_TPH_COMPLETER 13:12 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_TPH_COMPLETER_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER 16:16 /* R-EVF */ #define NV_XVE_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED 0x00000001 /* R-E-V */ #define NV_XVE_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_NOT_SUPPORTED 0x00000000 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER 17:17 /* R-EVF */ #define NV_XVE_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED 0x00000001 /* R-E-V */ #define NV_XVE_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_NOT_SUPPORTED 0x00000000 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_OBFF 19:18 /* R--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_OBFF_NOT_SUPPORTED 0x00000000 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_MSG_SGNL 0x00000001 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_WAKE_SGNL 0x00000002 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_MSG_WAKE_SGNL 0x00000003 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_EXTENDED_FMT 20:20 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_EXTENDED_FMT_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX 21:21 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_NOT_SUPPORTED 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX 23:22 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_BITS 30:24 /* C--VF */ #define NV_XVE_DEVICE_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_FRS 31:31 /* R-EVF */ #define NV_XVE_DEVICE_CAPABILITIES_2_FRS_SUPPORTED 0x00000001 /* R---V */ #define NV_XVE_DEVICE_CAPABILITIES_2_FRS_NOT_SUPPORTED 0x00000000 /* R-E-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES 3:0 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_LO 0x00000001 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_HI 0x00000002 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_LO 0x00000005 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_HI 0x00000006 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_DEFAULT 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE 4:4 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_ENABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_DISABLED 0x00000001 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE 5:5 /* C--VF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE 6:6 /* C--VF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING 7:7 /* C--VF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE 8:8 /* C--VF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE 9:9 /* C--VF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE_INIT 0x00000000 /* C---V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE 12:12 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE 14:13 /* RWIVF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_MSG_SGNL_VA 0x00000001 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_MSG_SGNL_VB 0x00000002 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_WAKE_SGNL 0x00000003 /* RW--V */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_BITS 31:15 /* C--VF */ #define NV_XVE_DEVICE_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */ #define NV_XVE_LINK_CAPABILITIES_2 0x000000A4 /* R--4R */ #define NV_XVE_LINK_CAPABILITIES_2_RSVD 0:0 /* C--VF */ #define NV_XVE_LINK_CAPABILITIES_2_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */ #define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */ #define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */ #define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */ #define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */ #define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4 0x0000000F /* R---V */ #define NV_XVE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT 8:8 /* C--VF */ #define NV_XVE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */ #define NV_XVE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP 23:23 /* R-EVF */ #define NV_XVE_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */ #define NV_XVE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP 24:24 /* R-EVF */ #define NV_XVE_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R-E-V */ #define NV_XVE_LINK_CAPABILITIES_2_RSVD1 31:25 /* C--VF */ #define NV_XVE_LINK_CAPABILITIES_2_RSVD1_INIT 0x00000000 /* C---V */ #define NV_XVE_LINK_CONTROL_STATUS_2 0x000000A8 /* RW-4R */ #define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED 3:0 /* RWCVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_GEN2_PROTO_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_2P5 0x00000001 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_5P0 0x00000002 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_8P0 0x00000003 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_16P0 0x00000004 /* RWC-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE 4:4 /* RWCVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_GEN2_PROTO_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE 5:5 /* RWCVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_RVSD 6:6 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_2_RVSD_0 0x00000000 /* C---V */ #define NV_XVE_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN 9:7 /* RWCVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE 10:10 /* RWCVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS 11:11 /* RWCVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS 15:12 /* RWCVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_CUR_DEEMPHASIS_LEVEL 16:16 /* R--VF */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE 17:17 /* R-CVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE_NOT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE_DONE 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL 18:18 /* R-CVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL_NOT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL_DONE 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL 19:19 /* R-CVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL_NOT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL_DONE 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL 20:20 /* R-CVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL_NOT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL_DONE 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST 21:21 /* RWCVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_SET 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_CLEAR 0x00000001 /* -W--V */ #define NV_XVE_LINK_CONTROL_STATUS_2_RET_PRESENCE_DET 22:22 /* R-CVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_RET_PRESENCE_DET_UNSET 0x00000000 /* R-C-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_RET_PRESENCE_DET_SET 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_2_2RET_PRESENCE_DET 23:23 /* R-CVF */ #define NV_XVE_LINK_CONTROL_STATUS_2_2RET_PRESENCE_DET_UNSET 0x00000000 /* R-C-V */ #define NV_XVE_LINK_CONTROL_STATUS_2_2RET_PRESENCE_DET_SET 0x00000001 /* R---V */ #define NV_XVE_LINK_CONTROL_STATUS_2_RSVD 31:25 /* C--VF */ #define NV_XVE_LINK_CONTROL_STATUS_2_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_SLOT_CAPABILITIES_2 0x000000AC /* C--4R */ #define NV_XVE_SLOT_CAPABILITIES_2_BITS 31:0 /* C--VF */ #define NV_XVE_SLOT_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */ #define NV_XVE_SLOT_CONTROL_STATUS_2 0x000000B0 /* C--4R */ #define NV_XVE_SLOT_CONTROL_STATUS_2_BITS 31:0 /* C--VF */ #define NV_XVE_SLOT_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY 0x000000B4 /* R--4R */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_LIST_CAPABILITY_ID 7:0 /* C--VF */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_LIST_CAPABILITY_ID_INIT 0x00000009 /* C---V */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_LIST_NEXT_CAPABILITY_PTR 15:8 /* R-IVF */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_INIT 0x00000000 /* R-I-V */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_MSIX 0x000000C8 /* R---V */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_LIST_LENGTH 23:16 /* C--VF */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_LIST_LENGTH_INIT 0x00000014 /* C---V */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_FEATURE_MSGBOX 24:24 /* C--VF */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_FEATURE_MSGBOX_ENABLED 0x00000001 /* C---V */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_FEATURE_RSVD 31:25 /* C--VF */ #define NV_XVE_VENDOR_SPECIFIC_CAPABILITY_FEATURE_RSVD_0 0x00000000 /* C---V */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND 0x000000B8 /* RW-4R */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND_INTR 31:31 /* RWIVF */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND_INTR_INIT 0x00000000 /* R-I-V */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND_BITS 30:0 /* RWIVF */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND_BITS_INIT 0x00000000 /* R-I-V */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_IN 0x000000BC /* RW-4R */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_IN_BITS 31:0 /* RWIVF */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_IN_BITS_INIT 0x00000000 /* R-I-V */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_OUT 0x000000C0 /* RW-4R */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_OUT_BITS 31:0 /* RWIVF */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_OUT_BITS_INIT 0x00000000 /* R-I-V */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX 0x000000C4 /* RWI4R */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX_BITS 7:0 /* RWIVF */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX_BITS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX_RSVD 31:8 /* C--VF */ #define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX_RSVD_0 0x00000000 /* C---V */ #define NV_XVE_MSIX_CAP_HDR 0x000000C8 /* RW-4R */ #define NV_XVE_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */ #define NV_XVE_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_MSIX_CAP_HDR_FUNCTION_MASK 30:30 /* RWIVF */ #define NV_XVE_MSIX_CAP_HDR_FUNCTION_MASK_MASKED 0x00000001 /* RW--V */ #define NV_XVE_MSIX_CAP_HDR_FUNCTION_MASK_UNMASKED 0x00000000 /* RWI-V */ #define NV_XVE_MSIX_CAP_HDR_RSVD 29:27 /* C--VF */ #define NV_XVE_MSIX_CAP_HDR_RSVD_VAL 0x00000000 /* C---V */ #define NV_XVE_MSIX_CAP_HDR_TABLE_SIZE 26:16 /* R-IVF */ #define NV_XVE_MSIX_CAP_HDR_TABLE_SIZE_PF 6 /* R-I-V */ #define NV_XVE_MSIX_CAP_HDR_NXT_PTR 15:8 /* C--VF */ #define NV_XVE_MSIX_CAP_HDR_NXT_PTR_NULL 0x00000000 /* C---V */ #define NV_XVE_MSIX_CAP_HDR_CAP_ID 7:0 /* C--VF */ #define NV_XVE_MSIX_CAP_HDR_CAP_ID_MSIX 0x00000011 /* C---V */ #define NV_XVE_MSIX_CAP_TABLE 0x000000CC /* C--4R */ #define NV_XVE_MSIX_CAP_TABLE_OFFSET 31:0 /* C--VF */ #define NV_XVE_MSIX_CAP_TABLE_OFFSET_VALUE 0x00B90000 /* C---V */ #define NV_XVE_MSIX_CAP_TABLE_BIR 2:0 /* C--VF */ #define NV_XVE_MSIX_CAP_TABLE_BIR_BAR0 0x00000000 /* C---V */ #define NV_XVE_MSIX_CAP_PBA 0x000000D0 /* C--4R */ #define NV_XVE_MSIX_CAP_PBA_OFFSET 31:0 /* C--VF */ #define NV_XVE_MSIX_CAP_PBA_OFFSET_VALUE 0x00BA0000 /* C---V */ #define NV_XVE_MSIX_CAP_PBA_BIR 2:0 /* C--VF */ #define NV_XVE_MSIX_CAP_PBA_BIR_BAR0 0x00000000 /* C---V */ #define NV_XVE_LINK_CAPABILITIES_OVERRIDE 0x000000F0 /* RW-4R */ #define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_WRITE 0:0 /* RWCVF */ #define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_WRITE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_WRITE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_READ 1:1 /* RWCVF */ #define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_READ_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_READ_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_VCCAP_HDR 0x00000100 /* R--4R */ #define NV_XVE_VCCAP_HDR_ID 15:0 /* C--VF */ #define NV_XVE_VCCAP_HDR_ID_VC 0x00000002 /* C---V */ #define NV_XVE_VCCAP_HDR_VER 19:16 /* C--VF */ #define NV_XVE_VCCAP_HDR_VER_1 0x00000001 /* C---V */ #define NV_XVE_VCCAP_HDR_NXT 31:20 /* R--VF */ #define NV_XVE_VCCAP_HDR_NXT_PWR_BUDGET 0x00000128 /* R---V */ #define NV_XVE_VCCAP_HDR_NXT_LTR 0x00000250 /* R---V */ #define NV_XVE_VCCAP_HDR_NXT_L1_SUBSTATES 0x00000258 /* R---V */ #define NV_XVE_VCCAP_PVC1 0x00000104 /* R-E4R */ #define NV_XVE_VCCAP_PVC1_EVC 2:0 /* R-EVF */ #define NV_XVE_VCCAP_PVC1_EVC_CNT 0x00000000 /* R-E-V */ #define NV_XVE_VCCAP_PVC1_LPVC 6:4 /* R-EVF */ #define NV_XVE_VCCAP_PVC1_LPVC_CNT 0x00000000 /* R-E-V */ #define NV_XVE_VCCAP_PVC1_REF 9:8 /* C--VF */ #define NV_XVE_VCCAP_PVC1_REF_100 0x00000000 /* C---V */ #define NV_XVE_VCCAP_PVC1_PATS 11:10 /* C--VF */ #define NV_XVE_VCCAP_PVC1_PATS_0 0x00000000 /* C---V */ #define NV_XVE_VCCAP_PVC2 0x00000108 /* C--4R */ #define NV_XVE_VCCAP_PVC2_ARB 7:0 /* C--VF */ #define NV_XVE_VCCAP_PVC2_ARB_0 0x00000000 /* C---V */ #define NV_XVE_VCCAP_PVC2_OFF 31:24 /* C--VF */ #define NV_XVE_VCCAP_PVC2_OFF_0 0x00000000 /* C---V */ #define NV_XVE_VCCAP_PCSR 0x0000010C /* RW-4R */ #define NV_XVE_VCCAP_PCSR_LOAD 0:0 /* C--VF */ #define NV_XVE_VCCAP_PCSR_LOAD_0 0x00000000 /* C---V */ #define NV_XVE_VCCAP_PCSR_SEL 3:1 /* RWEVF */ #define NV_XVE_VCCAP_PCSR_SEL_0 0x00000000 /* RWE-V */ #define NV_XVE_VCCAP_PCSR_STAT 16:16 /* C--VF */ #define NV_XVE_VCCAP_PCSR_STAT_0 0x00000000 /* C---V */ #define NV_XVE_VCCAP_VCR0 0x00000110 /* C--4R */ #define NV_XVE_VCCAP_VCR0_ALL 31:0 /* C--VF */ #define NV_XVE_VCCAP_VCR0_ALL_0 0x00000000 /* C---V */ #define NV_XVE_VCCAP_CTRL0 0x00000114 /* RW-4R */ #define NV_XVE_VCCAP_CTRL0_TC0 0:0 /* C--VF */ #define NV_XVE_VCCAP_CTRL0_TC0_ENABLE 0x00000001 /* C---V */ #define NV_XVE_VCCAP_CTRL0_MAP 7:1 /* RWEVF */ #define NV_XVE_VCCAP_CTRL0_MAP_ALL 0x0000007F /* RWE-V */ #define NV_XVE_VCCAP_CTRL0_LOAD 16:16 /* C--VF */ #define NV_XVE_VCCAP_CTRL0_LOAD_0 0x00000000 /* C---V */ #define NV_XVE_VCCAP_CTRL0_SEL 19:17 /* RWEVF */ #define NV_XVE_VCCAP_CTRL0_SEL_0 0x00000000 /* RWE-V */ #define NV_XVE_VCCAP_CTRL0_VCID 26:24 /* C--VF */ #define NV_XVE_VCCAP_CTRL0_VCID_0 0x00000000 /* C---V */ #define NV_XVE_VCCAP_CTRL0_VCEN 31:31 /* C--VF */ #define NV_XVE_VCCAP_CTRL0_VCEN_1 0x00000001 /* C---V */ #define NV_XVE_VCCAP_STAT0 0x00000118 /* R--4R */ #define NV_XVE_VCCAP_STAT0_PORT_ARBITRATION_TABLE_STATUS 0:0 /* C--VF */ #define NV_XVE_VCCAP_STAT0_PORT_ARBITRATION_TABLE_STATUS_DEFAULT 0x00000000 /* C---V */ #define NV_XVE_VCCAP_STAT0_VC_NEGOTIATION_PENDING 1:1 /* R-EVF */ #define NV_XVE_VCCAP_STAT0_VC_NEGOTIATION_PENDING_INIT 0x00000000 /* R-E-V */ #define NV_XVE_VCCAP_STAT0_ALL 31:2 /* C--VF */ #define NV_XVE_VCCAP_STAT0_ALL_0 0x00000000 /* C---V */ #define NV_XVE_PWR_BDGT_0 0x00000128 /* R--4R */ #define NV_XVE_PWR_BDGT_0_EXT_CAP_ID 15:0 /* C--VF */ #define NV_XVE_PWR_BDGT_0_EXT_CAP_ID_PCI_EXPRESS 0x00000004 /* C---V */ #define NV_XVE_PWR_BDGT_0_EXT_CAP_VERSION 19:16 /* C--VF */ #define NV_XVE_PWR_BDGT_0_EXT_CAP_VERSION_PWR_BDGT 0x00000001 /* C---V */ #define NV_XVE_PWR_BDGT_0_NEXT_EXT_CAP 31:20 /* R-IVF */ #define NV_XVE_PWR_BDGT_0_NEXT_EXT_CAP_NULL 0x00000000 /* R-I-V */ #define NV_XVE_PWR_BDGT_0_NEXT_EXT_CAP_AER 0x00000420 /* R---V */ #define NV_XVE_PWR_BDGT_0_NEXT_EXT_CAP_VEND_SPECIFIC_ENHANCED_CAP 0x00000600 /* R---V */ #define NV_XVE_PWR_BDGT_0_NEXT_EXT_CAP_SEC_PCIE_CAP 0x00000900 /* R---V */ #define NV_XVE_PWR_BDGT_1 0x0000012C /* RW-4R */ #define NV_XVE_PWR_BDGT_1_DSEL 7:0 /* RWIVF */ #define NV_XVE_PWR_BDGT_1_DSEL_00 0x00000000 /* RWI-V */ #define NV_XVE_PWR_BDGT_1_DSEL_01 0x00000001 /* RW--V */ #define NV_XVE_PWR_BDGT_1_DSEL_FF 0x000000FF /* RW--V */ #define NV_XVE_PWR_BDGT_1_RSVD 31:8 /* C--VF */ #define NV_XVE_PWR_BDGT_1_RSVD_0 0x00000000 /* C---V */ #define NV_XVE_PWR_BDGT_2 0x00000130 /* R--4R */ #define NV_XVE_PWR_BDGT_2_BASE_PWR 7:0 /* R-IVF */ #define NV_XVE_PWR_BDGT_2_BASE_PWR_3P3_WATTS 0x00000021 /* R-I-V */ #define NV_XVE_PWR_BDGT_2_BASE_PWR_00_9P9_WATTS 0x00000063 /* ----V */ #define NV_XVE_PWR_BDGT_2_BASE_PWR_01_9P9_WATTS 0x00000063 /* ----V */ #define NV_XVE_PWR_BDGT_2_BASE_PWR_02_66_WATTS 0x00000042 /* ----V */ #define NV_XVE_PWR_BDGT_2_BASE_PWR_03_66_WATTS 0x00000042 /* ----V */ #define NV_XVE_PWR_BDGT_2_BASE_PWR_04_150_WATTS 0x00000096 /* ----V */ #define NV_XVE_PWR_BDGT_2_BASE_PWR_05_150_WATTS 0x00000096 /* ----V */ #define NV_XVE_PWR_BDGT_2_BASE_PWR_END_TO_FF 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_SCALE 9:8 /* R-IVF */ #define NV_XVE_PWR_BDGT_2_SCALE_00_X0P1 0x00000001 /* R-I-V */ #define NV_XVE_PWR_BDGT_2_SCALE_01_X0P1 0x00000001 /* ----V */ #define NV_XVE_PWR_BDGT_2_SCALE_02_X1 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_SCALE_03_X1 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_SCALE_04_X1 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_SCALE_05_X1 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_SCALE_END_TO_FF 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_SUB_STATE 12:10 /* R-IVF */ #define NV_XVE_PWR_BDGT_2_PM_SUB_STATE_00 0x00000000 /* R-I-V */ #define NV_XVE_PWR_BDGT_2_PM_SUB_STATE_01 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_SUB_STATE_02 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_SUB_STATE_03 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_SUB_STATE_04 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_SUB_STATE_05 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_SUB_STATE_END_TO_FF 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_STATE 14:13 /* R-IVF */ #define NV_XVE_PWR_BDGT_2_PM_STATE_00_D0 0x00000000 /* R-I-V */ #define NV_XVE_PWR_BDGT_2_PM_STATE_01_D0 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_STATE_02_D0 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_STATE_03_D0 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_STATE_04_D0 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_STATE_05_D0 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_PM_STATE_END_TO_FF 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_TYPE 17:15 /* R-IVF */ #define NV_XVE_PWR_BDGT_2_TYPE_00_MAX 0x00000007 /* R-I-V */ #define NV_XVE_PWR_BDGT_2_TYPE_01_SUS 0x00000003 /* ----V */ #define NV_XVE_PWR_BDGT_2_TYPE_02_MAX 0x00000007 /* ----V */ #define NV_XVE_PWR_BDGT_2_TYPE_03_SUS 0x00000003 /* ----V */ #define NV_XVE_PWR_BDGT_2_TYPE_04_MAX 0x00000007 /* ----V */ #define NV_XVE_PWR_BDGT_2_TYPE_05_SUS 0x00000003 /* ----V */ #define NV_XVE_PWR_BDGT_2_TYPE_END_TO_FF 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_RAIL 20:18 /* R-IVF */ #define NV_XVE_PWR_BDGT_2_RAIL_00_3P3V 0x00000001 /* R-I-V */ #define NV_XVE_PWR_BDGT_2_RAIL_01_3P3V 0x00000001 /* ----V */ #define NV_XVE_PWR_BDGT_2_RAIL_02_12V 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_RAIL_03_12V 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_RAIL_04_THERMAL 0x00000007 /* ----V */ #define NV_XVE_PWR_BDGT_2_RAIL_05_THERMAL 0x00000007 /* ----V */ #define NV_XVE_PWR_BDGT_2_RAIL_END_TO_FF 0x00000000 /* ----V */ #define NV_XVE_PWR_BDGT_2_RSVD 31:21 /* R-IVF */ #define NV_XVE_PWR_BDGT_2_RSVD_0 0x00000000 /* R-I-V */ #define NV_XVE_PWR_BDGT_3 0x00000134 /* R--4R */ #define NV_XVE_PWR_BDGT_3_SYS_ALLOCATED 0:0 /* R-IVF */ #define NV_XVE_PWR_BDGT_3_SYS_ALLOCATED_INIT 0x00000000 /* R-I-V */ #define NV_XVE_PWR_BDGT_3_RSVD 31:1 /* C--VF */ #define NV_XVE_PWR_BDGT_3_RSVD_0 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_TIMEOUT 0x00000144 /* RW-4R */ #define NV_XVE_PRIV_XV_TIMEOUT_MILLISECOND 7:0 /* RWCVF */ #define NV_XVE_PRIV_XV_TIMEOUT_MILLISECOND_16 0x00000010 /* RWC-V */ #define NV_XVE_PRIV_XV_TIMEOUT_DISABLE 8:8 /* RWCVF */ #define NV_XVE_PRIV_XV_TIMEOUT_DISABLE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_XV_TIMEOUT_RSVD_MERGER_NP 19:16 /* C--VF */ #define NV_XVE_PRIV_XV_TIMEOUT_RSVD_MERGER_NP_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_TIMEOUT_RSVD_MERGER_PW 23:20 /* C--VF */ #define NV_XVE_PRIV_XV_TIMEOUT_RSVD_MERGER_PW_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_TIMEOUT_OVERRIDE 24:24 /* RWCVF */ #define NV_XVE_PRIV_XV_TIMEOUT_OVERRIDE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_XV_TIMEOUT_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PRIV_XV_TIMEOUT_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PRIV_MISC 0x0000014C /* RW-4R */ #define NV_XVE_PRIV_MISC_RSVD_WRR_NUM_CLK_PHASE 15:0 /* C--VF */ #define NV_XVE_PRIV_MISC_RSVD_WRR_NUM_CLK_PHASE_INIT 0x0000001B /* C---V */ #define NV_XVE_PRIV_MISC_RSVD_NUM_NPT_VC1 20:16 /* C--VF */ #define NV_XVE_PRIV_MISC_RSVD_NUM_NPT_VC1_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_MISC_CYA_NOT_USE_TC0_NON_COHERENT 21:21 /* RWCVF */ #define NV_XVE_PRIV_MISC_CYA_NOT_USE_TC0_NON_COHERENT_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_RSVD_CYA_SINGLE_FUNC 22:22 /* C--VF */ #define NV_XVE_PRIV_MISC_RSVD_CYA_SINGLE_FUNC_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_MISC_CYA_IGNORE_POISONED_WDATA 23:23 /* RWCVF */ #define NV_XVE_PRIV_MISC_CYA_IGNORE_POISONED_WDATA_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_COHERENT_RELAXED_ORDERING 24:24 /* RWCVF */ #define NV_XVE_PRIV_MISC_COHERENT_RELAXED_ORDERING_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_MISC_NON_COHERENT_RELAXED_ORDERING 25:25 /* RWCVF */ #define NV_XVE_PRIV_MISC_NON_COHERENT_RELAXED_ORDERING_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_MISC_RSVD_CYA_GPIO_XP_ENTER_L1 30:30 /* C--VF */ #define NV_XVE_PRIV_MISC_RSVD_CYA_GPIO_XP_ENTER_L1_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_MISC_CYA_PMCSR_POWER_STATE_D3HOT_IGNORE 31:31 /* RWCVF */ #define NV_XVE_PRIV_MISC_CYA_PMCSR_POWER_STATE_D3HOT_IGNORE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_XV_0 0x00000150 /* RW-4R */ #define NV_XVE_PRIV_XV_0_PM_PCIE_UTIL_MODE 2:0 /* RWCVF */ #define NV_XVE_PRIV_XV_0_PM_PCIE_UTIL_MODE_INIT 0x00000005 /* RWC-V */ #define NV_XVE_PRIV_XV_0_UNUSED 3:3 /* RWCVF */ #define NV_XVE_PRIV_XV_0_UNUSED_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_CPU_REQUEST_RELAXED_ORDERING 4:4 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_CPU_REQUEST_RELAXED_ORDERING_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_USE_SERR_ENABLE_FOR_ERROR_REPORTING 6:6 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_USE_SERR_ENABLE_FOR_ERROR_REPORTING_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_L0S_ENABLE 7:7 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_L0S_ENABLE_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_L0S_ENABLE_ENABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_0_CYA_L0S_ENABLE_DISABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_XV_0_CYA_L1_ENABLE 8:8 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_L1_ENABLE_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_L1_ENABLE_ENABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_0_CYA_L1_ENABLE_DISABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_16BYTES 9:9 /* C--VF */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_16BYTES_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_32BYTES 10:10 /* C--VF */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_32BYTES_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_64BYTES 11:11 /* C--VF */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_64BYTES_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_16BYTES 12:12 /* C--VF */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_16BYTES_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_32BYTES 13:13 /* C--VF */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_32BYTES_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_64BYTES 14:14 /* C--VF */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_64BYTES_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_128BYTES 15:15 /* C--VF */ #define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_128BYTES_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_0_RSVD_MERGER_HOLD_OFF_TIMER 23:16 /* C--VF */ #define NV_XVE_PRIV_XV_0_RSVD_MERGER_HOLD_OFF_TIMER_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_0_CYA_CPLD_TO_L1 24:24 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_CPLD_TO_L1_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_FORCE_SNOOP_WRITES_VC0 25:25 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_FORCE_SNOOP_WRITES_VC0_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_FORCE_SNOOP_READS_VC0 26:26 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_FORCE_SNOOP_READS_VC0_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0 0x00000154 /* RW-4R */ #define NV_XVE_CYA_0__PRIV_LEVEL_MASK 0x00000EC8 /* */ #define NV_XVE_CYA_0_RSVD1 3:0 /* RWCVF */ #define NV_XVE_CYA_0_RSVD1_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1 6:4 /* RWCVF */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1_LESS_THAN_1US 0x00000000 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1_1US_TO_2US 0x00000001 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1_2US_TO_4US 0x00000002 /* RWC-V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1_4US_TO_8US 0x00000003 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1_8US_TO_16US 0x00000004 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1_16US_TO_32US 0x00000005 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1_32US_TO_64US 0x00000006 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN1_MORE_THAN_64US 0x00000007 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2 9:7 /* RWCVF */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2_LESS_THAN_1US 0x00000000 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2_1US_TO_2US 0x00000001 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2_2US_TO_4US 0x00000002 /* RWC-V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2_4US_TO_8US 0x00000003 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2_8US_TO_16US 0x00000004 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2_16US_TO_32US 0x00000005 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2_32US_TO_64US 0x00000006 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN2_MORE_THAN_64US 0x00000007 /* R---V */ #define NV_XVE_CYA_0_RSVD_2 11:10 /* RWCVF */ #define NV_XVE_CYA_0_RSVD_2_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY 14:12 /* RWCVF */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY_LESS_THAN_64NS 0x00000000 /* R---V */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY_64NS_TO_128NS 0x00000001 /* R---V */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY_128NS_TO_256NS 0x00000002 /* R---V */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY_256NS_TO_512NS 0x00000003 /* R---V */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY_512NS_TO_1US 0x00000004 /* R---V */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY_1US_TO_2US 0x00000005 /* R---V */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY_2US_TO_4US 0x00000006 /* RW--V */ #define NV_XVE_CYA_0_L0S_ACCEPTABLE_LATENCY_MORE_THAN_4US 0x00000007 /* R-C-V */ #define NV_XVE_CYA_0_RSVD_3 15:15 /* RWCVF */ #define NV_XVE_CYA_0_RSVD_3_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_RSVD_DOWNSTREAM_NP 16:16 /* C--VF */ #define NV_XVE_CYA_0_RSVD_DOWNSTREAM_NP_INIT 0x00000000 /* C---V */ #define NV_XVE_CYA_0_SYSMEM_0B_FLUSH 17:17 /* RWCVF */ #define NV_XVE_CYA_0_SYSMEM_0B_FLUSH_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_SYSMEM_0B_FLUSH_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_0_SYSMEM_0B_FLUSH_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_0_DISABLE_4DW_TLP_CHECK 18:18 /* RWCVF */ #define NV_XVE_CYA_0_DISABLE_4DW_TLP_CHECK_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_DISABLE_4DW_TLP_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3 21:19 /* RWCVF */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3_LESS_THAN_1US 0x00000000 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3_1US_TO_2US 0x00000001 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3_2US_TO_4US 0x00000002 /* RWC-V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3_4US_TO_8US 0x00000003 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3_8US_TO_16US 0x00000004 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3_16US_TO_32US 0x00000005 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3_32US_TO_64US 0x00000006 /* R---V */ #define NV_XVE_CYA_0_L1_EXIT_LATENCY_GEN3_MORE_THAN_64US 0x00000007 /* R---V */ #define NV_XVE_CYA_0_ATTR_TC_MISMATCH_AS_MALFORM 22:22 /* RWCVF */ #define NV_XVE_CYA_0_ATTR_TC_MISMATCH_AS_MALFORM_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_0_ATTR_TC_MISMATCH_AS_MALFORM_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_CYA_0_SHADOW_PCIE_CAP_VERSION_ID 25:24 /* RWCVF */ #define NV_XVE_CYA_0_SHADOW_PCIE_CAP_VERSION_ID_GEN1 0x00000001 /* RW--V */ #define NV_XVE_CYA_0_SHADOW_PCIE_CAP_VERSION_ID_GEN2 0x00000002 /* RWC-V */ #define NV_XVE_CYA_0_SHADOW_ASPM_OPTIONALITY_COMPLIANCE 26:26 /* RWCVF */ #define NV_XVE_CYA_0_SHADOW_ASPM_OPTIONALITY_COMPLIANCE_SUPPORTED 0x00000001 /* RWC-V */ #define NV_XVE_CYA_0_SHADOW_ASPM_OPTIONALITY_COMPLIANCE_NOT_SUPPORTED 0x00000000 /* RW--V */ #define NV_XVE_CYA_0_MIN_LATENCY_CPLTO_REPORTING 27:27 /* RWCVF */ #define NV_XVE_CYA_0_MIN_LATENCY_CPLTO_REPORTING_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_CYA_0_MIN_LATENCY_CPLTO_REPORTING_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_HIDE_FN0_10_BIT_TAG_REQUESTER 28:28 /* RWCVF */ #define NV_XVE_CYA_0_HIDE_FN0_10_BIT_TAG_REQUESTER_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_HIDE_FN0_10_BIT_TAG_REQUESTER_TRUE 0x00000001 /* RW--V */ #define NV_XVE_CYA_0_HIDE_FN0_10_BIT_TAG_REQUESTER_FALSE 0x00000000 /* RW--V */ #define NV_XVE_CYA_0_HIDE_FN1_10_BIT_TAG_REQUESTER 29:29 /* RWCVF */ #define NV_XVE_CYA_0_HIDE_FN1_10_BIT_TAG_REQUESTER_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_HIDE_FN1_10_BIT_TAG_REQUESTER_TRUE 0x00000001 /* RW--V */ #define NV_XVE_CYA_0_HIDE_FN1_10_BIT_TAG_REQUESTER_FALSE 0x00000000 /* RW--V */ #define NV_XVE_CYA_0_HIDE_10_BIT_TAG_COMPLETER_SUPPORT 31:31 /* RWCVF */ #define NV_XVE_CYA_0_HIDE_10_BIT_TAG_COMPLETER_SUPPORT_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_0_HIDE_10_BIT_TAG_COMPLETER_SUPPORT_TRUE 0x00000001 /* RW--V */ #define NV_XVE_CYA_0_HIDE_10_BIT_TAG_COMPLETER_SUPPORT_FALSE 0x00000000 /* RW--V */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU 0x00000158 /* RW-4R */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU__PRIV_LEVEL_MASK 0x00000EC0 /* */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU_DL_UP 0:0 /* RWCVF */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU_DL_UP_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU_DL_UP_RESET 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU_DL_UP_NORESET 0x00000000 /* RW--V */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU_HOT_RESET 8:8 /* RWCVF */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU_HOT_RESET_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU_HOT_RESET_RESET 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_CYA_RESET_GPU_HOT_RESET_NORESET 0x00000000 /* RW--V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX 0x0000015C /* RW-4R */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_BASE_PWR 7:0 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_BASE_PWR_3P3_WATTS 0x00000021 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_SCALE 9:8 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_SCALE_X0P1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_PM_SUB_STATE 12:10 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_PM_SUB_STATE_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_PM_STATE 14:13 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_PM_STATE_D0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_TYPE 17:15 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_TYPE_MAX 0x00000007 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_RAIL 20:18 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_RAIL_3P3V 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_RSVD 31:21 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_MAX_RSVD_0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS 0x00000160 /* RW-4R */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_BASE_PWR 7:0 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_BASE_PWR_3P3_WATTS 0x00000021 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_SCALE 9:8 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_SCALE_X0P1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_PM_SUB_STATE 12:10 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_PM_SUB_STATE_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_PM_STATE 14:13 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_PM_STATE_D0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_TYPE 17:15 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_TYPE_SUS 0x00000003 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_RAIL 20:18 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_RAIL_3P3V 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_RSVD 31:21 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_3P3V_SUS_RSVD_0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX 0x00000164 /* RW-4R */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_BASE_PWR 7:0 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_BASE_PWR_2_WATTS 0x00000002 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_SCALE 9:8 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_SCALE_X1 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_PM_SUB_STATE 12:10 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_PM_SUB_STATE_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_PM_STATE 14:13 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_PM_STATE_D0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_TYPE 17:15 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_TYPE_MAX 0x00000007 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_RAIL 20:18 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_RAIL_12V 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_RSVD 31:21 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_MAX_RSVD_0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS 0x00000168 /* RW-4R */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_BASE_PWR 7:0 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_BASE_PWR_2_WATTS 0x00000002 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_SCALE 9:8 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_SCALE_X1 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_PM_SUB_STATE 12:10 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_PM_SUB_STATE_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_PM_STATE 14:13 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_PM_STATE_D0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_TYPE 17:15 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_TYPE_SUS 0x00000003 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_RAIL 20:18 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_RAIL_12V 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_RSVD 31:21 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_12V_SUS_RSVD_0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX 0x0000016C /* RW-4R */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_BASE_PWR 7:0 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_BASE_PWR_6_WATTS 0x00000006 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_SCALE 9:8 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_SCALE_X1 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_PM_SUB_STATE 12:10 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_PM_SUB_STATE_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_PM_STATE 14:13 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_PM_STATE_D0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_TYPE 17:15 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_TYPE_MAX 0x00000007 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_RAIL 20:18 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_RAIL_THERMAL 0x00000007 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_RSVD 31:21 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_MAX_RSVD_0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS 0x00000170 /* RW-4R */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_BASE_PWR 7:0 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_BASE_PWR_6_WATTS 0x00000006 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_SCALE 9:8 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_SCALE_X1 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_PM_SUB_STATE 12:10 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_PM_SUB_STATE_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_PM_STATE 14:13 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_PM_STATE_D0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_TYPE 17:15 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_TYPE_SUS 0x00000003 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_RAIL 20:18 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_RAIL_THERMAL 0x00000007 /* RWC-V */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_RSVD 31:21 /* RWCVF */ #define NV_XVE_PRIV_PWR_BDGT_THERMAL_SUS_RSVD_0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG 0x00000174 /* RW-4R */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG__PRIV_LEVEL_MASK 0x00000EC4 /* */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_DL_UP 0:0 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_DL_UP_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_DL_UP_RESET 0x00000001 /* RW--V */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_DL_UP_NORESET 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_HOT_RESET 8:8 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_HOT_RESET_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_HOT_RESET_RESET 0x00000001 /* RW--V */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_HOT_RESET_NORESET 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_D3HOT_NO_SOFT_RESET 16:16 /* RWCVF */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_D3HOT_NO_SOFT_RESET_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_0_CYA_RESET_CFG_D3HOT_NO_SOFT_RESET_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_LTR_0 0x00000250 /* R--4R */ #define NV_XVE_LTR_0_EXT_CAP_ID 15:0 /* C--VF */ #define NV_XVE_LTR_0_EXT_CAP_ID_LTR 0x00000018 /* C---V */ #define NV_XVE_LTR_0_EXT_CAP_VERSION 19:16 /* C--VF */ #define NV_XVE_LTR_0_EXT_CAP_VERSION_LTR 0x00000001 /* C---V */ #define NV_XVE_LTR_0_NEXT_EXT_CAP 31:20 /* R--VF */ #define NV_XVE_LTR_0_NEXT_EXT_CAP_PWR_BUDGET 0x00000128 /* R---V */ #define NV_XVE_LTR_0_NEXT_EXT_CAP_L1_SUBSTATES 0x00000258 /* R---V */ #define NV_XVE_LTR_1 0x00000254 /* RW-4R */ #define NV_XVE_LTR_1_SNOOP_LATENCY_VALUE 9:0 /* RWIVF */ #define NV_XVE_LTR_1_SNOOP_LATENCY_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_LTR_1_SNOOP_LATENCY_SCALE 12:10 /* RWIVF */ #define NV_XVE_LTR_1_SNOOP_LATENCY_SCALE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_LTR_1_NO_SNOOP_LATENCY_VALUE 25:16 /* RWIVF */ #define NV_XVE_LTR_1_NO_SNOOP_LATENCY_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_LTR_1_NO_SNOOP_LATENCY_SCALE 28:26 /* RWIVF */ #define NV_XVE_LTR_1_NO_SNOOP_LATENCY_SCALE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_L1_PM_SUBSTATES_EXT_CAP 0x00000258 /* C--4R */ #define NV_XVE_L1_PM_SUBSTATES_EXT_CAP_ID 15:0 /* C--VF */ #define NV_XVE_L1_PM_SUBSTATES_EXT_CAP_ID_L1_SUBSTATES 0x0000001E /* C---V */ #define NV_XVE_L1_PM_SUBSTATES_EXT_CAP_VERSION 19:16 /* C--VF */ #define NV_XVE_L1_PM_SUBSTATES_EXT_CAP_VERSION_L1_SUBSTATES 0x00000001 /* C---V */ #define NV_XVE_L1_PM_SUBSTATES_EXT_CAP_NEXT_CAP 31:20 /* C--VF */ #define NV_XVE_L1_PM_SUBSTATES_EXT_CAP_NEXT_CAP_PWR_BUDGET 0x00000128 /* C---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP 0x0000025C /* R--4R */ #define NV_XVE_L1_PM_SUBSTATES_CAP_PCI_PM_L1_2_SUPPORTED 0:0 /* R--VF */ #define NV_XVE_L1_PM_SUBSTATES_CAP_PCI_PM_L1_2_SUPPORTED_ENABLE 0x00000001 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_PCI_PM_L1_2_SUPPORTED_DISABLE 0x00000000 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_PCI_PM_L1_1_SUPPORTED 1:1 /* R--VF */ #define NV_XVE_L1_PM_SUBSTATES_CAP_PCI_PM_L1_1_SUPPORTED_ENABLE 0x00000001 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_PCI_PM_L1_1_SUPPORTED_DISABLE 0x00000000 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_ASPM_L1_2_SUPPORTED 2:2 /* R--VF */ #define NV_XVE_L1_PM_SUBSTATES_CAP_ASPM_L1_2_SUPPORTED_ENABLE 0x00000001 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_ASPM_L1_2_SUPPORTED_DISABLE 0x00000000 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_ASPM_L1_1_SUPPORTED 3:3 /* R--VF */ #define NV_XVE_L1_PM_SUBSTATES_CAP_ASPM_L1_1_SUPPORTED_ENABLE 0x00000001 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_ASPM_L1_1_SUPPORTED_DISABLE 0x00000000 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_L1_PM_SUBSTATES_SUPPORTED 4:4 /* R--VF */ #define NV_XVE_L1_PM_SUBSTATES_CAP_L1_PM_SUBSTATES_SUPPORTED_ENABLE 0x00000001 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_L1_PM_SUBSTATES_SUPPORTED_DISABLE 0x00000000 /* R---V */ #define NV_XVE_L1_PM_SUBSTATES_CAP_CM_RESTORE_TIME 15:8 /* R--VF */ #define NV_XVE_L1_PM_SUBSTATES_CAP_T_PWRON_SCALE 17:16 /* R--VF */ #define NV_XVE_L1_PM_SUBSTATES_CAP_T_PWRON_VALUE 23:19 /* R--VF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1 0x00000260 /* RW-4R */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_PCIPM_L1_2_EN 0:0 /* RWIVF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_PCIPM_L1_2_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_PCIPM_L1_1_EN 1:1 /* RWIVF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_PCIPM_L1_1_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_ASPM_L1_2_EN 2:2 /* RWIVF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_ASPM_L1_2_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_ASPM_L1_1_EN 3:3 /* RWIVF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_ASPM_L1_1_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_LTR_L1_2_THRES_VAL 25:16 /* RWIVF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_LTR_L1_2_THRES_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_LTR_L1_2_THRES_SCALE 31:29 /* RWIVF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL1_LTR_L1_2_THRES_SCALE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_L1_PM_SUBSTATES_CTRL2 0x00000264 /* RW-4R */ #define NV_XVE_L1_PM_SUBSTATES_CTRL2_T_PWRON_SCALE 1:0 /* RWIVF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL2_T_PWRON_SCALE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_L1_PM_SUBSTATES_CTRL2_T_PWRON_VALUE 7:3 /* RWIVF */ #define NV_XVE_L1_PM_SUBSTATES_CTRL2_T_PWRON_VALUE_INIT 0x00000005 /* RWI-V */ #define NV_XVE_ROM_SHADOW_OFFSET 0x00000418 /* RW-4R */ #define NV_XVE_ROM_SHADOW_OFFSET_VALUE 19:12 /* RWIVF */ #define NV_XVE_ROM_SHADOW_OFFSET_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_MISC_1 0x0000041C /* RW-4R */ #define NV_XVE_PRIV_MISC_1_NUM_NPT_VC1 7:0 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_NUM_NPT_VC1_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_AER 8:8 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_AER_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_AER_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_AER_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_VEND_SPECIFIC_ENHANCED_CAP 10:10 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_VEND_SPECIFIC_ENHANCED_CAP_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_VEND_SPECIFIC_ENHANCED_CAP_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_EN 11:11 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_EN_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_VAL 12:12 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_VAL_GEN1P1 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_VAL_GEN2 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_EN 13:13 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_EN_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_VAL 14:14 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_VAL_2P5 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_VAL_5P0 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_EN 15:15 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_EN_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_VAL 16:16 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_VAL_GEN2 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_VAL_GEN3 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_MSGBOX 17:17 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_MSGBOX_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_MSGBOX_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_LINKCAP_CLOCK_PM 18:18 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_LINKCAP_CLOCK_PM_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_LINKCAP_CLOCK_PM_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY 21:19 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_INIT 0x00000006 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_0 0x00000000 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_1 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_2 0x00000002 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_3 0x00000003 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_4 0x00000004 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_5 0x00000005 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_6 0x00000006 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_7 0x00000007 /* RW--V */ #define NV_XVE_PRIV_MISC_1_RSVD_CYA_NO_P2P_WRT_BUBBLE 22:22 /* C--VF */ #define NV_XVE_PRIV_MISC_1_RSVD_CYA_NO_P2P_WRT_BUBBLE_DISABLE 0x00000000 /* C---V */ #define NV_XVE_PRIV_MISC_1_CYA_ROUTE_MSGBOX_CMD_INTR_TO_PMU 23:23 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_ROUTE_MSGBOX_CMD_INTR_TO_PMU_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_ROUTE_MSGBOX_CMD_INTR_TO_PMU_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_SHADOW_RCB 24:24 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_SHADOW_RCB_64B 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_SHADOW_RCB_128B 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_RSVD_CYA_WR_BLOCK_CPL_ONLY_WHEN_P2P_CPL 25:25 /* C--VF */ #define NV_XVE_PRIV_MISC_1_RSVD_CYA_WR_BLOCK_CPL_ONLY_WHEN_P2P_CPL_DISABLE 0x00000000 /* C---V */ #define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_EN 26:26 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_EN_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_VAL 27:27 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_VAL_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_VAL_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING 28:28 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP 29:29 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_TRUE 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_HIDE_MSIX_CAP_FALSE 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_EN 30:30 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_EN_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_VAL 31:31 /* RWCVF */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_VAL_5P0 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_VAL_8P0 0x00000000 /* RWC-V */ #define NV_XVE_AER_CAP_HDR 0x00000420 /* R--4R */ #define NV_XVE_AER_CAP_HDR_ID 15:0 /* R-IVF */ #define NV_XVE_AER_CAP_HDR_ID_LINK_DEC 0x00000001 /* R-I-V */ #define NV_XVE_AER_CAP_HDR_ID_AER_DISABLED 0x00000000 /* R---V */ #define NV_XVE_AER_CAP_HDR_ID_VERSION 19:16 /* R-IVF */ #define NV_XVE_AER_CAP_HDR_ID_VERSION_1 0x00000001 /* R---V */ #define NV_XVE_AER_CAP_HDR_ID_VERSION_2 0x00000002 /* R-I-V */ #define NV_XVE_AER_CAP_HDR_ID_VERSION_AER_DISABLED 0x00000000 /* R---V */ #define NV_XVE_AER_CAP_HDR_ID_NEXT_PTR 31:20 /* R-IVF */ #define NV_XVE_AER_CAP_HDR_ID_NEXT_PTR_NONE 0x00000000 /* R---V */ #define NV_XVE_AER_CAP_HDR_ID_NEXT_PTR_VEND_SPECIFIC_ENHANCED_CAP 0x00000600 /* R-I-V */ #define NV_XVE_AER_CAP_HDR_ID_NEXT_PTR_SEC_PCIE_CAP 0x00000900 /* R---V */ #define NV_XVE_AER_CAP_HDR_ID_NEXT_PTR_AER_DISABLED 0x00000000 /* R---V */ #define NV_XVE_AER_UNCORR_ERR 0x00000424 /* RW-4R */ #define NV_XVE_AER_UNCORR_ERR_RSVD 0:0 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR 4:4 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_SURPRISE_DOWN 5:5 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SURPRISE_DOWN_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_POISONED_TLP 12:12 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_FC_PROTO_ERR 13:13 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_FC_PROTO_ERR_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_FC_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_FC_PROTO_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT 14:14 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_CPL_ABORT 15:15 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_CPL_ABORT_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_CPL_ABORT_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_CPL_ABORT_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL 16:16 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_RCVR_OVERFLOW 17:17 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_RCVR_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_RCVR_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_RCVR_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP 18:18 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_ECRC_ERROR 19:19 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_ECRC_ERROR_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ 20:20 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_UNCORR_ERR_ACS_VIOLATION 21:21 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_ACS_VIOLATION_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_INTERNAL_ERROR 22:22 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_INTERNAL_ERROR_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MC_BLOCKED_TLP 23:23 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED 25:25 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK 0x00000428 /* RW-4R */ #define NV_XVE_AER_UNCORR_ERR_MASK_RSVD 0:0 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR 4:4 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_SURPRISE_DOWN 5:5 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_SURPRISE_DOWN_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK_POISONED_TLP 12:12 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_POISONED_TLP_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_POISONED_TLP_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_FC_PROTO_ERR 13:13 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_CPL_TIMEOUT 14:14 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_CPL_ABORT 15:15 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_CPL_ABORT_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_CPL_ABORT_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_UNEXP_CPL 16:16 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_UNEXP_CPL_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_UNEXP_CPL_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW 17:17 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_MALFORMED_TLP 18:18 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_MALFORMED_TLP_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_MALFORMED_TLP_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_ECRC_ERR 19:19 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_ECRC_ERR_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ 20:20 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_MASK_ACS_VIOLATION 21:21 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_ACS_VIOLATION_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK_INTERNAL_ERROR 22:22 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_INTERNAL_ERROR_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP 23:23 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED 25:25 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_MASK_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_MASK_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR 0x0000042C /* RW-4R */ #define NV_XVE_AER_UNCORR_ERR_SEVR_RSVD 0:0 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR 4:4 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_NON_FATAL 0x00000000 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_FATAL 0x00000001 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN 5:5 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN_INIT 0x00000001 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_POISONED_TLP 12:12 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_POISONED_TLP_NON_FATAL 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_POISONED_TLP_FATAL 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR 13:13 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_NON_FATAL 0x00000000 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_FATAL 0x00000001 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT 14:14 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_NON_FATAL 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_FATAL 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_ABORT 15:15 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_ABORT_NON_FATAL 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_ABORT_FATAL 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_UNEXP_CPL 16:16 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_UNEXP_CPL_NON_FATAL 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_UNEXP_CPL_FATAL 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW 17:17 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_NON_FATAL 0x00000000 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_FATAL 0x00000001 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_MALFORMED_TLP 18:18 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_NON_FATAL 0x00000000 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_FATAL 0x00000001 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_ECRC_ERR 19:19 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_ECRC_ERR_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ 20:20 /* RWCVF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_NON_FATAL 0x00000000 /* RWC-V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_FATAL 0x00000001 /* RW--V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_ACS_VIOLATION 21:21 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_ACS_VIOLATION_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR 22:22 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR_INIT 0x00000001 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP 23:23 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED 25:25 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_UNCORR_ERR_SEVR_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */ #define NV_XVE_AER_UNCORR_ERR_SEVR_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_CORR_ERR 0x00000430 /* RW-4R */ #define NV_XVE_AER_CORR_ERR_RCV_ERR 0:0 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_RCV_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_CORR_ERR_RCV_ERR_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_CORR_ERR_RCV_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_CORR_ERR_BAD_TLP 6:6 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_BAD_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_CORR_ERR_BAD_TLP_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_CORR_ERR_BAD_TLP_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_CORR_ERR_BAD_DLLP 7:7 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_BAD_DLLP_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_CORR_ERR_BAD_DLLP_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_CORR_ERR_BAD_DLLP_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER 8:8 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT 12:12 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL 13:13 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_CORR_ERR_INTERNAL_ERROR 14:14 /* C--VF */ #define NV_XVE_AER_CORR_ERR_INTERNAL_ERROR_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_CORR_ERR_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_HEADER_LOG_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_AER_CORR_ERR_HEADER_LOG_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_AER_CORR_ERR_HEADER_LOG_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_AER_CORR_ERR_MASK 0x00000434 /* RW-4R */ #define NV_XVE_AER_CORR_ERR_MASK_RCV_ERR 0:0 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_MASK_RCV_ERR_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_CORR_ERR_MASK_RCV_ERR_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_CORR_ERR_MASK_BAD_TLP 6:6 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_MASK_BAD_TLP_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_CORR_ERR_MASK_BAD_TLP_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_CORR_ERR_MASK_BAD_DLLP 7:7 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_MASK_BAD_DLLP_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_CORR_ERR_MASK_BAD_DLLP_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_CORR_ERR_MASK_RPLY_ROLLOVER 8:8 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_MASK_RPLY_ROLLOVER_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_CORR_ERR_MASK_RPLY_ROLLOVER_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_CORR_ERR_MASK_RPLY_TIMEOUT 12:12 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_MASK_RPLY_TIMEOUT_NOT_MASKED 0x00000000 /* RWC-V */ #define NV_XVE_AER_CORR_ERR_MASK_RPLY_TIMEOUT_MASKED 0x00000001 /* RW--V */ #define NV_XVE_AER_CORR_ERR_MASK_ADVISORY_NONFATAL 13:13 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_NOT_MASKED 0x00000000 /* RW--V */ #define NV_XVE_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_MASKED 0x00000001 /* RWC-V */ #define NV_XVE_AER_CORR_ERR_MASK_INTERNAL_ERROR 14:14 /* C--VF */ #define NV_XVE_AER_CORR_ERR_MASK_INTERNAL_ERROR_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */ #define NV_XVE_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_NOT_MASKED 0x00000000 /* RW--V */ #define NV_XVE_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_MASKED 0x00000001 /* RWC-V */ #define NV_XVE_AER_CAP_CNTL 0x00000438 /* RW-4R */ #define NV_XVE_AER_CAP_CNTL_ERR_PTR 4:0 /* R--VF */ #define NV_XVE_AER_CAP_CNTL_ECRC_GEN_CAP 5:5 /* C--VF */ #define NV_XVE_AER_CAP_CNTL_ECRC_GEN_CAP_FALSE 0x00000000 /* C---V */ #define NV_XVE_AER_CAP_CNTL_ECRC_GEN_EN 6:6 /* RWCVF */ #define NV_XVE_AER_CAP_CNTL_ECRC_GEN_EN_FALSE 0x00000000 /* RWC-V */ #define NV_XVE_AER_CAP_CNTL_ECRC_GEN_EN_TRUE 0x00000001 /* RW--V */ #define NV_XVE_AER_CAP_CNTL_ECRC_CHK_CAP 7:7 /* C--VF */ #define NV_XVE_AER_CAP_CNTL_ECRC_CHK_CAP_FALSE 0x00000000 /* C---V */ #define NV_XVE_AER_CAP_CNTL_ECRC_CHK_EN 8:8 /* RWCVF */ #define NV_XVE_AER_CAP_CNTL_ECRC_CHK_EN_FALSE 0x00000000 /* RWC-V */ #define NV_XVE_AER_CAP_CNTL_ECRC_CHK_EN_TRUE 0x00000001 /* RW--V */ #define NV_XVE_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_CAP 9:9 /* C--VF */ #define NV_XVE_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_CAP_FALSE 0x00000000 /* C---V */ #define NV_XVE_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_EN 10:10 /* C--VF */ #define NV_XVE_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_EN_FALSE 0x00000000 /* C---V */ #define NV_XVE_AER_CAP_CNTL_TLP_PREFIX_LOG_PRESENT 11:11 /* C--VF */ #define NV_XVE_AER_CAP_CNTL_TLP_PREFIX_LOG_PRESENT_INIT 0x00000000 /* C---V */ #define NV_XVE_AER_HDR_LOG_DW0 0x0000043C /* R--4R */ #define NV_XVE_AER_HDR_LOG_DW0_0 31:0 /* R-CVF */ #define NV_XVE_AER_HDR_LOG_DW0_0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_AER_HDR_LOG_DW1 0x00000440 /* R--4R */ #define NV_XVE_AER_HDR_LOG_DW1_1 31:0 /* R-CVF */ #define NV_XVE_AER_HDR_LOG_DW1_1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_AER_HDR_LOG_DW2 0x00000444 /* R--4R */ #define NV_XVE_AER_HDR_LOG_DW2_2 31:0 /* R-CVF */ #define NV_XVE_AER_HDR_LOG_DW2_2_INIT 0x00000000 /* R-C-V */ #define NV_XVE_AER_HDR_LOG_DW3 0x00000448 /* R--4R */ #define NV_XVE_AER_HDR_LOG_DW3_3 31:0 /* R-CVF */ #define NV_XVE_AER_HDR_LOG_DW3_3_INIT 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_RSVD_MICROSECOND 0x0000047C /* RW-4R */ #define NV_XVE_PRIV_RSVD_MICROSECOND_GEN1 9:0 /* RWCVF */ #define NV_XVE_PRIV_RSVD_MICROSECOND_GEN1_250 0x000000FA /* RW--V */ #define NV_XVE_PRIV_RSVD_MICROSECOND_GEN1_500 0x000001F4 /* RWC-V */ #define NV_XVE_PRIV_RSVD_MICROSECOND_GEN2 19:10 /* RWCVF */ #define NV_XVE_PRIV_RSVD_MICROSECOND_GEN2_250 0x000000FA /* RW--V */ #define NV_XVE_PRIV_RSVD_MICROSECOND_GEN2_500 0x000001F4 /* RWC-V */ #define NV_XVE_PRIV_INTR 0x00000480 /* RW-4R */ #define NV_XVE_PRIV_INTR_CPL_TIMEOUT 0:0 /* RWIVF */ #define NV_XVE_PRIV_INTR_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_MSGBOX_INTERRUPT 1:1 /* RWIVF */ #define NV_XVE_PRIV_INTR_MSGBOX_INTERRUPT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_MSGBOX_INTERRUPT_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_AZA_CPL_TIMEOUT 2:2 /* RWIVF */ #define NV_XVE_PRIV_INTR_AZA_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_AZA_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_AZA_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT 3:3 /* RWIVF */ #define NV_XVE_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT 4:4 /* RWIVF */ #define NV_XVE_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_BAR_OVERLAP 5:5 /* RWIVF */ #define NV_XVE_PRIV_INTR_BAR_OVERLAP_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_BAR_OVERLAP_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_BAR_OVERLAP_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_P2PMASTER_CPL_TIMEOUT 8:8 /* RWIVF */ #define NV_XVE_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_P2P_SPLIT_ERR 9:9 /* RWIVF */ #define NV_XVE_PRIV_INTR_P2P_SPLIT_ERR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_P2P_SPLIT_ERR_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_P2P_SPLIT_ERR_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_OBFF_MSG 10:10 /* RWIVF */ #define NV_XVE_PRIV_INTR_OBFF_MSG_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_OBFF_MSG_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_OBFF_MSG_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_VF_FLR 11:11 /* RWIVF */ #define NV_XVE_PRIV_INTR_VF_FLR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_VF_FLR_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_VF_FLR_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_VF_DISABLE 12:12 /* RWIVF */ #define NV_XVE_PRIV_INTR_VF_DISABLE_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_VF_DISABLE_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_VF_DISABLE_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_VF_BME_GATED 13:13 /* RWIVF */ #define NV_XVE_PRIV_INTR_VF_BME_GATED_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_VF_BME_GATED_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_VF_BME_GATED_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_VF_TAG_CPL_TIMEOUT 15:15 /* RWIVF */ #define NV_XVE_PRIV_INTR_VF_TAG_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_VF_TAG_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_PRIV_INTR_VF_TAG_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_PRIV_INTR_EN 0x00000484 /* RW-4R */ #define NV_XVE_PRIV_INTR_EN_CPL_TIMEOUT 0:0 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_CPL_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_CPL_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_CPL_TIMEOUT__PROD 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_MSGBOX_INTERRUPT 1:1 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_MSGBOX_INTERRUPT_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_MSGBOX_INTERRUPT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_AZA_CPL_TIMEOUT 2:2 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_AZA_CPL_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_AZA_CPL_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_P2PSLAVE_CPL_TIMEOUT 3:3 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_P2PSLAVE_CPL_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_P2PSLAVE_CPL_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_POSTED_DEADLOCK_TIMEOUT 4:4 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_POSTED_DEADLOCK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_POSTED_DEADLOCK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_BAR_OVERLAP 5:5 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_BAR_OVERLAP_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_BAR_OVERLAP_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_P2PMASTER_CPL_TIMEOUT 8:8 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_P2PMASTER_CPL_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_P2PMASTER_CPL_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_P2P_SPLIT_ERR 9:9 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_P2P_SPLIT_ERR_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_P2P_SPLIT_ERR_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_OBFF_MSG 10:10 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_OBFF_MSG_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_OBFF_MSG_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_VF_FLR 11:11 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_VF_FLR_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_VF_FLR_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_VF_DISABLE 12:12 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_VF_DISABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_VF_DISABLE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_VF_BME_GATED 13:13 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_VF_BME_GATED_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_INTR_EN_VF_BME_GATED_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_INTR_EN_VF_TAG_CPL_TIMEOUT 15:15 /* RWIVF */ #define NV_XVE_PRIV_INTR_EN_VF_TAG_CPL_TIMEOUT_DISABLED 0x00000000 /* R-I-V */ #define NV_XVE_PRIV_INTR_EN_VF_TAG_CPL_TIMEOUT_ENABLED 0x00000001 /* R---V */ #define NV_XVE_PRIV_XV_1 0x00000488 /* RW-4R */ #define NV_XVE_PRIV_XV_1__PRIV_LEVEL_MASK 0x00000ECC /* */ #define NV_XVE_PRIV_XV_1_RSVD_CYA_XV2FB_BUSY_NP_NEXT 0:0 /* C--VF */ #define NV_XVE_PRIV_XV_1_RSVD_CYA_XV2FB_BUSY_NP_NEXT_INIT 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_1_RSVD_CYA_NP_ENTRIES_XV2FB_BUSY_NP_NEXT 5:1 /* C--VF */ #define NV_XVE_PRIV_XV_1_RSVD_CYA_NP_ENTRIES_XV2FB_BUSY_NP_NEXT_ZERO 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_1_CPL_PENDING 24:16 /* R--VF */ #define NV_XVE_PRIV_XV_1_CYA_XVE_MULTIFUNC 25:25 /* RWCVF */ #define NV_XVE_PRIV_XV_1_CYA_XVE_MULTIFUNC_INIT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_1_CYA_XVE_MULTIFUNC_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_1_CYA_XVE_MULTIFUNC_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PRIV_XV_1_UNUSED 31:26 /* RWCVF */ #define NV_XVE_PRIV_XV_1_UNUSED_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ERROR_COUNTER 0x000004AC /* R--4R */ #define NV_XVE_ERROR_COUNTER_RSVD_CORR_ERROR_COUNT_VALUE 7:0 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RSVD_CORR_ERROR_COUNT_VALUE_INIT 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_NON_FATAL_ERROR_COUNT_VALUE 15:8 /* R-XVF */ #define NV_XVE_ERROR_COUNTER_FATAL_ERROR_COUNT_VALUE 23:16 /* R-XVF */ #define NV_XVE_ERROR_COUNTER_UNSUPP_REQ_COUNT_VALUE 31:24 /* R-XVF */ #define NV_XVE_ERROR_COUNTER_FREEZE 0x000004B0 /* RW-4R */ #define NV_XVE_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT 0:0 /* RWCVF */ #define NV_XVE_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT 1:1 /* RWCVF */ #define NV_XVE_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT 2:2 /* RWCVF */ #define NV_XVE_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT 3:3 /* RWCVF */ #define NV_XVE_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ERROR_COUNTER_RESET 0x000004B8 /* RW-4R */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_CHIPSET_XMIT_L0S_ENTRY_COUNT 0:0 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_CHIPSET_XMIT_L0S_ENTRY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_GPU_XMIT_L0S_ENTRY_COUNT 1:1 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_GPU_XMIT_L0S_ENTRY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1_ENTRY_COUNT 2:2 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1_ENTRY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1P_ENTRY_COUNT 3:3 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1P_ENTRY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1_TO_RECOVERY_COUNT 4:4 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1_TO_RECOVERY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_L0_TO_RECOVERY_COUNT 5:5 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_L0_TO_RECOVERY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_CORR_ERROR_COUNT 6:6 /* RWCVF */ #define NV_XVE_ERROR_COUNTER_RESET_CORR_ERROR_COUNT_TRIGGER 0x00000001 /* -W--T */ #define NV_XVE_ERROR_COUNTER_RESET_CORR_ERROR_COUNT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_ERROR_COUNTER_RESET_CORR_ERROR_COUNT_PENDING 0x00000001 /* R---V */ #define NV_XVE_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT 7:7 /* RWCVF */ #define NV_XVE_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT_TRIGGER 0x00000001 /* -W--T */ #define NV_XVE_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT_PENDING 0x00000001 /* R---V */ #define NV_XVE_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT 8:8 /* RWCVF */ #define NV_XVE_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT_TRIGGER 0x00000001 /* -W--T */ #define NV_XVE_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT_PENDING 0x00000001 /* R---V */ #define NV_XVE_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT 9:9 /* RWCVF */ #define NV_XVE_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT_TRIGGER 0x00000001 /* -W--T */ #define NV_XVE_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT_PENDING 0x00000001 /* R---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_DEEP_L1_ENTRY_COUNT 10:10 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_DEEP_L1_ENTRY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_ASLM_COUNT 11:11 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_ASLM_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_NAK_COUNT 12:12 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_NAK_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_REPLAY_COUNT 13:13 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_REPLAY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_RECOVERY_COUNT 14:14 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_RECOVERY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_CLKREQ_DEASSERT_ENTRY_COUNT 15:15 /* C--VF */ #define NV_XVE_ERROR_COUNTER_RESET_RSVD_CLKREQ_DEASSERT_ENTRY_COUNT_DONE 0x00000000 /* C---V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0 0x000004C0 /* RW-4R */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0_PWH1_CRD_RESERVED 7:0 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0_PWH1_CRD_RESERVED_INIT 0x00000003 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0_NPH1_CRD_RESERVED 15:8 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0_NPH1_CRD_RESERVED_INIT 0x00000003 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0_PWD1_CRD_RESERVED 27:16 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0_PWD1_CRD_RESERVED_INIT 0x00000018 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0_SPARE 31:28 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL0_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL1 0x000004C4 /* RW-4R */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL1_CPLH1_CRD_RESERVED 7:0 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL1_CPLH1_CRD_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL1_CPLD1_CRD_RESERVED 19:8 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL1_CPLD1_CRD_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL1_NPD1_CRD_RESERVED 31:20 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL1_NPD1_CRD_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2 0x000004C8 /* RW-4R */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_PWH1_CRD_RESERVATION_ENABLE 0:0 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_PWH1_CRD_RESERVATION_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_PWH1_CRD_RESERVATION_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_PWH1_CRD_RESERVATION_ENABLE_EN 0x00000001 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_NPH1_CRD_RESERVATION_ENABLE 1:1 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_NPH1_CRD_RESERVATION_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_NPH1_CRD_RESERVATION_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_NPH1_CRD_RESERVATION_ENABLE_EN 0x00000001 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_PWD1_CRD_RESERVATION_ENABLE 2:2 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_PWD1_CRD_RESERVATION_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_PWD1_CRD_RESERVATION_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_PWD1_CRD_RESERVATION_ENABLE_EN 0x00000001 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_CPLH1_CRD_RESERVATION_ENABLE 3:3 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_CPLH1_CRD_RESERVATION_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_CPLH1_CRD_RESERVATION_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_CPLH1_CRD_RESERVATION_ENABLE_EN 0x00000001 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_CPLD1_CRD_RESERVATION_ENABLE 4:4 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_CPLD1_CRD_RESERVATION_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_CPLD1_CRD_RESERVATION_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_CPLD1_CRD_RESERVATION_ENABLE_EN 0x00000001 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_NPD1_CRD_RESERVATION_ENABLE 5:5 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_NPD1_CRD_RESERVATION_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_NPD1_CRD_RESERVATION_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_NPD1_CRD_RESERVATION_ENABLE_EN 0x00000001 /* RW--V */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_SPARE 31:6 /* RWIVF */ #define NV_XVE_PRIV_PSEUDO_VC_CTRL2_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_0 0x000004CC /* R--4R */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_0_NUM_PWH_CREDITS 7:0 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_0_NUM_NPH_CREDITS 15:8 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_0_NUM_PWD_CREDITS 27:16 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_1 0x000004D0 /* R--4R */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_1_NUM_CPLH_CREDITS 7:0 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_1_NUM_CPLD_CREDITS 19:8 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_1_NUM_NPD_CREDITS 31:20 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_2 0x000004D4 /* R--4R */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_2_PWH_SCALE_FACTOR 1:0 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_2_PWD_SCALE_FACTOR 3:2 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_2_NPH_SCALE_FACTOR 5:4 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_2_NPD_SCALE_FACTOR 7:6 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_2_CPLH_SCALE_FACTOR 9:8 /* R--VF */ #define NV_XVE_REMOTE_CREDIT_ADVERTISED_2_CPLD_SCALE_FACTOR 11:10 /* R--VF */ #define NV_XVE_PM_CTRL 0x000004E0 /* RW-4R */ #define NV_XVE_PM_CTRL_SEL0 7:0 /* RWCUF */ #define NV_XVE_PM_CTRL_SEL0_GRP0 0x00000000 /* RWC-V */ #define NV_XVE_PM_CTRL_SEL0_GRP1 0x00000001 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP2 0x00000002 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP3 0x00000003 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP4 0x00000004 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP5 0x00000005 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP6 0x00000006 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP7 0x00000007 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP8 0x00000008 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP9 0x00000009 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP10 0x0000000a /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP11 0x0000000b /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP12 0x0000000c /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP13 0x0000000d /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP14 0x0000000e /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP15 0x0000000f /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP16 0x00000010 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP17 0x00000011 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP18 0x00000012 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP19 0x00000013 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP20 0x00000014 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP21 0x00000015 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP22 0x00000016 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP23 0x00000017 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP24 0x00000018 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP25 0x00000019 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP26 0x0000001a /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP27 0x0000001b /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP28 0x0000001c /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP29 0x0000001d /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP30 0x0000001e /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP31 0x0000001f /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP32 0x00000020 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP33 0x00000021 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP34 0x00000022 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP35 0x00000023 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP36 0x00000024 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP37 0x00000025 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP38 0x00000026 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP39 0x00000027 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP40 0x00000028 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP41 0x00000029 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP42 0x0000002a /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP43 0x0000002b /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP44 0x0000002c /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP45 0x0000002d /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP46 0x0000002e /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP47 0x0000002f /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP48 0x00000030 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP49 0x00000031 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP50 0x00000032 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP51 0x00000033 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP52 0x00000034 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP53 0x00000035 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP54 0x00000036 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP55 0x00000037 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP56 0x00000038 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP57 0x00000039 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP58 0x0000003a /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP59 0x0000003b /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP60 0x0000003c /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP61 0x0000003d /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP62 0x0000003e /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP63 0x0000003f /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP64 0x00000040 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP65 0x00000041 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP66 0x00000042 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP67 0x00000043 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP68 0x00000044 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP69 0x00000045 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP70 0x00000046 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP71 0x00000047 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP72 0x00000048 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP73 0x00000049 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP74 0x0000004A /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP75 0x0000004B /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP76 0x0000004C /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP77 0x0000004D /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP78 0x0000004E /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP79 0x0000004F /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP80 0x00000050 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP81 0x00000051 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP82 0x00000052 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP83 0x00000053 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP84 0x00000054 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP85 0x00000055 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP86 0x00000056 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP87 0x00000057 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_STATIC_PATTERN_1555_13_GROUP 0x0000005E /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_STATIC_PATTERN_0AAA_13_GROUP 0x0000005F /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP_MAX 0x00000060 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP0_SC 0x00000080 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP1_SC 0x00000081 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP2_SC 0x00000082 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP3_SC 0x00000083 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP4_SC 0x00000084 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP5_SC 0x00000085 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP6_SC 0x00000086 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP7_SC 0x00000087 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP8_SC 0x00000088 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP9_SC 0x00000089 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP10_SC 0x0000008a /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP11_SC 0x0000008b /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP12_SC 0x0000008c /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP13_SC 0x0000008d /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP14_SC 0x0000008e /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP15_SC 0x0000008f /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP16_SC 0x00000090 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP17_SC 0x00000091 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP18_SC 0x00000092 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP19_SC 0x00000093 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP20_SC 0x00000094 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP21_SC 0x00000095 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP22_SC 0x00000096 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP23_SC 0x00000097 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP24_SC 0x00000098 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP25_SC 0x00000099 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP26_SC 0x0000009a /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP27_SC 0x0000009b /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP28_SC 0x0000009c /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP29_SC 0x0000009d /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP30_SC 0x0000009e /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP31_SC 0x0000009f /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP32_SC 0x000000a0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP33_SC 0x000000a1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP34_SC 0x000000a2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP35_SC 0x000000a3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP36_SC 0x000000a4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP37_SC 0x000000a5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP38_SC 0x000000a6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP39_SC 0x000000a7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP40_SC 0x000000a8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP41_SC 0x000000a9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP42_SC 0x000000aa /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP43_SC 0x000000ab /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP44_SC 0x000000ac /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP45_SC 0x000000ad /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP46_SC 0x000000ae /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP47_SC 0x000000af /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP48_SC 0x000000b0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP49_SC 0x000000b1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP50_SC 0x000000b2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP51_SC 0x000000b3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP52_SC 0x000000b4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP53_SC 0x000000b5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP54_SC 0x000000b6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP55_SC 0x000000b7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP56_SC 0x000000b8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP57_SC 0x000000b9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP58_SC 0x000000ba /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP59_SC 0x000000bb /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP60_SC 0x000000bc /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP61_SC 0x000000bd /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP62_SC 0x000000be /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP63_SC 0x000000bf /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP64_SC 0x000000c0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP65_SC 0x000000c1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP66_SC 0x000000c2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP67_SC 0x000000c3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP68_SC 0x000000c4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP69_SC 0x000000c5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP70_SC 0x000000c6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP71_SC 0x000000c7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP72_SC 0x000000c8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP73_SC 0x000000c9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP74_SC 0x000000ca /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP75_SC 0x000000cb /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP76_SC 0x000000cc /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP77_SC 0x000000cd /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP78_SC 0x000000ce /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP79_SC 0x000000cf /* RW--V */ #define NV_XVE_PM_CTRL_SEL0_GRP_MAX_SC 0x000000cf /* RW--V */ #define NV_XVE_PM_CTRL_SEL1 15:8 /* RWCUF */ #define NV_XVE_PM_CTRL_SEL1_GRP0 0x00000000 /* RWC-V */ #define NV_XVE_PM_CTRL_SEL1_GRP1 0x00000001 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP2 0x00000002 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP3 0x00000003 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP4 0x00000004 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP5 0x00000005 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP6 0x00000006 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP7 0x00000007 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP8 0x00000008 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP9 0x00000009 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP10 0x0000000a /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP11 0x0000000b /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP12 0x0000000c /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP13 0x0000000d /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP14 0x0000000e /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP15 0x0000000f /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP16 0x00000010 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP17 0x00000011 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP18 0x00000012 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP19 0x00000013 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP20 0x00000014 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP21 0x00000015 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP22 0x00000016 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP23 0x00000017 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP24 0x00000018 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP25 0x00000019 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP26 0x0000001a /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP27 0x0000001b /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP28 0x0000001c /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP29 0x0000001d /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP30 0x0000001e /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP31 0x0000001f /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP32 0x00000020 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP33 0x00000021 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP34 0x00000022 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP35 0x00000023 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP36 0x00000024 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP37 0x00000025 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP38 0x00000026 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP39 0x00000027 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP40 0x00000028 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP41 0x00000029 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP42 0x0000002a /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP43 0x0000002b /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP44 0x0000002c /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP45 0x0000002d /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP46 0x0000002e /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP47 0x0000002f /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP48 0x00000030 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP49 0x00000031 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP50 0x00000032 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP51 0x00000033 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP52 0x00000034 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP53 0x00000035 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP54 0x00000036 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP55 0x00000037 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP56 0x00000038 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP57 0x00000039 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP58 0x0000003a /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP59 0x0000003b /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP60 0x0000003c /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP61 0x0000003d /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP62 0x0000003e /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP63 0x0000003f /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP64 0x00000040 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP65 0x00000041 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP66 0x00000042 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP67 0x00000043 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP68 0x00000044 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP69 0x00000045 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP70 0x00000046 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP71 0x00000047 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP72 0x00000048 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP73 0x00000049 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP74 0x0000004A /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP75 0x0000004B /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP76 0x0000004C /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP77 0x0000004D /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP78 0x0000004E /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP79 0x0000004F /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP80 0x00000050 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP81 0x00000051 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_STATIC_PATTERN_1111_13_GROUP 0x0000005E /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_STATIC_PATTERN_0EEE_13_GROUP 0x0000005F /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP_MAX 0x0000005F /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP0_SC 0x00000080 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP1_SC 0x00000081 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP2_SC 0x00000082 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP3_SC 0x00000083 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP4_SC 0x00000084 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP5_SC 0x00000085 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP6_SC 0x00000086 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP7_SC 0x00000087 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP8_SC 0x00000088 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP9_SC 0x00000089 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP10_SC 0x0000008a /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP11_SC 0x0000008b /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP12_SC 0x0000008c /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP13_SC 0x0000008d /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP14_SC 0x0000008e /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP15_SC 0x0000008f /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP16_SC 0x00000090 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP17_SC 0x00000091 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP18_SC 0x00000092 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP19_SC 0x00000093 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP20_SC 0x00000094 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP21_SC 0x00000095 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP22_SC 0x00000096 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP23_SC 0x00000097 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP24_SC 0x00000098 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP25_SC 0x00000099 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP26_SC 0x0000009a /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP27_SC 0x0000009b /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP28_SC 0x0000009c /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP29_SC 0x0000009d /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP30_SC 0x0000009e /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP31_SC 0x0000009f /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP32_SC 0x000000a0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP33_SC 0x000000a1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP34_SC 0x000000a2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP35_SC 0x000000a3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP36_SC 0x000000a4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP37_SC 0x000000a5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP38_SC 0x000000a6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP39_SC 0x000000a7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP40_SC 0x000000a8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP41_SC 0x000000a9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP42_SC 0x000000aa /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP43_SC 0x000000ab /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP44_SC 0x000000ac /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP45_SC 0x000000ad /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP46_SC 0x000000ae /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP47_SC 0x000000af /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP48_SC 0x000000b0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP49_SC 0x000000b1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP50_SC 0x000000b2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP51_SC 0x000000b3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP52_SC 0x000000b4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP53_SC 0x000000b5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP54_SC 0x000000b6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP55_SC 0x000000b7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP56_SC 0x000000b8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP57_SC 0x000000b9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP58_SC 0x000000ba /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP59_SC 0x000000bb /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP60_SC 0x000000bc /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP61_SC 0x000000bd /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP62_SC 0x000000be /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP63_SC 0x000000bf /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP64_SC 0x000000c0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP65_SC 0x000000c1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP66_SC 0x000000c2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP67_SC 0x000000c3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP68_SC 0x000000c4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP69_SC 0x000000c5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP70_SC 0x000000c6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP71_SC 0x000000c7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP72_SC 0x000000c8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP73_SC 0x000000c9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP74_SC 0x000000ca /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP75_SC 0x000000cb /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP76_SC 0x000000cc /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP77_SC 0x000000cd /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP78_SC 0x000000ce /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP79_SC 0x000000cf /* RW--V */ #define NV_XVE_PM_CTRL_SEL1_GRP_MAX_SC 0x000000cf /* RW--V */ #define NV_XVE_PM_CTRL_SEL2 23:16 /* RWCUF */ #define NV_XVE_PM_CTRL_SEL2_GRP0 0x00000000 /* RWC-V */ #define NV_XVE_PM_CTRL_SEL2_GRP1 0x00000001 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP2 0x00000002 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP3 0x00000003 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP4 0x00000004 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP5 0x00000005 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP6 0x00000006 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP7 0x00000007 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP8 0x00000008 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP9 0x00000009 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP10 0x0000000a /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP11 0x0000000b /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP12 0x0000000c /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP13 0x0000000d /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP14 0x0000000e /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP15 0x0000000f /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP16 0x00000010 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP17 0x00000011 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP18 0x00000012 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP19 0x00000013 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP20 0x00000014 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP21 0x00000015 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP22 0x00000016 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP23 0x00000017 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP24 0x00000018 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP25 0x00000019 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP26 0x0000001a /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP27 0x0000001b /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP28 0x0000001c /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP29 0x0000001d /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP30 0x0000001e /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP31 0x0000001f /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP32 0x00000020 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP33 0x00000021 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP34 0x00000022 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP35 0x00000023 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP36 0x00000024 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP37 0x00000025 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP38 0x00000026 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP39 0x00000027 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP40 0x00000028 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP41 0x00000029 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP42 0x0000002a /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP43 0x0000002b /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP44 0x0000002c /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP45 0x0000002d /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP46 0x0000002e /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP47 0x0000002f /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP48 0x00000030 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP49 0x00000031 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP50 0x00000032 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP51 0x00000033 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP52 0x00000034 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP53 0x00000035 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP54 0x00000036 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP55 0x00000037 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP56 0x00000038 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP57 0x00000039 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP58 0x0000003a /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP59 0x0000003b /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP60 0x0000003c /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP61 0x0000003d /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP62 0x0000003e /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP63 0x0000003f /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP64 0x00000040 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP65 0x00000041 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP66 0x00000042 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP67 0x00000043 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP68 0x00000044 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP69 0x00000045 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP70 0x00000046 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP71 0x00000047 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP_MAX 0x00000047 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP0_SC 0x00000080 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP1_SC 0x00000081 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP2_SC 0x00000082 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP3_SC 0x00000083 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP4_SC 0x00000084 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP5_SC 0x00000085 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP6_SC 0x00000086 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP7_SC 0x00000087 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP8_SC 0x00000088 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP9_SC 0x00000089 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP10_SC 0x0000008a /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP11_SC 0x0000008b /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP12_SC 0x0000008c /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP13_SC 0x0000008d /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP14_SC 0x0000008e /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP15_SC 0x0000008f /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP16_SC 0x00000090 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP17_SC 0x00000091 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP18_SC 0x00000092 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP19_SC 0x00000093 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP20_SC 0x00000094 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP21_SC 0x00000095 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP22_SC 0x00000096 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP23_SC 0x00000097 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP24_SC 0x00000098 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP25_SC 0x00000099 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP26_SC 0x0000009a /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP27_SC 0x0000009b /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP28_SC 0x0000009c /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP29_SC 0x0000009d /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP30_SC 0x0000009e /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP31_SC 0x0000009f /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP32_SC 0x000000a0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP33_SC 0x000000a1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP34_SC 0x000000a2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP35_SC 0x000000a3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP36_SC 0x000000a4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP37_SC 0x000000a5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP38_SC 0x000000a6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP39_SC 0x000000a7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP40_SC 0x000000a8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP41_SC 0x000000a9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP42_SC 0x000000aa /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP43_SC 0x000000ab /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP44_SC 0x000000ac /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP45_SC 0x000000ad /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP46_SC 0x000000ae /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP47_SC 0x000000af /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP48_SC 0x000000b0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP49_SC 0x000000b1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP50_SC 0x000000b2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP51_SC 0x000000b3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP52_SC 0x000000b4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP53_SC 0x000000b5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP54_SC 0x000000b6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP55_SC 0x000000b7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP56_SC 0x000000b8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP57_SC 0x000000b9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP58_SC 0x000000ba /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP59_SC 0x000000bb /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP60_SC 0x000000bc /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP61_SC 0x000000bd /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP62_SC 0x000000be /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP63_SC 0x000000bf /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP64_SC 0x000000c0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP65_SC 0x000000c1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP66_SC 0x000000c2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP67_SC 0x000000c3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP68_SC 0x000000c4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP69_SC 0x000000c5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP70_SC 0x000000c6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP71_SC 0x000000c7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL2_GRP_MAX_SC 0x000000c7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3 31:24 /* RWCUF */ #define NV_XVE_PM_CTRL_SEL3_GRP0 0x00000000 /* RWC-V */ #define NV_XVE_PM_CTRL_SEL3_GRP1 0x00000001 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP2 0x00000002 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP3 0x00000003 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP4 0x00000004 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP5 0x00000005 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP6 0x00000006 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP7 0x00000007 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP8 0x00000008 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP9 0x00000009 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP10 0x0000000a /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP11 0x0000000b /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP12 0x0000000c /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP13 0x0000000d /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP14 0x0000000e /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP15 0x0000000f /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP16 0x00000010 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP17 0x00000011 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP18 0x00000012 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP19 0x00000013 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP20 0x00000014 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP21 0x00000015 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP22 0x00000016 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP23 0x00000017 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP24 0x00000018 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP25 0x00000019 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP26 0x0000001a /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP27 0x0000001b /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP28 0x0000001c /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP29 0x0000001d /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP30 0x0000001e /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP31 0x0000001f /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP32 0x00000020 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP33 0x00000021 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP34 0x00000022 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP35 0x00000023 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP36 0x00000024 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP37 0x00000025 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP38 0x00000026 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP39 0x00000027 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP40 0x00000028 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP41 0x00000029 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP42 0x0000002a /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP43 0x0000002b /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP44 0x0000002c /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP45 0x0000002d /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP46 0x0000002e /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP47 0x0000002f /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP48 0x00000030 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP49 0x00000031 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP50 0x00000032 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP51 0x00000033 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP52 0x00000034 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP53 0x00000035 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP54 0x00000036 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP55 0x00000037 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP56 0x00000038 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP57 0x00000039 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP58 0x0000003a /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP59 0x0000003b /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP60 0x0000003c /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP61 0x0000003d /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP62 0x0000003e /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP63 0x0000003f /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP64 0x00000040 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP65 0x00000041 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP66 0x00000042 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP67 0x00000043 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP68 0x00000044 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP69 0x00000045 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP70 0x00000046 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP71 0x00000047 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP_MAX 0x00000047 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP0_SC 0x00000080 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP1_SC 0x00000081 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP2_SC 0x00000082 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP3_SC 0x00000083 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP4_SC 0x00000084 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP5_SC 0x00000085 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP6_SC 0x00000086 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP7_SC 0x00000087 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP8_SC 0x00000088 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP9_SC 0x00000089 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP10_SC 0x0000008a /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP11_SC 0x0000008b /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP12_SC 0x0000008c /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP13_SC 0x0000008d /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP14_SC 0x0000008e /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP15_SC 0x0000008f /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP16_SC 0x00000090 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP17_SC 0x00000091 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP18_SC 0x00000092 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP19_SC 0x00000093 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP20_SC 0x00000094 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP21_SC 0x00000095 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP22_SC 0x00000096 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP23_SC 0x00000097 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP24_SC 0x00000098 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP25_SC 0x00000099 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP26_SC 0x0000009a /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP27_SC 0x0000009b /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP28_SC 0x0000009c /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP29_SC 0x0000009d /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP30_SC 0x0000009e /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP31_SC 0x0000009f /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP32_SC 0x000000a0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP33_SC 0x000000a1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP34_SC 0x000000a2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP35_SC 0x000000a3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP36_SC 0x000000a4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP37_SC 0x000000a5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP38_SC 0x000000a6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP39_SC 0x000000a7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP40_SC 0x000000a8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP41_SC 0x000000a9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP42_SC 0x000000aa /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP43_SC 0x000000ab /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP44_SC 0x000000ac /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP45_SC 0x000000ad /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP46_SC 0x000000ae /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP47_SC 0x000000af /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP48_SC 0x000000b0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP49_SC 0x000000b1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP50_SC 0x000000b2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP51_SC 0x000000b3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP52_SC 0x000000b4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP53_SC 0x000000b5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP54_SC 0x000000b6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP55_SC 0x000000b7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP56_SC 0x000000b8 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP57_SC 0x000000b9 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP58_SC 0x000000ba /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP59_SC 0x000000bb /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP60_SC 0x000000bc /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP61_SC 0x000000bd /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP62_SC 0x000000be /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP63_SC 0x000000bf /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP64_SC 0x000000c0 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP65_SC 0x000000c1 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP66_SC 0x000000c2 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP67_SC 0x000000c3 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP68_SC 0x000000c4 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP69_SC 0x000000c5 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP70_SC 0x000000c6 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP71_SC 0x000000c7 /* RW--V */ #define NV_XVE_PM_CTRL_SEL3_GRP_MAX_SC 0x000000c7 /* RW--V */ #define NV_XVE_PM_FILTER0 0x000004E4 /* RW-4R */ #define NV_XVE_PM_FILTER0_VC0_CPU_RD 0:0 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC0_CPU_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC0_CPU_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER0_VC0_CPU_WR 1:1 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC0_CPU_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC0_CPU_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER0_VC0_GPU_RD 2:2 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC0_GPU_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC0_GPU_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER0_VC0_GPU_WR 3:3 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC0_GPU_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC0_GPU_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER0_VC0_P2P_RD 11:4 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC0_P2P_RD_ALL_PEERS_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC0_P2P_RD_ALL_PEERS_RECORD 0x000000FF /* RWC-V */ #define NV_XVE_PM_FILTER0_VC0_P2P_WR 19:12 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC0_P2P_WR_ALL_PEERS_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC0_P2P_WR_ALL_PEERS_RECORD 0x000000FF /* RWC-V */ #define NV_XVE_PM_FILTER0_VC1_CPU_RD 20:20 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC1_CPU_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC1_CPU_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER0_VC1_CPU_WR 21:21 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC1_CPU_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC1_CPU_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER0_VC1_GPU_RD 22:22 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC1_GPU_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC1_GPU_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER0_VC1_GPU_WR 23:23 /* RWCUF */ #define NV_XVE_PM_FILTER0_VC1_GPU_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER0_VC1_GPU_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PRI_XVE_CG 0x000004E8 /* RWI4R */ #define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ #define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ #define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_XVE_PRI_XVE_CG_IDLE_CG_EN 6:6 /* RWIVF */ #define NV_XVE_PRI_XVE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRI_XVE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRI_XVE_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_XVE_PRI_XVE_CG_STATE_CG_EN 7:7 /* */ #define NV_XVE_PRI_XVE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_XVE_PRI_XVE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_STALL_CG_EN 14:14 /* RWIVF */ #define NV_XVE_PRI_XVE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRI_XVE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRI_XVE_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */ #define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ #define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT 23:20 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_EN 28:28 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN 30:30 /* */ #define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_HALT_CG_EN 31:31 /* */ #define NV_XVE_PRI_XVE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_XVE_PRI_XVE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_XVE_PRI_XVE_CG1 0x000004EC /* RWI4R */ #define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN 0:0 /* RWIVF */ #define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_XVE_PRI_XVE_CG1_SLCG 17:1 /* RWIVF */ #define NV_XVE_PRI_XVE_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_XVE_PRI_XVE_CG1_SLCG_DISABLED 0x0001FFFF /* RWI-V */ #define NV_XVE_PRI_XVE_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_XVE_BLKPG 0x000004F0 /* RW-4R */ #define NV_XVE_BLKPG_PG_EN 0:0 /* RWCVF */ #define NV_XVE_BLKPG_PG_EN_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_BLKPG_PG_EN_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_BLKPG_WAKEUP_DLY_CNT 18:16 /* RWCVF */ #define NV_XVE_BLKPG_WAKEUP_DLY_CNT_INIT 0x00000000 /* RWC-V */ #define NV_XVE_BLKPG_WAKEUP_DLY_EN 19:19 /* RWCVF */ #define NV_XVE_BLKPG_WAKEUP_DLY_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BLKPG_WAKEUP_DLY_EN_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_PERFMON 0x000004F4 /* RW-4R */ #define NV_XVE_PERFMON_ENABLE 31:31 /* RWCVF */ #define NV_XVE_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_PERFMON_ENABLE_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0 4:0 /* RWCUF */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP0 0x00000000 /* RWC-V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP1 0x00000001 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP2 0x00000002 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP3 0x00000003 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP4 0x00000004 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP5 0x00000005 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP6 0x00000006 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP7 0x00000007 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP8 0x00000008 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP9 0x00000009 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP10 0x0000000a /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP11 0x0000000b /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP12 0x0000000c /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP13 0x0000000d /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP14 0x0000000e /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP15 0x0000000f /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP16 0x00000010 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP17 0x00000011 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP18 0x00000012 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_STATIC_PATTERN_1222_13_GROUP 0x00000011 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_STATIC_PATTERN_0DDD_13_GROUP 0x00000012 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL0_GRP_MAX 0x00000012 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1 9:5 /* RWCUF */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP0 0x00000000 /* RWC-V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP1 0x00000001 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP2 0x00000002 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP3 0x00000003 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP4 0x00000004 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP5 0x00000005 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP6 0x00000006 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP7 0x00000007 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP8 0x00000008 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP9 0x00000009 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP10 0x0000000a /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP11 0x0000000b /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP12 0x0000000c /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP13 0x0000000d /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP14 0x0000000e /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP15 0x0000000f /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP16 0x00000010 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP17 0x00000011 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP18 0x00000012 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP19 0x00000013 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP20 0x00000014 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP21 0x00000015 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP22 0x00000016 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP23 0x00000017 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP24 0x00000018 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP25 0x00000019 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_STATIC_PATTERN_1333_13_GROUP 0x00000018 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_STATIC_PATTERN_0CCC_13_GROUP 0x00000019 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL1_GRP_MAX 0x00000019 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2 14:10 /* RWCUF */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP0 0x00000000 /* RWC-V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP1 0x00000001 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP2 0x00000002 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP3 0x00000003 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP4 0x00000004 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP5 0x00000005 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP6 0x00000006 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP7 0x00000007 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP8 0x00000008 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP9 0x00000009 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP10 0x0000000a /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP11 0x0000000b /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP12 0x0000000c /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP13 0x0000000d /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP14 0x0000000e /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP15 0x0000000f /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP16 0x00000010 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL2_GRP_MAX 0x0000001f /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3 19:15 /* RWCUF */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP0 0x00000000 /* RWC-V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP1 0x00000001 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP2 0x00000002 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP3 0x00000003 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP4 0x00000004 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP5 0x00000005 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP6 0x00000006 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP7 0x00000007 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP8 0x00000008 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP9 0x00000009 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP10 0x0000000a /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP11 0x0000000b /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP12 0x0000000c /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP13 0x0000000d /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP14 0x0000000e /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP15 0x0000000f /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP16 0x00000010 /* RW--V */ #define NV_XVE_PERFMON_XCLK_CTRL_SEL3_GRP_MAX 0x0000001f /* RW--V */ #define NV_XVE_ILA_HOSTCLK_PM 0x00000500 /* RW-4R */ #define NV_XVE_ILA_HOSTCLK_PM_SEL0 5:0 /* RWCUF */ #define NV_XVE_ILA_HOSTCLK_PM_SEL0_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_PM_SEL1 11:6 /* RWCUF */ #define NV_XVE_ILA_HOSTCLK_PM_SEL1_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_PM_SEL2 17:12 /* RWCUF */ #define NV_XVE_ILA_HOSTCLK_PM_SEL2_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_PM_SEL3 23:18 /* RWCUF */ #define NV_XVE_ILA_HOSTCLK_PM_SEL3_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_PM_SEL4 29:24 /* RWCUF */ #define NV_XVE_ILA_HOSTCLK_PM_SEL4_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_DET 0x00000504 /* RW-4R */ #define NV_XVE_ILA_HOSTCLK_DET_FUNC 31:0 /* RWCUF */ #define NV_XVE_ILA_HOSTCLK_DET_FUNC_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_DET1 0x00000508 /* RW-4R */ #define NV_XVE_ILA_HOSTCLK_DET1_EN 0:0 /* RWCVF */ #define NV_XVE_ILA_HOSTCLK_DET1_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_DET1_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_ILA_HOSTCLK_DET1_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ILA_HOSTCLK_DET1_SZ 2:1 /* RWCVF */ #define NV_XVE_ILA_HOSTCLK_DET1_SZ_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_RPT_EN 15:12 /* RWCVF */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_RPT_EN_INIT 0x00000003 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWCVF */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWCVF */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWCVF */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWCVF */ #define NV_XVE_ILA_HOSTCLK_DET1_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_PM 0x0000050C /* RW-4R */ #define NV_XVE_ILA_XCLK_PM_SEL0 5:0 /* RWCUF */ #define NV_XVE_ILA_XCLK_PM_SEL0_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_PM_SEL1 11:6 /* RWCUF */ #define NV_XVE_ILA_XCLK_PM_SEL1_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_PM_SEL2 17:12 /* RWCUF */ #define NV_XVE_ILA_XCLK_PM_SEL2_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_PM_SEL3 23:18 /* RWCUF */ #define NV_XVE_ILA_XCLK_PM_SEL3_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_PM_SEL4 29:24 /* RWCUF */ #define NV_XVE_ILA_XCLK_PM_SEL4_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_DET 0x00000510 /* RW-4R */ #define NV_XVE_ILA_XCLK_DET_FUNC 31:0 /* RWCUF */ #define NV_XVE_ILA_XCLK_DET_FUNC_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_DET1 0x00000514 /* RW-4R */ #define NV_XVE_ILA_XCLK_DET1_EN 0:0 /* RWCVF */ #define NV_XVE_ILA_XCLK_DET1_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_DET1_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_ILA_XCLK_DET1_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ILA_XCLK_DET1_SZ 2:1 /* RWCVF */ #define NV_XVE_ILA_XCLK_DET1_SZ_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_RPT_EN 15:12 /* RWCVF */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_RPT_EN_INIT 0x00000003 /* RWC-V */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWCVF */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWCVF */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWCVF */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWCVF */ #define NV_XVE_ILA_XCLK_DET1_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_INTF 0x0000051C /* RW-4R */ #define NV_XVE_ILA_INTF_SEL 3:0 /* RWCUF */ #define NV_XVE_ILA_INTF_SEL_AZA2XVE 0x00000000 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_XVE2AZA 0x00000001 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_FB2XVE 0x00000002 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_XVE2FB 0x00000003 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_HOST2XVE 0x00000004 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_XVE2HOST 0x00000005 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_UC2TXB 0x00000006 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_NONE 0x0000000f /* RWC-V */ #define NV_XVE_ILA_INTF_THREAD_ID 6:4 /* RWCUF */ #define NV_XVE_ILA_INTF_THREAD_ID_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_INTF_THREAD_ID_NONE 0x00000007 /* RW--V */ #define NV_XVE_ILA_INTF_ID 10:7 /* RWCUF */ #define NV_XVE_ILA_INTF_ID_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_INTF_ID_NONE 0x0000000f /* RW--V */ #define NV_XVE_ILA_INTF_ID_ALL 0x0000000E /* RW--V */ #define NV_XVE_ILA_INTF_UC2TXB_SEL 12:11 /* RWCUF */ #define NV_XVE_ILA_INTF_UC2TXB_SEL_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_INTF_UC2TXB_SEL_HDR_ONLY 0x00000000 /* RW--V */ #define NV_XVE_ILA_INTF_UC2TXB_SEL_DAT_ONLY 0x00000001 /* RW--V */ #define NV_XVE_ILA_INTF_UC2TXB_SEL_HDR 0x00000002 /* RW--V */ #define NV_XVE_ILA_INTF_UC2TXB_SEL_DAT 0x00000003 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_DATA_CHUNK 14:13 /* RWCUF */ #define NV_XVE_ILA_INTF_SEL_DATA_CHUNK_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ILA_INTF_SEL_DATA_CHUNK_0 0x00000000 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_DATA_CHUNK_1 0x00000001 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_DATA_CHUNK_2 0x00000002 /* RW--V */ #define NV_XVE_ILA_INTF_SEL_DATA_CHUNK_3 0x00000003 /* RW--V */ #define NV_XVE_VEND_SPECIFIC_ENHANCED_CAP_HEADER 0x00000600 /* R--4R */ #define NV_XVE_VEND_SPECIFIC_ENHANCED_CAP_HEADER_EXTENDED_CAPABILITY_ID 15:0 /* R-IVF */ #define NV_XVE_VEND_SPECIFIC_ENHANCED_CAP_HEADER_EXTENDED_CAPABILITY_ID_VENDOR_SPECIFIC 0x0000000B /* R-I-V */ #define NV_XVE_VEND_SPECIFIC_ENHANCED_CAP_HEADER_CAPABILITY_VERSION 19:16 /* R-IVF */ #define NV_XVE_VEND_SPECIFIC_ENHANCED_CAP_HEADER_CAPABILITY_VERSION_ONE 0x00000001 /* R-I-V */ #define NV_XVE_VEND_SPECIFIC_ENHANCED_CAP_HEADER_NEXT_CAP_OFFSET 31:20 /* R-IVF */ #define NV_XVE_VEND_SPECIFIC_ENHANCED_CAP_HEADER_NEXT_CAP_OFFSET_NULL 0x00000000 /* R---V */ #define NV_XVE_VEND_SPECIFIC_ENHANCED_CAP_HEADER_NEXT_CAP_OFFSET_SEC_PCIE_CAP 0x00000900 /* R-I-V */ #define NV_XVE_VENDOR_SPECIFIC_HEADER 0x00000604 /* R--4R */ #define NV_XVE_VENDOR_SPECIFIC_HEADER_VSEC_ID 15:0 /* R-IVF */ #define NV_XVE_VENDOR_SPECIFIC_HEADER_VSEC_ID_ONE 0x00000001 /* R-I-V */ #define NV_XVE_VENDOR_SPECIFIC_HEADER_VSEC_REV 19:16 /* R-IVF */ #define NV_XVE_VENDOR_SPECIFIC_HEADER_VSEC_REV_ONE 0x00000001 /* R-I-V */ #define NV_XVE_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH 31:20 /* R-IVF */ #define NV_XVE_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_36 0x00000024 /* R-I-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_CAPABILITY_HEADER 0x00000608 /* R--4R */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_CAPABILITY_HEADER_CAP_ID 15:0 /* R-IVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_CAPABILITY_HEADER_CAP_ID_NSF 0x00000002 /* R-I-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_CAPABILITY_HEADER_VERSION 19:16 /* R-IVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_CAPABILITY_HEADER_VERSION_ONE 0x00000001 /* R-I-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_CAPABILITY_HEADER_NEXT_CAP_OFFSET 31:20 /* R-IVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_CAPABILITY_HEADER_NEXT_CAP_OFFSET_NULL 0x00000000 /* R---V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_CAPABILITY_HEADER_NEXT_CAP_OFFSET_PRIVATE_PCIE 0x00000014 /* R-I-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE 0x0000060C /* R--4R */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN2_PCIE 0:0 /* R-CVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN2_PCIE_CAPABLE 0x00000001 /* R-C-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN2_PCIE_DISABLED 0x00000000 /* R---V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_PSEUDO_VC 2:2 /* C--VF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_PSEUDO_VC_NOT_CAPABLE 0x00000000 /* C---V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_RSVD_0 10:3 /* C--VF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_RSVD_0_INIT 0x00000000 /* C---V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_FB_SIZE_OVERRIDE 11:11 /* R-CVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_FB_SIZE_OVERRIDE_SUPPORTED 0x00000001 /* R-C-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_FB_SIZE_OVERRIDE_NOT_SUPPORTED 0x00000000 /* R---V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN3_PCIE 12:12 /* R-CVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN3_PCIE_CAPABLE 0x00000001 /* R-C-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN3_PCIE_DISABLED 0x00000000 /* R---V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_RSVD_1 31:13 /* C--VF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_RSVD_1_INIT 0x00000000 /* C---V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY 0x00000610 /* RW-4R */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN2_PCIE 0:0 /* RWCVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN2_PCIE_NOT_CAPABLE 0x00000000 /* RWC-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN2_PCIE_CAPABLE 0x00000001 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_MULTIBYTE_ENABLE_WRITE 1:1 /* RWCVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_MULTIBYTE_ENABLE_WRITE_NOT_CAPABLE 0x00000000 /* RWC-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_MULTIBYTE_ENABLE_WRITE_CAPABLE 0x00000001 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_RSVD_0 6:2 /* RWCVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_RSVD_0_INIT 0x00000000 /* RWC-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL 10:7 /* RWCVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_INIT 0x00000000 /* RWC-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_64MB 0x00000000 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_128MB 0x00000001 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_256MB 0x00000002 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_512MB 0x00000003 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_1GB 0x00000004 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_2GB 0x00000005 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_4GB 0x00000006 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_8GB 0x00000007 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_16GB 0x00000008 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_32GB 0x00000009 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_64GB 0x0000000a /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_128GB 0x0000000b /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_256GB 0x0000000c /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_512GB 0x0000000d /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_1TB 0x0000000e /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_RSVD 0x0000000f /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_EN 11:11 /* RWCVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_EN_CAPABLE 0x00000001 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_EN_NOT_CAPABLE 0x00000000 /* RWC-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN3_PCIE 12:12 /* RWCVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN3_PCIE_NOT_CAPABLE 0x00000000 /* RWC-V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN3_PCIE_CAPABLE 0x00000001 /* RW--V */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_RSVD_1 31:13 /* RWCVF */ #define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_RSVD_1_INIT 0x00000000 /* RWC-V */ #define NV_XVE_TCIPHER_KEY(i) (0x00000624+(i)*8) /* -W-4A */ #define NV_XVE_TCIPHER_KEY__SIZE_1 4 /* */ #define NV_XVE_TCIPHER_KEY_VALUE 31:0 /* -WCVF */ #define NV_XVE_TCIPHER_KEY_VALUE_INIT 0x00000000 /* -WC-V */ #define NV_XVE_PRIV_XV_BLKCG2 0x00000658 /* RW-4R */ #define NV_XVE_PRIV_XV_BLKCG2_HOST2XV_HOST_IDLE_WAKE_EN 0:0 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_HOST2XV_HOST_IDLE_WAKE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_HOST2XV_HOST_IDLE_WAKE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_BLKCG2_RSVD_HOST2XV_FORCE_CLK_ON_WAKE_EN 1:1 /* C--VF */ #define NV_XVE_PRIV_XV_BLKCG2_RSVD_HOST2XV_FORCE_CLK_ON_WAKE_EN_ENABLED 0x00000001 /* C---V */ #define NV_XVE_PRIV_XV_BLKCG2_UPSTREAM_REQ_WAKE_EN 2:2 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_UPSTREAM_REQ_WAKE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_UPSTREAM_REQ_WAKE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_BLKCG2_RSVD_XP_PAD_IDLE_WAKE_EN 3:3 /* C--VF */ #define NV_XVE_PRIV_XV_BLKCG2_RSVD_XP_PAD_IDLE_WAKE_EN_DISABLED 0x00000000 /* C---V */ #define NV_XVE_PRIV_XV_BLKCG2_CONFIG0_UPDATE_WAKE_EN 4:4 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_CONFIG0_UPDATE_WAKE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_XV_BLKCG2_CONFIG0_UPDATE_WAKE_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_CONFIG1_UPDATE_WAKE_EN 5:5 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_CONFIG1_UPDATE_WAKE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_XV_BLKCG2_CONFIG1_UPDATE_WAKE_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_INTR_PENDING_WAKE_EN 8:8 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_INTR_PENDING_WAKE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_INTR_PENDING_WAKE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_BLKCG2_FN1_INTR_PENDING_WAKE_EN 9:9 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_FN1_INTR_PENDING_WAKE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_FN1_INTR_PENDING_WAKE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_EOI_PENDING_WAKE_EN 10:10 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_EOI_PENDING_WAKE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_EOI_PENDING_WAKE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_BLKCG2_FN1_EOI_PENDING_WAKE_EN 11:11 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_FN1_EOI_PENDING_WAKE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_FN1_EOI_PENDING_WAKE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_MSIX_PENDING_WAKE_EN 14:14 /* RWIVF */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_MSIX_PENDING_WAKE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_XV_BLKCG2_FN0_MSIX_PENDING_WAKE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_CODEC_PW 0x00000660 /* RW-4R */ #define NV_XVE_CYA_CODEC_PW_0 0:0 /* RWCVF */ #define NV_XVE_CYA_CODEC_PW_0_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_CODEC_PW_0_ENABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_CODEC_PW_0_DISABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_CODEC_PW_1 1:1 /* RWCVF */ #define NV_XVE_CYA_CODEC_PW_1_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_CODEC_PW_1_ENABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_CODEC_PW_1_DISABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_CODEC_PW_2 2:2 /* RWCVF */ #define NV_XVE_CYA_CODEC_PW_2_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_CODEC_PW_2_ENABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_CODEC_PW_2_DISABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_CODEC_PW_3 3:3 /* RWCVF */ #define NV_XVE_CYA_CODEC_PW_3_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_CODEC_PW_3_ENABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_CODEC_PW_3_DISABLE 0x00000001 /* RW--V */ #define NV_XVE_RESET_CTRL 0x00000700 /* RW-4R */ #define NV_XVE_RESET_CTRL__PRIV_LEVEL_MASK 0x00000FF8 /* */ #define NV_XVE_RESET_CTRL_GPU_RESET 0:0 /* C--VF */ #define NV_XVE_RESET_CTRL_GPU_RESET_INIT 0x00000000 /* C---V */ #define NV_XVE_RESET_CTRL_RESET_COUNTER_VAL 11:1 /* RWCVF */ #define NV_XVE_RESET_CTRL_RESET_COUNTER_VAL_INIT 0x000007FF /* RWC-V */ #define NV_XVE_RESET_CTRL_FB_INTF_RESET 16:16 /* RWCVF */ #define NV_XVE_RESET_CTRL_FB_INTF_RESET_INIT 0x00000000 /* RWC-V */ #define NV_XVE_RESET_CTRL_FB_INTF_RESET_ASSERT 0x00000001 /* RW--V */ #define NV_XVE_RESET_CTRL_FB_INTF_RESET_DEASSERT 0x00000000 /* RW--V */ #define NV_XVE_RESET_CTRL_ASSERT_FUNDAMENTAL_RESET_ON_HOT_RESET 17:17 /* RWCVF */ #define NV_XVE_RESET_CTRL_ASSERT_FUNDAMENTAL_RESET_ON_HOT_RESET_INIT 0x00000000 /* RWC-V */ #define NV_XVE_RESET_CTRL_ASSERT_FUNDAMENTAL_RESET_ON_HOT_RESET_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_RESET_CTRL_ASSERT_FUNDAMENTAL_RESET_ON_HOT_RESET_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_2 0x00000704 /* RW-4R */ #define NV_XVE_CYA_2_RSVD 31:0 /* RWCVF */ #define NV_XVE_CYA_2_RSVD_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3 0x00000708 /* RW-4R */ #define NV_XVE_CYA_3_CP_XSUBCH_STARVATION_FIX 0:0 /* RWCVF */ #define NV_XVE_CYA_3_CP_XSUBCH_STARVATION_FIX_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_CP_XSUBCH_STARVATION_FIX_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_CP_XSUBCH_SPLIT_RAM_X_FIX 1:1 /* RWCVF */ #define NV_XVE_CYA_3_CP_XSUBCH_SPLIT_RAM_X_FIX_ENABLED 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_CP_XSUBCH_SPLIT_RAM_X_FIX_DISABLED 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_BLOCK_UPSTREAM_IN_NON_D0_PWR_STATES 2:2 /* RWCVF */ #define NV_XVE_CYA_3_BLOCK_UPSTREAM_IN_NON_D0_PWR_STATES_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_BLOCK_UPSTREAM_IN_NON_D0_PWR_STATES_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_BUS_MASTER_DIS_BLOCK_UPSTREAM_P2P 3:3 /* RWCVF */ #define NV_XVE_CYA_3_BUS_MASTER_DIS_BLOCK_UPSTREAM_P2P_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_BUS_MASTER_DIS_BLOCK_UPSTREAM_P2P_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_US_P2P_CPL_STARVATION_FIX 5:5 /* RWCVF */ #define NV_XVE_CYA_3_US_P2P_CPL_STARVATION_FIX_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_US_P2P_CPL_STARVATION_FIX_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_US_P2P_PW_STARVATION_FIX 6:6 /* RWCVF */ #define NV_XVE_CYA_3_US_P2P_PW_STARVATION_FIX_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_US_P2P_PW_STARVATION_FIX_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_MSGD_INVALID_TYPE_ERROR 7:7 /* RWCVF */ #define NV_XVE_CYA_3_MSGD_INVALID_TYPE_ERROR_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_MSGD_INVALID_TYPE_ERROR_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_LEGACY_ENDPOINT_DEVICE 8:8 /* RWCVF */ #define NV_XVE_CYA_3_LEGACY_ENDPOINT_DEVICE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_LEGACY_ENDPOINT_DEVICE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_HIDE_OBFF_CAP 9:9 /* RWCVF */ #define NV_XVE_CYA_3_HIDE_OBFF_CAP_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_HIDE_OBFF_CAP_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_HIDE_OBFF_CAP_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_UC_ARB1_STARVATION_FIX 10:10 /* RWCVF */ #define NV_XVE_CYA_3_UC_ARB1_STARVATION_FIX_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_UC_ARB1_STARVATION_FIX_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_UC_ARB1_STARVATION_FIX_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_P2P_8DW_FLUSH_LEN 11:11 /* RWCVF */ #define NV_XVE_CYA_3_P2P_8DW_FLUSH_LEN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_P2P_8DW_FLUSH_LEN_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_P2P_8DW_FLUSH_LEN_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_TXB_CREDIT_CHECK_FIX 13:13 /* RWCVF */ #define NV_XVE_CYA_3_TXB_CREDIT_CHECK_FIX_INIT 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_TXB_CREDIT_CHECK_FIX_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_TXB_CREDIT_CHECK_FIX_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_UC_ARB1_WLRU_FIX 14:14 /* RWCVF */ #define NV_XVE_CYA_3_UC_ARB1_WLRU_FIX_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_UC_ARB1_WLRU_FIX_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_UC_ARB1_WLRU_FIX_DEFAULT 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_TXB_ARBCTL_STARVATION_FIX 15:15 /* RWCVF */ #define NV_XVE_CYA_3_TXB_ARBCTL_STARVATION_FIX_INIT 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_TXB_ARBCTL_STARVATION_FIX_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_TXB_ARBCTL_STARVATION_FIX_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_P2P_ESCAPED_UCPL_FIX 16:16 /* RWCVF */ #define NV_XVE_CYA_3_P2P_ESCAPED_UCPL_FIX_INIT 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_P2P_ESCAPED_UCPL_FIX_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_P2P_ESCAPED_UCPL_FIX_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_UC_HOSTCPL_MSIX_ORDCTRL 17:17 /* RWCVF */ #define NV_XVE_CYA_3_UC_HOSTCPL_MSIX_ORDCTRL_INIT 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_UC_HOSTCPL_MSIX_ORDCTRL_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_UC_HOSTCPL_MSIX_ORDCTRL_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_UC_CFGCPL_MSIX_ORDCTRL 18:18 /* RWCVF */ #define NV_XVE_CYA_3_UC_CFGCPL_MSIX_ORDCTRL_INIT 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_UC_CFGCPL_MSIX_ORDCTRL_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_UC_CFGCPL_MSIX_ORDCTRL_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_EN 19:19 /* RWCVF */ #define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_EN_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_VAL 20:20 /* RWCVF */ #define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_VAL_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_VAL_ONE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_VAL_ZERO 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_GEN4L_CAP_STATUS_CONFIG 21:21 /* RWCVF */ #define NV_XVE_CYA_3_GEN4L_CAP_STATUS_CONFIG_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_GEN4L_CAP_STATUS_CONFIG_8GTS_MODE 0x00000000 /* R---V */ #define NV_XVE_CYA_3_GEN4L_CAP_STATUS_CONFIG_16GTS_MODE 0x00000001 /* R---V */ #define NV_XVE_CYA_3_SKIP_UR_INCR_CE_CNT 22:22 /* RWCVF */ #define NV_XVE_CYA_3_SKIP_UR_INCR_CE_CNT_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_SCALED_FC_CAP 23:23 /* RWCVF */ #define NV_XVE_CYA_3_SCALED_FC_CAP_DISBLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_SCALED_FC_CAP_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_DL_FEATURE_CAP 24:24 /* RWCVF */ #define NV_XVE_CYA_3_DL_FEATURE_CAP_DISBLE 0x00000000 /* RW--V */ #define NV_XVE_CYA_3_DL_FEATURE_CAP_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_CYA_3_DISABLE_RX_MARGINING 25:25 /* RWCVF */ #define NV_XVE_CYA_3_DISABLE_RX_MARGINING_DISBLE 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_DISABLE_RX_MARGINING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_FRS 26:26 /* RWCVF */ #define NV_XVE_CYA_3_FRS_NOT_CAPABLE 0x00000000 /* R-C-V */ #define NV_XVE_CYA_3_FRS_CAPABLE 0x00000001 /* R---V */ #define NV_XVE_CYA_3_AUX_POWER 27:27 /* RWCVF */ #define NV_XVE_CYA_3_AUX_POWER_NOT_AVAIL 0x00000000 /* R-C-V */ #define NV_XVE_CYA_3_AUX_POWER_AVAIL 0x00000001 /* R---V */ #define NV_XVE_CYA_3_NO_COMMAND_MARGINING_INTERRUPT 28:28 /* RWCVF */ #define NV_XVE_CYA_3_NO_COMMAND_MARGINING_INTERRUPT_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_NO_COMMAND_MARGINING_INTERRUPT_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_SET_ERROR_COUNT_LIMIT_COMMAND_MARGINING_INTERRUPT 29:29 /* RWCVF */ #define NV_XVE_CYA_3_SET_ERROR_COUNT_LIMIT_COMMAND_MARGINING_INTERRUPT_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_SET_ERROR_COUNT_LIMIT_COMMAND_MARGINING_INTERRUPT_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_3_ANY_COMMAND_MARGINING_INTERRUPT 30:30 /* RWCVF */ #define NV_XVE_CYA_3_ANY_COMMAND_MARGINING_INTERRUPT_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_CYA_3_ANY_COMMAND_MARGINING_INTERRUPT_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_1 0x0000070C /* RW-4R */ #define NV_XVE_DEBUG_1__PRIV_LEVEL_MASK 0x00000ED8 /* */ #define NV_XVE_DEBUG_1_RSVD_P2P_TIMEOUT 1:0 /* C--VF */ #define NV_XVE_DEBUG_1_RSVD_P2P_TIMEOUT_MAX 0x00000000 /* C---V */ #define NV_XVE_DEBUG_1_P2PSLAVE_CPL_TO_DISABLE 2:2 /* RWCUF */ #define NV_XVE_DEBUG_1_P2PSLAVE_CPL_TO_DISABLE_ENABLED 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_1_P2PSLAVE_CPL_TO_DISABLE_DISABLED 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_1_SUBSYSTEM_ID_LOCK 3:3 /* RWCVF */ #define NV_XVE_DEBUG_1_SUBSYSTEM_ID_LOCK_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_1_SUBSYSTEM_ID_LOCK_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_1_RSVD_UC_RESP_BUF_BLOCK_PW 4:4 /* C--VF */ #define NV_XVE_DEBUG_1_RSVD_UC_RESP_BUF_BLOCK_PW_DISABLED 0x00000000 /* C---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE 8:5 /* R-CVF */ #define NV_XVE_DEBUG_1_BAR1_SIZE_INIT 0x00000000 /* R-C-V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_64MB 0x00000000 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_128MB 0x00000001 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_256MB 0x00000002 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_512MB 0x00000003 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_1GB 0x00000004 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_2GB 0x00000005 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_4GB 0x00000006 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_8GB 0x00000007 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_16GB 0x00000008 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_32GB 0x00000009 /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_64GB 0x0000000A /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_128GB 0x0000000B /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_256GB 0x0000000C /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_512GB 0x0000000D /* R---V */ #define NV_XVE_DEBUG_1_BAR1_SIZE_1TB 0x0000000E /* R---V */ #define NV_XVE_DEBUG_1_RSVD_DWNSTREAM_READ_COUNT 15:9 /* C--VF */ #define NV_XVE_DEBUG_1_RSVD_DWNSTREAM_READ_COUNT_INIT 0x00000000 /* C---V */ #define NV_XVE_DEBUG_1_P2PSLAVE_CPL_TO_MILLISECOND 31:16 /* RWCUF */ #define NV_XVE_DEBUG_1_P2PSLAVE_CPL_TO_MILLISECOND_1MS 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_1_P2PSLAVE_CPL_TO_MILLISECOND_16MS 0x00000010 /* RWC-V */ #define NV_XVE_DEBUG_2 0x00000710 /* RW-4R */ #define NV_XVE_DEBUG_2_P2P_FIFO_RESERVE 15:0 /* RWCUF */ #define NV_XVE_DEBUG_2_P2P_FIFO_RESERVE_0 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_2_P2P_FIFO_RESERVE_MIN 0x00000000 /* RW--V */ #define NV_XVE_DEBUG_2_P2P_FIFO_RESERVE_MAX 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_2_P2P_MAX_READ_REQS 23:16 /* RWCUF */ #define NV_XVE_DEBUG_2_P2P_MAX_READ_REQS_0 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_2_P2P_MAX_READ_REQS_MIN 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_2_P2P_MAX_READ_REQS_MAX 0x00000002 /* RW--V */ #define NV_XVE_DEBUG_2_P2P_LIMIT_READ_REQS 24:24 /* RWCUF */ #define NV_XVE_DEBUG_2_P2P_LIMIT_READ_REQS_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_2_SPARE 25:25 /* RWCUF */ #define NV_XVE_DEBUG_2_SPARE_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_DEBUG_2_P2P_SERIALIZE 26:26 /* RWCUF */ #define NV_XVE_DEBUG_2_P2P_SERIALIZE_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_2_P2P_ONLY_ONE_FLUSH 27:27 /* RWCUF */ #define NV_XVE_DEBUG_2_P2P_ONLY_ONE_FLUSH_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_2_P2P_SERIALIZE_ON_FLUSH 28:28 /* RWCUF */ #define NV_XVE_DEBUG_2_P2P_SERIALIZE_ON_FLUSH_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_2_P2P_NOP_ALL_FLUSHES 29:29 /* RWCUF */ #define NV_XVE_DEBUG_2_P2P_NOP_ALL_FLUSHES_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_2_SPARE1 31:30 /* RWCUF */ #define NV_XVE_DEBUG_2_SPARE1_0 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_3 0x00000714 /* RW-4R */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP 3:0 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MIN 0x00000000 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MAX 0x0000000f /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_DEFAULT 0x0000000D /* RWC-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP__PROD 0x0000000D /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN 10:4 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_128 0x00000000 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_160 0x00000021 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_196 0x00000040 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_224 0x00000060 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_DEFAULT 0x00000075 /* RWC-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN__PROD 0x00000075 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EN 11:11 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EN_DEFAULT 0x00000001 /* RWC-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS0 12:12 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS0_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS0_PENDING 0x00000001 /* R---V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS0_RESET 0x00000001 /* -W--C */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS1 13:13 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS1_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS1_PENDING 0x00000001 /* R---V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS1_RESET 0x00000001 /* -W--C */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_TO_INTR 14:14 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_TO_INTR_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_TO_INTR_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_TO_INTR_DEFAULT 0x00000001 /* RWC-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA1_PW_DROP 15:15 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA1_PW_DROP_EN 0x00000001 /* RWC-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA1_PW_DROP_DIS 0x00000000 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA2_PW_DROP 16:16 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA2_PW_DROP_EN 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA2_PW_DROP_DIS 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MSB 17:17 /* RWCVF */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MSB_MIN 0x00000000 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MSB_MAX 0x00000001 /* RW--V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MSB_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MSB__PROD 0x00000000 /* RW--V */ #define NV_XVE_DEBUG_3_SPARE 31:18 /* RWCVF */ #define NV_XVE_DEBUG_3_SPARE_DEFAULT 0x00000000 /* RWC-V */ #define NV_XVE_SW_RESET 0x00000718 /* RW-4R */ #define NV_XVE_SW_RESET__PRIV_LEVEL_MASK 0x00000FF4 /* */ #define NV_XVE_SW_RESET_RESET 0:0 /* RWCVF */ #define NV_XVE_SW_RESET_RESET_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_RESET_GPU_ON_SW_RESET 1:1 /* RWCVF */ #define NV_XVE_SW_RESET_GPU_ON_SW_RESET_INIT 0x00000001 /* RWC-V */ #define NV_XVE_SW_RESET_GPU_ON_SW_RESET_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_SW_RESET_GPU_ON_SW_RESET_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_SW_RESET_COUNTER_EN 2:2 /* RWCVF */ #define NV_XVE_SW_RESET_COUNTER_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_RESET_COUNTER_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_SW_RESET_COUNTER_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_SW_RESET_COUNTER_VAL 14:4 /* RWCVF */ #define NV_XVE_SW_RESET_COUNTER_VAL_INIT 0x00000001 /* RWC-V */ #define NV_XVE_SW_RESET_CLOCK_ON_SW_RESET 15:15 /* RWCVF */ #define NV_XVE_SW_RESET_CLOCK_ON_SW_RESET_INIT 0x00000001 /* RWC-V */ #define NV_XVE_SW_RESET_CLOCK_ON_SW_RESET_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_SW_RESET_CLOCK_ON_SW_RESET_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_SW_RESET_CLOCK_COUNTER_EN 16:16 /* RWCVF */ #define NV_XVE_SW_RESET_CLOCK_COUNTER_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_RESET_CLOCK_COUNTER_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_SW_RESET_CLOCK_COUNTER_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_SW_RESET_CLOCK_COUNTER_VAL 27:17 /* RWCVF */ #define NV_XVE_SW_RESET_CLOCK_COUNTER_VAL_INIT 0x00000001 /* RWC-V */ #define NV_XVE_SW_RESET_CYA_DISABLE_FAULT_TRIGGER_SWRESET 31:31 /* RWCVF */ #define NV_XVE_SW_RESET_CYA_DISABLE_FAULT_TRIGGER_SWRESET_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_4 0x0000071C /* RW-4R */ #define NV_XVE_CYA_4__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_CYA_4_SRIOV_ARI_CAP_HIDE 0:0 /* RWCVF */ #define NV_XVE_CYA_4_SRIOV_ARI_CAP_HIDE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_CYA_4_SRIOV_ARI_CAP_HIDE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_CYA_4_FIRST_VF_OFFSET_OVERRIDE_EN 1:1 /* RWCVF */ #define NV_XVE_CYA_4_FIRST_VF_OFFSET_OVERRIDE_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_4_FIRST_VF_OFFSET_OVERRIDE_EN_DIS 0x00000000 /* RW--V */ #define NV_XVE_CYA_4_FIRST_VF_OFFSET_OVERRIDE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_4_FIRST_VF_OFFSET_OVERRIDE_VAL 17:2 /* RWCVF */ #define NV_XVE_CYA_4_FIRST_VF_OFFSET_OVERRIDE_VAL_TWO 0x00000002 /* RW--V */ #define NV_XVE_CYA_4_FIRST_VF_OFFSET_OVERRIDE_VAL_FOUR 0x00000004 /* RWC-V */ #define NV_XVE_CYA_4_FLR_SUPPORTED 23:20 /* RWCVF */ #define NV_XVE_CYA_4_FLR_SUPPORTED_INIT 0x0000000F /* RWC-V */ #define NV_XVE_CYA_4_VF_CLASS_CODE_SEL 31:28 /* RWCVF */ #define NV_XVE_CYA_4_VF_CLASS_CODE_SEL_PF0 0x00000000 /* RWC-V */ #define NV_XVE_CYA_4_VF_CLASS_CODE_SEL_VGA 0x00000001 /* RW--V */ #define NV_XVE_CYA_4_VF_CLASS_CODE_SEL_3D 0x00000002 /* RW--V */ #define NV_XVE_CYA_4_VF_CLASS_CODE_SEL_MULTIMEDIA 0x00000003 /* RW--V */ #define NV_XVE_CYA_5 0x00000720 /* RW-4R */ #define NV_XVE_CYA_5__PRIV_LEVEL_MASK 0x00000ED4 /* */ #define NV_XVE_CYA_5_OVERRIDE_GEN4L 0:0 /* RWCVF */ #define NV_XVE_CYA_5_OVERRIDE_GEN4L_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_5_OVERRIDE_GEN4L_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_CYA_5_OVERRIDE_GEN4L_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_5_RESIZE_BAR_CAP_HIDE 1:1 /* RWCVF */ #define NV_XVE_CYA_5_RESIZE_BAR_CAP_HIDE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_CYA_5_RESIZE_BAR_CAP_HIDE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_CYA_5_RESIZE_BAR_SIZE_RESTORE_DIS 2:2 /* RWCVF */ #define NV_XVE_CYA_5_RESIZE_BAR_SIZE_RESTORE_DIS_UNSET 0x00000000 /* RWC-V */ #define NV_XVE_CYA_5_RESIZE_BAR_SIZE_RESTORE_DIS_SET 0x00000001 /* RW--V */ #define NV_XVE_CYA_5_PM_PME_FOR_ANY_WAKEUP 8:8 /* RWCVF */ #define NV_XVE_CYA_5_PM_PME_FOR_ANY_WAKEUP_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_CYA_5_PM_PME_FOR_ANY_WAKEUP_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_CYA_5_PME_STATUS_LDACK 9:9 /* RWCVF */ #define NV_XVE_CYA_5_PME_STATUS_LDACK_WAIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_5_PME_STATUS_LDACK_TIE_HI 0x00000001 /* RW--V */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW 12:10 /* RWCVF */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW_SELF_POWERED 0x00000000 /* RWC-V */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW_55MA 0x00000001 /* RW--V */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW_100MA 0x00000002 /* RW--V */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW_160MA 0x00000003 /* RW--V */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW_220MA 0x00000004 /* RW--V */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW_270MA 0x00000005 /* RW--V */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW_320MA 0x00000006 /* RW--V */ #define NV_XVE_CYA_5_AUX_CURRENT_SHADOW_375MA 0x00000007 /* RW--V */ #define NV_XVE_CYA_5_PME_STROBE_SCALE 18:16 /* RWCVF */ #define NV_XVE_CYA_5_PME_STROBE_SCALE_128NS 0x00000001 /* RWC-V */ #define NV_XVE_CYA_5_PME_STROBE_SCALE_256NS 0x00000002 /* RW--V */ #define NV_XVE_CYA_5_PME_STROBE_SCALE_512NS 0x00000004 /* RW--V */ #define NV_XVE_CYA_5_PM_PME_TIMEOUT 27:20 /* RWCVF */ #define NV_XVE_CYA_5_PM_PME_TIMEOUT_50MS 0x00000000 /* RW--V */ #define NV_XVE_CYA_5_PM_PME_TIMEOUT_100MS 0x00000032 /* RWC-V */ #define NV_XVE_CYA_5_PM_PME_TIMEOUT_150MS 0x00000064 /* RW--V */ #define NV_XVE_CYA_5_CYA_ALL_HOT_RESET 28:28 /* RWCVF */ #define NV_XVE_CYA_5_CYA_ALL_HOT_RESET_INIT 0x00000001 /* RWC-V */ #define NV_XVE_CYA_5_CYA_ALL_HOT_RESET_RESET 0x00000001 /* RW--V */ #define NV_XVE_CYA_5_CYA_ALL_HOT_RESET_NORESET 0x00000000 /* RW--V */ #define NV_XVE_CYA_RESIZE_BAR1 0x00000724 /* RW-4R */ #define NV_XVE_CYA_RESIZE_BAR1__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_CYA_RESIZE_BAR1_SIZE 4:0 /* RWCVF */ #define NV_XVE_CYA_RESIZE_BAR1_SIZE_VAL 0x00000008 /* RWC-V */ #define NV_XVE_CYA_RESIZE_BAR1_SIZE_WR_EN 5:5 /* RWCVF */ #define NV_XVE_CYA_RESIZE_BAR1_SIZE_WR_EN_SET 0x00000001 /* RW--V */ #define NV_XVE_CYA_RESIZE_BAR1_SIZE_WR_EN_UNSET 0x00000000 /* RWC-V */ #define NV_XVE_ADVNF_RPT 0x00000728 /* RW-4R */ #define NV_XVE_ADVNF_RPT_CYA_CFGWR_EP 0:0 /* RWCVF */ #define NV_XVE_ADVNF_RPT_CYA_CFGWR_EP_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ADVNF_RPT_CYA_CFGWR_EP_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ADVNF_RPT_CYA_CFGWR_EP_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_ADVNF_RPT_CYA_MEMWR_IOWR_MSGD_EP 1:1 /* RWCVF */ #define NV_XVE_ADVNF_RPT_CYA_MEMWR_IOWR_MSGD_EP_INIT 0x00000000 /* RWC-V */ #define NV_XVE_ADVNF_RPT_CYA_MEMWR_IOWR_MSGD_EP_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_ADVNF_RPT_CYA_MEMWR_IOWR_MSGD_EP_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_ADVNF_RPT_RSVD 31:2 /* C--VF */ #define NV_XVE_ADVNF_RPT_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_FUSE_OVERRIDE 0x0000072C /* RW-4R */ #define NV_XVE_FUSE_OVERRIDE__PRIV_LEVEL_MASK 0x00000FE8 /* */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN23_DIS_OVR_VAL 0:0 /* RWCVF */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN23_DIS_OVR_VAL_GEN1 0x00000001 /* RW--V */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN23_DIS_OVR_VAL_GEN23 0x00000000 /* RWC-V */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN23_DIS_OVR 1:1 /* RWCVF */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN23_DIS_OVR_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN23_DIS_OVR_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN3_DIS_OVR_VAL 2:2 /* RWCVF */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN3_DIS_OVR_VAL_GEN12 0x00000001 /* RW--V */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN3_DIS_OVR_VAL_GEN3 0x00000000 /* RWC-V */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN3_DIS_OVR 3:3 /* RWCVF */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN3_DIS_OVR_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_FUSE_OVERRIDE_BOOT_GEN3_DIS_OVR_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_BUS_DEV_FN0 0x00000730 /* RW-4R */ #define NV_XVE_BUS_DEV_FN0_BUS_NUM 12:5 /* RWCVF */ #define NV_XVE_BUS_DEV_FN0_BUS_NUM_INIT 0x00000000 /* RWC-V */ #define NV_XVE_BUS_DEV_FN0_DEV_NUM 4:0 /* RWCVF */ #define NV_XVE_BUS_DEV_FN0_DEV_NUM_INIT 0x00000000 /* RWC-V */ #define NV_XVE_BUS_DEV_FN1 0x00000734 /* RW-4R */ #define NV_XVE_BUS_DEV_FN1_BUS_NUM 12:5 /* RWCVF */ #define NV_XVE_BUS_DEV_FN1_BUS_NUM_INIT 0x00000000 /* RWC-V */ #define NV_XVE_BUS_DEV_FN1_DEV_NUM 4:0 /* RWCVF */ #define NV_XVE_BUS_DEV_FN1_DEV_NUM_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_6 0x00000740 /* RW-4R */ #define NV_XVE_CYA_6_UC_TAG_HOL_BLOCKING_FIX 0:0 /* RWCVF */ #define NV_XVE_CYA_6_UC_TAG_HOL_BLOCKING_FIX_ENABLED 0x00000001 /* RWC-V */ #define NV_XVE_CYA_6_UC_TAG_HOL_BLOCKING_FIX_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_CYA_6_NUM_10B_TAGS_RESERVED 10:1 /* RWCVF */ #define NV_XVE_CYA_6_NUM_10B_TAGS_RESERVED_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_6_INCLUDE_VF_IN_FN0_TP 11:11 /* RWCVF */ #define NV_XVE_CYA_6_INCLUDE_VF_IN_FN0_TP_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_6_PCI_IOBAR_OVERRIDE_EN 12:12 /* RWCVF */ #define NV_XVE_CYA_6_PCI_IOBAR_OVERRIDE_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_6_PCI_IOBAR_OVERRIDE_VALUE 13:13 /* RWCVF */ #define NV_XVE_CYA_6_PCI_IOBAR_OVERRIDE_VALUE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_6_DISABLE_RXB_HDR_TRACKER_FIX 14:14 /* RWCVF */ #define NV_XVE_CYA_6_DISABLE_RXB_HDR_TRACKER_FIX_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_6_DISABLE_ARI_PWRSTATE_FIX 15:15 /* RWCVF */ #define NV_XVE_CYA_6_DISABLE_ARI_PWRSTATE_FIX_INIT 0x00000000 /* RWC-V */ #define NV_XVE_CYA_6_BLOCK_INTR_PIN_DEASRT_REARM_MSI 16:16 /* RWCVF */ #define NV_XVE_CYA_6_BLOCK_INTR_PIN_DEASRT_REARM_MSI_UNSET 0x00000000 /* RWC-V */ #define NV_XVE_CYA_6_BLOCK_INTR_PIN_DEASRT_REARM_MSI_SET 0x00000001 /* RW--V */ #define NV_XVE_CYA_6_RSVD 31:17 /* RWCVF */ #define NV_XVE_CYA_6_RSVD_INIT 0x00000000 /* RWC-V */ #define NV_XVE_RX_HDR_LIMIT 0x00000800 /* RW-4R */ #define NV_XVE_RX_HDR_LIMIT_CPL_VC0_OVERRIDE 0:0 /* RWIVF */ #define NV_XVE_RX_HDR_LIMIT_CPL_VC0_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_RX_HDR_LIMIT_CPL_VC0_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_RX_HDR_LIMIT_CPL_VC0_OVERRIDE_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_RX_HDR_LIMIT_CPL_VC0 14:4 /* RWIVF */ #define NV_XVE_RX_HDR_LIMIT_CPL_VC0_INIT 0x00000060 /* RWI-V */ #define NV_XVE_RX_HDR_LIMIT_CPL_VC0_UPDATE_PENDING 15:15 /* R-IVF */ #define NV_XVE_RX_HDR_LIMIT_CPL_VC0_UPDATE_PENDING_INIT 0x00000000 /* R-I-V */ #define NV_XVE_RX_DATA_LIMIT 0x00000804 /* RW-4R */ #define NV_XVE_RX_DATA_LIMIT_CPL_VC0_OVERRIDE 0:0 /* RWIVF */ #define NV_XVE_RX_DATA_LIMIT_CPL_VC0_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_RX_DATA_LIMIT_CPL_VC0_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_RX_DATA_LIMIT_CPL_VC0_OVERRIDE_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_RX_DATA_LIMIT_CPL_VC0 14:4 /* RWIVF */ #define NV_XVE_RX_DATA_LIMIT_CPL_VC0_INIT 0x00000060 /* RWI-V */ #define NV_XVE_XV_DBG0 0x00000808 /* R--4R */ #define NV_XVE_XV_DBG0_RX_NPH_VC0_FULL 1:0 /* R-CVF */ #define NV_XVE_XV_DBG0_RX_NPH_VC0_FULL_YES 0x00000003 /* R---V */ #define NV_XVE_XV_DBG0_RX_NPH_VC0_FULL_NO 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG0_RX_NPD_VC0_FULL 3:2 /* R-CVF */ #define NV_XVE_XV_DBG0_RX_NPD_VC0_FULL_YES 0x00000003 /* R---V */ #define NV_XVE_XV_DBG0_RX_NPD_VC0_FULL_NO 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG0_RX_NPH_VC0_EMPTY 5:4 /* R-IVF */ #define NV_XVE_XV_DBG0_RX_NPH_VC0_EMPTY_YES 0x00000003 /* R-I-V */ #define NV_XVE_XV_DBG0_RX_NPH_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG0_RX_NPD_VC0_EMPTY 7:6 /* R-IVF */ #define NV_XVE_XV_DBG0_RX_NPD_VC0_EMPTY_YES 0x00000003 /* R-I-V */ #define NV_XVE_XV_DBG0_RX_NPD_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG0_RX_PWH_VC0_FULL 9:8 /* R-CVF */ #define NV_XVE_XV_DBG0_RX_PWH_VC0_FULL_YES 0x00000003 /* R---V */ #define NV_XVE_XV_DBG0_RX_PWH_VC0_FULL_NO 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG0_RX_PWD_VC0_FULL 11:10 /* R-CVF */ #define NV_XVE_XV_DBG0_RX_PWD_VC0_FULL_YES 0x00000003 /* R---V */ #define NV_XVE_XV_DBG0_RX_PWD_VC0_FULL_NO 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG0_RX_PWH_VC0_EMPTY 13:12 /* R-IVF */ #define NV_XVE_XV_DBG0_RX_PWH_VC0_EMPTY_YES 0x00000003 /* R-I-V */ #define NV_XVE_XV_DBG0_RX_PWH_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG0_RX_PWD_VC0_EMPTY 15:14 /* R-IVF */ #define NV_XVE_XV_DBG0_RX_PWD_VC0_EMPTY_YES 0x00000003 /* R-I-V */ #define NV_XVE_XV_DBG0_RX_PWD_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG0_RX_CPH_VC0_FULL 17:16 /* R-CVF */ #define NV_XVE_XV_DBG0_RX_CPH_VC0_FULL_YES 0x00000003 /* R---V */ #define NV_XVE_XV_DBG0_RX_CPH_VC0_FULL_NO 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG0_RX_CPH_VC0_EMPTY 19:18 /* R-CVF */ #define NV_XVE_XV_DBG0_RX_CPH_VC0_EMPTY_YES 0x00000003 /* R-C-V */ #define NV_XVE_XV_DBG0_RX_CPH_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG0_RX_CPH_STS_VECTOR_FULL 20:20 /* R-IVF */ #define NV_XVE_XV_DBG0_RX_CPH_STS_VECTOR_FULL_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG0_RX_CPH_STS_VECTOR_FULL_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG0_RX_CPH_STS_VECTOR_EMPTY 21:21 /* R-IVF */ #define NV_XVE_XV_DBG0_RX_CPH_STS_VECTOR_EMPTY_YES 0x00000001 /* R-I-V */ #define NV_XVE_XV_DBG0_RX_CPH_STS_VECTOR_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2 0x00000810 /* R--4R */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_FULL 0:0 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_FULL_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_FULL_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_FULL 1:1 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_FULL_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_FULL_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_EMPTY 2:2 /* R-CVF */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_EMPTY_YES 0x00000001 /* R-C-V */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_EMPTY 3:3 /* R-CVF */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_EMPTY_YES 0x00000001 /* R-C-V */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_FULL 4:4 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_FULL_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_FULL_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_FULL 5:5 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_FULL_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_FULL_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_EMPTY 6:6 /* R-CVF */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_EMPTY_YES 0x00000001 /* R-C-V */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_EMPTY 7:7 /* R-CVF */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_EMPTY_YES 0x00000001 /* R-C-V */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_FULL 8:8 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_FULL_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_FULL_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_FULL 9:9 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_FULL_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_FULL_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_EMPTY 10:10 /* R-CVF */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_EMPTY_YES 0x00000001 /* R-C-V */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_EMPTY 11:11 /* R-CVF */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_EMPTY_YES 0x00000001 /* R-C-V */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2_TX_TAG_VECTOR_FULL 12:12 /* R-CVF */ #define NV_XVE_XV_DBG2_TX_TAG_VECTOR_FULL_YES 0x00000001 /* R-C-V */ #define NV_XVE_XV_DBG2_TX_TAG_VECTOR_FULL_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2_TX_TAG_VECTOR_EMPTY 13:13 /* R-CVF */ #define NV_XVE_XV_DBG2_TX_TAG_VECTOR_EMPTY_YES 0x00000001 /* R-C-V */ #define NV_XVE_XV_DBG2_TX_TAG_VECTOR_EMPTY_NO 0x00000000 /* R---V */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_FULL_ONE_LESS 14:14 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_FULL_ONE_LESS_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_NPH_VC0_FULL_ONE_LESS_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_FULL_ONE_LESS 15:15 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_FULL_ONE_LESS_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_NPD_VC0_FULL_ONE_LESS_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_FULL_ONE_LESS 16:16 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_FULL_ONE_LESS_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_PWH_VC0_FULL_ONE_LESS_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_FULL_ONE_LESS 17:17 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_FULL_ONE_LESS_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_PWD_VC0_FULL_ONE_LESS_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_FULL_ONE_LESS 18:18 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_FULL_ONE_LESS_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_CPH_VC0_FULL_ONE_LESS_NO 0x00000000 /* R-I-V */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_FULL_ONE_LESS 19:19 /* R-IVF */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_FULL_ONE_LESS_YES 0x00000001 /* R---V */ #define NV_XVE_XV_DBG2_TX_CPD_VC0_FULL_ONE_LESS_NO 0x00000000 /* R-I-V */ #define NV_XVE_P2P_DBG 0x00000818 /* RW-4R */ #define NV_XVE_P2P_DBG__PRIV_LEVEL_MASK 0x00000FF0 /* */ #define NV_XVE_P2P_DBG_UNEXPECTED_P2PCPL_ERR 0:0 /* RWCVF */ #define NV_XVE_P2P_DBG_UNEXPECTED_P2PCPL_ERR_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_P2P_DBG_UNEXPECTED_P2PCPL_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_P2P_DBG_UNEXPECTED_P2PCPL_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_P2P_DBG_P2PMASTER_CPL_TO_DISABLE 1:1 /* RWCVF */ #define NV_XVE_P2P_DBG_P2PMASTER_CPL_TO_DISABLE_ENABLED 0x00000000 /* RWC-V */ #define NV_XVE_P2P_DBG_P2PMASTER_CPL_TO_DISABLE_DISABLED 0x00000001 /* RW--V */ #define NV_XVE_P2P_DBG_P2PMASTER_CPL_TO_ERR 2:2 /* RWCVF */ #define NV_XVE_P2P_DBG_P2PMASTER_CPL_TO_ERR_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_P2P_DBG_P2PMASTER_CPL_TO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_P2P_DBG_P2PMASTER_CPL_TO_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_PRIV_XV_VC_WRR 0x0000081C /* RW-4R */ #define NV_XVE_PRIV_XV_VC_WRR__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_XV_VC_WRR_VC0_WEIGHT 4:0 /* RWCVF */ #define NV_XVE_PRIV_XV_VC_WRR_VC0_WEIGHT_1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_PKT_WRR 0x00000820 /* RW-4R */ #define NV_XVE_PRIV_XV_PKT_WRR__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_XV_PKT_WRR_0_VC0_WEIGHT 4:0 /* RWCVF */ #define NV_XVE_PRIV_XV_PKT_WRR_0_VC0_WEIGHT_1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_PKT_WRR_1_VC0_WEIGHT 9:5 /* RWCVF */ #define NV_XVE_PRIV_XV_PKT_WRR_1_VC0_WEIGHT_1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_XV_PKT_WRR_2_VC0_WEIGHT 14:10 /* RWCVF */ #define NV_XVE_PRIV_XV_PKT_WRR_2_VC0_WEIGHT_1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE0 0x00000824 /* RW-4R */ #define NV_XVE_PRIV_RX_THROTTLE0__PRIV_LEVEL_MASK 0x00000FFC /* */ #define NV_XVE_PRIV_RX_THROTTLE0_NPH_THROTLLED 7:0 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE0_NPH_THROTLLED_1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE0_PWH_THROTLLED 15:8 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE0_PWH_THROTLLED_1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE0_NPH_THROTLLING_EN 24:24 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE0_NPH_THROTLLING_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE0_NPH_THROTLLING_EN_CLEAR 0x00000000 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE0_NPH_THROTLLING_EN_SET 0x00000001 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE0_PWH_THROTLLING_EN 28:28 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE0_PWH_THROTLLING_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE0_PWH_THROTLLING_EN_CLEAR 0x00000000 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE0_PWH_THROTLLING_EN_SET 0x00000001 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE1 0x00000828 /* RW-4R */ #define NV_XVE_PRIV_RX_THROTTLE1__PRIV_LEVEL_MASK 0x00000FFC /* */ #define NV_XVE_PRIV_RX_THROTTLE1_NPD_THROTLLED 11:0 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE1_NPD_THROTLLED_1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE1_PWD_THROTLLED 27:16 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE1_PWD_THROTLLED_1 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE1_NPD_THROTLLING_EN 28:28 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE1_NPD_THROTLLING_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE1_NPD_THROTLLING_EN_CLEAR 0x00000000 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE1_NPD_THROTLLING_EN_SET 0x00000001 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE1_PWD_THROTLLING_EN 29:29 /* RWCVF */ #define NV_XVE_PRIV_RX_THROTTLE1_PWD_THROTLLING_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_RX_THROTTLE1_PWD_THROTLLING_EN_CLEAR 0x00000000 /* RW--V */ #define NV_XVE_PRIV_RX_THROTTLE1_PWD_THROTLLING_EN_SET 0x00000001 /* RW--V */ #define NV_XVE_PRIV_C11_MISC 0x0000082C /* RW-4R */ #define NV_XVE_PRIV_C11_MISC_SOFTFLUSH_HOST 0:0 /* RWIVF */ #define NV_XVE_PRIV_C11_MISC_SOFTFLUSH_HOST_ENABLED 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_C11_MISC_SOFTFLUSH_HOST_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_SOFTFLUSH_AZA 1:1 /* RWIVF */ #define NV_XVE_PRIV_C11_MISC_SOFTFLUSH_AZA_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_SOFTFLUSH_AZA_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_C11_MISC_IGNORE_POISONED_CPLD_HOST 2:2 /* RWIVF */ #define NV_XVE_PRIV_C11_MISC_IGNORE_POISONED_CPLD_HOST_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_C11_MISC_IGNORE_POISONED_CPLD_HOST_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_IGNORE_POISONED_CPLD_AZA 3:3 /* RWIVF */ #define NV_XVE_PRIV_C11_MISC_IGNORE_POISONED_CPLD_AZA_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_C11_MISC_IGNORE_POISONED_CPLD_AZA_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_EN 4:4 /* RWIVF */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL 14:8 /* RWIVF */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_INIT 0x00000030 /* RWI-V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_1_PERCENT 0x00000001 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_2_PERCENT 0x00000002 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_3_PERCENT 0x00000003 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_4_PERCENT 0x00000004 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_5_PERCENT 0x00000005 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_6_PERCENT 0x00000006 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_7_PERCENT 0x00000007 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_8_PERCENT 0x00000008 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_9_PERCENT 0x00000009 /* RW--V */ #define NV_XVE_PRIV_C11_MISC_X8_THROTTLING_VAL_10_PERCENT 0x0000000A /* RW--V */ #define NV_XVE_PRIV_C11_MISC_OBFF_CODE 18:15 /* R-IVF */ #define NV_XVE_PRIV_C11_MISC_OBFF_CODE_CPU_ACTIVE 0x0000000F /* R-I-V */ #define NV_XVE_PRIV_C11_MISC_OBFF_CODE_CPU_OBFF 0x00000001 /* R---V */ #define NV_XVE_PRIV_C11_MISC_OBFF_CODE_CPU_IDLE 0x00000000 /* R---V */ #define NV_XVE_PRIV_ARB1_WRR 0x00000830 /* RW-4R */ #define NV_XVE_PRIV_ARB1_WRR_WEIGHT_CHANNEL0 4:0 /* RWIVF */ #define NV_XVE_PRIV_ARB1_WRR_WEIGHT_CHANNEL0_DEFAULT 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_ARB1_WRR_WEIGHT_CHANNEL1 9:5 /* RWIVF */ #define NV_XVE_PRIV_ARB1_WRR_WEIGHT_CHANNEL1_DEFAULT 0x00000001 /* RWI-V */ #define NV_XVE_PRIV_XV_LATENCY 0x00000838 /* RW-4R */ #define NV_XVE_PRIV_XV_LATENCY_HOSTCLK_LE_2X_XCLK 0:0 /* RWIVF */ #define NV_XVE_PRIV_XV_LATENCY_HOSTCLK_LE_2X_XCLK_DEFAULT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_XV_LATENCY_XCLK_LE_2X_HOSTCLK 1:1 /* RWIVF */ #define NV_XVE_PRIV_XV_LATENCY_XCLK_LE_2X_HOSTCLK_DEFAULT 0x00000000 /* RWI-V */ #define NV_XVE_PRIV_BLCG_STS 0x0000083C /* R--4R */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_INTF 1:0 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_INTF_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_UC_CPL_INTF 3:2 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_UC_CPL_INTF_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_UC_CPL_ARB 5:4 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_UC_CPL_ARB_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_ERR 7:6 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_ERR_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_DC_REQ_ARB_VC0 9:8 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_DC_REQ_ARB_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_DC_REQ_DEC_DCBUF_VC0 11:10 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_DC_REQ_DEC_DCBUF_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_DC_REQ_INTF_VC0 13:12 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_DC_REQ_INTF_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_DC_CPL_ARB_VC0 15:14 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_DC_CPL_ARB_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_DC_CPL_INTF_VC0 17:16 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_DC_CPL_INTF_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_MISC_VC0 19:18 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_MISC_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_SPLIT_VC0 21:20 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_SPLIT_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_BUF_STG2_VC0 23:22 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_BUF_STG2_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_MIXER_ARB3_VC0 25:24 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_UC_REQ_MIXER_ARB3_VC0_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_P2PTGT 27:26 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_P2PTGT_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_PRIV_BLCG_STS_DC_REQ_PRI 29:28 /* R-CVF */ #define NV_XVE_PRIV_BLCG_STS_DC_REQ_PRI_IDLE 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0 0x00000840 /* R--4R */ #define NV_XVE_CPLTO_HDR0_SYSMEM 0:0 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_SYSMEM_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0_PEERMEM 1:1 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_PEERMEM_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0_PEER_ID 5:2 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_PEER_ID_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0_FN 10:8 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_FN_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0_TC 13:11 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_TC_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0_NO_SNOOP 14:14 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_NO_SNOOP_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0_RELAXED_ORD 15:15 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_RELAXED_ORD_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0_LENGTH 23:16 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_LENGTH_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR0_TAG 31:24 /* R-CVF */ #define NV_XVE_CPLTO_HDR0_TAG_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_HDR1 0x00000844 /* R--4R */ #define NV_XVE_CPLTO_HDR1_ADDR_DW0 31:0 /* R-CVF */ #define NV_XVE_CPLTO_HDR1_ADDR_DW0_INIT 0x00000844 /* R-C-V */ #define NV_XVE_CPLTO_MISC 0x00000848 /* RW-4R */ #define NV_XVE_CPLTO_MISC_SYSMEM 0:0 /* R-CVF */ #define NV_XVE_CPLTO_MISC_SYSMEM_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_PEERMEM 1:1 /* R-CVF */ #define NV_XVE_CPLTO_MISC_PEERMEM_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_PEER_ID 4:2 /* R-CVF */ #define NV_XVE_CPLTO_MISC_PEER_ID_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_FN 7:5 /* R-CVF */ #define NV_XVE_CPLTO_MISC_FN_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_NO_SNOOP 8:8 /* R-CVF */ #define NV_XVE_CPLTO_MISC_NO_SNOOP_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_RELAXED_ORD 9:9 /* R-CVF */ #define NV_XVE_CPLTO_MISC_RELAXED_ORD_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_LENGTH 17:10 /* R-CVF */ #define NV_XVE_CPLTO_MISC_LENGTH_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_ADDR_DW0_VLD 18:18 /* RWCVF */ #define NV_XVE_CPLTO_MISC_ADDR_DW0_VLD_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_ADDR_DW0_VLD_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_CPLTO_MISC_CYA_BYPASS_DCPWFIFO_FULL_CHECK 30:30 /* RWCVF */ #define NV_XVE_CPLTO_MISC_CYA_BYPASS_DCPWFIFO_FULL_CHECK_INIT 0x00000001 /* RWC-V */ #define NV_XVE_CPLTO_MISC_UC2TXB_INTF_VIOLATION 31:31 /* RWCVF */ #define NV_XVE_CPLTO_MISC_UC2TXB_INTF_VIOLATION_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CPLTO_MISC_UC2TXB_INTF_VIOLATION_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0 0x0000084C /* RW-4R */ #define NV_XVE_DBG0_OUTSTANDING_UPSTREAM_READ_VC0 8:0 /* R--VF */ #define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET 9:9 /* RWCVF */ #define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_TRIGGER 0x00000001 /* -W--T */ #define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_DONE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG0_XVE2FB_IDLE_CREDITS 21:21 /* R--VF */ #define NV_XVE_DBG0_FB2XVE_IDLE_CREDITS 22:22 /* R--VF */ #define NV_XVE_DBG0_FB_IDLE 23:23 /* R--VF */ #define NV_XVE_DBG0_OUTSTANDING_DOWNSTREAM_READ 31:24 /* R--VF */ #define NV_XVE_ERROR_COUNTER1 0x00000854 /* R--4R */ #define NV_XVE_ERROR_COUNTER1_CORR_ERROR_COUNT_VALUE 15:0 /* R-XVF */ #define NV_XVE_PM_FILTER1 0x00000858 /* RW-4R */ #define NV_XVE_PM_FILTER1_BAR0_RD 0:0 /* RWCUF */ #define NV_XVE_PM_FILTER1_BAR0_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_BAR0_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_BAR0_WR 1:1 /* RWCUF */ #define NV_XVE_PM_FILTER1_BAR0_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_BAR0_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_BAR1_RD 2:2 /* RWCUF */ #define NV_XVE_PM_FILTER1_BAR1_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_BAR1_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_BAR1_WR 3:3 /* RWCUF */ #define NV_XVE_PM_FILTER1_BAR1_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_BAR1_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_BAR2_RD 4:4 /* RWCUF */ #define NV_XVE_PM_FILTER1_BAR2_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_BAR2_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_BAR2_WR 5:5 /* RWCUF */ #define NV_XVE_PM_FILTER1_BAR2_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_BAR2_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_BAR3_RD 6:6 /* RWCUF */ #define NV_XVE_PM_FILTER1_BAR3_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_BAR3_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_BAR3_WR 7:7 /* RWCUF */ #define NV_XVE_PM_FILTER1_BAR3_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_BAR3_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_IO_RD 8:8 /* RWCUF */ #define NV_XVE_PM_FILTER1_IO_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_IO_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_IO_WR 9:9 /* RWCUF */ #define NV_XVE_PM_FILTER1_IO_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_IO_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_ROM_RD 10:10 /* RWCUF */ #define NV_XVE_PM_FILTER1_ROM_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_ROM_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_ROM_WR 11:11 /* RWCUF */ #define NV_XVE_PM_FILTER1_ROM_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_ROM_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_VGA_RD 12:12 /* RWCUF */ #define NV_XVE_PM_FILTER1_VGA_RD_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_VGA_RD_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_PM_FILTER1_VGA_WR 13:13 /* RWCUF */ #define NV_XVE_PM_FILTER1_VGA_WR_IGNORE 0x00000000 /* RW--V */ #define NV_XVE_PM_FILTER1_VGA_WR_RECORD 0x00000001 /* RWC-V */ #define NV_XVE_DBG_HDRLOG_POS_DW0 0x0000085C /* R--4R */ #define NV_XVE_DBG_HDRLOG_POS_DW0_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_POS_DW1 0x00000860 /* R--4R */ #define NV_XVE_DBG_HDRLOG_POS_DW1_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_POS_DW2 0x00000864 /* R--4R */ #define NV_XVE_DBG_HDRLOG_POS_DW2_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_POS_DW3 0x00000868 /* R--4R */ #define NV_XVE_DBG_HDRLOG_POS_DW3_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_UR_DW0 0x0000086C /* R--4R */ #define NV_XVE_DBG_HDRLOG_UR_DW0_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_UR_DW1 0x00000870 /* R--4R */ #define NV_XVE_DBG_HDRLOG_UR_DW1_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_UR_DW2 0x00000874 /* R--4R */ #define NV_XVE_DBG_HDRLOG_UR_DW2_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_UR_DW3 0x00000878 /* R--4R */ #define NV_XVE_DBG_HDRLOG_UR_DW3_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_MALFORMED_DW0 0x0000087C /* R--4R */ #define NV_XVE_DBG_HDRLOG_MALFORMED_DW0_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_MALFORMED_DW1 0x00000880 /* R--4R */ #define NV_XVE_DBG_HDRLOG_MALFORMED_DW1_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_MALFORMED_DW2 0x00000884 /* R--4R */ #define NV_XVE_DBG_HDRLOG_MALFORMED_DW2_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_MALFORMED_DW3 0x00000888 /* R--4R */ #define NV_XVE_DBG_HDRLOG_MALFORMED_DW3_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_UNEXP_CPL_DW0 0x0000088C /* R--4R */ #define NV_XVE_DBG_HDRLOG_UNEXP_CPL_DW0_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_UNEXP_CPL_DW1 0x00000890 /* R--4R */ #define NV_XVE_DBG_HDRLOG_UNEXP_CPL_DW1_0 31:0 /* R--VF */ #define NV_XVE_DBG_HDRLOG_UNEXP_CPL_DW2 0x00000894 /* R--4R */ #define NV_XVE_DBG_HDRLOG_UNEXP_CPL_DW2_0 31:0 /* R--VF */ #define NV_XVE_DBG_CYA_0 0x00000898 /* RW-4R */ #define NV_XVE_DBG_CYA_0__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_DBG_CYA_0_DOWNSTREAM_NP_HOST 7:0 /* RWIVF */ #define NV_XVE_DBG_CYA_0_DOWNSTREAM_NP_HOST_INIT 0x000000FF /* RWI-V */ #define NV_XVE_DBG_CYA_0_DOWNSTREAM_NP_AZA 15:8 /* RWIVF */ #define NV_XVE_DBG_CYA_0_DOWNSTREAM_NP_AZA_INIT 0x000000FF /* RWI-V */ #define NV_XVE_DBG_CYA_0_POSTED_DEADLOCK_P2P_PW_DROP 16:16 /* RWIVF */ #define NV_XVE_DBG_CYA_0_POSTED_DEADLOCK_P2P_PW_DROP_DISABLE 0x00000000 /* RWI-V */ #define NV_XVE_DBG_CYA_0_POSTED_DEADLOCK_P2P_PW_DROP_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_DBG_CYA_0_VF_BME_GATE 17:17 /* RWCVF */ #define NV_XVE_DBG_CYA_0_VF_BME_GATE_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_DBG_CYA_0_VF_BME_GATE_DISBLE 0x00000000 /* RW--V */ #define NV_XVE_DBG_CYA_0_VF_BME_FIX 18:18 /* RWCVF */ #define NV_XVE_DBG_CYA_0_VF_BME_FIX_ENBALE 0x00000001 /* RWC-V */ #define NV_XVE_DBG_CYA_0_VF_BME_FIX_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_DBG_CYA_0_BAR0_ADDR_WIDTH 19:19 /* RWCVF */ #define NV_XVE_DBG_CYA_0_BAR0_ADDR_WIDTH_32BIT 0x00000000 /* RWC-V */ #define NV_XVE_DBG_CYA_0_BAR0_ADDR_WIDTH_64BIT 0x00000001 /* RW--V */ #define NV_XVE_DBG_CYA_0_MSIX_THROTTLE 20:20 /* RWCVF */ #define NV_XVE_DBG_CYA_0_MSIX_THROTTLE_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_DBG_CYA_0_MSIX_THROTTLE_ENABLE 0x00000001 /* RWC-V */ #define NV_XVE_DBG_CYA_0_MSIX_ALLOW_NUM 31:24 /* RWCVF */ #define NV_XVE_DBG_CYA_0_MSIX_ALLOW_NUM_INIT 0x00000001 /* RWC-V */ #define NV_XVE_MAX_LATENCY_0 0x0000089C /* RW-4R */ #define NV_XVE_MAX_LATENCY_0_COH_SYSMEM 31:0 /* RWCVF */ #define NV_XVE_MAX_LATENCY_0_COH_SYSMEM_INIT 0x00000000 /* R-C-V */ #define NV_XVE_MAX_LATENCY_0_COH_SYSMEM_REFRESH 0xFFFFFFFF /* -W--V */ #define NV_XVE_MAX_LATENCY_1 0x000008A0 /* RW-4R */ #define NV_XVE_MAX_LATENCY_1_NCOH_SYSMEM 31:0 /* RWCVF */ #define NV_XVE_MAX_LATENCY_1_NCOH_SYSMEM_INIT 0x00000000 /* R-C-V */ #define NV_XVE_MAX_LATENCY_1_NCOH_SYSMEM_REFRESH 0xFFFFFFFF /* -W--V */ #define NV_XVE_MAX_LATENCY_2 0x000008A4 /* RW-4R */ #define NV_XVE_MAX_LATENCY_2_PEERMEM 31:0 /* RWCVF */ #define NV_XVE_MAX_LATENCY_2_PEERMEM_INIT 0x00000000 /* R-C-V */ #define NV_XVE_MAX_LATENCY_2_PEERMEM_REFRESH 0xFFFFFFFF /* -W--V */ #define NV_XVE_MIN_LATENCY_0 0x000008A8 /* RW-4R */ #define NV_XVE_MIN_LATENCY_0_COH_SYSMEM 31:0 /* RWCVF */ #define NV_XVE_MIN_LATENCY_0_COH_SYSMEM_INIT 0xFFFFFFFF /* R-C-V */ #define NV_XVE_MIN_LATENCY_0_COH_SYSMEM_REFRESH 0x00000000 /* -W--V */ #define NV_XVE_MIN_LATENCY_1 0x000008AC /* RW-4R */ #define NV_XVE_MIN_LATENCY_1_NCOH_SYSMEM 31:0 /* RWCVF */ #define NV_XVE_MIN_LATENCY_1_NCOH_SYSMEM_INIT 0xFFFFFFFF /* R-C-V */ #define NV_XVE_MIN_LATENCY_1_NCOH_SYSMEM_REFRESH 0x00000000 /* -W--V */ #define NV_XVE_MIN_LATENCY_2 0x000008B0 /* RW-4R */ #define NV_XVE_MIN_LATENCY_2_PEERMEM 31:0 /* RWCVF */ #define NV_XVE_MIN_LATENCY_2_PEERMEM_INIT 0xFFFFFFFF /* R-C-V */ #define NV_XVE_MIN_LATENCY_2_PEERMEM_REFRESH 0x00000000 /* -W--V */ #define NV_XVE_PRIV_MICROSECOND_XCLK 0x000008B4 /* RW-4R */ #define NV_XVE_PRIV_MICROSECOND_XCLK__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_MICROSECOND_XCLK_ALT 9:0 /* RWCVF */ #define NV_XVE_PRIV_MICROSECOND_XCLK_ALT_27 0x0000001B /* RWC-V */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE 16:16 /* RWCVF */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE_VAL 31:20 /* RWCVF */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE_VAL_100 0x00000064 /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE_VAL_125 0x0000007D /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE_VAL_250 0x000000FA /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE_VAL_1000 0x000003E8 /* RWC-V */ #define NV_XVE_PRIV_MICROSECOND_XCLK_OVERRIDE_VAL_500 0x000001F4 /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK 0x000008B8 /* RW-4R */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_ALT 9:0 /* RWCVF */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_ALT_27 0x0000001B /* RWC-V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE 16:16 /* RWCVF */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_VAL 31:20 /* RWCVF */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_VAL_100 0x00000065 /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_VAL_277 0x00000115 /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_VAL_417 0x000001A1 /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_VAL_444 0x000001BC /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_VAL_500 0x000001F4 /* RW--V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_VAL_1142 0x00000476 /* RWC-V */ #define NV_XVE_PRIV_MICROSECOND_HOSTCLK_OVERRIDE_VAL_571 0x0000023B /* RW--V */ #define NV_XVE_XV_DBG4 0x000008BC /* RW-4R */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_OVERFLOW_BANK0 0:0 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_OVERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_OVERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_OVERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_OVERFLOW_BANK1 1:1 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_OVERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_OVERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_OVERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_OVERFLOW_BANK0 2:2 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_OVERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_OVERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_OVERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_OVERFLOW_BANK1 3:3 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_OVERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_OVERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_OVERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_UNDERFLOW_BANK0 4:4 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_UNDERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_UNDERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_UNDERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_UNDERFLOW_BANK1 5:5 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_UNDERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_UNDERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_NPH_VC0_UNDERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_UNDERFLOW_BANK0 6:6 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_UNDERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_UNDERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_UNDERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_UNDERFLOW_BANK1 7:7 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_UNDERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_UNDERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_NPD_VC0_UNDERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_OVERFLOW_BANK0 8:8 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_OVERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_OVERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_OVERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_OVERFLOW_BANK1 9:9 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_OVERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_OVERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_OVERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_OVERFLOW_BANK0 10:10 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_OVERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_OVERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_OVERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_OVERFLOW_BANK1 11:11 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_OVERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_OVERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_OVERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_UNDERFLOW_BANK0 12:12 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_UNDERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_UNDERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_UNDERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_UNDERFLOW_BANK1 13:13 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_UNDERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_UNDERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_PWH_VC0_UNDERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_UNDERFLOW_BANK0 14:14 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_UNDERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_UNDERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_UNDERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_UNDERFLOW_BANK1 15:15 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_UNDERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_UNDERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_PWD_VC0_UNDERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_OVERFLOW_BANK1 16:16 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_OVERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_OVERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_OVERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_OVERFLOW_BANK0 17:17 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_OVERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_OVERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_OVERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_UNDERFLOW_BANK0 18:18 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_UNDERFLOW_BANK0_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_UNDERFLOW_BANK0_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_UNDERFLOW_BANK0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_UNDERFLOW_BANK1 19:19 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_UNDERFLOW_BANK1_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_UNDERFLOW_BANK1_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_CPH_PROCSTAGE_UNDERFLOW_BANK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_CPH_STS_VECTOR_OVERFLOW 20:20 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_CPH_STS_VECTOR_OVERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_CPH_STS_VECTOR_OVERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_CPH_STS_VECTOR_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG4_RX_CPH_STS_VECTOR_UNDERFLOW 21:21 /* RWCVF */ #define NV_XVE_XV_DBG4_RX_CPH_STS_VECTOR_UNDERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG4_RX_CPH_STS_VECTOR_UNDERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG4_RX_CPH_STS_VECTOR_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6 0x000008C4 /* RW-4R */ #define NV_XVE_XV_DBG6_TX_NPH_VC0_OVERFLOW 0:0 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_NPH_VC0_OVERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_NPH_VC0_OVERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_NPH_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_NPD_VC0_OVERFLOW 1:1 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_NPD_VC0_OVERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_NPD_VC0_OVERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_NPD_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_NPH_VC0_UNDERFLOW 2:2 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_NPH_VC0_UNDERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_NPH_VC0_UNDERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_NPH_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_NPD_VC0_UNDERFLOW 3:3 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_NPD_VC0_UNDERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_NPD_VC0_UNDERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_NPD_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_PWH_VC0_OVERFLOW 4:4 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_PWH_VC0_OVERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_PWH_VC0_OVERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_PWH_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_PWD_VC0_OVERFLOW 5:5 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_PWD_VC0_OVERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_PWD_VC0_OVERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_PWD_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_PWH_VC0_UNDERFLOW 6:6 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_PWH_VC0_UNDERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_PWH_VC0_UNDERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_PWH_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_PWD_VC0_UNDERFLOW 7:7 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_PWD_VC0_UNDERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_PWD_VC0_UNDERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_PWD_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_CPH_VC0_OVERFLOW 8:8 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_CPH_VC0_OVERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_CPH_VC0_OVERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_CPH_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_CPD_VC0_OVERFLOW 9:9 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_CPD_VC0_OVERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_CPD_VC0_OVERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_CPD_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_CPH_VC0_UNDERFLOW 10:10 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_CPH_VC0_UNDERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_CPH_VC0_UNDERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_CPH_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_CPD_VC0_UNDERFLOW 11:11 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_CPD_VC0_UNDERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_CPD_VC0_UNDERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_CPD_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_TAG_VECTOR_OVERFLOW 12:12 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_TAG_VECTOR_OVERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_TAG_VECTOR_OVERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_TAG_VECTOR_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_XV_DBG6_TX_TAG_VECTOR_UNDERFLOW 13:13 /* RWCVF */ #define NV_XVE_XV_DBG6_TX_TAG_VECTOR_UNDERFLOW_INIT 0x00000000 /* R-C-V */ #define NV_XVE_XV_DBG6_TX_TAG_VECTOR_UNDERFLOW_ERR_SET 0x00000001 /* R---V */ #define NV_XVE_XV_DBG6_TX_TAG_VECTOR_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG_PRIV_INTR 0x000008CC /* RW-4R */ #define NV_XVE_DBG_PRIV_INTR_CPL_TIMEOUT 0:0 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_DBG_PRIV_INTR_MSGBOX_INTERRUPT 1:1 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_MSGBOX_INTERRUPT_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_MSGBOX_INTERRUPT_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_AZA_CPL_TIMEOUT 2:2 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_AZA_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_AZA_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_AZA_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_DBG_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT 3:3 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_DBG_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT 4:4 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_DBG_PRIV_INTR_BAR_OVERLAP 5:5 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_BAR_OVERLAP_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_BAR_OVERLAP_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_BAR_OVERLAP_RESET 0x00000001 /* -W--C */ #define NV_XVE_DBG_PRIV_INTR_P2PMASTER_CPL_TIMEOUT 8:8 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_XVE_DBG_PRIV_INTR_P2P_SPLIT_ERR 9:9 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_P2P_SPLIT_ERR_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_P2P_SPLIT_ERR_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_P2P_SPLIT_ERR_RESET 0x00000001 /* -W--C */ #define NV_XVE_DBG_PRIV_INTR_OBFF_MSG 10:10 /* RWCVF */ #define NV_XVE_DBG_PRIV_INTR_OBFF_MSG_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_DBG_PRIV_INTR_OBFF_MSG_PENDING 0x00000001 /* R---V */ #define NV_XVE_DBG_PRIV_INTR_OBFF_MSG_RESET 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC 0x000008D0 /* RW-4R */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLH_CHECK1 0:0 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLH_CHECK1_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLH_CHECK1_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLH_CHECK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLH_CHECK2 1:1 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLH_CHECK2_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLH_CHECK2_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLH_CHECK2_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLD_CHECK1 2:2 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLD_CHECK1_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLD_CHECK1_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLD_CHECK1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLD_CHECK2 3:3 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLD_CHECK2_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLD_CHECK2_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_SPLIT_VC0_CPLD_CHECK2_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_PW_OVERFLOW 4:4 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_PW_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_PW_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_PW_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_PW_UNDERFLOW 5:5 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_PW_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_PW_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_PW_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_NP_OVERFLOW 6:6 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_NP_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_NP_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_NP_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_NP_UNDERFLOW 7:7 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_NP_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_NP_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_INTF_FN0_VC0_NP_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_CPLH_VC0_CREDIT_OVERFLOW 8:8 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_CPLH_VC0_CREDIT_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_CPLH_VC0_CREDIT_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_CPLH_VC0_CREDIT_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_CPLH_VC0_CREDIT_UNDERFLOW 9:9 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_CPLH_VC0_CREDIT_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_CPLH_VC0_CREDIT_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_CPLH_VC0_CREDIT_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_CPLD_VC0_CREDIT_OVERFLOW 10:10 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_CPLD_VC0_CREDIT_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_CPLD_VC0_CREDIT_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_CPLD_VC0_CREDIT_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_CPLD_VC0_CREDIT_UNDERFLOW 11:11 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_CPLD_VC0_CREDIT_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_CPLD_VC0_CREDIT_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_CPLD_VC0_CREDIT_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_HDR_OVERFLOW 12:12 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_HDR_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_HDR_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_HDR_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_HDR_UNDERFLOW 13:13 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_HDR_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_HDR_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_HDR_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT_OVERFLOW 14:14 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT_UNDERFLOW 15:15 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT2_OVERFLOW 16:16 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT2_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT2_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT2_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT2_UNDERFLOW 17:17 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT2_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT2_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_PW_DAT2_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_NP_HDR_OVERFLOW 18:18 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_NP_HDR_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_NP_HDR_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_NP_HDR_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_NP_HDR_UNDERFLOW 19:19 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_NP_HDR_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_NP_HDR_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_BUF_STG2_VC0_NP_HDR_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_DC_CPL_FIFO_VC0_OVERFLOW 20:20 /* RWCVF */ #define NV_XVE_DBG0_MISC_DC_CPL_FIFO_VC0_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_DC_CPL_FIFO_VC0_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_DC_CPL_FIFO_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_DC_CPL_FIFO_VC0_UNDERFLOW 21:21 /* RWCVF */ #define NV_XVE_DBG0_MISC_DC_CPL_FIFO_VC0_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_DC_CPL_FIFO_VC0_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_DC_CPL_FIFO_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_DCBUF_NP_CREDIT_VC0_OVERFLOW 22:22 /* RWCVF */ #define NV_XVE_DBG0_MISC_DCBUF_NP_CREDIT_VC0_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_DCBUF_NP_CREDIT_VC0_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_DCBUF_NP_CREDIT_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_DCBUF_NP_CREDIT_VC0_UNDERFLOW 23:23 /* RWCVF */ #define NV_XVE_DBG0_MISC_DCBUF_NP_CREDIT_VC0_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_DCBUF_NP_CREDIT_VC0_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_DCBUF_NP_CREDIT_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_DS_ERR_FIFO_CREDIT_VC0_OVERFLOW 24:24 /* RWCVF */ #define NV_XVE_DBG0_MISC_DS_ERR_FIFO_CREDIT_VC0_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_DS_ERR_FIFO_CREDIT_VC0_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_DS_ERR_FIFO_CREDIT_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_DS_ERR_FIFO_CREDIT_VC0_UNDERFLOW 25:25 /* RWCVF */ #define NV_XVE_DBG0_MISC_DS_ERR_FIFO_CREDIT_VC0_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_DS_ERR_FIFO_CREDIT_VC0_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_DS_ERR_FIFO_CREDIT_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_CPL_ERR_CREDIT_VC0_OVERFLOW 26:26 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_CPL_ERR_CREDIT_VC0_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_CPL_ERR_CREDIT_VC0_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_CPL_ERR_CREDIT_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_CPL_ERR_CREDIT_VC0_UNDERFLOW 27:27 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_CPL_ERR_CREDIT_VC0_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_CPL_ERR_CREDIT_VC0_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_CPL_ERR_CREDIT_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_CPL_CFG_FIFO_CREDIT_VC0_OVERFLOW 28:28 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_CPL_CFG_FIFO_CREDIT_VC0_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_CPL_CFG_FIFO_CREDIT_VC0_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_CPL_CFG_FIFO_CREDIT_VC0_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG0_MISC_UC_CPL_CFG_FIFO_CREDIT_VC0_UNDERFLOW 29:29 /* RWCVF */ #define NV_XVE_DBG0_MISC_UC_CPL_CFG_FIFO_CREDIT_VC0_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG0_MISC_UC_CPL_CFG_FIFO_CREDIT_VC0_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG0_MISC_UC_CPL_CFG_FIFO_CREDIT_VC0_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG2_MISC 0x000008D8 /* RW-4R */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_PW_OVERFLOW 0:0 /* RWCVF */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_PW_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_PW_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_PW_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_PW_UNDERFLOW 1:1 /* RWCVF */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_PW_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_PW_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_PW_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_NP_OVERFLOW 2:2 /* RWCVF */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_NP_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_NP_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_NP_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_NP_UNDERFLOW 3:3 /* RWCVF */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_NP_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_NP_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG2_MISC_UC_INTF_FN1_VC0_NP_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG2_MISC_UC_HOST_CPL_OVERFLOW 4:4 /* RWCVF */ #define NV_XVE_DBG2_MISC_UC_HOST_CPL_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG2_MISC_UC_HOST_CPL_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG2_MISC_UC_HOST_CPL_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG2_MISC_UC_HOST_CPL_UNDERFLOW 5:5 /* RWCVF */ #define NV_XVE_DBG2_MISC_UC_HOST_CPL_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG2_MISC_UC_HOST_CPL_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG2_MISC_UC_HOST_CPL_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG2_MISC_UC_AZA_CPL_OVERFLOW 6:6 /* RWCVF */ #define NV_XVE_DBG2_MISC_UC_AZA_CPL_OVERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG2_MISC_UC_AZA_CPL_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG2_MISC_UC_AZA_CPL_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG2_MISC_UC_AZA_CPL_UNDERFLOW 7:7 /* RWCVF */ #define NV_XVE_DBG2_MISC_UC_AZA_CPL_UNDERFLOW_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_DBG2_MISC_UC_AZA_CPL_UNDERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_DBG2_MISC_UC_AZA_CPL_UNDERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_DBG3_MISC 0x000008DC /* R--4R */ #define NV_XVE_DBG3_MISC_UC_SPLIT_VC0_CPLH_FULL 0:0 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_SPLIT_VC0_CPLH_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_SPLIT_VC0_CPLH_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_SPLIT_VC0_CPLD_FULL 1:1 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_SPLIT_VC0_CPLD_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_SPLIT_VC0_CPLD_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_PW_FULL 2:2 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_PW_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_PW_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_PW_EMPTY 3:3 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_PW_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_PW_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_NP_FULL 4:4 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_NP_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_NP_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_NP_EMPTY 5:5 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_NP_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_INTF_FN0_VC0_NP_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_DC_CPL_CREDIT_VC0_AVAIL 6:6 /* R-CVF */ #define NV_XVE_DBG3_MISC_DC_CPL_CREDIT_VC0_AVAIL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_DC_CPL_CREDIT_VC0_AVAIL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_HDR_FULL 7:7 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_HDR_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_HDR_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_HDR_EMPTY 8:8 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_HDR_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_HDR_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT_FULL 9:9 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT_EMPTY 10:10 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT2_FULL 11:11 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT2_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT2_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT2_EMPTY 12:12 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT2_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_PW_DAT2_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_NP_HDR_FULL 13:13 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_NP_HDR_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_NP_HDR_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_NP_HDR_EMPTY 14:14 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_NP_HDR_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_BUF_STG2_VC0_NP_HDR_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_DC_CPL_FIFO_VC0_FULL 15:15 /* R-CVF */ #define NV_XVE_DBG3_MISC_DC_CPL_FIFO_VC0_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_DC_CPL_FIFO_VC0_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_DC_CPL_FIFO_VC0_EMPTY 16:16 /* R-CVF */ #define NV_XVE_DBG3_MISC_DC_CPL_FIFO_VC0_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_DC_CPL_FIFO_VC0_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_ARB2_VC0_PW_CREDIT_STALL 17:17 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_ARB2_VC0_PW_CREDIT_STALL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_ARB2_VC0_PW_CREDIT_STALL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG3_MISC_UC_ARB2_VC0_NP_CREDIT_STALL 18:18 /* R-CVF */ #define NV_XVE_DBG3_MISC_UC_ARB2_VC0_NP_CREDIT_STALL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG3_MISC_UC_ARB2_VC0_NP_CREDIT_STALL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG5_MISC 0x000008E4 /* R--4R */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_PW_FULL 0:0 /* R-CVF */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_PW_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_PW_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_PW_EMPTY 1:1 /* R-CVF */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_PW_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_PW_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_NP_FULL 2:2 /* R-CVF */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_NP_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_NP_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_NP_EMPTY 3:3 /* R-CVF */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_NP_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG5_MISC_UC_INTF_FN1_VC0_NP_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG5_MISC_UC_HOST_CPL_EMPTY 4:4 /* R-CVF */ #define NV_XVE_DBG5_MISC_UC_HOST_CPL_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG5_MISC_UC_HOST_CPL_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG5_MISC_UC_HOST_CPL_FULL 5:5 /* R-CVF */ #define NV_XVE_DBG5_MISC_UC_HOST_CPL_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG5_MISC_UC_HOST_CPL_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG5_MISC_UC_AZA_CPL_EMPTY 6:6 /* R-CVF */ #define NV_XVE_DBG5_MISC_UC_AZA_CPL_EMPTY_SET 0x00000001 /* R---V */ #define NV_XVE_DBG5_MISC_UC_AZA_CPL_EMPTY_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_DBG5_MISC_UC_AZA_CPL_FULL 7:7 /* R-CVF */ #define NV_XVE_DBG5_MISC_UC_AZA_CPL_FULL_SET 0x00000001 /* R---V */ #define NV_XVE_DBG5_MISC_UC_AZA_CPL_FULL_NOT_SET 0x00000000 /* R-C-V */ #define NV_XVE_TXB_HBUF_FIFO_LIMIT 0x000008E8 /* RW-4R */ #define NV_XVE_TXB_HBUF_FIFO_LIMIT__PRIV_LEVEL_MASK 0x00000FF0 /* */ #define NV_XVE_TXB_HBUF_FIFO_LIMIT_PW_CP_THREAD_0 5:0 /* RWCVF */ #define NV_XVE_TXB_HBUF_FIFO_LIMIT_PW_CP_THREAD_0_VAL 0x00000010 /* RWC-V */ #define NV_XVE_TXB_HBUF_FIFO_LIMIT_PW_CP_THREAD_1 13:8 /* RWCVF */ #define NV_XVE_TXB_HBUF_FIFO_LIMIT_PW_CP_THREAD_1_VAL 0x00000010 /* RWC-V */ #define NV_XVE_TXB_HBUF_FIFO_LIMIT_NP 20:16 /* RWCVF */ #define NV_XVE_TXB_HBUF_FIFO_LIMIT_NP_VAL 0x00000010 /* RWC-V */ #define NV_XVE_TXB_DBUF_FIFO_LIMIT 0x000008EC /* RW-4R */ #define NV_XVE_TXB_DBUF_FIFO_LIMIT__PRIV_LEVEL_MASK 0x00000FF0 /* */ #define NV_XVE_TXB_DBUF_FIFO_LIMIT_THREAD_0 6:0 /* RWCVF */ #define NV_XVE_TXB_DBUF_FIFO_LIMIT_THREAD_0_VAL 0x00000002 /* RWC-V */ #define NV_XVE_TXB_DBUF_FIFO_LIMIT_THREAD_1 14:8 /* RWCVF */ #define NV_XVE_TXB_DBUF_FIFO_LIMIT_THREAD_1_VAL 0x00000020 /* RWC-V */ #define NV_XVE_TXB_DBUF_FIFO_LIMIT_THREAD_2 22:16 /* RWCVF */ #define NV_XVE_TXB_DBUF_FIFO_LIMIT_THREAD_2_VAL 0x00000020 /* RWC-V */ #define NV_XVE_UC_REQ_FIFO_LIMIT 0x000008F0 /* RW-4R */ #define NV_XVE_UC_REQ_FIFO_LIMIT__PRIV_LEVEL_MASK 0x00000FF0 /* */ #define NV_XVE_UC_REQ_FIFO_LIMIT_PW_HDR 3:0 /* RWCVF */ #define NV_XVE_UC_REQ_FIFO_LIMIT_PW_HDR_VAL 0x00000008 /* RWC-V */ #define NV_XVE_UC_REQ_FIFO_LIMIT_NP_HDR 7:4 /* RWCVF */ #define NV_XVE_UC_REQ_FIFO_LIMIT_NP_HDR_VAL 0x00000008 /* RWC-V */ #define NV_XVE_UC_REQ_FIFO_LIMIT_PW_DAT 11:8 /* RWCVF */ #define NV_XVE_UC_REQ_FIFO_LIMIT_PW_DAT_VAL 0x00000008 /* RWC-V */ #define NV_XVE_UC_REQ_FIFO_LIMIT_PW_DAT2 13:12 /* RWCVF */ #define NV_XVE_UC_REQ_FIFO_LIMIT_PW_DAT2_VAL 0x00000003 /* RWC-V */ #define NV_XVE_SEC_PCIE_CAP_HDR 0x00000900 /* R-I4R */ #define NV_XVE_SEC_PCIE_CAP_HDR_ID 15:0 /* R-IVF */ #define NV_XVE_SEC_PCIE_CAP_HDR_ID_SEC_PCIE 0x00000019 /* R-I-V */ #define NV_XVE_SEC_PCIE_CAP_HDR_ID_NULL 0x00000000 /* R---V */ #define NV_XVE_SEC_PCIE_CAP_HDR_ID_VERSION 19:16 /* R-IVF */ #define NV_XVE_SEC_PCIE_CAP_HDR_ID_VERSION_1 0x00000001 /* R-I-V */ #define NV_XVE_SEC_PCIE_CAP_HDR_ID_NEXT_PTR 31:20 /* R-IVF */ #define NV_XVE_SEC_PCIE_CAP_HDR_ID_NEXT_PTR_RESIZE_CAP 0x00000BB0 /* R-I-V */ #define NV_XVE_SEC_PCIE_CAP_HDR_ID_NEXT_PTR_NONE 0x00000000 /* R---V */ #define NV_XVE_SEC_PCIE_LINK_CONTROL_3 0x00000904 /* C--4R */ #define NV_XVE_SEC_PCIE_LINK_CONTROL_3_PERFORM_EQUALIZATION 0:0 /* C--VF */ #define NV_XVE_SEC_PCIE_LINK_CONTROL_3_PERFORM_EQUALIZATION_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LINK_CONTROL_3_LINK_EQUALIZATION_REQ_INTR_EN 1:1 /* C--VF */ #define NV_XVE_SEC_PCIE_LINK_CONTROL_3_LINK_EQUALIZATION_REQ_INTR_EN_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LINK_CONTROL_3_EN_LOW_SKPOS_GEN_VECTOR 15:9 /* C--VF */ #define NV_XVE_SEC_PCIE_LINK_CONTROL_3_EN_LOW_SKPOS_GEN_VECTOR_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS 0x00000908 /* RW-4R */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE0 0:0 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE0_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE0_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE0_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE1 1:1 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE1_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE1_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE1_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE2 2:2 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE2_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE2_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE2_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE3 3:3 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE3_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE3_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE3_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE4 4:4 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE4_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE4_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE4_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE5 5:5 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE5_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE5_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE5_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE6 6:6 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE6_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE6_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE6_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE7 7:7 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE7_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE7_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE7_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE8 8:8 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE8_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE8_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE8_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE9 9:9 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE9_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE9_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE9_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE10 10:10 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE10_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE10_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE10_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE11 11:11 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE11_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE11_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE11_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE12 12:12 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE12_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE12_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE12_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE13 13:13 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE13_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE13_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE13_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE14 14:14 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE14_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE14_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE14_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE15 15:15 /* RWCVF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE15_ACTIVE 0x00000001 /* R---V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE15_NOT_ACTIVE 0x00000000 /* R-C-V */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_LANE15_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_RSVD 31:16 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_ERROR_STATUS_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL(i) (0x0000090C+(i)*4) /* R--4A */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL__SIZE_1 8 /* */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_UP_TX_PRESET 3:0 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_UP_TX_PRESET_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_UP_RX_PRESET_HINT 6:4 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_UP_RX_PRESET_HINT_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_RSVD_0 7:7 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_RSVD_0_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_DWN_TX_PRESET 11:8 /* R-EVF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_DWN_TX_PRESET_INIT 0x0000000F /* R-E-V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_DWN_RX_PRESET_HINT 14:12 /* R-EVF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_DWN_RX_PRESET_HINT_INIT 0x00000007 /* R-E-V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_RSVD_1 15:15 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_0_RSVD_1_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_UP_TX_PRESET 19:16 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_UP_TX_PRESET_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_UP_RX_PRESET_HINT 22:20 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_UP_RX_PRESET_HINT_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_RSVD_0 23:23 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_RSVD_0_INIT 0x00000000 /* C---V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_DWN_TX_PRESET 27:24 /* R-EVF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_DWN_TX_PRESET_INIT 0x0000000F /* R-E-V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_DWN_RX_PRESET_HINT 30:28 /* R-EVF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_DWN_RX_PRESET_HINT_INIT 0x00000007 /* R-E-V */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_RSVD_1 31:31 /* C--VF */ #define NV_XVE_SEC_PCIE_LANE_EQUALIZATION_CTRL_1_RSVD_1_INIT 0x00000000 /* C---V */ #define NV_XVE_BAR_BLOCKER 0x0000092C /* RW-4R */ #define NV_XVE_BAR_BLOCKER__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_CTRL_BLOCKER_MODE 1:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CTRL_BLOCKER_MODE_BLOCK_NOTHING 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CTRL_BLOCKER_MODE_BLOCK_EQUATION 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CTRL_BLOCKER_MODE_BLOCK_EVERYTHING 0x00000003 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CTRL_BLOCKER_MODE_OVERWRITE 2:2 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CTRL_BLOCKER_MODE_OVERWRITE_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_CTRL_BLOCKER_MODE_OVERWRITE_ENABLED 0x00000001 /* -W--V */ #define NV_XVE_BAR_BLOCKER_CTRL_BLOCKER_MODE_OVERWRITE_DISABLED 0x00000000 /* -W--V */ #define NV_XVE_BAR_BLOCKER_INTR_ACK 4:4 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_INTR_ACK_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_INTR_ACK_ISSUED 0x00000001 /* -W--V */ #define NV_XVE_BAR_BLOCKER_INTR_ACK_NOP 0x00000000 /* -W--V */ #define NV_XVE_BAR_BLOCKER_INTR_STAT 5:5 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_INTR_STAT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_INTR_STAT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_INTR_STAT_RESET 0x00000001 /* -W--C */ #define NV_XVE_BAR_BLOCKER_INTR_OVERRIDE_VAL 6:6 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_INTR_OVERRIDE_VAL_ASSERT 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_INTR_OVERRIDE_VAL_NOOP 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_ACK 7:7 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_INTR_ACK_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_ACK_ISSUED 0x00000001 /* -W--V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_ACK_NOP 0x00000000 /* -W--V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_STAT 8:8 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_INTR_STAT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_STAT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_STAT_RESET 0x00000001 /* -W--C */ #define NV_XVE_BAR_BLOCKER_GR_INTR_OVERRIDE_VAL 9:9 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_INTR_OVERRIDE_VAL_ASSERT 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_OVERRIDE_VAL_NOOP 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_PROFILE 10:10 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_PROFILE_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_PROFILE_DISABLE 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_PROFILE 11:11 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_PROFILE_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_PROFILE_DISABLE 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_FLUSH_CTRL 0x00000930 /* RW-4R */ #define NV_XVE_BAR_BLOCKER_FLUSH_CTRL__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_FLUSH_CTRL_WR_CMD 0:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_FLUSH_CTRL_WR_CMD_CLEAR 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_FLUSH_CTRL_WR_CMD_TRIGGER 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_FLUSH_WR_ADDR 0x00000934 /* RW-4R */ #define NV_XVE_BAR_BLOCKER_FLUSH_WR_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_FLUSH_WR_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_FLUSH_WR_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_FLUSH_WR_DATA 0x00000938 /* RW-4R */ #define NV_XVE_BAR_BLOCKER_FLUSH_WR_DATA__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_FLUSH_WR_DATA_DATA 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_FLUSH_WR_DATA_DATA_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_WAKE_ADDR_LO 0x0000093C /* R--4R */ #define NV_XVE_BAR_BLOCKER_WAKE_ADDR_LO__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_WAKE_ADDR_LO_ADDR 31:0 /* R-IVF */ #define NV_XVE_BAR_BLOCKER_WAKE_ADDR_LO_ADDR_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_WAKE_ADDR_HI 0x00000940 /* R--4R */ #define NV_XVE_BAR_BLOCKER_WAKE_ADDR_HI__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_WAKE_ADDR_HI_ADDR 31:0 /* R-IVF */ #define NV_XVE_BAR_BLOCKER_WAKE_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR 0x00000944 /* R--4R */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_CMD_TYPE 0:0 /* R-IVF */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_CMD_TYPE_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_CMD_TYPE_WR 0x00000001 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_CMD_TYPE_RD 0x00000000 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_BAR_TYPE 3:1 /* R-IVF */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_BAR_TYPE_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_BAR_TYPE_BAR0 0x00000001 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_BAR_TYPE_BAR1 0x00000002 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_BAR_TYPE_BAR2 0x00000003 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_BAR_TYPE_BAR3 0x00000004 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_BAR_TYPE_VGAIO 0x00000005 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_BAR_TYPE_VGAMEM 0x00000006 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_FN_TYPE 4:4 /* R-IVF */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_FN_TYPE_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_FN_TYPE_FN0 0x00000000 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_FN_TYPE_FN1 0x00000001 /* R---V */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_GFID 10:5 /* R-IVF */ #define NV_XVE_BAR_BLOCKER_WAKE_ATTR_GFID_INIT 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_CYA 0x00000948 /* RW-4R */ #define NV_XVE_BAR_BLOCKER_CYA__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_XVE 0:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_XVE_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_XVE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_XVE_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_HOST 1:1 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_HOST_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_HOST_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_HOST_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_DISPLAY 2:2 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_DISPLAY_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_DISPLAY_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_DISPLAY_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PMU 3:3 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PMU_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PMU_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PMU_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PERF 4:4 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PERF_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PERF_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PERF_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_FUSE 5:5 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_FUSE_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_FUSE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_FUSE_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PMGR 6:6 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PMGR_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PMGR_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_PMGR_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_AUDIO 7:7 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_AUDIO_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_AUDIO_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_AUDIO_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_GR 8:8 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_GR_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_GR_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_GR_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_UNIT_IDX(i) (i):(i) /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_UNIT_IDX__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_UNIT_IDX_ENABLED 1 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_UNIT_IDX_DISABLED 0 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX 4:0 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX_XVE 0 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX_HOST 1 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX_DISPLAY 2 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX_PMU 3 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX_PERF 4 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX_FUSE 5 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX_PMGR 6 /* */ #define NV_XVE_BAR_BLOCKER_CYA_NAMEMAP_INDEX_AUDIO 7 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE0 16:16 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE0_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE0_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE0_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE1 17:17 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE1_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE1_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE1_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE2 18:18 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE2_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE2_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE2_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE3 19:19 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE3_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE3_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE3_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE4 20:20 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE4_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE4_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE4_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE5 21:21 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE5_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE5_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE5_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE6 22:22 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE6_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE6_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE6_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE7 23:23 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE7_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE7_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE7_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_IDX(i) ((i)+16):((i)+16) /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_IDX__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_IDX_ENABLED 1 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_IDX_DISABLED 0 /* */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE0 24:24 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE0_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE0_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE0_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE1 25:25 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE1_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE1_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE1_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE2 26:26 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE2_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE2_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE2_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE3 27:27 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE3_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE3_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE3_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE4 28:28 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE4_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE4_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE4_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE5 29:29 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE5_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE5_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE5_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE6 30:30 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE6_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE6_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE6_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE7 31:31 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE7_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE7_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE7_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_IDX(i) ((i)+24):((i)+24) /* */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_IDX__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_IDX_ENABLED 1 /* */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_IDX_DISABLED 0 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_START_ADDR(i) (0x0000094C+(i)*8) /* RW-4A */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_START_ADDR__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_START_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_START_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_START_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_END_ADDR(i) (0x00000950+(i)*8) /* RW-4A */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_END_ADDR__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_END_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_END_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_ALLOW_RANGE_END_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_START_ADDR(i) (0x0000098C+(i)*8) /* RW-4A */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_START_ADDR__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_START_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_START_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_START_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_END_ADDR(i) (0x00000990+(i)*8) /* RW-4A */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_END_ADDR__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_END_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_END_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_CYA_DISALLOW_RANGE_END_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT 0x000009CC /* RW-4R */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_EN 0:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_STAT 1:1 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_STAT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_STAT_PENDING 0x00000001 /* R---V */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_STAT_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_VAL 31:16 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_VAL_INIT 0x000001F4 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_VAL_100US 0x00000064 /* RW--V */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_VAL_500US 0x000001F4 /* RW--V */ #define NV_XVE_BAR_BLOCKER_INTR_TIMEOUT_VAL_1000US 0x000003E8 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF 0x000009D4 /* RW-4R */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE0_ALLOW 0:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE0_ALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE0_ALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE1_ALLOW 1:1 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE1_ALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE1_ALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE2_ALLOW 2:2 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE2_ALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE2_ALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE3_ALLOW 3:3 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE3_ALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE3_ALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE4_ALLOW 4:4 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE4_ALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE4_ALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE5_ALLOW 5:5 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE5_ALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE5_ALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE6_ALLOW 6:6 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE6_ALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE6_ALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE7_ALLOW 7:7 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE7_ALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE7_ALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE0_DISALLOW 8:8 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE0_DISALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE0_DISALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE1_DISALLOW 9:9 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE1_DISALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE1_DISALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE2_DISALLOW 10:10 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE2_DISALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE2_DISALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE3_DISALLOW 11:11 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE3_DISALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE3_DISALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE4_DISALLOW 12:12 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE4_DISALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE4_DISALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE5_DISALLOW 13:13 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE5_DISALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE5_DISALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE6_DISALLOW 14:14 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE6_DISALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE6_DISALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE7_DISALLOW 15:15 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE7_DISALLOW_EN 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_MS_CYA_FOR_VF_RANGE7_DISALLOW_DIS 0x00000000 /* RWI-V */ #define NV_XVE_CYA_SHDW_BAR1_CTRL 0x00000A00 /* RW-4R */ #define NV_XVE_CYA_SHDW_BAR1_CTRL_VAL 4:0 /* RWCVF */ #define NV_XVE_CYA_SHDW_BAR1_CTRL_VAL_256MB 0x00000008 /* RWC-V */ #define NV_XVE_CYA_SHDW_BAR1_CTRL_RSVD 31:5 /* C--VF */ #define NV_XVE_CYA_SHDW_BAR1_CTRL_RSVD_VAL 0x00000000 /* C---V */ #define NV_XVE_FLT2_MASK 0x00000A04 /* C--4R */ #define NV_XVE_FLT2_MASK_RSVD 31:0 /* C--VF */ #define NV_XVE_FLT2_MASK_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_UC_STARVATION 0x00000A08 /* RW-4R */ #define NV_XVE_UC_STARVATION__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_UC_STARVATION_P2P_CPL_STARVATION_TIMER 15:1 /* RWCVF */ #define NV_XVE_UC_STARVATION_P2P_CPL_STARVATION_TIMER_INIT 0x00000200 /* RWC-V */ #define NV_XVE_UC_STARVATION_P2P_PW_STARVATION_TIMER 31:17 /* RWCVF */ #define NV_XVE_UC_STARVATION_P2P_PW_STARVATION_TIMER_INIT 0x00000200 /* RWC-V */ #define NV_XVE_LTR_FB_BW_MON_CTRL 0x00000A0C /* RW-4R */ #define NV_XVE_LTR_FB_BW_MON_CTRL_INTERVAL_VALUE 15:0 /* RWCVF */ #define NV_XVE_LTR_FB_BW_MON_CTRL_INTERVAL_VALUE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_FB_BW_MON_CTRL_THRESHOLD 30:16 /* RWCVF */ #define NV_XVE_LTR_FB_BW_MON_CTRL_THRESHOLD_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_FB_BW_MON_CTRL_ENABLE 31:31 /* RWCVF */ #define NV_XVE_LTR_FB_BW_MON_CTRL_ENABLE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_HIGH_LATENCY 0x00000A10 /* RW-4R */ #define NV_XVE_LTR_HIGH_LATENCY_SNOOP_LATENCY_VALUE 9:0 /* RWCVF */ #define NV_XVE_LTR_HIGH_LATENCY_SNOOP_LATENCY_VALUE_INIT 0x000000FA /* RWC-V */ #define NV_XVE_LTR_HIGH_LATENCY_SNOOP_LATENCY_SCALE 12:10 /* RWCVF */ #define NV_XVE_LTR_HIGH_LATENCY_SNOOP_LATENCY_SCALE_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_HIGH_LATENCY_NO_SNOOP_LATENCY_VALUE 25:16 /* RWCVF */ #define NV_XVE_LTR_HIGH_LATENCY_NO_SNOOP_LATENCY_VALUE_INIT 0x000000FA /* RWC-V */ #define NV_XVE_LTR_HIGH_LATENCY_NO_SNOOP_LATENCY_SCALE 28:26 /* RWCVF */ #define NV_XVE_LTR_HIGH_LATENCY_NO_SNOOP_LATENCY_SCALE_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_LOW_LATENCY 0x00000A14 /* RW-4R */ #define NV_XVE_LTR_LOW_LATENCY_SNOOP_LATENCY_VALUE 9:0 /* RWCVF */ #define NV_XVE_LTR_LOW_LATENCY_SNOOP_LATENCY_VALUE_INIT 0x000000FA /* RWC-V */ #define NV_XVE_LTR_LOW_LATENCY_SNOOP_LATENCY_SCALE 12:10 /* RWCVF */ #define NV_XVE_LTR_LOW_LATENCY_SNOOP_LATENCY_SCALE_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_LOW_LATENCY_NO_SNOOP_LATENCY_VALUE 25:16 /* RWCVF */ #define NV_XVE_LTR_LOW_LATENCY_NO_SNOOP_LATENCY_VALUE_INIT 0x000000FA /* RWC-V */ #define NV_XVE_LTR_LOW_LATENCY_NO_SNOOP_LATENCY_SCALE 28:26 /* RWCVF */ #define NV_XVE_LTR_LOW_LATENCY_NO_SNOOP_LATENCY_SCALE_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_LATENCY_REQUIREMENT 0x00000A18 /* RW-4R */ #define NV_XVE_LTR_LATENCY_REQUIREMENT_GPU_SNOOP 0:0 /* RWCVF */ #define NV_XVE_LTR_LATENCY_REQUIREMENT_GPU_SNOOP_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_LATENCY_REQUIREMENT_GPU_NO_SNOOP 1:1 /* RWCVF */ #define NV_XVE_LTR_LATENCY_REQUIREMENT_GPU_NO_SNOOP_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_LATENCY_REQUIREMENT_AZA_SNOOP 2:2 /* RWCVF */ #define NV_XVE_LTR_LATENCY_REQUIREMENT_AZA_SNOOP_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_LATENCY_REQUIREMENT_AZA_NO_SNOOP 3:3 /* RWCVF */ #define NV_XVE_LTR_LATENCY_REQUIREMENT_AZA_NO_SNOOP_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_AZA_BW_MON_CTRL 0x00000A1C /* RW-4R */ #define NV_XVE_LTR_AZA_BW_MON_CTRL_INTERVAL_VALUE 15:0 /* RWCVF */ #define NV_XVE_LTR_AZA_BW_MON_CTRL_INTERVAL_VALUE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_AZA_BW_MON_CTRL_THRESHOLD 30:16 /* RWCVF */ #define NV_XVE_LTR_AZA_BW_MON_CTRL_THRESHOLD_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_AZA_BW_MON_CTRL_ENABLE 31:31 /* RWCVF */ #define NV_XVE_LTR_AZA_BW_MON_CTRL_ENABLE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_MSG_CTRL 0x00000A20 /* RW-4R */ #define NV_XVE_LTR_MSG_CTRL_TRIGGER 0:0 /* RWCVF */ #define NV_XVE_LTR_MSG_CTRL_TRIGGER_NOT_PENDING 0x00000000 /* RWC-V */ #define NV_XVE_LTR_MSG_CTRL_TRIGGER_PENDING 0x00000001 /* RW--V */ #define NV_XVE_LTR_MSG_CTRL_HIDE_LTR 8:8 /* RWCVF */ #define NV_XVE_LTR_MSG_CTRL_HIDE_LTR_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_MSG_CTRL_D_STATE_CTRL 9:9 /* RWCVF */ #define NV_XVE_LTR_MSG_CTRL_D_STATE_CTRL_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_MSG_CTRL_NO_MSG_ON_LTR_EN 10:10 /* RWCVF */ #define NV_XVE_LTR_MSG_CTRL_NO_MSG_ON_LTR_EN_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_LAST_MSG_SENT 0x00000A24 /* R--4R */ #define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_VALUE 9:0 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_VALUE_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_SCALE 12:10 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_SCALE_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_REQUIREMENT 13:13 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_REQUIREMENT_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_VALUE 23:14 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_VALUE_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_SCALE 26:24 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_SCALE_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_REQUIREMENT 27:27 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_REQUIREMENT_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_D_STATE_TRIGGERED 28:28 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_D_STATE_TRIGGERED_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_SW_TRIGGERED 29:29 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_SW_TRIGGERED_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_FB_BW_TRIGGERED 30:30 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_FB_BW_TRIGGERED_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_LAST_MSG_SENT_AZA_BW_TRIGGERED 31:31 /* R-CVF */ #define NV_XVE_LTR_LAST_MSG_SENT_AZA_BW_TRIGGERED_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_NUM_MSG_SENT 0x00000A28 /* RW-4R */ #define NV_XVE_LTR_NUM_MSG_SENT_INTERVAL 15:0 /* RWCVF */ #define NV_XVE_LTR_NUM_MSG_SENT_INTERVAL_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_D_STATE_TRIGGER 16:16 /* RWCVF */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_D_STATE_TRIGGER_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_SW_TRIGGER 17:17 /* RWCVF */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_SW_TRIGGER_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_FB_BW_TRIGGER 18:18 /* RWCVF */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_FB_BW_TRIGGER_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_AZA_BW_TRIGGER 19:19 /* RWCVF */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_AZA_BW_TRIGGER_INIT 0x00000000 /* RWC-V */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT 29:20 /* R-CVF */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_INIT 0x00000000 /* R-C-V */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_DONE 31:31 /* RWCVF */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_DONE_INIT 0x00000001 /* RWC-V */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_DONE_SET 0x00000001 /* RW--V */ #define NV_XVE_LTR_NUM_MSG_SENT_COUNT_DONE_CLEAR 0x00000000 /* RW--V */ #define NV_XVE_SW_MSG_HDR_DW0 0x00000A2C /* RW-4R */ #define NV_XVE_SW_MSG_HDR_DW0_LENGTH 9:0 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_LENGTH_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_ATTR 11:10 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_ATTR_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_EP 12:12 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_EP_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_TD 13:13 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_TD_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_TH 14:14 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_TH_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_ATTR_2 15:15 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_ATTR_2_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_TC 18:16 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_TC_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_TYPE 23:19 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_TYPE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_FORMAT 25:24 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW0_FORMAT_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW0_RSVD 31:26 /* C--VF */ #define NV_XVE_SW_MSG_HDR_DW0_RSVD_0 0x00000000 /* C---V */ #define NV_XVE_SW_MSG_HDR_DW1 0x00000A30 /* RW-4R */ #define NV_XVE_SW_MSG_HDR_DW1_MSG_TYPE 7:0 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW1_MSG_TYPE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW1_TAG 15:8 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW1_TAG_0 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW1_REQ_ID_FN_NO 18:16 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW1_REQ_ID_FN_NO_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW1_REQ_ID_DEV_NO 23:19 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW1_REQ_ID_DEV_NO_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW1_REQ_ID_BUS_NO 31:24 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW1_REQ_ID_BUS_NO_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW2 0x00000A34 /* RW-4R */ #define NV_XVE_SW_MSG_HDR_DW2_DATA 31:0 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW2_DATA_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_HDR_DW3 0x00000A38 /* RW-4R */ #define NV_XVE_SW_MSG_HDR_DW3_DATA 31:0 /* RWCVF */ #define NV_XVE_SW_MSG_HDR_DW3_DATA_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_DATA 0x00000A3C /* RW-4R */ #define NV_XVE_SW_MSG_DATA_DATA 31:0 /* RWCVF */ #define NV_XVE_SW_MSG_DATA_DATA_INIT 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_CTRL 0x00000A40 /* RW-4R */ #define NV_XVE_SW_MSG_CTRL__PRIV_LEVEL_MASK 0x00000FE8 /* */ #define NV_XVE_SW_MSG_CTRL_TRIGGER 0:0 /* RWCVF */ #define NV_XVE_SW_MSG_CTRL_TRIGGER_TRIGGER 0x00000001 /* RW--T */ #define NV_XVE_SW_MSG_CTRL_TRIGGER_NOT_PENDING 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_CTRL_TRIGGER_PENDING 0x00000001 /* RW--V */ #define NV_XVE_SW_MSG_CTRL_REQ_ID_OVERRIDE 1:1 /* RWCVF */ #define NV_XVE_SW_MSG_CTRL_REQ_ID_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_SW_MSG_CTRL_REQ_ID_OVERRIDE_DISABLE 0x00000000 /* RWC-V */ #define NV_XVE_SW_MSG_CTRL_RSVD 31:2 /* C--VF */ #define NV_XVE_SW_MSG_CTRL_RSVD_0 0x00000000 /* C---V */ #define NV_XVE_PCIE_UTIL_CTRL 0x00000A44 /* RW-4R */ #define NV_XVE_PCIE_UTIL_CTRL_ENABLE 0:0 /* RWCVF */ #define NV_XVE_PCIE_UTIL_CTRL_ENABLE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_BYTES_COUNT 1:1 /* RWCVF */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_BYTES_COUNT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_BYTES_COUNT_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_BYTES_COUNT 2:2 /* RWCVF */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_BYTES_COUNT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_BYTES_COUNT_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0_COUNT 3:3 /* RWCVF */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0_COUNT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0_COUNT_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0_COUNT 4:4 /* RWCVF */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0_COUNT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0_COUNT_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0S_COUNT 5:5 /* RWCVF */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0S_COUNT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0S_COUNT_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0S_COUNT 6:6 /* RWCVF */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0S_COUNT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0S_COUNT_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_NON_L0_L0S_COUNT 7:7 /* RWCVF */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_NON_L0_L0S_COUNT_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_CTRL_RESET_NON_L0_L0S_COUNT_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_TX_BYTES 0x00000A48 /* RW-4R */ #define NV_XVE_PCIE_UTIL_TX_BYTES_COUNT 30:0 /* R--VF */ #define NV_XVE_PCIE_UTIL_TX_BYTES_COUNT_WRAP_STATUS 31:31 /* RWCVF */ #define NV_XVE_PCIE_UTIL_TX_BYTES_COUNT_WRAP_STATUS_CLR_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_TX_BYTES_COUNT_WRAP_STATUS_CLR_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_RX_BYTES 0x00000A4C /* RW-4R */ #define NV_XVE_PCIE_UTIL_RX_BYTES_COUNT 30:0 /* R--VF */ #define NV_XVE_PCIE_UTIL_RX_BYTES_COUNT_WRAP_STATUS 31:31 /* RWCVF */ #define NV_XVE_PCIE_UTIL_RX_BYTES_COUNT_WRAP_STATUS_CLR_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_RX_BYTES_COUNT_WRAP_STATUS_CLR_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_TX_L0 0x00000A50 /* RW-4R */ #define NV_XVE_PCIE_UTIL_TX_L0_COUNT 30:0 /* R--VF */ #define NV_XVE_PCIE_UTIL_TX_L0_COUNT_WRAP_STATUS 31:31 /* RWCVF */ #define NV_XVE_PCIE_UTIL_TX_L0_COUNT_WRAP_STATUS_CLR_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_TX_L0_COUNT_WRAP_STATUS_CLR_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_RX_L0 0x00000A54 /* RW-4R */ #define NV_XVE_PCIE_UTIL_RX_L0_COUNT 30:0 /* R--VF */ #define NV_XVE_PCIE_UTIL_RX_L0_COUNT_WRAP_STATUS 31:31 /* RWCVF */ #define NV_XVE_PCIE_UTIL_RX_L0_COUNT_WRAP_STATUS_CLR_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_RX_L0_COUNT_WRAP_STATUS_CLR_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_TX_L0S 0x00000A58 /* RW-4R */ #define NV_XVE_PCIE_UTIL_TX_L0S_COUNT 30:0 /* R--VF */ #define NV_XVE_PCIE_UTIL_TX_L0S_COUNT_WRAP_STATUS 31:31 /* RWCVF */ #define NV_XVE_PCIE_UTIL_TX_L0S_COUNT_WRAP_STATUS_CLR_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_TX_L0S_COUNT_WRAP_STATUS_CLR_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_RX_L0S 0x00000A60 /* RW-4R */ #define NV_XVE_PCIE_UTIL_RX_L0S_COUNT 30:0 /* R--VF */ #define NV_XVE_PCIE_UTIL_RX_L0S_COUNT_WRAP_STATUS 31:31 /* RWCVF */ #define NV_XVE_PCIE_UTIL_RX_L0S_COUNT_WRAP_STATUS_CLR_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_RX_L0S_COUNT_WRAP_STATUS_CLR_DONE 0x00000000 /* RWC-V */ #define NV_XVE_PCIE_UTIL_NON_L0_L0S 0x00000A64 /* RW-4R */ #define NV_XVE_PCIE_UTIL_NON_L0_L0S_COUNT 30:0 /* R--VF */ #define NV_XVE_PCIE_UTIL_NON_L0_L0S_COUNT_WRAP_STATUS 31:31 /* RWCVF */ #define NV_XVE_PCIE_UTIL_NON_L0_L0S_COUNT_WRAP_STATUS_CLR_PENDING 0x00000001 /* RW--V */ #define NV_XVE_PCIE_UTIL_NON_L0_L0S_COUNT_WRAP_STATUS_CLR_DONE 0x00000000 /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA 0x00000A68 /* RW-4R */ #define NV_XVE_L1_PM_SUBSTATES_CYA__PRIV_LEVEL_MASK 0x00000EDC /* */ #define NV_XVE_L1_PM_SUBSTATES_CYA_PCI_PM_L1_2 0:0 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_PCI_PM_L1_2_SUPPORTED 0x00000001 /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_PCI_PM_L1_2_NOT_SUPPORTED 0x00000000 /* RW--V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_PCI_PM_L1_1 1:1 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_PCI_PM_L1_1_SUPPORTED 0x00000001 /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_PCI_PM_L1_1_NOT_SUPPORTED 0x00000000 /* RW--V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_ASPM_L1_2 2:2 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_ASPM_L1_2_SUPPORTED 0x00000001 /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_ASPM_L1_2_NOT_SUPPORTED 0x00000000 /* RW--V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_ASPM_L1_1 3:3 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_ASPM_L1_1_SUPPORTED 0x00000001 /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_ASPM_L1_1_NOT_SUPPORTED 0x00000000 /* RW--V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_L1_PM_SUBSTATES 4:4 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_L1_PM_SUBSTATES_SUPPORTED 0x00000001 /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_L1_PM_SUBSTATES_NOT_SUPPORTED 0x00000000 /* RW--V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_CM_RESTORE_TIME 15:8 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_CM_RESTORE_TIME_INIT 0x000000FF /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_T_PWRON_SCALE 17:16 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_T_PWRON_SCALE_INIT 0x00000000 /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_T_PWRON_VALUE 23:19 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_T_PWRON_VALUE_INIT 0x00000005 /* RWC-V */ #define NV_XVE_L1_PM_SUBSTATES_CYA_HIDE_CAP 24:24 /* RWCVF */ #define NV_XVE_L1_PM_SUBSTATES_CYA_HIDE_CAP_INIT 0x00000000 /* RWC-V */ #define NV_XVE_PRIV_UC_ARB1_WLRU_NP_WEIGHT 0x00000A6C /* RW-4R */ #define NV_XVE_PRIV_UC_ARB1_WLRU_NP_WEIGHT__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_UC_ARB1_WLRU_NP_WEIGHT_CHANNEL0 4:0 /* RWCVF */ #define NV_XVE_PRIV_UC_ARB1_WLRU_NP_WEIGHT_CHANNEL0_DEFAULT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_UC_ARB1_WLRU_NP_WEIGHT_CHANNEL1 9:5 /* RWCVF */ #define NV_XVE_PRIV_UC_ARB1_WLRU_NP_WEIGHT_CHANNEL1_DEFAULT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_UC_ARB1_WLRU_PW_WEIGHT 0x00000A70 /* RW-4R */ #define NV_XVE_PRIV_UC_ARB1_WLRU_PW_WEIGHT__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_UC_ARB1_WLRU_PW_WEIGHT_CHANNEL0 4:0 /* RWCVF */ #define NV_XVE_PRIV_UC_ARB1_WLRU_PW_WEIGHT_CHANNEL0_DEFAULT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_UC_ARB1_WLRU_PW_WEIGHT_CHANNEL1 9:5 /* RWCVF */ #define NV_XVE_PRIV_UC_ARB1_WLRU_PW_WEIGHT_CHANNEL1_DEFAULT 0x00000001 /* RWC-V */ #define NV_XVE_PRIV_NANOSECOND_XCLK 0x00000A74 /* RW-4R */ #define NV_XVE_PRIV_NANOSECOND_XCLK__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_PRIV_NANOSECOND_XCLK_ALT 6:0 /* RWCVF */ #define NV_XVE_PRIV_NANOSECOND_XCLK_ALT_27 0x00000025 /* RWC-V */ #define NV_XVE_PRIV_NANOSECOND_XCLK_OVERRIDE_VAL 13:7 /* RWCVF */ #define NV_XVE_PRIV_NANOSECOND_XCLK_OVERRIDE_VAL_100 0x0000000A /* RW--V */ #define NV_XVE_PRIV_NANOSECOND_XCLK_OVERRIDE_VAL_125 0x00000008 /* RW--V */ #define NV_XVE_PRIV_NANOSECOND_XCLK_OVERRIDE_VAL_250 0x00000004 /* RW--V */ #define NV_XVE_PRIV_NANOSECOND_XCLK_OVERRIDE_VAL_500 0x00000002 /* RW--V */ #define NV_XVE_PRIV_NANOSECOND_XCLK_OVERRIDE_VAL_1000 0x00000001 /* RWC-V */ #define NV_XVE_BUBBLE_WIDTH_FN0_NP 0x00000A78 /* RW-4R */ #define NV_XVE_BUBBLE_WIDTH_FN0_NP_VAL 20:0 /* RWIVF */ #define NV_XVE_BUBBLE_WIDTH_FN0_NP_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_WIDTH_FN0_PW 0x00000A7C /* RW-4R */ #define NV_XVE_BUBBLE_WIDTH_FN0_PW_VAL 20:0 /* RWIVF */ #define NV_XVE_BUBBLE_WIDTH_FN0_PW_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_NP 0x00000A80 /* RW-4R */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_NP_CNT_HDR_ONLY 0:0 /* RWIVF */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_NP_CNT_HDR_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_NP_VAL 23:1 /* RWIVF */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_NP_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_PW 0x00000A84 /* RW-4R */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_PW_CNT_HDR_ONLY 0:0 /* RWIVF */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_PW_CNT_HDR_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_PW_VAL 23:1 /* RWIVF */ #define NV_XVE_BUBBLE_THRESHOLD_FN0_PW_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_FN0 0x00000A88 /* RW-4R */ #define NV_XVE_BUBBLE_CTRL_FN0_NP_INTERVAL 10:0 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_FN0_NP_INTERVAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_FN0_PW_INTERVAL 26:16 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_FN0_PW_INTERVAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_WIDTH_FN1_NP 0x00000A8C /* RW-4R */ #define NV_XVE_BUBBLE_WIDTH_FN1_NP_VAL 20:0 /* RWIVF */ #define NV_XVE_BUBBLE_WIDTH_FN1_NP_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_WIDTH_FN1_PW 0x00000A90 /* RW-4R */ #define NV_XVE_BUBBLE_WIDTH_FN1_PW_VAL 20:0 /* RWIVF */ #define NV_XVE_BUBBLE_WIDTH_FN1_PW_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_NP 0x00000A94 /* RW-4R */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_NP_CNT_HDR_ONLY 0:0 /* RWIVF */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_NP_CNT_HDR_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_NP_VAL 23:1 /* RWIVF */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_NP_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_PW 0x00000A98 /* RW-4R */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_PW_CNT_HDR_ONLY 0:0 /* RWIVF */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_PW_CNT_HDR_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_PW_VAL 23:1 /* RWIVF */ #define NV_XVE_BUBBLE_THRESHOLD_FN1_PW_VAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_FN1 0x00000A9C /* RW-4R */ #define NV_XVE_BUBBLE_CTRL_FN1_NP_INTERVAL 10:0 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_FN1_NP_INTERVAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_FN1_PW_INTERVAL 26:16 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_FN1_PW_INTERVAL_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL 0x00000AA0 /* RW-4R */ #define NV_XVE_BUBBLE_CTRL_FN0_NP_EN 0:0 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_FN0_NP_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_FN0_NP_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_FN0_NP_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_FN0_PW_EN 1:1 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_FN0_PW_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_FN0_PW_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_FN0_PW_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_FN1_NP_EN 2:2 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_FN1_NP_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_FN1_NP_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_FN1_NP_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_FN1_PW_EN 3:3 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_FN1_PW_EN_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_FN1_PW_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_FN1_PW_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_P2P_CPL_EN 4:4 /* RWIVF */ #define NV_XVE_BUBBLE_CTRL_P2P_CPL_EN_INIT 0x00000001 /* RWI-V */ #define NV_XVE_BUBBLE_CTRL_P2P_CPL_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BUBBLE_CTRL_P2P_CPL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN0_NP 0x00000AA4 /* RW-4R */ #define NV_XVE_STARVATION_COUNTER_FN0_NP__PRIV_LEVEL_MASK 0x00000FF0 /* */ #define NV_XVE_STARVATION_COUNTER_FN0_NP_EN 0:0 /* RWCVF */ #define NV_XVE_STARVATION_COUNTER_FN0_NP_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_STARVATION_COUNTER_FN0_NP_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN0_NP_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN0_NP_MAX_LATENCY 20:1 /* R--VF */ #define NV_XVE_STARVATION_COUNTER_FN0_PW 0x00000AA8 /* RW-4R */ #define NV_XVE_STARVATION_COUNTER_FN0_PW__PRIV_LEVEL_MASK 0x00000FF0 /* */ #define NV_XVE_STARVATION_COUNTER_FN0_PW_EN 0:0 /* RWCVF */ #define NV_XVE_STARVATION_COUNTER_FN0_PW_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_STARVATION_COUNTER_FN0_PW_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN0_PW_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN0_PW_MAX_LATENCY 20:1 /* R--VF */ #define NV_XVE_STARVATION_COUNTER_FN1_NP 0x00000AAC /* RW-4R */ #define NV_XVE_STARVATION_COUNTER_FN1_NP__PRIV_LEVEL_MASK 0x00000FF0 /* */ #define NV_XVE_STARVATION_COUNTER_FN1_NP_EN 0:0 /* RWCVF */ #define NV_XVE_STARVATION_COUNTER_FN1_NP_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_STARVATION_COUNTER_FN1_NP_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN1_NP_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN1_NP_MAX_LATENCY 20:1 /* R--VF */ #define NV_XVE_STARVATION_COUNTER_FN1_PW 0x00000AB0 /* RW-4R */ #define NV_XVE_STARVATION_COUNTER_FN1_PW__PRIV_LEVEL_MASK 0x00000FF0 /* */ #define NV_XVE_STARVATION_COUNTER_FN1_PW_EN 0:0 /* RWCVF */ #define NV_XVE_STARVATION_COUNTER_FN1_PW_EN_INIT 0x00000000 /* RWC-V */ #define NV_XVE_STARVATION_COUNTER_FN1_PW_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN1_PW_EN_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_STARVATION_COUNTER_FN1_PW_MAX_LATENCY 20:1 /* R--VF */ #define NV_XVE_RTD3 0x00000AB8 /* RW-4R */ #define NV_XVE_RTD3_PME_TURNOFF_RCVD 0:0 /* RWCVF */ #define NV_XVE_RTD3_PME_TURNOFF_RCVD_NOT_PENDING 0x00000000 /* R-C-V */ #define NV_XVE_RTD3_PME_TURNOFF_RCVD_PENDING 0x00000001 /* R---V */ #define NV_XVE_RTD3_PME_TURNOFF_RCVD_RESET 0x00000001 /* -W--C */ #define NV_XVE_RTD3_DISABLE_PME_TO_ACK 16:16 /* RWCVF */ #define NV_XVE_RTD3_DISABLE_PME_TO_ACK_UNSET 0x00000000 /* RWC-V */ #define NV_XVE_RTD3_DISABLE_PME_TO_ACK_SET 0x00000001 /* RW--V */ #define NV_XVE_RTD3_FN0_PME_FSM_STATE 18:17 /* R--VF */ #define NV_XVE_RTD3_FN0_PME_FSM_STATE_PME_IDLE 0x00000000 /* R---V */ #define NV_XVE_RTD3_FN0_PME_FSM_STATE_PME_REQ 0x00000001 /* R---V */ #define NV_XVE_RTD3_FN0_PME_FSM_STATE_PME_SENT 0x00000002 /* R---V */ #define NV_XVE_RTD3_PME_TO 0x00000ABC /* R--4R */ #define NV_XVE_RTD3_PME_TO_COUNT 15:0 /* R-CVF */ #define NV_XVE_RTD3_PME_TO_COUNT_RESET 0x00000000 /* R-C-V */ #define NV_XVE_GEN4L_PCIE_CAP_HDR 0x00000AC0 /* R--4R */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID 15:0 /* C--VF */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID_EXT_CAP 0x00000023 /* C---V */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID_VERSION 19:16 /* C--VF */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID_VERSION_1 0x00000001 /* C---V */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID_NEXT_PTR 31:20 /* R-IVF */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID_NEXT_PTR_RESIZE_CAP 0x00000BB0 /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID_NEXT_PTR_NONE 0x00000000 /* R-I-V */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID_NEXT_PTR_SRIOV 0x00000BCC /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_HDR_ID_NEXT_PTR_GEN4 0x00000C1C /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_DVSEC 0x00000AC4 /* C--4R */ #define NV_XVE_GEN4L_PCIE_CAP_DVSEC_VID 15:0 /* C--VF */ #define NV_XVE_GEN4L_PCIE_CAP_DVSEC_VID_NV 0x000010DE /* C---V */ #define NV_XVE_GEN4L_PCIE_CAP_DVSEC_REV 19:16 /* C--VF */ #define NV_XVE_GEN4L_PCIE_CAP_DVSEC_REV_1 0x00000001 /* C---V */ #define NV_XVE_GEN4L_PCIE_CAP_DVSEC_LEN 31:20 /* C--VF */ #define NV_XVE_GEN4L_PCIE_CAP_DVSEC_LEN_C 0x0000000C /* C---V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS 0x00000AC8 /* R--4R */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_SUBID 15:0 /* C--VF */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_SUBID_1 0x00000001 /* C---V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_CONFIG 19:16 /* R-CVF */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_CONFIG_INIT 0x00000000 /* R-C-V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_CONFIG_8GTS_MODE 0x00000000 /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_CONFIG_16GTS_MODE 0x00000001 /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_CONFIG_IMP_SPEC 0x0000000E /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_CONFIG_UNDEF 0x0000000F /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_EQ_NEEDED 20:20 /* R-CVF */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_EQ_NEEDED_INIT 0x00000001 /* R-C-V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_EQ_NEEDED_UNSET 0x00000000 /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_EQ_NEEDED_SET 0x00000001 /* R---V */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_RSVD 31:21 /* C--VF */ #define NV_XVE_GEN4L_PCIE_CAP_STATUS_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_CAP_HDR 0x00000BB0 /* R--4R */ #define NV_XVE_RESIZE_CAP_HDR_ID 15:0 /* C--VF */ #define NV_XVE_RESIZE_CAP_HDR_ID_EXT_CAP 0x00000015 /* C---V */ #define NV_XVE_RESIZE_CAP_HDR_ID_VERSION 19:16 /* C--VF */ #define NV_XVE_RESIZE_CAP_HDR_ID_VERSION_1 0x00000001 /* C---V */ #define NV_XVE_RESIZE_CAP_HDR_ID_NEXT_PTR 31:20 /* R-IVF */ #define NV_XVE_RESIZE_CAP_HDR_ID_NEXT_PTR_SRIOV 0x00000BCC /* R-I-V */ #define NV_XVE_RESIZE_CAP_HDR_ID_NEXT_PTR_GEN4 0x00000C1C /* R---V */ #define NV_XVE_RESIZE_CAP_HDR_ID_NEXT_PTR_NONE 0x00000000 /* R---V */ #define NV_XVE_RESIZE_BAR0_CAP 0x00000BB4 /* C--4R */ #define NV_XVE_RESIZE_BAR0_CAP_RSVDP 3:0 /* C--VF */ #define NV_XVE_RESIZE_BAR0_CAP_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR0_CAP_UNSUPPORTED 7:4 /* C--VF */ #define NV_XVE_RESIZE_BAR0_CAP_UNSUPPORTED_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR0_CAP_ADV_SIZE 23:8 /* C--VF */ #define NV_XVE_RESIZE_BAR0_CAP_ADV_SIZE_INIT 0x00000001 /* C---V */ #define NV_XVE_RESIZE_BAR0_CAP_ADV_SIZE_16MB 0x00000001 /* ----V */ #define NV_XVE_RESIZE_BAR0_CAP_RSVD 31:24 /* C--VF */ #define NV_XVE_RESIZE_BAR0_CAP_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR0_CTRL 0x00000BB8 /* RW-4R */ #define NV_XVE_RESIZE_BAR0_CTRL_BAR_INDEX 2:0 /* C--VF */ #define NV_XVE_RESIZE_BAR0_CTRL_BAR_INDEX_OFFSET_10H 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR0_CTRL_RSVDP 4:3 /* C--VF */ #define NV_XVE_RESIZE_BAR0_CTRL_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR0_CTRL_NUM_RESIZE_BAR 7:5 /* C--VF */ #define NV_XVE_RESIZE_BAR0_CTRL_NUM_RESIZE_BAR_INIT 0x00000003 /* C---V */ #define NV_XVE_RESIZE_BAR0_CTRL_BAR_SIZE 12:8 /* RWIVF */ #define NV_XVE_RESIZE_BAR0_CTRL_BAR_SIZE_INIT 0x00000004 /* RWI-V */ #define NV_XVE_RESIZE_BAR0_CTRL_BAR_SIZE_16MB 0x00000004 /* ----V */ #define NV_XVE_RESIZE_BAR0_CTRL_BAR_SIZE_32MB 0x00000005 /* ----V */ #define NV_XVE_RESIZE_BAR0_CTRL_RSVD 31:13 /* C--VF */ #define NV_XVE_RESIZE_BAR0_CTRL_RSVD_NULL 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR1_CAP 0x00000BBC /* R-I4R */ #define NV_XVE_RESIZE_BAR1_CAP_RSVDP 3:0 /* C--VF */ #define NV_XVE_RESIZE_BAR1_CAP_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR1_CAP_UNSUPPORTED 9:4 /* C--VF */ #define NV_XVE_RESIZE_BAR1_CAP_UNSUPPORTED_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE 23:10 /* R-IVF */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_INIT 0x00000007 /* R-I-V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_MIN 0x00000001 /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_64MB 0x00000001 /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_128MB 0x00000003 /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_256MB 0x00000007 /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_512MB 0x0000000F /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_1GB 0x0000001F /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_2GB 0x0000003F /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_4GB 0x0000007F /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_8GB 0x000000FF /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_16GB 0x000001FF /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_32GB 0x000003FF /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_64GB 0x000007FF /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_128GB 0x00000FFF /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_256GB 0x00001FFF /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_512GB 0x00003FFF /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_ADV_SIZE_MAX 0x00003FFF /* ----V */ #define NV_XVE_RESIZE_BAR1_CAP_RSVD 31:24 /* C--VF */ #define NV_XVE_RESIZE_BAR1_CAP_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR1_CTRL 0x00000BC0 /* RW-4R */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_INDEX 2:0 /* R--VF */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_INDEX_OFFSET_14H 0x00000001 /* R---V */ #define NV_XVE_RESIZE_BAR1_CTRL_RSVDP 4:3 /* C--VF */ #define NV_XVE_RESIZE_BAR1_CTRL_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR1_CTRL_NUM_RESIZE_BAR 7:5 /* C--VF */ #define NV_XVE_RESIZE_BAR1_CTRL_NUM_RESIZE_BAR_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE 12:8 /* RWIVF */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_INIT 0x00000008 /* RWI-V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_MIN 0x00000006 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_64MB 0x00000006 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_128MB 0x00000007 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_256MB 0x00000008 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_512MB 0x00000009 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_1GB 0x0000000A /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_2GB 0x0000000B /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_4GB 0x0000000C /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_8GB 0x0000000D /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_16GB 0x0000000E /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_32GB 0x0000000F /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_64GB 0x00000010 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_128GB 0x00000011 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_256GB 0x00000012 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_512GB 0x00000013 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_1T_RESERVED 0x00000014 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_2T_RESERVED 0x00000015 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_BAR_SIZE_MAX 0x00000013 /* ----V */ #define NV_XVE_RESIZE_BAR1_CTRL_RSVD 31:13 /* C--VF */ #define NV_XVE_RESIZE_BAR1_CTRL_RSVD_NULL 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR2_CAP 0x00000BC4 /* R-I4R */ #define NV_XVE_RESIZE_BAR2_CAP_RSVDP 3:0 /* C--VF */ #define NV_XVE_RESIZE_BAR2_CAP_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR2_CAP_UNSUPPORTED 7:4 /* C--VF */ #define NV_XVE_RESIZE_BAR2_CAP_UNSUPPORTED_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR2_CAP_ADV_SIZE 23:8 /* R-IVF */ #define NV_XVE_RESIZE_BAR2_CAP_ADV_SIZE_INIT 0x00000002 /* R-I-V */ #define NV_XVE_RESIZE_BAR2_CAP_ADV_SIZE_32MB 0x00000002 /* ----V */ #define NV_XVE_RESIZE_BAR2_CAP_RSVD 31:24 /* C--VF */ #define NV_XVE_RESIZE_BAR2_CAP_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR2_CTRL 0x00000BC8 /* RW-4R */ #define NV_XVE_RESIZE_BAR2_CTRL_BAR_INDEX 2:0 /* R--VF */ #define NV_XVE_RESIZE_BAR2_CTRL_BAR_INDEX_OFFSET_1CH 0x00000003 /* R---V */ #define NV_XVE_RESIZE_BAR2_CTRL_RSVDP 4:3 /* C--VF */ #define NV_XVE_RESIZE_BAR2_CTRL_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR2_CTRL_NUM_RESIZE_BAR 7:5 /* C--VF */ #define NV_XVE_RESIZE_BAR2_CTRL_NUM_RESIZE_BAR_INIT 0x00000000 /* C---V */ #define NV_XVE_RESIZE_BAR2_CTRL_BAR_SIZE 12:8 /* RWIVF */ #define NV_XVE_RESIZE_BAR2_CTRL_BAR_SIZE_INIT 0x00000005 /* RWI-V */ #define NV_XVE_RESIZE_BAR2_CTRL_BAR_SIZE_16MB 0x00000004 /* ----V */ #define NV_XVE_RESIZE_BAR2_CTRL_BAR_SIZE_32MB 0x00000005 /* ----V */ #define NV_XVE_RESIZE_BAR2_CTRL_RSVD 31:13 /* C--VF */ #define NV_XVE_RESIZE_BAR2_CTRL_RSVD_NULL 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR0 0x00000BCC /* C--4R */ #define NV_XVE_SRIOV_CAP_HDR0_ID 15:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR0_ID_EXT_CAP 0x00000010 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR0_ID_VERSION 19:16 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR0_ID_VERSION_1 0x00000001 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR0_ID_NEXT_PTR 31:20 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR0_ID_NEXT_PTR_ARI 0x00000C14 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR1 0x00000BD0 /* R--4R */ #define NV_XVE_SRIOV_CAP_HDR1_VF_MIGRATION_CAPABLE 0:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR1_VF_MIGRATION_CAPABLE_FALSE 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR1_ARI_HIER_PSVD 1:1 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR1_ARI_HIER_PSVD_TRUE 0x00000001 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR1_10BIT_TAG_REQ 2:2 /* R--VF */ #define NV_XVE_SRIOV_CAP_HDR1_10BIT_TAG_REQ_UNSUPP 0x00000000 /* R---V */ #define NV_XVE_SRIOV_CAP_HDR1_10BIT_TAG_REQ_SUPP 0x00000001 /* R---V */ #define NV_XVE_SRIOV_CAP_HDR1_RSVD 20:3 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR1_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR1_VF_MIGR_INTR_MSG_NUM 31:21 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR1_VF_MIGR_INTR_MSG_NUM_FALSE 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR2 0x00000BD4 /* RW-4R */ #define NV_XVE_SRIOV_CAP_HDR2_VF_ENABLE 0:0 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR2_VF_ENABLE_FALSE 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MIGR_ENABLE 1:1 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MIGR_ENABLE_FALSE 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MIGR_INTR_ENABLE 2:2 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MIGR_INTR_ENABLE_FALSE 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MSE 3:3 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MSE_FALSE 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MSE_TRUE 0x00000001 /* RW--V */ #define NV_XVE_SRIOV_CAP_HDR2_ARI_CAP_HIER 4:4 /* RWEVF */ #define NV_XVE_SRIOV_CAP_HDR2_ARI_CAP_HIER_FALSE 0x00000000 /* RWE-V */ #define NV_XVE_SRIOV_CAP_HDR2_ARI_CAP_HIER_TRUE 0x00000001 /* RW--V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_10BIT_TAG_REQ_ENABLE 5:5 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR2_VF_10BIT_TAG_REQ_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_10BIT_TAG_REQ_ENABLE_UNSET 0x00000000 /* RW--V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_10BIT_TAG_REQ_ENABLE_SET 0x00000001 /* RW--V */ #define NV_XVE_SRIOV_CAP_HDR2_RSVD1 15:6 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR2_RSVD1_INIT 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MIGR_STATUS 16:16 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR2_VF_MIGR_STATUS_FALSE 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR2_RSVD2 31:17 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR2_RSVD2_INIT 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR3 0x00000BD8 /* R--4R */ #define NV_XVE_SRIOV_CAP_HDR3_INITIAL_VFS 15:0 /* R-EVF */ #define NV_XVE_SRIOV_CAP_HDR3_INITIAL_VFS_VAL 0x0000003F /* R-E-V */ #define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS 31:16 /* R-EVF */ #define NV_XVE_SRIOV_CAP_HDR3_TOTAL_VFS_VAL 0x0000003F /* R-E-V */ #define NV_XVE_SRIOV_CAP_HDR4 0x00000BDC /* RW-4R */ #define NV_XVE_SRIOV_CAP_HDR4_NUM_VFS 15:0 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR4_NUM_VFS_VAL 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR4_FUNC_DEP_LINK 31:16 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR4_FUNC_DEP_LINK_PF0 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR5 0x00000BE0 /* R--4R */ #define NV_XVE_SRIOV_CAP_HDR5_FIRST_VF_OFFSET 15:0 /* R-IVF */ #define NV_XVE_SRIOV_CAP_HDR5_FIRST_VF_OFFSET_VAL 0x00000004 /* R-I-V */ #define NV_XVE_SRIOV_CAP_HDR5_VF_STRIDE 31:16 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR5_VF_STRIDE_ONE 0x00000001 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR6 0x00000BE4 /* R--4R */ #define NV_XVE_SRIOV_CAP_HDR6_RSVD1 15:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR6_RSVD1_INIT 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR6_VF_DEVICE_ID 31:16 /* R--VF */ #define NV_XVE_SRIOV_CAP_HDR6_VF_DEVICE_ID_VAL 0x00000000 /* R---V */ #define NV_XVE_SRIOV_CAP_HDR7 0x00000BE8 /* C--4R */ #define NV_XVE_SRIOV_CAP_HDR7_SUPP_PAGE_SZ 31:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR7_SUPP_PAGE_SZ_VAL 0x00000573 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR8 0x00000BEC /* RW-4R */ #define NV_XVE_SRIOV_CAP_HDR8_SYS_PAGE_SZ 31:0 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR8_SYS_PAGE_SZ_VAL 0x00000001 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR9 0x00000BF0 /* RW-4R */ #define NV_XVE_SRIOV_CAP_HDR9_VF_BAR0_SPACE_TYP 0:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR9_VF_BAR0_SPACE_TYP_VAL 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR9_VF_BAR0_ADR_TYPE 2:1 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR9_VF_BAR0_ADR_TYPE_32B 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR9_VF_BAR0_PREFETCH 3:3 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR9_VF_BAR0_PREFETCH_DIS 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR9_VF_BAR0_BASE_ADR 31:18 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR9_VF_BAR0_BASE_ADR_VAL 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR10 0x00000BF4 /* RW-4R */ #define NV_XVE_SRIOV_CAP_HDR10_VF_BAR1_SPACE_TYP 0:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR10_VF_BAR1_SPACE_TYP_VAL 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR10_VF_BAR1_ADR_TYPE 2:1 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR10_VF_BAR1_ADR_TYPE_64B 0x00000002 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR10_VF_BAR1_PREFETCH 3:3 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR10_VF_BAR1_PREFETCH_ENABLE 0x00000001 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR10_VF_BAR1_BASE_ADR 31:26 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR10_VF_BAR1_BASE_ADR_VAL 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR11_VF_BAR1_HI 0x00000BF8 /* RW-4R */ #define NV_XVE_SRIOV_CAP_HDR11_VF_BAR1_HI_BASE_ADDRESS 31:0 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR11_VF_BAR1_HI_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR12 0x00000BFC /* RW-4R */ #define NV_XVE_SRIOV_CAP_HDR12_VF_BAR2_SPACE_TYP 0:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR12_VF_BAR2_SPACE_TYP_VAL 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR12_VF_BAR2_ADR_TYPE 2:1 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR12_VF_BAR2_ADR_TYPE_64B 0x00000002 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR12_VF_BAR2_PREFETCH 3:3 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR12_VF_BAR2_PREFETCH_ENABLE 0x00000001 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR12_VF_BAR2_BASE_ADR 31:24 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR12_VF_BAR2_BASE_ADR_VAL 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR13_VF_BAR2_HI 0x00000C00 /* RW-4R */ #define NV_XVE_SRIOV_CAP_HDR13_VF_BAR2_HI_BASE_ADDRESS 31:0 /* RWIVF */ #define NV_XVE_SRIOV_CAP_HDR13_VF_BAR2_HI_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CAP_HDR14_VF_BAR3 0x00000C04 /* C--4R */ #define NV_XVE_SRIOV_CAP_HDR14_VF_BAR3_BASE_ADDRESS 31:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR14_VF_BAR3_BASE_ADDRESS_INIT 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CAP_HDR17 0x00000C08 /* C--4R */ #define NV_XVE_SRIOV_CAP_HDR17_VF_MIGR_ST_ARRAY_OFFSET 31:0 /* C--VF */ #define NV_XVE_SRIOV_CAP_HDR17_VF_MIGR_ST_ARRAY_OFFSET_VAL 0x00000000 /* C---V */ #define NV_XVE_ARI_CAP0 0x00000C14 /* R--4R */ #define NV_XVE_ARI_CAP0_CAPID 15:0 /* C--VF */ #define NV_XVE_ARI_CAP0_CAPID_EXT_CAP 0x0000000E /* C---V */ #define NV_XVE_ARI_CAP0_HDR0_ID_VERSION 19:16 /* C--VF */ #define NV_XVE_ARI_CAP0_HDR0_ID_VERSION_1 0x00000001 /* C---V */ #define NV_XVE_ARI_CAP0_HDR0_ID_NEXT_PTR 31:20 /* R-IVF */ #define NV_XVE_ARI_CAP0_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* R---V */ #define NV_XVE_ARI_CAP0_HDR0_ID_NEXT_PTR_GEN4 0x00000C1C /* R-I-V */ #define NV_XVE_ARI_CAP1 0x00000C18 /* R--4R */ #define NV_XVE_ARI_CAP1_MFVC_FN_GRPS_CAP 0:0 /* C--VF */ #define NV_XVE_ARI_CAP1_MFVC_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */ #define NV_XVE_ARI_CAP1_ACS_FN_GRPS_CAP 1:1 /* C--VF */ #define NV_XVE_ARI_CAP1_ACS_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */ #define NV_XVE_ARI_CAP1_NXT_FN_NUM 15:8 /* R--VF */ #define NV_XVE_ARI_CAP1_NXT_FN_NUM_VAL 0x00000001 /* R---V */ #define NV_XVE_ARI_CAP1_MFVC_FN_GRPS_EN 16:16 /* C--VF */ #define NV_XVE_ARI_CAP1_MFVC_FN_GRPS_EN_UNSET 0x00000000 /* C---V */ #define NV_XVE_ARI_CAP1_ACS_FN_GRPS_EN 17:17 /* C--VF */ #define NV_XVE_ARI_CAP1_ACS_FN_GRPS_EN_UNSET 0x00000000 /* C---V */ #define NV_XVE_ARI_CAP1_FN_GRP 22:20 /* C--VF */ #define NV_XVE_ARI_CAP1_FN_GRP_ZERO 0x00000000 /* C---V */ #define NV_XVE_GEN4_EXT_CAP_HDR 0x00000C1C /* C--4R */ #define NV_XVE_GEN4_EXT_CAP_HDR_CAPID 15:0 /* C--VF */ #define NV_XVE_GEN4_EXT_CAP_HDR_CAPID_EXT_CAP 0x00000026 /* C---V */ #define NV_XVE_GEN4_EXT_CAP_HDR_HDR0_ID_VERSION 19:16 /* C--VF */ #define NV_XVE_GEN4_EXT_CAP_HDR_HDR0_ID_VERSION_1 0x00000001 /* C---V */ #define NV_XVE_GEN4_EXT_CAP_HDR_HDR0_ID_NEXT_PTR 31:20 /* C--VF */ #define NV_XVE_GEN4_EXT_CAP_HDR_HDR0_ID_NEXT_PTR_MARGINING 0x00000D00 /* C---V */ #define NV_XVE_GEN4_CAP 0x00000C20 /* C--4R */ #define NV_XVE_GEN4_CAP_RSVDP 31:0 /* C--VF */ #define NV_XVE_GEN4_CAP_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_GEN4_CTRL 0x00000C24 /* C--4R */ #define NV_XVE_GEN4_CTRL_RSVDP 31:0 /* C--VF */ #define NV_XVE_GEN4_CTRL_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_GEN4_STATUS 0x00000C28 /* RW-4R */ #define NV_XVE_GEN4_STATUS_EQ_COMPLETE 0:0 /* R-CVF */ #define NV_XVE_GEN4_STATUS_EQ_COMPLETE_UNSET 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_STATUS_EQ_COMPLETE_SET 0x00000001 /* R---V */ #define NV_XVE_GEN4_STATUS_EQ_PH1_SUCCESS 1:1 /* R-CVF */ #define NV_XVE_GEN4_STATUS_EQ_PH1_SUCCESS_UNSET 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_STATUS_EQ_PH1_SUCCESS_SET 0x00000001 /* R---V */ #define NV_XVE_GEN4_STATUS_EQ_PH2_SUCCESS 2:2 /* R-CVF */ #define NV_XVE_GEN4_STATUS_EQ_PH2_SUCCESS_UNSET 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_STATUS_EQ_PH2_SUCCESS_SET 0x00000001 /* R---V */ #define NV_XVE_GEN4_STATUS_EQ_PH3_SUCCESS 3:3 /* R-CVF */ #define NV_XVE_GEN4_STATUS_EQ_PH3_SUCCESS_UNSET 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_STATUS_EQ_PH3_SUCCESS_SET 0x00000001 /* R---V */ #define NV_XVE_GEN4_STATUS_EQ_LINK_REQ 4:4 /* RWCVF */ #define NV_XVE_GEN4_STATUS_EQ_LINK_REQ_UNSET 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_STATUS_EQ_LINK_REQ_SET 0x00000001 /* R---V */ #define NV_XVE_GEN4_STATUS_EQ_LINK_REQ_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_STATUS_RSVD 31:5 /* C--VF */ #define NV_XVE_GEN4_STATUS_RSVD_NULL 0x00000000 /* C---V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM 0x00000C2C /* RW-4R */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_0 0:0 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_0_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_0_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_1 1:1 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_1_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_1_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_2 2:2 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_2_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_2_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_3 3:3 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_3_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_3_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_4 4:4 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_4_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_4_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_5 5:5 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_5_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_5_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_6 6:6 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_6_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_6_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_7 7:7 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_7_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_7_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_8 8:8 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_8_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_8_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_9 9:9 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_9_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_9_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_10 10:10/* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_10_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_10_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_11 11:11 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_11_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_11_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_12 12:12 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_12_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_12_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_13 13:13 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_13_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_13_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_14 14:14 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_14_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_14_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_15 15:15 /* RWCVF */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_15_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_LOCAL_DATA_PARITY_MISM_STATUS_15_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM 0x00000C30 /* RW-4R */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_0 0:0 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_0_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_0_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_1 1:1 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_1_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_1_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_2 2:2 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_2_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_2_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_3 3:3 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_3_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_3_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_4 4:4 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_4_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_4_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_5 5:5 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_5_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_5_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_6 6:6 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_6_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_6_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_7 7:7 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_7_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_7_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_8 8:8 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_8_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_8_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_9 9:9 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_9_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_9_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_10 10:10/* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_10_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_10_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_11 11:11 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_11_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_11_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_12 12:12 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_12_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_12_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_13 13:13 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_13_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_13_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_14 14:14 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_14_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_14_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_15 15:15 /* RWCVF */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_15_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_FIRST_RET_PARITY_MISM_STATUS_15_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM 0x00000C34 /* RW-4R */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_0 0:0 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_0_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_0_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_1 1:1 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_1_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_1_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_2 2:2 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_2_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_2_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_3 3:3 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_3_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_3_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_4 4:4 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_4_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_4_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_5 5:5 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_5_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_5_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_6 6:6 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_6_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_6_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_7 7:7 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_7_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_7_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_8 8:8 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_8_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_8_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_9 9:9 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_9_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_9_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_10 10:10/* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_10_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_10_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_11 11:11 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_11_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_11_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_12 12:12 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_12_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_12_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_13 13:13 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_13_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_13_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_14 14:14 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_14_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_14_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_15 15:15 /* RWCVF */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_15_NONE 0x00000000 /* R-C-V */ #define NV_XVE_GEN4_SECOND_RET_PARITY_MISM_STATUS_15_RESET 0x00000001 /* -W--C */ #define NV_XVE_GEN4_LANE_EQ_CTRL(i) (0x00000C3C+(i)*4) /* R--4A */ #define NV_XVE_GEN4_LANE_EQ_CTRL__SIZE_1 4 /* */ #define NV_XVE_GEN4_LANE_EQ_CTRL_0_DN_PORT_16GTS_PRESET 3:0 /* C--VF */ #define NV_XVE_GEN4_LANE_EQ_CTRL_0_DN_PORT_16GTS_PRESET_INIT 0x00000000 /* C---V */ #define NV_XVE_GEN4_LANE_EQ_CTRL_0_UP_PORT_16GTS_PRESET 7:4 /* R-EVF */ #define NV_XVE_GEN4_LANE_EQ_CTRL_0_UP_PORT_16GTS_PRESET_INIT 0x0000000F /* R-E-V */ #define NV_XVE_GEN4_LANE_EQ_CTRL_1_DN_PORT_16GTS_PRESET 11:8 /* C--VF */ #define NV_XVE_GEN4_LANE_EQ_CTRL_1_DN_PORT_16GTS_PRESET_INIT 0x00000000 /* C---V */ #define NV_XVE_GEN4_LANE_EQ_CTRL_1_UP_PORT_16GTS_PRESET 15:12 /* R-EVF */ #define NV_XVE_GEN4_LANE_EQ_CTRL_1_UP_PORT_16GTS_PRESET_INIT 0x0000000F /* R-E-V */ #define NV_XVE_GEN4_LANE_EQ_CTRL_2_DN_PORT_16GTS_PRESET 19:16 /* C--VF */ #define NV_XVE_GEN4_LANE_EQ_CTRL_2_DN_PORT_16GTS_PRESET_INIT 0x00000000 /* C---V */ #define NV_XVE_GEN4_LANE_EQ_CTRL_2_UP_PORT_16GTS_PRESET 23:20 /* R-EVF */ #define NV_XVE_GEN4_LANE_EQ_CTRL_2_UP_PORT_16GTS_PRESET_INIT 0x0000000F /* R-E-V */ #define NV_XVE_GEN4_LANE_EQ_CTRL_3_DN_PORT_16GTS_PRESET 27:24 /* C--VF */ #define NV_XVE_GEN4_LANE_EQ_CTRL_3_DN_PORT_16GTS_PRESET_INIT 0x00000000 /* C---V */ #define NV_XVE_GEN4_LANE_EQ_CTRL_3_UP_PORT_16GTS_PRESET 31:28 /* R-EVF */ #define NV_XVE_GEN4_LANE_EQ_CTRL_3_UP_PORT_16GTS_PRESET_INIT 0x0000000F /* R-E-V */ #define NV_XVE_MARGINING_EXT_CAP_HDR 0x00000D00 /* C--4R */ #define NV_XVE_MARGINING_EXT_CAP_HDR_CAPID 15:0 /* C--VF */ #define NV_XVE_MARGINING_EXT_CAP_HDR_CAPID_EXT_CAP 0x00000027 /* C---V */ #define NV_XVE_MARGINING_EXT_CAP_HDR_HDR0_ID_VERSION 19:16 /* C--VF */ #define NV_XVE_MARGINING_EXT_CAP_HDR_HDR0_ID_VERSION_1 0x00000001 /* C---V */ #define NV_XVE_MARGINING_EXT_CAP_HDR_HDR0_ID_NEXT_PTR 31:20 /* C--VF */ #define NV_XVE_MARGINING_EXT_CAP_HDR_HDR0_ID_NEXT_PTR_DL_FEATURE 0x00000E00 /* C---V */ #define NV_XVE_MARGINING_PORT_CAP_AND_STATUS 0x00000D04 /* R-E4R */ #define NV_XVE_MARGINING_PORT_CAP_AND_STATUS_USES_DRVR_SW 0:0 /* C--VF */ #define NV_XVE_MARGINING_PORT_CAP_AND_STATUS_USES_DRVR_SW_INIT 0x00000001 /* C---V */ #define NV_XVE_MARGINING_PORT_CAP_AND_STATUS_MARGINING_RDY 16:16 /* R-EVF */ #define NV_XVE_MARGINING_PORT_CAP_AND_STATUS_MARGINING_RDY_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_PORT_CAP_AND_STATUS_MARGINING_SW_RDY 17:17 /* R-EVF */ #define NV_XVE_MARGINING_PORT_CAP_AND_STATUS_MARGINING_SW_RDY_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_LANE(i) (0x00000D08+(i)*4) /* RW-4A */ #define NV_XVE_MARGINING_LANE__SIZE_1 16 /* */ #define NV_XVE_MARGINING_LANE_CTRL_RCVR_NUM 2:0 /* RWEVF */ #define NV_XVE_MARGINING_LANE_CTRL_RCVR_NUM_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_LANE_CTRL_MARGIN_TYPE 5:3 /* RWEVF */ #define NV_XVE_MARGINING_LANE_CTRL_MARGIN_TYPE_INIT 0x00000007 /* RWE-V */ #define NV_XVE_MARGINING_LANE_CTRL_USAGE_MODEL 6:6 /* RWEVF */ #define NV_XVE_MARGINING_LANE_CTRL_USAGE_MODEL_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_LANE_CTRL_MARGIN_PAYLOAD 15:8 /* RWEVF */ #define NV_XVE_MARGINING_LANE_CTRL_MARGIN_PAYLOAD_INIT 0x0000009C /* RWE-V */ #define NV_XVE_MARGINING_LANE_STATUS_RCVR_NUM 18:16 /* R-EVF */ #define NV_XVE_MARGINING_LANE_STATUS_RCVR_NUM_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_LANE_STATUS_MARGIN_TYPE 21:19 /* R-EVF */ #define NV_XVE_MARGINING_LANE_STATUS_MARGIN_TYPE_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_LANE_STATUS_USAGE_MODEL 22:22 /* R-EVF */ #define NV_XVE_MARGINING_LANE_STATUS_USAGE_MODEL_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_LANE_STATUS_MARGIN_PAYLOAD 31:24 /* R-EVF */ #define NV_XVE_MARGINING_LANE_STATUS_MARGIN_PAYLOAD_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_SHADOW_PORT_STATUS 0x00000D48 /* RWE4R */ #define NV_XVE_MARGINING_SHADOW_PORT_STATUS_MARGINING_RDY 0:0 /* RWEVF */ #define NV_XVE_MARGINING_SHADOW_PORT_STATUS_MARGINING_RDY_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_SHADOW_PORT_STATUS_MARGINING_SW_RDY 1:1 /* RWEVF */ #define NV_XVE_MARGINING_SHADOW_PORT_STATUS_MARGINING_SW_RDY_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS(i) (0x00000D4C+(i)*4) /* RW-4A */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS__SIZE_1 16 /* */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS_RCVR_NUM 2:0 /* RWEVF */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS_RCVR_NUM_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS_MARGIN_TYPE 5:3 /* RWEVF */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS_MARGIN_TYPE_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS_USAGE_MODEL 6:6 /* RWEVF */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS_USAGE_MODEL_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS_MARGIN_PAYLOAD 15:8 /* RWEVF */ #define NV_XVE_MARGINING_SHADOW_LANE_STATUS_MARGIN_PAYLOAD_INIT 0x00000000 /* RWE-V */ #define NV_XVE_DL_FEATURE_EXT_CAP_HDR 0x00000E00 /* C--4R */ #define NV_XVE_DL_FEATURE_EXT_CAP_HDR_CAPID 15:0 /* C--VF */ #define NV_XVE_DL_FEATURE_EXT_CAP_HDR_CAPID_EXT_CAP 0x00000025 /* C---V */ #define NV_XVE_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_VERSION 19:16 /* C--VF */ #define NV_XVE_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_VERSION_1 0x00000001 /* C---V */ #define NV_XVE_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_NEXT_PTR 31:20 /* C--VF */ #define NV_XVE_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* C---V */ #define NV_XVE_DL_FEATURE_CAP 0x00000E04 /* R--4R */ #define NV_XVE_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP 0:0 /* R-EVF */ #define NV_XVE_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP_UNSET 0x00000000 /* R-E-V */ #define NV_XVE_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP_SET 0x00000001 /* R---V */ #define NV_XVE_DL_FEATURE_CAP_RSVDP 22:1 /* C--VF */ #define NV_XVE_DL_FEATURE_CAP_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_DL_FEATURE_CAP_EXCH_EN 31:31 /* R-EVF */ #define NV_XVE_DL_FEATURE_CAP_EXCH_EN_SET 0x00000001 /* R---V */ #define NV_XVE_DL_FEATURE_CAP_EXCH_EN_UNSET 0x00000000 /* R-E-V */ #define NV_XVE_DL_FEATURE_STATUS 0x00000E08 /* R--4R */ #define NV_XVE_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP 0:0 /* R-EVF */ #define NV_XVE_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP_UNSET 0x00000000 /* R-E-V */ #define NV_XVE_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP_SET 0x00000001 /* R---V */ #define NV_XVE_DL_FEATURE_STATUS_RSVDP 22:1 /* C--VF */ #define NV_XVE_DL_FEATURE_STATUS_RSVDP_NULL 0x00000000 /* C---V */ #define NV_XVE_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD 31:31 /* R-EVF */ #define NV_XVE_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD_UNSET 0x00000000 /* R-E-V */ #define NV_XVE_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD_SET 0x00000001 /* R---V */ #define NV_XVE_MARGINING_CAPABILITY0 0x00000D8C /* RWE4R */ #define NV_XVE_MARGINING_CAPABILITY0_M_IND_ERROR_SAMPLER 0:0 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY0_M_IND_ERROR_SAMPLER_INIT 0x00000001 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY0_M_SAMPLE_REPORTING_METHOD 1:1 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY0_M_SAMPLE_REPORTING_METHOD_INIT 0x00000001 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY0_M_IND_LEFT_RIGHT_TIMING 2:2 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY0_M_IND_LEFT_RIGHT_TIMING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY0_M_IND_LEFT_RIGHT_TIMING__PROD 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_CAPABILITY0_M_IND_UP_DOWN_VOLTAGE 3:3 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY0_M_IND_UP_DOWN_VOLTAGE_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY0_M_IND_UP_DOWN_VOLTAGE__PROD 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_CAPABILITY0_M_VOLTAGES_SUPPORTED 4:4 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY0_M_VOLTAGES_SUPPORTED_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY0_M_VOLTAGES_SUPPORTED__PROD 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_CAPABILITY0_M_NUM_VOLTAGE_STEPS 14:8 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY0_M_NUM_VOLTAGE_STEPS_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY0_M_NUM_VOLTAGE_STEPS__PROD 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_CAPABILITY0_M_NUM_TIMING_STEPS 21:16 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY0_M_NUM_TIMING_STEPS_INIT 0x00000007 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY0_M_NUM_TIMING_STEPS__PROD 0x00000007 /* RW--V */ #define NV_XVE_MARGINING_CAPABILITY0_M_MAX_TIMING_OFFSET 30:24 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY0_M_MAX_TIMING_OFFSET_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY0_M_MAX_TIMING_OFFSET__PROD 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_CAPABILITY1 0x00000D90 /* RWE4R */ #define NV_XVE_MARGINING_CAPABILITY1_M_MAX_VOLTAGE_OFFSET 6:0 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY1_M_MAX_VOLTAGE_OFFSET_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY1_M_SAMPLING_RATE_VOLTAGE 13:8 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY1_M_SAMPLING_RATE_VOLTAGE_INIT 0x0000001F /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY1_M_SAMPLING_RATE_VOLTAGE__PROD 0x0000001F /* RW--V */ #define NV_XVE_MARGINING_CAPABILITY1_M_SAMPLING_RATE_TIMING 21:16 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY1_M_SAMPLING_RATE_TIMING_INIT 0x0000001F /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY1_M_SAMPLING_RATE_TIMING__PROD 0x0000001F /* RW--V */ #define NV_XVE_MARGINING_CAPABILITY1_M_SAMPLE_COUNT 30:24 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY1_M_SAMPLE_COUNT_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY2 0x00000D94 /* RWE4R */ #define NV_XVE_MARGINING_CAPABILITY2_M_MAX_LANES 4:0 /* RWEVF */ #define NV_XVE_MARGINING_CAPABILITY2_M_MAX_LANES_INIT 0x0000000F /* RWE-V */ #define NV_XVE_MARGINING_CAPABILITY2_M_MAX_LANES__PROD 0x0000000F /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0 0x00000D98 /* R-E4R */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE0 5:0 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE0_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE1 11:6 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE1_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE2 17:12 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE2_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE3 23:18 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE3_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE4 29:24 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_0_LANE4_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1 0x00000D9C /* R-E4R */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE5 5:0 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE5_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE6 11:6 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE6_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE7 17:12 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE7_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE8 23:18 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE8_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE9 29:24 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_1_LANE9_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2 0x00000DA0 /* R-E4R */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE10 5:0 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE10_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE11 11:6 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE11_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE12 17:12 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE12_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE13 23:18 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE13_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE14 29:24 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_2_LANE14_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_3 0x00000DA4 /* R-E4R */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_3_LANE15 5:0 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_LIMIT_3_LANE15_INIT 0x00000004 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK 0x00000DA8 /* RWE4R */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE0 0:0 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE0_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE1 1:1 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE1_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE2 2:2 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE2_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE3 3:3 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE3_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE4 4:4 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE4_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE5 5:5 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE5_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE6 6:6 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE6_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE7 7:7 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE7_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE8 8:8 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE8_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE9 9:9 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE9_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE10 10:10 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE10_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE11 11:11 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE11_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE12 12:12 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE12_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE13 13:13 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE13_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE14 14:14 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE14_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE15 15:15 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_LANE15_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_ERROR_COUNT_LIMIT_EXCD 29:29 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_ERROR_COUNT_LIMIT_EXCD_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_ABORT 30:30 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_ABORT_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_READY 31:31 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_READY_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT 0x00000DAC /* RWE4R */ #define NV_XVE_MARGINING_INTERRUPT_LANE0 0:0 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE0_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE0_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE0_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE1 1:1 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE1_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE1_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE1_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE2 2:2 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE2_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE2_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE2_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE3 3:3 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE3_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE3_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE3_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE4 4:4 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE4_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE4_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE4_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE5 5:5 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE5_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE5_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE5_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE6 6:6 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE6_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE6_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE6_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE7 7:7 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE7_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE7_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE7_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE8 8:8 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE8_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE8_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE8_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE9 9:9 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE9_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE9_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE9_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE10 10:10 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE10_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE10_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE10_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE11 11:11 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE11_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE11_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE11_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE12 12:12 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE12_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE12_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE12_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE13 13:13 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE13_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE13_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE13_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE14 14:14 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE14_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE14_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE14_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_LANE15 15:15 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_LANE15_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_LANE15_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_LANE15_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_ERROR_COUNT_LIMIT_EXCD 29:29 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_ERROR_COUNT_LIMIT_EXCD_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_ERROR_COUNT_LIMIT_EXCD_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_ERROR_COUNT_LIMIT_EXCD_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_ABORT 30:30 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_ABORT_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_ABORT_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_ABORT_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_READY 31:31 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_READY_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_READY_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_READY_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1 0x00000E24 /* RWE4R */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE0 0:0 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE0_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE1 1:1 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE1_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE2 2:2 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE2_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE3 3:3 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE3_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE4 4:4 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE4_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE5 5:5 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE5_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE6 6:6 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE6_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE7 7:7 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE7_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE8 8:8 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE8_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE9 9:9 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE9_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE10 10:10 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE10_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE11 11:11 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE11_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE12 12:12 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE12_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE13 13:13 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE13_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE14 14:14 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE14_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE15 15:15 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_MASK_1_ERROR_COUNT_LIMIT_EXCD_LANE15_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_INTERRUPT_1 0x00000E28 /* RWE4R */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE0 0:0 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE0_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE0_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE0_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE1 1:1 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE1_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE1_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE1_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE2 2:2 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE2_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE2_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE2_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE3 3:3 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE3_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE3_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE3_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE4 4:4 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE4_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE4_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE4_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE5 5:5 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE5_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE5_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE5_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE6 6:6 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE6_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE6_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE6_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE7 7:7 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE7_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE7_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE7_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE8 8:8 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE8_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE8_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE8_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE9 9:9 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE9_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE9_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE9_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE10 10:10 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE10_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE10_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE10_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE11 11:11 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE11_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE11_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE11_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE12 12:12 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE12_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE12_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE12_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE13 13:13 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE13_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE13_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE13_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE14 14:14 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE14_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE14_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE14_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE15 15:15 /* RWEVF */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE15_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE15_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_INTERRUPT_1_ERROR_COUNT_LIMIT_EXCD_LANE15_RESET 0x00000001 /* -W--C */ #define NV_XVE_MARGINING_STAT_COUNT 0x00000DB0 /* R--4R */ #define NV_XVE_MARGINING_STAT_COUNT_ABORT 15:0 /* R--VF */ #define NV_XVE_MARGINING_STAT_COUNT_ABORT_INIT 0x00000000 /* R---V */ #define NV_XVE_MARGINING_STAT_COUNT_REQUEST 31:16 /* R--VF */ #define NV_XVE_MARGINING_STAT_COUNT_REQUEST_INIT 0x00000000 /* R---V */ #define NV_XVE_MARGINING_STAT_COUNT_RESET 0x00000DB4 /* RW-4R */ #define NV_XVE_MARGINING_STAT_COUNT_RESET_ABORT 0:0 /* RWCVF */ #define NV_XVE_MARGINING_STAT_COUNT_RESET_ABORT_TRIGGER 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_STAT_COUNT_RESET_ABORT_DONE 0x00000000 /* R-C-V */ #define NV_XVE_MARGINING_STAT_COUNT_RESET_ABORT_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_STAT_COUNT_RESET_REQUEST 1:1 /* RWCVF */ #define NV_XVE_MARGINING_STAT_COUNT_RESET_REQUEST_TRIGGER 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_STAT_COUNT_RESET_REQUEST_DONE 0x00000000 /* R-C-V */ #define NV_XVE_MARGINING_STAT_COUNT_RESET_REQUEST_PENDING 0x00000001 /* R---V */ #define NV_XVE_MARGINING_ERROR_COUNT_0 0x00000E14 /* RWE4R */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0 5:0 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_START_COUNTING 6:6 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_RESET 7:7 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE0_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1 13:8 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_START_COUNTING 14:14 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_RESET 15:15 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE1_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2 21:16 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_START_COUNTING 22:22 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_RESET 23:23 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE2_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3 29:24 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_START_COUNTING 30:30 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_RESET 31:31 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_0_LANE3_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_1 0x00000E18 /* RWE4R */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4 5:0 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_START_COUNTING 6:6 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_RESET 7:7 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE4_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5 13:8 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_START_COUNTING 14:14 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_RESET 15:15 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE5_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6 21:16 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_START_COUNTING 22:22 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_RESET 23:23 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE6_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7 29:24 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_START_COUNTING 30:30 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_RESET 31:31 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_1_LANE7_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_2 0x00000E1C /* RWE4R */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8 5:0 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_START_COUNTING 6:6 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_RESET 7:7 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE8_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9 13:8 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_START_COUNTING 14:14 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_RESET 15:15 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE9_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10 21:16 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_START_COUNTING 22:22 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_RESET 23:23 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE10_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11 29:24 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_START_COUNTING 30:30 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_RESET 31:31 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_2_LANE11_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_3 0x00000E20 /* RWE4R */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12 5:0 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_START_COUNTING 6:6 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_RESET 7:7 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE12_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13 13:8 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_START_COUNTING 14:14 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_RESET 15:15 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE13_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14 21:16 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_START_COUNTING 22:22 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_RESET 23:23 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE14_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15 29:24 /* R-EVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_INIT 0x00000000 /* R-E-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_START_COUNTING 30:30 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_START_COUNTING_INIT 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_START_COUNTING_DISABLE 0x00000000 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_START_COUNTING_ENABLE 0x00000001 /* RW--V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_RESET 31:31 /* RWEVF */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_RESET_INIT 0x00000000 /* */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_RESET_DONE 0x00000000 /* RWE-V */ #define NV_XVE_MARGINING_ERROR_COUNT_3_LANE15_RESET_PENDING 0x00000001 /* -W--T */ #define NV_XVE_VF_BAR1_SIZE 0x00000CE0 /* RW-4R */ #define NV_XVE_VF_BAR1_SIZE__PRIV_LEVEL_MASK 0x00000FE8 /* */ #define NV_XVE_VF_BAR1_SIZE_RSVD 31:6 /* C--VF */ #define NV_XVE_VF_BAR1_SIZE_RSVD_VAL 0x00084000 /* C---V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS 5:0 /* RWCVF */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_64MB 0x00000000 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_128MB 0x00000001 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_256MB 0x00000002 /* RWC-V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_512MB 0x00000003 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_1GB 0x00000004 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_2GB 0x00000005 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_4GB 0x00000006 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_8GB 0x00000007 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_16GB 0x00000008 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_32GB 0x00000009 /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_64GB 0x0000000A /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_128GB 0x0000000B /* RW--V */ #define NV_XVE_VF_BAR1_SIZE_NUM_WR_BITS_HIGHEST_VAL 0x0000000B /* RW--V */ #define NV_XVE_SRIOV_CFG0 0x00000CE4 /* RW-4R */ #define NV_XVE_SRIOV_CFG0__PRIV_LEVEL_MASK 0x00000FE8 /* */ #define NV_XVE_SRIOV_CFG0_TOTALVFS 15:0 /* RWCVF */ #define NV_XVE_SRIOV_CFG0_TOTALVFS_SIXTYTHREE 0x0000003F /* RWC-V */ #define NV_XVE_SRIOV_CFG0_RSVD 31:16 /* C--VF */ #define NV_XVE_SRIOV_CFG0_RSVD_INIT0 0x00000000 /* C---V */ #define NV_XVE_SRIOV_CFG1 0x00000CE8 /* RW-4R */ #define NV_XVE_SRIOV_CFG1_PAGESIZE 31:0 /* RWIVF */ #define NV_XVE_SRIOV_CFG1_PAGESIZE_DEFAULT 0x00000573 /* RWI-V */ #define NV_XVE_SRIOV_CFG2 0x00000CEC /* RW-4R */ #define NV_XVE_SRIOV_CFG2_SSID 15:0 /* RWIVF */ #define NV_XVE_SRIOV_CFG2_SSID_DEFAULT 0x00000000 /* RWI-V */ #define NV_XVE_SRIOV_CFG2_RSVD 31:16 /* C--VF */ #define NV_XVE_SRIOV_CFG2_RSVD_INIT0 0x00000000 /* C---V */ #define NV_XVE_VF_FLR_INTR_PENDING(i) (0x00000CF0+(i)*4) /* RW-4A */ #define NV_XVE_VF_FLR_INTR_PENDING__SIZE_1 2 /* */ #define NV_XVE_VF_FLR_INTR_PENDING_BIT 31:0 /* RWIVF */ #define NV_XVE_VF_FLR_INTR_PENDING_BIT_RESET 0x00000000 /* R-I-V */ #define NV_XVE_VF_TRANSACTIONS_PENDING(i) (0x00000CF8+(i)*4) /* R--4A */ #define NV_XVE_VF_TRANSACTIONS_PENDING__SIZE_1 2 /* */ #define NV_XVE_VF_TRANSACTIONS_PENDING_BITS 31:0 /* R-IVF */ #define NV_XVE_VF_TRANSACTIONS_PENDING_BITS_RESET 0x00000000 /* R-I-V */ #define NV_XVE_VF_BUS_MASTER(i) (0x00000DE8+(i)*4) /* R--4A */ #define NV_XVE_VF_BUS_MASTER__SIZE_1 2 /* */ #define NV_XVE_VF_BUS_MASTER_BITS 31:0 /* R-IVF */ #define NV_XVE_VF_BUS_MASTER_BITS_RESET 0x00000000 /* R-I-V */ #define NV_XVE_VF_FLR_PENDING(i) (0x00000DC0+(i)*4) /* RW-4A */ #define NV_XVE_VF_FLR_PENDING__SIZE_1 2 /* */ #define NV_XVE_VF_FLR_PENDING_BIT 31:0 /* RWIVF */ #define NV_XVE_VF_FLR_PENDING_BIT_RESET 0x00000000 /* R-I-V */ #define NV_XVE_VF_BAR2_SIZE 0x00000DC8 /* R--4R */ #define NV_XVE_VF_BAR2_SIZE_RSVD 31:6 /* C--VF */ #define NV_XVE_VF_BAR2_SIZE_RSVD_VAL 0x00084000 /* C---V */ #define NV_XVE_VF_BAR2_SIZE_NUM_WR_BITS 5:0 /* R-IVF */ #define NV_XVE_VF_BAR2_SIZE_NUM_WR_BITS_VAL 0x00000001 /* R-I-V */ #define NV_XVE_BAR1_CONFIG 0x0000DCC /* RW-4R */ #define NV_XVE_BAR1_CONFIG__PRIV_LEVEL_MASK 0x00000ED0 /* */ #define NV_XVE_BAR1_CONFIG_SIZE 3:0 /* RWCVF */ #define NV_XVE_BAR1_CONFIG_SIZE_INIT 2 /* RWC-V */ #define NV_XVE_BAR1_CONFIG_SIZE_64M 0x00000000 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_128M 0x00000001 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_256M 0x00000002 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_512M 0x00000003 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_1G 0x00000004 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_2G 0x00000005 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_4G 0x00000006 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_8G 0x00000007 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_16G 0x00000008 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_32G 0x00000009 /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_64G 0x0000000A /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_128G 0x0000000B /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_256G 0x0000000C /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_512G 0x0000000D /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_1T_RESERVED 0x0000000E /* RW--V */ #define NV_XVE_BAR1_CONFIG_SIZE_2T_RESERVED 0x0000000F /* RW--V */ #define NV_XVE_BAR1_CONFIG_OVERWRITE 31:31 /* RWCVF */ #define NV_XVE_BAR1_CONFIG_OVERWRITE_DISABLED 0x00000000 /* RWC-V */ #define NV_XVE_BAR1_CONFIG_OVERWRITE_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_FLR_RESET_WIDTH 0x0000DD0 /* RW-4R */ #define NV_XVE_FLR_RESET_WIDTH__PRIV_LEVEL_MASK 0x00000FE8 /* */ #define NV_XVE_FLR_RESET_WIDTH_COUNT 17:0 /* RWCVF */ #define NV_XVE_FLR_RESET_WIDTH_COUNT_VAL 0x0000008 /* RWC-V */ #define NV_XVE_CYA_FLR_RESET 0x0000DF0 /* RW-4R */ #define NV_XVE_CYA_FLR_RESET__PRIV_LEVEL_MASK 0x00000FEC /* */ #define NV_XVE_CYA_FLR_RESET_BUSY_OVERRIDE 0:0 /* RWCVF */ #define NV_XVE_CYA_FLR_RESET_BUSY_OVERRIDE_VAL 0x0000000 /* RWC-V */ #define NV_XVE_CYA_FLR_RESET_BUSY_STRETCH_COUNTER_WIDTH 8:1 /* RWCVF */ #define NV_XVE_CYA_FLR_RESET_BUSY_STRETCH_COUNTER_WIDTH_VAL 0x0000010 /* RWC-V */ #define NV_XVE_CYA_FLR_RESET_ERROR_BUSY_OVERRIDE 9:9 /* RWCVF */ #define NV_XVE_CYA_FLR_RESET_ERROR_BUSY_OVERRIDE_VAL 0x0000000 /* RWC-V */ #define NV_XVE_VF_TAG_CPL_TIMEOUT(i) (0x00000DF4+(i)*4) /* RW-4A */ #define NV_XVE_VF_TAG_CPL_TIMEOUT__SIZE_1 2 /* */ #define NV_XVE_VF_TAG_CPL_TIMEOUT_BIT 31:0 /* RWIVF */ #define NV_XVE_VF_TAG_CPL_TIMEOUT_BIT_RESET 0x00000000 /* R-I-V */ #define NV_XVE_STICKY_SHADOW_0 0x00000C88 /* RW-4R */ #define NV_XVE_STICKY_SHADOW_0_FN0_PME 23:23 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_AUXILLARY_POWER_PM_ENABLE 22:22 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_2RET_PRESENCE_DET 21:21 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_RET_PRESENCE_DET 20:20 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_EQUALIZATION_REQUEST 19:19 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_EQUALIZATION_PHASE3_SUCCESSFUL 18:18 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_EQUALIZATION_PHASE2_SUCCESSFUL 17:17 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_EQUALIZATION_PHASE1_SUCCESSFUL 16:16 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_EQUALIZATION_COMPLETE 15:15 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_COMPLIANCE_PRESET_DEEMPHASIS 14:11 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_COMPLIANCE_SOS 10:10 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_ENTER_MOD_COMPLIANCE 9:9 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_TRANSMIT_MARGIN 8:6 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_HW_AUTO_SPEED_DISABLE 5:5 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_ENTER_COMPLIANCE 4:4 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_0_TARGET_LINK_SPEED 3:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1 0x00000C8C /* RW-4R */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE15 15:15 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE14 14:14 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE13 13:13 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE12 12:12 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE11 11:11 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE10 10:10 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE9 9:9 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE8 8:8 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE7 7:7 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE6 6:6 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE5 5:5 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE4 4:4 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE3 3:3 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE2 2:2 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE1 1:1 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_1_LANE_ERROR_STATUS_LANE0 0:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_2(i) (0x00000C90+(i)*24) /* RW-4A */ #define NV_XVE_STICKY_SHADOW_2__SIZE_1 1 /* */ #define NV_XVE_STICKY_SHADOW_2_UNCORR_ERR_SEVR 29:20 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_2_UNCORR_ERR_MASK 19:10 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_2_UNCORR_ERR_STATUS 9:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_3(i) (0x00000C94+(i)*24) /* RW-4A */ #define NV_XVE_STICKY_SHADOW_3__SIZE_1 1 /* */ #define NV_XVE_STICKY_SHADOW_3_CORR_ERR_PTR 20:16 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_3_CORR_ERR_MASK 15:8 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_3_CORR_ERR_STATUS 7:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_4(i) (0x00000C98+(i)*24) /* RW-4A */ #define NV_XVE_STICKY_SHADOW_4__SIZE_1 1 /* */ #define NV_XVE_STICKY_SHADOW_4_AER_HDR_LOG_DW0 31:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_5(i) (0x00000C9C+(i)*24) /* RW-4A */ #define NV_XVE_STICKY_SHADOW_5__SIZE_1 1 /* */ #define NV_XVE_STICKY_SHADOW_5_AER_HDR_LOG_DW1 31:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_6(i) (0x00000CA0+(i)*24) /* RW-4A */ #define NV_XVE_STICKY_SHADOW_6__SIZE_1 1 /* */ #define NV_XVE_STICKY_SHADOW_6_AER_HDR_LOG_DW2 31:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_7(i) (0x00000CA4+(i)*24) /* RW-4A */ #define NV_XVE_STICKY_SHADOW_7__SIZE_1 1 /* */ #define NV_XVE_STICKY_SHADOW_7_AER_HDR_LOG_DW3 31:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_8 0x00000CD8 /* RW-4R */ #define NV_XVE_STICKY_SHADOW_8_GEN4_LOCAL_DATA_PARITY_MISM_STATUS 31:16 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_8_GEN4_STATUS_EQ_LINK_REQ 4:4 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_8_GEN4_STATUS_EQ_PH3_SUCCESS 3:3 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_8_GEN4_STATUS_EQ_PH2_SUCCESS 2:2 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_8_GEN4_STATUS_EQ_PH1_SUCCESS 1:1 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_8_GEN4_STATUS_EQ_COMPLETE 0:0 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_9 0x00000CDC /* RW-4R */ #define NV_XVE_STICKY_SHADOW_9_GEN4_SECOND_RET_PARITY_MISM 31:16 /* RWXVF */ #define NV_XVE_STICKY_SHADOW_9_GEN4_FIRST_RET_PARITY_MISM 15:0 /* RWXVF */ #define NV_XVE_MISC_4 0x00000E0C /* RW-4R */ #define NV_XVE_MISC_4_SCRATCH 31:0 /* RWIVF */ #define NV_XVE_MISC_4_SCRATCH_DEFAULT 0x00000000 /* RWI-V */ #define NV_XVE_MISC_5 0x00000E10 /* RW-4R */ #define NV_XVE_MISC_5_SCRATCH 31:0 /* RWEVF */ #define NV_XVE_MISC_5_SCRATCH_DEFAULT 0x00000000 /* RWE-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA 0x00000E2C /* RW-4R */ #define NV_XVE_BAR_BLOCKER_GR_CYA__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE0 0:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE0_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE0_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE0_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE1 1:1 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE1_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE1_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE1_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE2 2:2 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE2_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE2_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE2_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE3 3:3 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE3_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE3_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE3_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE4 4:4 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE4_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE4_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE4_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE5 5:5 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE5_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE5_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE5_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE6 6:6 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE6_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE6_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE6_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE7 7:7 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE7_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE7_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE7_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE0 8:8 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE0_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE0_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE0_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE1 9:9 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE1_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE1_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE1_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE2 10:10 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE2_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE2_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE2_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE3 11:11 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE3_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE3_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE3_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE4 12:12 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE4_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE4_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE4_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE5 13:13 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE5_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE5_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE5_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE6 14:14 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE6_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE6_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE6_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE7 15:15 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE7_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE7_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE7_DISABLED 0x00000000 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RSVD 31:16 /* C--VF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RSVD_INIT 0x00000000 /* C---V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_START_ADDR(i) (0x00000E30+(i)*8) /* RW-4A */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_START_ADDR__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_START_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_START_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_START_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_END_ADDR(i) (0x00000E34+(i)*8) /* RW-4A */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_END_ADDR__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_END_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_END_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_ALLOW_RANGE_END_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_START_ADDR(i) (0x00000E70+(i)*8) /* RW-4A */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_START_ADDR__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_START_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_START_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_START_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_END_ADDR(i) (0x00000E74+(i)*8) /* RW-4A */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_END_ADDR__SIZE_1 8 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_END_ADDR__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_END_ADDR_ADDR 31:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_CYA_DISALLOW_RANGE_END_ADDR_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT 0x00000EB0 /* RW-4R */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT__PRIV_LEVEL_MASK 0x00000FE4 /* */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_EN 0:0 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_STAT 1:1 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_STAT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_STAT_PENDING 0x00000001 /* R---V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_STAT_CLEAR 0x00000001 /* -W--C */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_VAL 31:16 /* RWIVF */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_VAL_INIT 0x00002710 /* RWI-V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_VAL_1MS 0x000003E8 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_VAL_10MS 0x00002710 /* RW--V */ #define NV_XVE_BAR_BLOCKER_GR_INTR_TIMEOUT_VAL_50MS 0x0000C350 /* RW--V */ #define NV_XVE_HOT_RESET_WIDTH 0x0000EB4 /* RW-4R */ #define NV_XVE_HOT_RESET_WIDTH__PRIV_LEVEL_MASK 0x00000FE8 /* */ #define NV_XVE_HOT_RESET_WIDTH_VAL 17:0 /* RWCVF */ #define NV_XVE_HOT_RESET_WIDTH_VAL_INIT 0x0000008 /* RWC-V */ #define NV_XVE_MITIGATE_FAULT_INJECTION 0x00000EB8 /* R--4R */ #define NV_XVE_MITIGATE_FAULT_INJECTION_BITS 5:0 /* R-CVF */ #define NV_XVE_MITIGATE_FAULT_INJECTION_BITS_INIT 0x00000000 /* R-C-V */ #define NV_XVE_CYA_7 0x00000EBC /* RW-4R */ #define NV_XVE_CYA_7_RSVD 31:0 /* RWCVF */ #define NV_XVE_CYA_7_RSVD_INIT 0x00000000 /* RWC-V */ #endif // __ga102_dev_nv_xve_h__