/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_mmu_hshub_SW_h__ #define __ga102_dev_mmu_hshub_SW_h__ /* This file is autogenerated. Do not edit */ #define NV_PFB_HSMMU(dev) 0x0000a3ff+(dev)*1024:0x0000a000+(dev)*1024 /* RW--D */ #define NV_PFB_HSMMU__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CTRL(dev) (0x0000a080+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_CTRL__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_VM_PG_SIZE_64KB 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_COMP_FAULT_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_COMP_FAULT_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN_FULL 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN_HALF 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN_QUARTER 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL(dev) (0x0000a0a0+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_UTLB_SIZE 1:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_UTLB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE 3:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE 5:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE 7:6 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE 9:8 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG 11:10 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG 13:12 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE 15:14 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_SIZE 17:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE 19:18 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE 21:20 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG 23:22 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG 25:24 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE 26:26 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE 27:27 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE 29:28 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_SECURE_LOCK 30:30 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_SECURE_LOCK_FALSE 0x0 /* R---V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_SECURE_LOCK_INIT 0x0 /* R---V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_SECURE_LOCK_TRUE 0x1 /* R---V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE 31:31 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH(dev) (0x0000a0a4+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_DISABLE 0:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_BIG_DISABLE 1:1 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_BIG_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_BIG_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_UNFILLED_DISABLE 2:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_UNFILLED_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_UNFILLED_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_ENABLE 3:3 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_ENABLE_TRUE 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH 12:12 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_DISABLE 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_ENABLE 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE 14:13 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_1 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_2 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_4 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_8 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE 16:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_BIG_DISABLE 17:17 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE 18:18 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_ENABLE 19:19 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_ENABLE_TRUE 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH 28:28 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_DISABLE 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_ENABLE 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE 30:29 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_1 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_2 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_4 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_8 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL(dev) (0x0000a0c4+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT 0x00 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT 0x00 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR(dev) (0x0000a0c8+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_VOL_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_VOL_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD(dev) (0x0000a0cc+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_VOL_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_VOL_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PFB_HSMMU_PRI_MMU_PM(dev) (0x0000a084+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_PM__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT 7:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_00 0x00 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_01 0x01 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_02 0x02 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_03 0x03 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_04 0x04 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_05 0x05 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_06 0x06 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_07 0x07 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_08 0x08 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_09 0x09 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_0A 0x0a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_0B 0x0b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_0C 0x0c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_0D 0x0d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_0E 0x0e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_0F 0x0f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_10 0x10 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_11 0x11 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_12 0x12 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_13 0x13 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_14 0x14 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_15 0x15 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_16 0x16 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_17 0x17 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_18 0x18 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_19 0x19 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_1A 0x1a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_1B 0x1b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_1C 0x1c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_1D 0x1d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_1E 0x1e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_1F 0x1f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_20 0x20 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_21 0x21 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_22 0x22 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_23 0x23 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_24 0x24 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_25 0x25 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_26 0x26 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_27 0x27 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_28 0x28 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_29 0x29 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_2A 0x2a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_2B 0x2b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_2C 0x2c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_2D 0x2d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_2E 0x2e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_2F 0x2f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_30 0x30 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_31 0x31 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_32 0x32 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_33 0x33 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_34 0x34 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_35 0x35 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_36 0x36 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_37 0x37 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_38 0x38 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_39 0x39 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_3A 0x3a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_3B 0x3b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_3C 0x3c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_3D 0x3d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_3E 0x3e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_3F 0x3f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_40 0x40 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_41 0x41 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_42 0x42 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_43 0x43 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_44 0x44 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_45 0x45 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_46 0x46 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_47 0x47 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_48 0x48 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_49 0x49 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_4A 0x4a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_4B 0x4b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_4C 0x4c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_4D 0x4d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_4E 0x4e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_4F 0x4f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_50 0x50 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_51 0x51 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_52 0x52 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_53 0x53 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_54 0x54 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_55 0x55 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_56 0x56 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_57 0x57 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_58 0x58 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_59 0x59 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_5A 0x5a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_5B 0x5b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_5C 0x5c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_5D 0x5d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_5E 0x5e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_5F 0x5f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_60 0x60 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_61 0x61 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_62 0x62 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_63 0x63 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_64 0x64 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_65 0x65 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_66 0x66 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_67 0x67 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_68 0x68 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_69 0x69 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_6A 0x6a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_6B 0x6b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_6C 0x6c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_6D 0x6d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_6E 0x6e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_6F 0x6f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_70 0x70 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_71 0x71 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_72 0x72 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_73 0x73 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_74 0x74 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_75 0x75 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_76 0x76 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_77 0x77 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_78 0x78 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_79 0x79 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_7A 0x7a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_7B 0x7b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_7C 0x7c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_7D 0x7d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x7e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x7f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_80 0x80 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_81 0x81 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_82 0x82 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_83 0x83 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_84 0x84 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_85 0x85 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_86 0x86 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_87 0x87 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_88 0x88 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_89 0x89 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_8A 0x8a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_8B 0x8b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_8C 0x8c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_8D 0x8d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_8E 0x8e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_8F 0x8f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_90 0x90 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_91 0x91 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_92 0x92 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_93 0x93 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_94 0x94 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_95 0x95 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_96 0x96 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_97 0x97 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_98 0x98 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_99 0x99 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_9A 0x9a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_9B 0x9b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_9C 0x9c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_9D 0x9d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_9E 0x9e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_9F 0x9f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A0 0xa0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A1 0xa1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A2 0xa2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A3 0xa3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A4 0xa4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A5 0xa5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A6 0xa6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A7 0xa7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A8 0xa8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_A9 0xa9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_AA 0xaa /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_AB 0xab /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_AC 0xac /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_AD 0xad /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_AE 0xae /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_AF 0xaf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B0 0xb0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B1 0xb1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B2 0xb2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B3 0xb3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B4 0xb4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B5 0xb5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B6 0xb6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B7 0xb7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B8 0xb8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_B9 0xb9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_BA 0xba /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_BB 0xbb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_BC 0xbc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_BD 0xbd /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_BE 0xbe /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_BF 0xbf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C0 0xc0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C1 0xc1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C2 0xc2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C3 0xc3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C4 0xc4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C5 0xc5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C6 0xc6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C7 0xc7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C8 0xc8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_C9 0xc9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_CA 0xca /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_CB 0xcb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_CC 0xcc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_CD 0xcd /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_CE 0xce /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_CF 0xcf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D0 0xd0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D1 0xd1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D2 0xd2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D3 0xd3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D4 0xd4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D5 0xd5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D6 0xd6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D7 0xd7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D8 0xd8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_D9 0xd9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_DA 0xda /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_DB 0xdb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_DC 0xdc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_DD 0xdd /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_DE 0xde /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_DF 0xdf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E0 0xe0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E1 0xe1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E2 0xe2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E3 0xe3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E4 0xe4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E5 0xe5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E6 0xe6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E7 0xe7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E8 0xe8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_E9 0xe9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_EA 0xea /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_EB 0xeb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_EC 0xec /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_ED 0xed /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_EE 0xee /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_EF 0xef /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F0 0xf0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F1 0xf1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F2 0xf2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F3 0xf3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F4 0xf4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F5 0xf5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F6 0xf6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F7 0xf7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F8 0xf8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_F9 0xf9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_FA 0xfa /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_FB 0xfb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_FC 0xfc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_GRP_FD 0xfd /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1 15:8 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_00 0x00 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_01 0x01 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_02 0x02 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_03 0x03 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_04 0x04 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_05 0x05 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_06 0x06 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_07 0x07 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_08 0x08 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_09 0x09 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_0A 0x0a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_0B 0x0b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_0C 0x0c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_0D 0x0d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_0E 0x0e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_0F 0x0f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_10 0x10 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_11 0x11 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_12 0x12 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_13 0x13 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_14 0x14 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_15 0x15 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_16 0x16 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_17 0x17 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_18 0x18 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_19 0x19 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_1A 0x1a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_1B 0x1b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_1C 0x1c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_1D 0x1d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_1E 0x1e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_1F 0x1f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_20 0x20 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_21 0x21 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_22 0x22 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_23 0x23 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_24 0x24 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_25 0x25 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_26 0x26 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_27 0x27 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_28 0x28 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_29 0x29 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_2A 0x2a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_2B 0x2b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_2C 0x2c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_2D 0x2d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_2E 0x2e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_2F 0x2f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_30 0x30 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_31 0x31 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_32 0x32 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_33 0x33 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_34 0x34 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_35 0x35 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_36 0x36 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_37 0x37 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_38 0x38 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_39 0x39 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_3A 0x3a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_3B 0x3b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_3C 0x3c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_3D 0x3d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_3E 0x3e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_3F 0x3f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_40 0x40 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_41 0x41 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_42 0x42 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_43 0x43 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_44 0x44 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_45 0x45 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_46 0x46 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_47 0x47 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_48 0x48 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_49 0x49 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_4A 0x4a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_4B 0x4b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_4C 0x4c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_4D 0x4d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_4E 0x4e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_4F 0x4f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_50 0x50 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_51 0x51 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_52 0x52 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_53 0x53 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_54 0x54 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_55 0x55 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_56 0x56 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_57 0x57 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_58 0x58 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_59 0x59 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_5A 0x5a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_5B 0x5b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_5C 0x5c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_5D 0x5d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_5E 0x5e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_5F 0x5f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_60 0x60 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_61 0x61 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_62 0x62 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_63 0x63 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_64 0x64 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_65 0x65 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_66 0x66 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_67 0x67 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_68 0x68 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_69 0x69 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_6A 0x6a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_6B 0x6b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_6C 0x6c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_6D 0x6d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_6E 0x6e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_6F 0x6f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_70 0x70 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_71 0x71 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_72 0x72 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_73 0x73 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_74 0x74 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_75 0x75 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_76 0x76 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_77 0x77 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_78 0x78 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_79 0x79 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_7A 0x7a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_7B 0x7b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_7C 0x7c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_7D 0x7d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x7e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x7f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_80 0x80 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_81 0x81 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_82 0x82 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_83 0x83 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_84 0x84 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_85 0x85 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_86 0x86 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_87 0x87 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_88 0x88 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_89 0x89 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_8A 0x8a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_8B 0x8b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_8C 0x8c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_8D 0x8d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_8E 0x8e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_8F 0x8f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_90 0x90 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_91 0x91 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_92 0x92 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_93 0x93 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_94 0x94 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_95 0x95 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_96 0x96 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_97 0x97 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_98 0x98 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_99 0x99 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_9A 0x9a /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_9B 0x9b /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_9C 0x9c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_9D 0x9d /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_9E 0x9e /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_9F 0x9f /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A0 0xa0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A1 0xa1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A2 0xa2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A3 0xa3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A4 0xa4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A5 0xa5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A6 0xa6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A7 0xa7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A8 0xa8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_A9 0xa9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_AA 0xaa /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_AB 0xab /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_AC 0xac /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_AD 0xad /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_AE 0xae /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_AF 0xaf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B0 0xb0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B1 0xb1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B2 0xb2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B3 0xb3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B4 0xb4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B5 0xb5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B6 0xb6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B7 0xb7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B8 0xb8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_B9 0xb9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_BA 0xba /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_BB 0xbb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_BC 0xbc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_BD 0xbd /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_BE 0xbe /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_BF 0xbf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C0 0xc0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C1 0xc1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C2 0xc2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C3 0xc3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C4 0xc4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C5 0xc5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C6 0xc6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C7 0xc7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C8 0xc8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_C9 0xc9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_CA 0xca /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_CB 0xcb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_CC 0xcc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_CD 0xcd /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_CE 0xce /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_CF 0xcf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D0 0xd0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D1 0xd1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D2 0xd2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D3 0xd3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D4 0xd4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D5 0xd5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D6 0xd6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D7 0xd7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D8 0xd8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_D9 0xd9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_DA 0xda /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_DB 0xdb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_DC 0xdc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_DD 0xdd /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_DE 0xde /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_DF 0xdf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E0 0xe0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E1 0xe1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E2 0xe2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E3 0xe3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E4 0xe4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E5 0xe5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E6 0xe6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E7 0xe7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E8 0xe8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_E9 0xe9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_EA 0xea /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_EB 0xeb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_EC 0xec /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_ED 0xed /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_EE 0xee /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_EF 0xef /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F0 0xf0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F1 0xf1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F2 0xf2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F3 0xf3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F4 0xf4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F5 0xf5 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F6 0xf6 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F7 0xf7 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F8 0xf8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_F9 0xf9 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_FA 0xfa /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_FB 0xfb /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_FC 0xfc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_SELECT_MUX1_GRP_FD 0xfd /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_BLK_ACT_DISABLE 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_BLK_ACT_ENABLE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_BLK_ACT_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_ENABLE 31:31 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_LOW(dev) (0x0000a088+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_LOW__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_LOW(dev) (0x0000a08c+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_LOW__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT 0x000000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_HIGH(dev) (0x0000a090+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_HIGH__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_HIGH(dev) (0x0000a094+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_HIGH__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT 0x000000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK(dev) (0x0000a098+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE0 0:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE0_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE0_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE1 1:1 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE1_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE1_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE2 2:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE2_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE2_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE3 3:3 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE3_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE3_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE4 4:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE4_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE4_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE5 5:5 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE5_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE5_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE6 6:6 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE6_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE6_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE7 7:7 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE7_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE7_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE8 8:8 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE8_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE8_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE9 9:9 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE9_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE9_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE10 10:10 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE10_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE10_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE11 11:11 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE11_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE11_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE12 12:12 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE12_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE12_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE13 13:13 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE13_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE13_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE14 14:14 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE14_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE14_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE15 15:15 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE15_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_CE15_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL0 16:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL0_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL0_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL1 17:17 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL1_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL1_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL2 18:18 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL2_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL2_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL3 19:19 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL3_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL3_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL4 20:20 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL4_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL4_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL5 21:21 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL5_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL5_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL6 22:22 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL6_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL6_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL7 23:23 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL7_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL7_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL8 24:24 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL8_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL8_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL9 25:25 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL9_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL9_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL10 26:26 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL10_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL10_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL11 27:27 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL11_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL11_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL12 28:28 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL12_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL12_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL13 29:29 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL13_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL13_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL14 30:30 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL14_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL14_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL15 31:31 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL15_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_UNIT_MASK_NVL15_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK(dev) (0x0000a09c+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_RD_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_WR_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_WR_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_GRED_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PEER_ENABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_PEER_DISABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0(dev) (0x0000a0d4+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE 2:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_32MB 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_64MB 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_128MB 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_256MB 0x3 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_512MB 0x4 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_INIT 0x3 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID 31:22 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID_INIT 0x180 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_SRIOV_VMMU_TABLE(dev,i) (0x0000a0d8+(dev)*1024+(i)*4) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_2 12 /* */ #define NV_PFB_HSMMU_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP 31:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP_INIT 0x00000000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK(dev) (0x0000a3fc+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0xc /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0004c /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL(dev) (0x0000a3f8+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK(dev) (0x0000a3fc+(dev)*1024) /* */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS(dev) (0x0000a3f4+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT(dev) (0x0000a3f0+(dev)*1024) /* R--4A */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* R-E-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* R-E-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT(dev) (0x0000a3ec+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_ADDRESS(dev) (0x0000a3e8+(dev)*1024) /* R--4A */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_ADDRESS__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL(dev) (0x0000a3e4+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK(dev) (0x0000a3fc+(dev)*1024) /* */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS(dev) (0x0000a3e0+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT(dev) (0x0000a3dc+(dev)*1024) /* R--4A */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* R-E-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* R-E-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT(dev) (0x0000a3d8+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS(dev) (0x0000a3d4+(dev)*1024) /* R--4A */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_HSHUBMMU_GLOBAL_ESR(dev) (0x0000a3d0+(dev)*1024) /* R-E4A */ #define NV_PFB_HSMMU_PRI_MMU_HSHUBMMU_GLOBAL_ESR__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PFB_HSMMU_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PFB_HSMMU_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PFB_HSMMU_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PFB_HSMMU_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PFB_HSMMU_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG(dev) (0x0000a3cc+(dev)*1024) /* RWE4A */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i) ((i)*4+1):((i)*4) /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x2 /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x3 /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PFB_HSMMU_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT(dev) (0x0000a110+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT 0x1 /* R-E-V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x5 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO(dev) (0x0000a114+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI(dev) (0x0000a118+(dev)*1024) /* RW-4A */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CG(dev) (0x0000a0b0+(dev)*1024) /* RWE4A */ #define NV_PFB_HSMMU_PRI_MMU_CG__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG1(dev) (0x0000a0b4+(dev)*1024) /* RWE4A */ #define NV_PFB_HSMMU_PRI_MMU_CG1__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG1_SLCG 8:1 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PG(dev) (0x0000a0b8+(dev)*1024) /* RWE4A */ #define NV_PFB_HSMMU_PRI_MMU_PG__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_DIDT_DELAY_HWINIT 0xa /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_RESET_DURATION_HWINIT 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_CLAMP_DELAY_HWINIT 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU_PRI_MMU_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG1(dev) (0x0000a0c0+(dev)*1024) /* RWE4A */ #define NV_PFB_HSMMU_PRI_MMU_PG1__SIZE_1 1 /* */ #define NV_PFB_HSMMU_PRI_MMU_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWE-V */ #define NV_PFB_HSMMU_PRI_MMU_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PFB_HSMMU_PRI_MMU_PG1_ZONE_MASK_HWINIT 0xff /* RWE-V */ #endif // __ga102_dev_mmu_hshub_SW_h__