/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2003-2016 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

#ifndef __ga102_dev_falcon_v1_h__
#define __ga102_dev_falcon_v1_h__
/* This file is autogenerated.  Do not edit */
#define NV_FALCON_NVDEC_BASE            0x00848000
#define NV_FALCON_NVDEC0_BASE           0x00848000
#define NV_FALCON_NVDEC1_BASE           0x0084c000
#define NV_FALCON_NVDEC2_BASE           0x00850000
#define NV_FALCON_NVDEC3_BASE           0x00854000
#define NV_FALCON_NVDEC4_BASE           0x00858000
#define NV_FALCON_MSVLD_BASE            0x00830000
#define NV_FALCON_MSPDEC_BASE           0x00831000
#define NV_FALCON_MSPPP_BASE            0x00832000
#define NV_FALCON_SEC_BASE              0x00087000
#define NV_FALCON_PWR_BASE              0x0010a000
#define NV_FALCON_CE0_BASE              0x00104000
#define NV_FALCON_CE1_BASE              0x00105000
#define NV_PCE_CE2_BASE                                     0x00106000
#define NV_FALCON_MSENC_BASE            0x001c2000
#define NV_FALCON_NVENC_BASE            0x001c8000
#define NV_FALCON_HDA_BASE              0x001c3000
#endif // __ga102_dev_falcon_v1_h__