/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_ctxsw_prog_h__ #define __ga102_dev_ctxsw_prog_h__ /* This file is autogenerated. Do not edit */ #define NV_CTXSW 0x000FFFFF:0x00000000 /* RW--D */ #define NV_CTXSW_CTXSW_HEADER 0x00000000 /* RW-4R */ #define NV_CTXSW_CTXSW_HEADER_SIZE_IN_BYTES 512 /* */ #define NV_CTXSW_FECS_HEADER 0x00000200 /* RW-4R */ #define NV_CTXSW_FECS_HEADER_SIZE_IN_BYTES 512 /* */ #define NV_CTXSW_GPCCS_HEADER(i) (0x00000400+(i)*512) /* RW-4A */ #define NV_CTXSW_GPCCS_HEADER__SIZE_1 8 /* */ #define NV_CTXSW_GPCCS_HEADER__STRIDE 512 /* */ #define NV_CTXSW_GPCCS_HEADER_SIZE_IN_BYTES 512 /* */ #define NV_CTXSW_MAIN_IMAGE_POOL_PTR 0x00000000 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_POOL_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_SIZE 0x00000004 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 0x00000008 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CTL 0x0000000C /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CTL_TYPE 5:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CTL_TYPE_UNDEFINED 0x0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_TYPE_OPENGL 0x8 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_TYPE_DX9 0x10 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_TYPE_DX10 0x11 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_TYPE_DX11 0x12 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_TYPE_COMPUTE 0x20 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_TYPE_PER_VEID_HEADER 0x21 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_INT_AFTER_RESTORE 9:8 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CTL_INT_AFTER_RESTORE_NEVER 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_INT_AFTER_RESTORE_ONCE 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_INT_AFTER_RESTORE_ALWAYS 2 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CTL_MAGIC_VALUE 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CTL_MAGIC_VALUE_VALUE 0x0000cafe /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 0x00000010 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 0x00000014 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 0x00000018 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_ZCULL 0x0000001c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_GLOBAL 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_PART_OF_REGULAR_BUF 3 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 0x00000020 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_SIZE 0x00000024 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PM 0x00000028 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PM_MODE_CTXSW 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PM_MODE_STREAM_OUT_CTXSW 2 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x0000002c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PM_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PM_SIZE 0x00000030 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_NUM_FBPS 0x00000034 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_ACCESS_HEADER 0x00000038 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_ACCESS_HEADER_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_ACCESS_HEADER_TYPE 19:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_ACCESS_HEADER_TYPE_MAIN 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_ACCESS_HEADER_TYPE_LOCAL 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_ACCESS_HEADER_INDEX 31:20 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_DYNAMIC_GFXP 0x00000038 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_DYNAMIC_GFXP_STATE 7:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_DYNAMIC_GFXP_STATE_NOT_GFXP_CAPABLE 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_DYNAMIC_GFXP_STATE_GFXP_CAPABLE 2 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_DYNAMIC_GFXP_STATE_GFXP_ENABLED 3 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_DYNAMIC_GFXP_SLOT_ID 15:8 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x0000003c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_SM_PRI_WAR 2:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_SM_PRI_WAR_DISABLED 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_SM_PRI_WAR_ENABLED 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES_DISABLED 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES_ENABLED 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_DYNAMIC_TPC_PG 4:4 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_DYNAMIC_TPC_PG_DISABLED 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_DYNAMIC_TPC_PG_ENABLED 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_0 0x00000040 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_0_GPC0 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_0_GPC1 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_1 0x00000044 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_1_GPC2 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_1_GPC3 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_2 0x00000048 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_2_GPC4 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_2_GPC5 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_3 0x0000004c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_3_GPC6 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_3_GPC7 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_4 0x00000050 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_4_GPC8 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_4_GPC9 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_5 0x00000054 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_5_GPC10 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_5_GPC11 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_6 0x00000058 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_6_GPC12 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_6_GPC13 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_7 0x0000005c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_7_GPC14 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GPC_TPC_MASK_7_GPC15 31:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR_HI 0x00000060 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_FULL_PREEMPTION_PTR_HI 0x00000064 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_FULL_PREEMPTION_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_FULL_PREEMPTION_PTR 0x00000068 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_FULL_PREEMPTION_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_SIZE 0x0000006c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_FULL_PREEMPTION_PTR_VEID0_HI 0x00000070 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_FULL_PREEMPTION_PTR_VEID0_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_FULL_PREEMPTION_PTR_VEID0 0x00000074 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_FULL_PREEMPTION_PTR_VEID0_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_BUFFER_PTR_HI 0x00000078 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_BUFFER_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_BUFFER_PTR 0x0000007c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_BUFFER_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GRAPHICS_PREEMPTION_OPTIONS 0x00000080 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GRAPHICS_PREEMPTION_OPTIONS_CONTROL 1:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GRAPHICS_PREEMPTION_OPTIONS_CONTROL_WFI 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_GRAPHICS_PREEMPTION_OPTIONS_CONTROL_GFXP 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_COMPUTE_PREEMPTION_OPTIONS 0x00000084 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_COMPUTE_PREEMPTION_OPTIONS_CONTROL 1:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_COMPUTE_PREEMPTION_OPTIONS_CONTROL_WFI 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_COMPUTE_PREEMPTION_OPTIONS_CONTROL_CTA 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_COMPUTE_PREEMPTION_OPTIONS_CONTROL_CILP 2 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE 0x00000088 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_GFX 3:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_GFX_WFI 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_GFX_GFXP 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_COMPUTE 7:4 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_COMPUTE_WFI 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_COMPUTE_CTA 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_COMPUTE_CILP 2 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_CONTEXT_PREEMPTED 8:8 /* R--VF */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_CONTEXT_PREEMPTED_FALSE 0 /* R---V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TYPE_ISSUED_BY_FE_CONTEXT_PREEMPTED_TRUE 1 /* R---V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TEST_OPTIONS 0x0000008c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TEST_OPTIONS_CONTROL 1:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TEST_OPTIONS_CONTROL_NONE 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TEST_OPTIONS_CONTROL_SKIP_SAVE_RESET_RESTORE 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TEST_OPTIONS_SAVE_COMPLETION_INTERRUPT 4:4 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TEST_OPTIONS_SAVE_COMPLETION_INTERRUPT_DISABLED 0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PREEMPTION_TEST_OPTIONS_SAVE_COMPLETION_INTERRUPT_ENABLED 1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_NUM_ROPS 0x00000090 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PM_PTR_HI 0x00000094 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PM_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_RTV_PTR 0x00000098 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_RTV_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_RTV_PTR_HI 0x0000009c /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_RTV_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0x000000a0 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0x00000000 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_NONE 0x00000001 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 0x00000002 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0x000000a4 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0x000000a8 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_CONTROL 0x000000ac /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_CONTROL_NUM_RECORDS 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI 0x000000b0 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR 0x000000b4 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_CB_PTR 0x000000b8 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_CB_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_CB_PTR_HI 0x000000bc /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_CB_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_PAGEPOOL_PTR 0x000000c0 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_PAGEPOOL_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_PAGEPOOL_PTR_HI 0x000000c4 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_GLOBAL_PAGEPOOL_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CONTROL_BLOCK_PTR 0x000000c8 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CONTROL_BLOCK_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CONTROL_BLOCK_PTR_HI 0x000000cc /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CONTROL_BLOCK_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_NUM_WFI_SAVE_OPERATIONS 0x000000d0 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_NUM_CTA_SAVE_OPERATIONS 0x000000d4 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_NUM_GFXP_SAVE_OPERATIONS 0x000000d8 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_NUM_CILP_SAVE_OPERATIONS 0x000000dc /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_SMC_INFO 0x000000e0 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_SMC_INFO_MODE 0:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_SMC_INFO_MODE_LEGACY 0x0 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_SMC_INFO_MODE_SMC 0x1 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_POOL_PTR_HI 0x000000e8 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_POOL_PTR_HI_V 16:0 /* RWXVF */ #define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0x000000ec /* RW-4R */ #define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CONTEXT_ID 0x000000f0 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0x000000f4 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0x000000f8 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_1 0x000000fc /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_1_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_1_V_VALUE 0x600dc0de /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_2 0x00000100 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_2_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_2_V_VALUE 0xdeadce11 /* RW--V */ #define NV_CTXSW_MAIN_IMAGE_CLIENT_CONTEXT_HANDLE_LO 0x00000104 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CLIENT_CONTEXT_HANDLE_LO_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_CLIENT_CONTEXT_HANDLE_HI 0x00000108 /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_CLIENT_CONTEXT_HANDLE_HI_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_3 0x000001fc /* RW-4R */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_3_V 31:0 /* RWXVF */ #define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_3_V_VALUE 0xfaceb00c /* RW--V */ #define NV_CTXSW_LOCAL_IMAGE_SIZE 0x00000000 /* RW-4R */ #define NV_CTXSW_LOCAL_IMAGE_CTL 0x00000004 /* RW-4R */ #define NV_CTXSW_LOCAL_IMAGE_CTL_NUM_RAMCHAINS 4:0 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_CTL_GFXP_CTX 5:5 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_CTL_SKIP_SWDX_DIRECT_CTXSW 6:6 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_CTL_MAGIC_VALUE 31:16 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_CTL_MAGIC_VALUE_VALUE 0x0000ca11 /* RW--V */ #define NV_CTXSW_LOCAL_IMAGE_RAMCHAIN_ENABLE 0x00000008 /* RW-4R */ #define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 0x0000000c /* RW-4R */ #define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_SIZE 23:16 /* RWXVF */ #define NV_CTXSW_LOCAL_PRI_REGISTER_IMAGE_SIZE 0x00000010 /* RW-4R */ #define NV_CTXSW_LOCAL_RAMCHAIN_IMAGE_SIZE 0x00000014 /* RW-4R */ #define NV_CTXSW_LOCAL_TPCID_TO_CILPID(i) (0x00000018+(i)*4) /* RW-4A */ #define NV_CTXSW_LOCAL_TPCID_TO_CILPID__SIZE_1 7 /* */ #define NV_CTXSW_LOCAL_TPCID_TO_CILPID_NUM_TPCS_PER_REG 5 /* */ #define NV_CTXSW_LOCAL_TPCID_TO_CILPID_BITS_PER_TPC 6 /* */ #define NV_CTXSW_LOCAL_TPCID_TO_CILPID_TPC_FIELD 5:0 /* RWXVF */ #define NV_CTXSW_LOCAL_GFXP_IMAGE_SIZE 0x00000094 /* RW-4R */ #define NV_CTXSW_LOCAL_GFXP_RAMCHAIN_OFFSET 0x00000098 /* RW-4R */ #define NV_CTXSW_LOCAL_GFXP_RAMCHAIN_OFFSET_V 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_ZCULL_IMAGE_SIZE 0x0000009c /* RW-4R */ #define NV_CTXSW_LOCAL_ZCULL_PRIV_REGISTER_CTL 0x000000a0 /* RW-4R */ #define NV_CTXSW_LOCAL_ZCULL_PRIV_REGISTER_CTL_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_ZCULL_PRIV_REGISTER_CTL_SIZE 23:16 /* RWXVF */ #define NV_CTXSW_LOCAL_GFXP_RAMCHAIN_CTL(i) (0x000000a4+(i)*8) /* RW-4A */ #define NV_CTXSW_LOCAL_GFXP_RAMCHAIN_CTL__SIZE_1 8 /* */ #define NV_CTXSW_LOCAL_GFXP_RAMCHAIN_CTL_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_GFXP_RAMCHAIN_SAVE(i) (0x000000a8+(i)*8) /* RW-4A */ #define NV_CTXSW_LOCAL_GFXP_RAMCHAIN_SAVE__SIZE_1 8 /* */ #define NV_CTXSW_LOCAL_GFXP_RAMCHAIN_SAVE_WORDS 23:0 /* RWXVF */ #define NV_CTXSW_LOCAL_PM_IMAGE_SIZE 0x000000e4 /* RW-4R */ #define NV_CTXSW_LOCAL_PM_PRIV_REGISTER_CTL 0x000000e8 /* RW-4R */ #define NV_CTXSW_LOCAL_PM_PRIV_REGISTER_CTL_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_PM_PRIV_REGISTER_CTL_SIZE 23:16 /* RWXVF */ #define NV_CTXSW_LOCAL_PM_PRIV_REGISTER_CTL2 0x000000ec /* RW-4R */ #define NV_CTXSW_LOCAL_PM_PRIV_REGISTER_CTL2_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_PM_PRIV_REGISTER_CTL2_SIZE 23:16 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_EXTENDED_BUFFER 0x000000f0 /* RW-4R */ #define NV_CTXSW_LOCAL_IMAGE_EXTENDED_BUFFER_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_EXTENDED_BUFFER_SIZE 23:16 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0x000000f4 /* RW-4R */ #define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 /* RWXVF */ #define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0x000000f8 /* RW-4R */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_1 0x000000fc /* RW-4R */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_1_V 31:0 /* RWXVF */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_1_V_VALUE 0xad0becab /* RW--V */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_2 0x00000100 /* RW-4R */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_2_V 31:0 /* RWXVF */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_2_V_VALUE 0x1ceb00da /* RW--V */ #define NV_CTXSW_LOCAL_RAMCHAIN_CTL(i) (0x00000104+(i)*8) /* RW-4A */ #define NV_CTXSW_LOCAL_RAMCHAIN_CTL__SIZE_1 31 /* */ #define NV_CTXSW_LOCAL_RAMCHAIN_CTL_OFFSET 15:0 /* RWXVF */ #define NV_CTXSW_LOCAL_RAMCHAIN_SAVE(i) (0x00000108+(i)*8) /* RW-4A */ #define NV_CTXSW_LOCAL_RAMCHAIN_SAVE__SIZE_1 31 /* */ #define NV_CTXSW_LOCAL_RAMCHAIN_SAVE_WORDS 23:0 /* RWXVF */ #define NV_CTXSW_LOCAL_RAMCHAIN_SAVE_CLASS 29:28 /* RWXVF */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_3 0x000001fc /* RW-4R */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_3_V 31:0 /* RWXVF */ #define NV_CTXSW_LOCAL_MAGIC_VALUE_3_V_VALUE 0xf00dbeef /* RW--V */ #define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 256 /* */ #define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 /* */ #define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 2 /* */ #define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL0 0 /* */ #define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL5 1 /* */ #define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 0 /* */ #define NV_CTXSW_RECORD_TIMESTAMP_RECORD_SIZE_IN_BYTES 128 #define NV_CTXSW_RECORD_TIMESTAMP_RECORD_SIZE_IN_WORDS (128 >> 2) #define NV_CTXSW_RECORD_TIMESTAMP_MAGIC_VALUE_LO 0x00000000 /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_MAGIC_VALUE_LO_V 31:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_MAGIC_VALUE_LO_V_VALUE 0x00000000 /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_MAGIC_VALUE_HI 0x00000004 /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_MAGIC_VALUE_HI_V 31:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_MAGIC_VALUE_HI_V_VALUE 0x600dbeef /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_CONTEXT_ID 0x00000008 /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_CONTEXT_ID_V 31:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_CONTEXT_PTR 0x0000000c /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_CONTEXT_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_NEW_CONTEXT_ID 0x00000010 /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_NEW_CONTEXT_ID_V 31:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_NEW_CONTEXT_PTR 0x00000014 /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_NEW_CONTEXT_PTR_V 31:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_LO 0x00000018 /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_LO_V 31:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI 0x0000001c /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_V 23:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG 31:24 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_CTXSW_REQ_BY_HOST 0x1 /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK 0x2 /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_WFI 0xa /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_GFXP 0xb /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_CTAP 0xc /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_CILP 0xd /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_SAVE_END 0x3 /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_RESTORE_START 0x4 /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_CONTEXT_START 0x5 /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_INVALID_TIMESTAMP 0xff /* RW--V */ #define NV_CTXSW_RECORD_TIMESTAMP_CLIENT_CONTEXT_HANDLE_LO 0x00000078 /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_CLIENT_CONTEXT_HANDLE_LO_V 31:0 /* RWXVF */ #define NV_CTXSW_RECORD_TIMESTAMP_CLIENT_CONTEXT_HANDLE_HI 0x0000007c /* RW-4R */ #define NV_CTXSW_RECORD_TIMESTAMP_CLIENT_CONTEXT_HANDLE_HI_V 31:0 /* RWXVF */ #define NV_CTXSW_TIMESTAMP_BUFFER_RD_WR_POINTER 30:0 /* */ #define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE 31:31 /* */ #define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE_ENABLED 0x1 /* */ #define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE_DISABLED 0x0 /* */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_PREEMPT_OFFSET 0x00000000 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_PREEMPT_OFFSET_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SPILL_OFFSET 0x00000004 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SPILL_OFFSET_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_CB_OFFSET 0x00000008 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_CB_OFFSET_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_PAGEPOOL_OFFSET 0x0000000c /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_PAGEPOOL_OFFSET_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_STRIDE 0x00000010 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_STRIDE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_BETA_SIZE 0x00000014 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_BETA_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_ALPHA_SIZE 0x00000018 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_ALPHA_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_PAGEPOOL_SIZE 0x0000001c /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_PAGEPOOL_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_BETA_SIZE 0x00000020 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_BETA_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_ALPHA_SIZE 0x00000024 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_ALPHA_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_PAGEPOOL_SIZE 0x00000028 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_PAGEPOOL_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_SPILL_SIZE 0x0000002c /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_SPILL_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_NUM_SLICES 0x00000030 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_NUM_SLICES_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY1 0x00000034 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY1_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY2 0x00000038 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY2_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY3 0x0000003c /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY3_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY4 0x00000040 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY4_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY1 0x00000044 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY1_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY2 0x00000048 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY2_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY3 0x0000004c /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY3_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY4 0x00000050 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY4_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_MAX_SLICES 0x00000054 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_MAX_SLICES_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_RTV_SIZE 0x00000058 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_RTV_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_RTV_SIZE 0x0000005c /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_RTV_SIZE_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RTV_OFFSET 0x00000060 /* RW-4R */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_RTV_OFFSET_V 31:0 /* RWXVF */ #define NV_CTXSW_GFXP_POOL_CTRL_BLK_SIZE 0x00000064 /* RW-4R */ #define NV_CTXSW_READ_PHYS_MEM_DATA_WORD 0x00000000 /* RW-4R */ #define NV_CTXSW_READ_PHYS_MEM_DATA_WORD_TARGET 17:16 /* RWXVF */ #define NV_CTXSW_READ_PHYS_MEM_DATA_WORD_TARGET_SYS_MEM_COHERENT 0x2 /* RW--V */ #define NV_CTXSW_READ_PHYS_MEM_DATA_WORD_TARGET_SYS_MEM_NONCOHERENT 0x3 /* RW--V */ #define NV_CTXSW_READ_PHYS_MEM_DATA_WORD_PHYS_ADDR_UPPER 7:0 /* RWXVF */ #define NV_CTXSW_READ_PHYS_MEM_MAILBOX4 0x00000000 /* RW-4R */ #define NV_CTXSW_READ_PHYS_MEM_MAILBOX4_PHYS_ADDR_LOWER 31:0 /* RWXVF */ #define NV_CTXSW_READ_PHYS_MEM_MAILBOX1 0x00000000 /* RW-4R */ #define NV_CTXSW_READ_PHYS_MEM_MAILBOX1_READ_DATA 31:0 /* RWXVF */ #define NV_CTXSW_ENABLE_PHYS_MEM_READS_WORD 0x00000000 /* RW-4R */ #define NV_CTXSW_ENABLE_PHYS_MEM_READS_WORD_DEVICE_ENABLE 16:0 /* RWXVF */ #define NV_CTXSW_ENABLE_PHYS_MEM_READS_WORD_DEVICE_ENABLE_GV11B 0xde01 /* RW--V */ #define NV_CTXSW_ENABLE_PHYS_MEM_READS_MAILBOX0_ENABLE_STATUS 0x00000000 /* RW-4R */ #define NV_CTXSW_ENABLE_PHYS_MEM_READS_MAILBOX0_ENABLE_STATUS_FAIL 0x0 /* RW--V */ #define NV_CTXSW_ENABLE_PHYS_MEM_READS_MAILBOX0_ENABLE_STATUS_SUCCESS 0x1 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK 0x0000a000 /* RWI4R */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK 0x0000a100 /* RWI4R */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x0000a200 /* RWI4R */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK 0x0000a300 /* RWI4R */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x0000a400 /* RWI4R */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x0000a500 /* RWI4R */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK 0x00003a00 /* RWI4R */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK 0x0000a600 /* RWI4R */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0000a700 /* RWI4R */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x0000f400 /* RWI4R */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x0000fc00 /* RWI4R */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x0000fd00 /* RWI4R */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x0000fe00 /* RWI4R */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x0000ff00 /* RWI4R */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x00006300+(i)*1024) /* RW-4A */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x0000ac00+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK 0x00006400 /* RW-4R */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x00006500 /* RW-4R */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK 0x00006600 /* RW-4R */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x00006700 /* RW-4R */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK 0x00006800 /* RW-4R */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x00006900 /* RW-4R */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x00006a00 /* RW-4R */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x00006c00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK 0x00006f00 /* RW-4R */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x00007800 /* RW-4R */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x00007900 /* RW-4R */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK 0x00007a00 /* RW-4R */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK 0x00007b00 /* RW-4R */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x00007c00 /* RW-4R */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK 0x00007d00 /* RW-4R */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x00007e00 /* RW-4R */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK 0x00007f00 /* RW-4R */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK 0x00008800 /* RW-4R */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x00008900 /* RW-4R */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK 0x00008b00 /* RW-4R */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_IRQSSET 0x00000000 /* -W-4R */ #define NV_CTXSW_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ1_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ2_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ3_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ4_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ5_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ6_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ7_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ8_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR 0x00000100 /* -W-4R */ #define NV_CTXSW_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSTAT 0x00000200 /* R--4R */ #define NV_CTXSW_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMODE 0x00000300 /* RW-4R */ #define NV_CTXSW_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_INIT 0x000000fc /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK 0x00003800 /* RW-4R */ #define NV_CTXSW_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x00006900 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMSET 0x00000400 /* -W-4R */ #define NV_CTXSW_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR 0x00000500 /* -W-4R */ #define NV_CTXSW_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMASK 0x00000600 /* R--4R */ #define NV_CTXSW_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQDEST 0x00000700 /* RW-4R */ #define NV_CTXSW_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2 0x00000f00 /* RW-4R */ #define NV_CTXSW_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_GPTMRINT 0x00000800 /* RW-4R */ #define NV_CTXSW_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CTXSW_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_GPTMRVAL 0x00000900 /* RW-4R */ #define NV_CTXSW_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CTXSW_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_GPTMRCTL 0x00000a00 /* RW-4R */ #define NV_CTXSW_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER0 0x00000b00 /* R--4R */ #define NV_CTXSW_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x00006f00 /* */ #define NV_CTXSW_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_PTIMER1 0x00000c00 /* R--4R */ #define NV_CTXSW_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x00006f00 /* */ #define NV_CTXSW_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_WDTMRVAL 0x00000d00 /* RW-4R */ #define NV_CTXSW_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0000a700 /* */ #define NV_CTXSW_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMRCTL 0x00000e00 /* RW-4R */ #define NV_CTXSW_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0000a700 /* */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_MTHDDATA 0x00001900 /* R--4R */ #define NV_CTXSW_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_CTXSW_FALCON_MTHDID 0x00001a00 /* RW-4R */ #define NV_CTXSW_FALCON_MTHDID__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_CTXSW_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_CTXSW_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_CTXSW_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_CTXSW_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_MTHDWDAT 0x00001b00 /* RW-4R */ #define NV_CTXSW_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_MTHDCOUNT 0x00001c00 /* R--4R */ #define NV_CTXSW_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_CTXSW_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_MTHDPOP 0x00001d00 /* -W-4R */ #define NV_CTXSW_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_MTHDRAMSZ 0x00001e00 /* RW-4R */ #define NV_CTXSW_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CURCTX 0x00001400 /* RW-4R */ #define NV_CTXSW_FALCON_CURCTX__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_CTXSW_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_NXTCTX 0x00001500 /* RW-4R */ #define NV_CTXSW_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_CTXSW_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CTXACK 0x00001600 /* -W-4R */ #define NV_CTXSW_FALCON_CTXACK__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_MAILBOX0 0x00001000 /* RW-4R */ #define NV_CTXSW_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_MAILBOX1 0x00001100 /* RW-4R */ #define NV_CTXSW_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN 0x00001200 /* RW-4R */ #define NV_CTXSW_FALCON_ITFEN__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_CTXSW_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IDLESTATE 0x00001300 /* RW-4R */ #define NV_CTXSW_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x00007800 /* */ #define NV_CTXSW_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_CTXSW_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_FHSTATE 0x00001700 /* R--4R */ #define NV_CTXSW_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x00007900 /* */ #define NV_CTXSW_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_CTXSW_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_CTXSW_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_CTXSW_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_CTXSW_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_PRIVSTATE 0x00001800 /* RW-4R */ #define NV_CTXSW_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x0000f400 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SFTRESET 0x00001f00 /* RW-4R */ #define NV_CTXSW_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_CTXSW_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL 0x00002900 /* RW-4R */ #define NV_CTXSW_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_CTXSW_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_CTXSW_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_CTXSW_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_CTXSW_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_CTXSW_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_CTXSW_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ADDR 0x00002b00 /* RW-4R */ #define NV_CTXSW_FALCON_ADDR__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_ADDR_LSB 5:0 /* RWIVF */ #define NV_CTXSW_FALCON_ADDR_LSB_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_CTXSW_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ADDR_EXT 11:0 /* */ #define NV_CTXSW_FALCON_DMACTL 0x00004300 /* RW-4R */ #define NV_CTXSW_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_CTXSW_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_CTXSW_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_CTXSW_FALCON_DMATRFBASE 0x00004400 /* RW-4R */ #define NV_CTXSW_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMATRFMOFFS 0x00004500 /* RW-4R */ #define NV_CTXSW_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMATRFCMD 0x00004600 /* RW-4R */ #define NV_CTXSW_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_CTXSW_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_CTXSW_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_CTXSW_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFFBOFFS 0x00004700 /* RW-4R */ #define NV_CTXSW_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_FB 0x00004800 /* RW-4R */ #define NV_CTXSW_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_CP 0x00004900 /* RW-4R */ #define NV_CTXSW_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x0000b000 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x0000b100 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x0000b200 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x0000b300 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x0000b400 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x0000b500 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x0000b600 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x0000b700 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CTL 0x0000b800 /* RW-4R */ #define NV_CTXSW_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_HIGH 0x0000b900 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_LOW 0x0000ba00 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_IMEMC(i) (0x00006000+(i)*1024) /* RW-4A */ #define NV_CTXSW_FALCON_IMEMC__SIZE_1 1 /* */ #define NV_CTXSW_FALCON_IMEMC__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEMD(i) (0x00006100+(i)*1024) /* RW-4A */ #define NV_CTXSW_FALCON_IMEMD__SIZE_1 1 /* */ #define NV_CTXSW_FALCON_IMEMD__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMEMT(i) (0x00006200+(i)*1024) /* RW-4A */ #define NV_CTXSW_FALCON_IMEMT__SIZE_1 1 /* */ #define NV_CTXSW_FALCON_IMEMT__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMEMT_FAULT_CORRECTED 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMT_FAULT_CORRECTED_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEMT_FAULT_UNCORRECTED 17:17 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMT_FAULT_UNCORRECTED_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEMC(i) (0x00007000+(i)*512) /* RW-4A */ #define NV_CTXSW_FALCON_DMEMC__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_DMEMC__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_CTXSW_FALCON_DMEMC_OFFS_INIT 0 /* */ #define NV_CTXSW_FALCON_DMEMC_BLK 23:8 /* */ #define NV_CTXSW_FALCON_DMEMC_BLK_INIT 0 /* */ #define NV_CTXSW_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_CTXSW_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_CTXSW_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_CTXSW_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEMD(i) (0x00007100+(i)*512) /* RW-4A */ #define NV_CTXSW_FALCON_DMEMD__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_DMEMD__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_DMEMT(i) (0x00008400+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_DMEMT__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_DMEMT__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_CTXSW_FALCON_DMEMT_FAULTED 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_DMEMT_FAULTED_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEML(i) (0x0000a800+(i)*256) /* -W-4A */ #define NV_CTXSW_FALCON_DMEML__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_DMEML__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_CTXSW_FALCON_DMEM_DUMMY 0x00009600 /* R--4R */ #define NV_CTXSW_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_CTXSW_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x0000a100 /* */ #define NV_CTXSW_FALCON_IMEM_DUMMY 0x00006d00 /* R--4R */ #define NV_CTXSW_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_CTXSW_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x0000a000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x0000c000+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x0000fc00 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x0000c400+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x0000fd00 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x0000c800+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x0000fe00 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x0000cc00+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x0000ff00 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PRGNVER 0x0000f500 /* R-I4R */ #define NV_CTXSW_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_CTXSW_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */ #define NV_CTXSW_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_CTXSW_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_CTXSW_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG 0x00004200 /* R--4R */ #define NV_CTXSW_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_CTXSW_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_CTXSW_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG1 0x00004b00 /* R--4R */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000002 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000004 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2 0x00003d00 /* R--4R */ #define NV_CTXSW_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG3 0x00009e00 /* R--4R */ #define NV_CTXSW_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_CTXSW_FALCON_CGCTL 0x00002800 /* RW-4R */ #define NV_CTXSW_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CG2 0x00004d00 /* RWI4R */ #define NV_CTXSW_FALCON_CG2__PRIV_LEVEL_MASK 0x00007a00 /* */ #define NV_CTXSW_FALCON_CG2_SLCG 17:1 /* */ #define NV_CTXSW_FALCON_CG2_SLCG_ENABLED 0 /* */ #define NV_CTXSW_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */ #define NV_CTXSW_FALCON_CG2_SLCG__PROD 0x000A0 /* */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL 0x00009000 /* RW-4R */ #define NV_CTXSW_FALCON_SCTL__PRIV_LEVEL_MASK 0x0000a600 /* */ #define NV_CTXSW_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_CTXSW_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_CTXSW_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */ #define NV_CTXSW_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL1 0x00009400 /* RW-4R */ #define NV_CTXSW_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL 0x00003900 /* RW-4R */ #define NV_CTXSW_FALCON_HSCTL__PRIV_LEVEL_MASK 0x00003a00 /* */ #define NV_CTXSW_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_ERB 0x0000bb00 /* -W-4R */ #define NV_CTXSW_FALCON_SAFETY_ERB_DATA 31:0 /* -WXVF */ #define NV_CTXSW_FALCON_SAFETY_ERB_DATA_CORRECTED_ERR 0xeafe0c00 /* -W--V */ #define NV_CTXSW_FALCON_SAFETY_ERB_DATA_UNCORRECTED_ERR 0xeafe1cff /* -W--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX 0x0000bc00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_DATA 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRADDR 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRADDR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE 31:24 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PF 0x000000f0 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PF 0x000000f1 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_SCP 0x000000f2 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_SCP 0x000000f3 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_SCP 0x000000f3 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_DMA 0x000000f4 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_DMA 0x000000f5 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_DMA 0x000000f5 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PMB 0x000000f6 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PMB 0x000000f7 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_PMB 0x000000f7 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_LDST 0x000000f8 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_PMB 0x000000f9 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_DMA 0x000000fa /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_SCP 0x000000fb /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_SHA 0x000000fc /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_SHA 0x000000fd /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_RISCV 0x000000fe /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_RISCV 0x000000ff /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IROM 0x000000e0 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IROM 0x000000e1 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL 0x0000bd00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x00006c00 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS 5:4 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_INIT 0x00000002 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_IMEM_ECC_DIS 1:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_INIT 0x00000002 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR 0x0000be00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_VALUE 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_HI 0x0000bf00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_HI_VALUE 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_OS 0x00002000 /* RW-4R */ #define NV_CTXSW_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_RM 0x00002100 /* RW-4R */ #define NV_CTXSW_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SOFT_PM 0x00002200 /* RW-4R */ #define NV_CTXSW_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CTXSW_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_CTXSW_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_CTXSW_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SOFT_MODE 0x00002300 /* RW-4R */ #define NV_CTXSW_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CTXSW_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_CTXSW_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM 0x00002a00 /* RW-4R */ #define NV_CTXSW_FALCON_PMM__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_CODE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_IPND 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_SB 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0000000d /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0000000e /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x00000010 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x00000011 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0x0000000d /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0x0000000e /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1 0x00002400 /* RW-4R */ #define NV_CTXSW_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_CTXSW_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_CTXSW_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DEBUGINFO 0x00002500 /* RW-4R */ #define NV_CTXSW_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_SP_MIN 0x00009c00 /* RW-4R */ #define NV_CTXSW_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x00007c00 /* */ #define NV_CTXSW_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI 0x00003400 /* R--4R */ #define NV_CTXSW_FALCON_EXCI__PRIV_LEVEL_MASK 0x00007d00 /* */ #define NV_CTXSW_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_FAULT_INS 0x00000014 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_CTXSW_FALCON_EXCI2 0x00002f00 /* R--4R */ #define NV_CTXSW_FALCON_EXCI2__PRIV_LEVEL_MASK 0x00007d00 /* */ #define NV_CTXSW_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_CTXSW_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_SVEC_SPR 0x00003500 /* R--4R */ #define NV_CTXSW_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x00007e00 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_CTXSW_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL 0x00004000 /* RW-4R */ #define NV_CTXSW_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x0000a200 /* */ #define NV_CTXSW_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_CTXSW_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_CTXSW_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS 0x00004c00 /* -W-4R */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_STACKCFG 0x00004e00 /* RW-4R */ #define NV_CTXSW_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_CTXSW_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC 0x00004100 /* RW-4R */ #define NV_CTXSW_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x00006500 /* */ #define NV_CTXSW_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL 0x00009500 /* RW-4R */ #define NV_CTXSW_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x00006a00 /* */ #define NV_CTXSW_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_CTXSW_FALCON_DBGCTL_VAL_INIT 0 /* */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1 0x00002600 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2 0x00002700 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3 0x00002c00 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4 0x00002d00 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5 0x00002e00 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD 0x00008000 /* RW-4R */ #define NV_CTXSW_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CTXSW_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_FAULTED 13:13 /* R-IVF */ #define NV_CTXSW_FALCON_ICD_CMD_FAULTED_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_ICD_CMD_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_CTXSW_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_CTXSW_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_ADDR 0x00008100 /* RW-4R */ #define NV_CTXSW_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CTXSW_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_WDATA 0x00008200 /* RW-4R */ #define NV_CTXSW_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CTXSW_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_RDATA 0x00008300 /* R--4R */ #define NV_CTXSW_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_CTXSW_FALCON_RSTAT0 0x00003600 /* R--4R */ #define NV_CTXSW_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x00008900 /* */ #define NV_CTXSW_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3 0x00003700 /* R--4R */ #define NV_CTXSW_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_CTXSW_FALCON_TRACEIDX 0x00005200 /* RW-4R */ #define NV_CTXSW_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CTXSW_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_CTXSW_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_CTXSW_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEPC 0x00005300 /* R--4R */ #define NV_CTXSW_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CTXSW_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_CTXSW_FALCON_TRACEINFO 0x00005f00 /* R--4R */ #define NV_CTXSW_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CTXSW_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_CTXSW_FALCON_IMCTL 0x00005000 /* RW-4R */ #define NV_CTXSW_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_CTXSW_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_DEBUG 0x00005700 /* RW-4R */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_IMSTAT 0x00005100 /* RW-4R */ #define NV_CTXSW_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMFILLRNG0 0x00005400 /* RW-4R */ #define NV_CTXSW_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLRNG0_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLRNG0_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMFILLRNG1 0x00005500 /* RW-4R */ #define NV_CTXSW_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLRNG1_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLRNG1_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMFILLCTL 0x00005600 /* RW-4R */ #define NV_CTXSW_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMCTL 0x00009800 /* RW-4R */ #define NV_CTXSW_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_CTXSW_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_CTXSW_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_DMSTAT 0x00009900 /* RW-4R */ #define NV_CTXSW_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_DMVACTL 0x00009a00 /* RW-4R */ #define NV_CTXSW_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x00006600 /* */ #define NV_CTXSW_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMVACTL_BOUND_INIT 0x00000020 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERRSTAT 0x00009100 /* RW-4R */ #define NV_CTXSW_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CTXSW_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_CTXSW_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_ADDR 0x00009300 /* R--4R */ #define NV_CTXSW_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CTXSW_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_CSBERR_INFO 0x00009200 /* R--4R */ #define NV_CTXSW_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CTXSW_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #endif // __ga102_dev_ctxsw_prog_h__