/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2003-2016 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

/* This file is autogenerated by ref2h.pl.  Do not edit */

/* ------------------------- System Includes -------------------------------- */
#include "dev_pwr_pri.h"
#include "dev_chiplet_pwr.h"

/* ------------------------- Macros and Defines ----------------------------- */

// Per Parition Profile Values for various Feature. (Value taken from the PARTITION register)
#define PROFILE_POWER_ON    0x0
#define PROFILE_RPPG        0x1
#define PROFILE_RPG         0x2

/* =============================================================== */
// Profile Bit Position in Partition regsiter
/* =============================================================== */
#define PROFILE0_BIT_POS    0
#define PROFILE1_BIT_POS    2
#define PROFILE2_BIT_POS    4
#define PROFILE3_BIT_POS    6

/* =============================================================== */
// Bit position for Autoincrement setting
/* =============================================================== */
#define PARTITION1_INDEX_WRITEINCR_BIT_POSITION   9

/* =============================================================== */
// FEATURE  |	PROFILE MAPPING
/* =============================================================== */
// GR-RPPG  |	PROFILE0
// GR-RPG   |	PROFILE1
// MS-RPPG  | 	PROFILE0
// L2-RPG   |	PROFILE1
/* =============================================================== */

/* =============================================================== */
// Macros for SW use while programing the Profile
/* =============================================================== */

// Profile to be used by SW for RPPG feature
#define SRAM_PG_PROFILE_RPPG             NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE0

// Profile to be used by SW for RPG feature
#define SRAM_PG_PROFILE_RPG              NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE1

// Profile to be used by SW for L2RPG feature
#define SRAM_PG_PROFILE_L2RPG            NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE1

/* =============================================================== */

#define FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED (NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED << PARTITION1_INDEX_WRITEINCR_BIT_POSITION)

/* =============================================================== */ \
/* ------- Program the MS PROFILEs for MS-RPPG & L2-RPG ---------- */ \
/* =============================================================== */ \

/* =============================================================== */ \
/* ------------------ FBP ---------------------- */
/* =============================================================== */ \
// This macro is defined in the format:
// _op_(RegAddr, regVal, wrCount)
//
// regAddr - Register address to program
// regVal  - Value to program in this register
// wrCount - Number of times this register has to be written with same value (for Auto increment feature on write for all the partition in given chiplet)
/* =============================================================== */ \
#define SRAM_PG_PROFILE_INIT(_op_) \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX, (FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED | NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN), 1) \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P0 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P1 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P2 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P3 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P4 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P5 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P6 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P7 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P8 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_POWER_ON << PROFILE0_BIT_POS), 1) /* P9 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P10 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P11 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P12 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P13 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P14 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P15 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P16 */ \
_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P17 */