/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_tpc_h__ #define __ga102_dev_tpc_h__ /* This file is autogenerated. Do not edit */ #define NV_PTPC 0x000007ff:0x00000000 /* RW--D */ #define NV_PTPC_PRI /* RW--L */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SELECT 0x00000520 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SELECT_INDEX 5:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SELECT_INDEX_LANE0 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SELECT_INDEX_LANE1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SELECT_INDEX_ALL 0x0000003f /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT 31:31 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SELECT_AUTO_INCREMENT_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANES 0x00000530 /* R--4R */ #define NV_PTPC_PRI_TPCCS_RC_LANES_NUM_CHAINS 5:0 /* R--VF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN 0x00000534 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE0 0:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE0_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE0_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE1 1:1 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE1_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE1_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE2 2:2 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE2_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE2_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE3 3:3 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE3_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE3_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE4 4:4 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE4_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE4_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE5 5:5 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE5_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE5_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE6 6:6 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE6_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE6_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE7 7:7 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE7_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE7_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE8 8:8 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE8_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE8_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE9 9:9 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE9_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE9_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE10 10:10 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE10_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE10_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE11 11:11 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE11_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE11_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE12 12:12 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE12_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE12_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE13 13:13 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE13_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE13_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE14 14:14 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE14_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE14_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE15 15:15 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE15_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE15_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE16 16:16 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE16_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE16_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE17 17:17 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE17_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RUN_LANE17_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS 0x00000538 /* R--4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE0 0:0 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE0_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE0_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE1 1:1 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE1_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE1_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE2 2:2 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE2_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE2_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE3 3:3 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE3_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE3_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE4 4:4 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE4_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE4_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE5 5:5 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE5_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE5_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE6 6:6 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE6_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE6_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE7 7:7 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE7_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE7_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE8 8:8 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE8_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE8_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE9 9:9 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE9_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE9_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE10 10:10 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE10_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE10_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE11 11:11 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE11_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE11_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE12 12:12 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE12_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE12_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE13 13:13 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE13_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE13_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE14 14:14 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE14_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE14_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE15 15:15 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE15_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE15_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE16 16:16 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE16_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE16_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE17 17:17 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE17_IDLE 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_STATUS_LANE17_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK 0x000005d0 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_FUSE0 0x000fffff /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_IFF_GPCCS_FECS_GSP_SEC2_FUSE1 0x0008007c /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL 0x00000584 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL_COMPRESSION 31:31 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL_COMPRESSION_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL_COMPRESSION_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL_BLOAT_BUDGET 9:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL_BLOAT_BUDGET_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS 27:10 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS__0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVE_OFFSET 0x00000588 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVE_OFFSET__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVE_OFFSET_V 31:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RESTORE_OFFSET 0x0000058c /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RESTORE_OFFSET_V 31:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RESTORE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CURRENT_OFFSET 0x000005ac /* R--4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CURRENT_OFFSET_V 31:0 /* R--VF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CURRENT_OFFSET_V_0 0x00000000 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CURRENT_SUBOFFSET 0x000005b0 /* R--4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CURRENT_SUBOFFSET_V 5:0 /* R--VF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CURRENT_SUBOFFSET_V_0 0x00000000 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SIZE 0x00000590 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SIZE__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SIZE_V 23:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SIZE_V_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_PREFETCH_OFFSET 0x00000594 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_PREFETCH_OFFSET__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_PREFETCH_OFFSET_V 13:7 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_PREFETCH_OFFSET_V_10 0x0000000a /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVED_WORDS 0x000005b4 /* R--4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVED_WORDS__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVED_WORDS_V 23:0 /* R--VF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVED_WORDS_V_0 0x00000000 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RESTORE_WORDS 0x000005b8 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RESTORE_WORDS__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RESTORE_WORDS_V 23:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_RESTORE_WORDS_V_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_DATA 0x00000598 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_DATA__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_DATA_V 31:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_LOC 0x0000059c /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_LOC__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_LOC_RAMID 9:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_LOC_RAMID_V 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_LOC_OFFSET 31:16 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_LOC_OFFSET_V 0x0000000f /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG 0x000005a0 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG_DELAY 6:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG_DELAY_V 0x00000041 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG_CREDITS 21:16 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG_CREDITS_V 0x0000003f /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK 31:31 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_CFG_AUTOSEEK_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_RCCLASS 0x000005bc /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_RCCLASS__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_RCCLASS_V 3:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_RCCLASS_V_3 0x00000003 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_RCCLASS_V_WFI 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_RCCLASS_V_GFXP 0x00000004 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS 0x000005a4 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD 4:0 /* RW-VF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_IDLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SEEK 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_DISCOVER_LENGTH 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SAVE 0x00000003 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RESTORE 0x00000004 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_LOAD 0x00000005 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_READ_POP 0x00000006 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_WRITE_PUSH 0x00000007 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_ENABLE 0x00000008 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_DISABLE 0x00000009 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_ENABLE 0x0000000a /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_DISABLE 0x0000000b /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_ENABLE 0x0000000c /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_DISABLE 0x0000000d /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_OVERRIDE 0x0000000e /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_FLUSH 0x0000000f /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SUSPEND 0x00000010 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_CURRENT 9:8 /* R--VF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_CURRENT_IDLE 0x00000000 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_STATUS_CURRENT_BUSY 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC 0x000005a8 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD 4:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_IDLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_SEEK 0x00000001 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_DISCOVER_LENGTH 0x00000002 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_SAVE 0x00000003 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_RESTORE 0x00000004 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_LOAD 0x00000005 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_READ_POP 0x00000006 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_WRITE_PUSH 0x00000007 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_ENABLE 0x00000008 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_DISABLE 0x00000009 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_ENABLE 0x0000000a /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_DISABLE 0x0000000b /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_ENABLE 0x0000000c /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_DISABLE 0x0000000d /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_OVERRIDE 0x0000000e /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_FLUSH 0x0000000f /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_SUSPEND 0x00000010 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CMD_EXEC_CMD_SCRUB 0x00000011 /* -W--T */ #define NV_PTPC_PRI_TPCCS_RC_LANE_COMPUTED_CHECKSUM 0x000005c4 /* R-E4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVED_CHECKSUM 0x000005c8 /* R-E4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CHECKSUM 0x000005cc /* RW-4R */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CHECKSUM__PRIV_LEVEL_MASK 0x000005d0 /* */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CHECKSUM_CTRL_ENABLED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CHECKSUM_CTRL_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CHECKSUM_STATUS_MATCH 0x00000000 /* R---V */ #define NV_PTPC_PRI_TPCCS_RC_LANE_CHECKSUM_STATUS_MISMATCH 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_CG1 0x00000524 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_CG1_SLCG 7:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_CG1_SLCG_DISABLED 0x000000ff /* RWE-V */ #define NV_PTPC_PRI_TPCCS_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_LANE_CTL 0x00000540 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES 3:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES_V 0x00000008 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_LANE_CTL_WRR_WEIGHT 6:4 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_LANE_CTL_WRR_WEIGHT_V 0x00000007 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_BASE_ADDR 0x00000544 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_BASE_ADDR_F 31:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_HI_BASE_ADDR 0x00000578 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_HI_BASE_ADDR_F 8:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_HI_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_ENGINE_CTL 0x0000057c /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_ENGINE_CTL_ENGINE_ID 7:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_ENGINE_CTL_ENGINE_ID_VEID0 0x00000040 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_ENGINE_CTL_ENGINE_ID_BAR2_FN0 0x000000c0 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_ENGINE_CTL_VEID 21:16 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_ENGINE_CTL_VEID_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_ENGINE_CTL_GFID 29:24 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_ENGINE_CTL_GFID_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK 0x00000568 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD 0x00000550 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD__PRIV_LEVEL_MASK 0x00000568 /* */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD 4:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_IDLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_FLUSH 0x00000005 /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_SOFT_FLUSH 0x00000006 /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_BIND_INST_BLK_PTR 0x00000007 /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_MMU_TLB_INVALIDATE 0x00000009 /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_PREFETCH 0x0000000a /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHYSICAL_L2_CACHE_MGMT 0x0000000b /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_CACHE_MGMT 0x0000000c /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_PEER_INVALIDATE 0x0000000d /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_SYSMEM_INVALIDATE 0x0000000e /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_CLEAN_COMPTAGS 0x0000000f /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_FLUSH_DIRTY 0x00000010 /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_CMD_MEMBAR 0x00000001 /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_SUB_OP 8:7 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_SUB_OP_INVALIDATE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_SUB_OP_CLEAN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_SUB_OP_DEMOTE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE 9:9 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACK 17:16 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACK_DEFAULT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACK_FLUSH 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACK_TLB 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACK_MEM 0x00000003 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACK_NONE_REQUIRED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACK_GLOBALLY 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_ACK_INTRANODE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_HALT 30:30 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_HALT_V 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_HALT_REQUEST 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_UNHALT 31:31 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_UNHALT_V 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CTX_CMD_UNHALT_REQUEST 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL 0x00000554 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL_WR 1:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL_WR_FIRST 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL_WR_NORMAL 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL_WR_LAST 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL_RD 9:8 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL_RD_FIRST 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL_RD_NORMAL 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_L2_EVICTION_CTL_RD_LAST 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_PRIV 0x00000558 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_PRIV_OVERRIDE 0:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_PRIV_OVERRIDE_PRIV 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_PRIV_OVERRIDE_NONPRIV 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS 0x0000055c /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_CLEAR 0:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_CLEAR_IDLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_CLEAR_CLEAR 0x00000001 /* -W--T */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_ACK 1:1 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_ACK_OK 0x00000001 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_ACK_NACK 0x00000000 /* R---V */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_SUBID 15:2 /* R--VF */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_OUTSTANDING_TRANSACTIONS 23:16 /* R--VF */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_BUFFER_NOT_EMPTY 24:24 /* R--VF */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY 28:28 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_DEFAULT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_ERROR 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_HALTED 30:30 /* R--VF */ #define NV_PTPC_PRI_TPCCS_ARB_STATUS_BUSY 31:31 /* R--VF */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE 0x00000560 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE_CMD 4:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE_CMD_VIRTUAL 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_VID_MEM 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_COHERENT 0x00000004 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE_ENABLE 31:31 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_CMD_OVERRIDE_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR 0x0000056c /* RWE4R */ #define NV_PTPC_PRI_TPCCS_ARB_WPR__PRIV_LEVEL_MASK 0x00000568 /* */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_RC_ID 1:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_RC_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_RC_SECURE_LEVEL 5:4 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_RC_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PVS_ID 9:8 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PVS_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PVS_SECURE_LEVEL 13:12 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_PVS_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_CMD_ID 17:16 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_CMD_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_CMD_SECURE_LEVEL 21:20 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_CMD_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES 24:24 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_BLOCKED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_ALLOWED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK 0x00000570 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG 0x00000574 /* RWE4R */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG__PRIV_LEVEL_MASK 0x00000570 /* */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T0 3:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T0_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T1 7:4 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T1_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T2 11:8 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T2_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T3 15:12 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T3_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T4 19:16 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T4_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T5 23:20 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T5_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T6 27:24 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T6_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T7 31:28 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_ARB_FALCON_REGIONCFG_T7_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0 0x00000500 /* R--4R */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE 2:0 /* R-IVF */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE_EMPTY 0x0 /* R-I-V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE_PREEMPTED 0x4 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE_FAULTED 0x6 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_PE_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC 5:3 /* R-IVF */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC_EMPTY 0x0 /* R-I-V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC_PREEMPTED 0x4 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC_FAULTED 0x6 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_MPC_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM 8:6 /* R-IVF */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM_EMPTY 0x0 /* R-I-V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM_PREEMPTED 0x4 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM_FAULTED 0x6 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_ACTIVITY0_SM_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION 0x00000508 /* R--4R */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_SM 1:1 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_SM_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_SM_PENDING 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_PE 2:2 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_PE_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_PE_PENDING 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_MPC 4:4 /* R-EVF */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_MPC_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_MPC_PENDING 0x00000001 /* R---V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN 0x0000050C /* RW-4R */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_SM 1:1 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_SM_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_SM_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_PE 2:2 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_PE_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_PE_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_MPC 4:4 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_MPC_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_TPC_EXCEPTION_EN_MPC_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TPCCS_DEBUG 0x00000510 /* RW-4R */ #define NV_PTPC_PRI_TPCCS_DEBUG_STATUS_FILTER 7:0 /* RWEVF */ #define NV_PTPC_PRI_TPCCS_DEBUG_STATUS_FILTER_INIT 0x14 /* RWE-V */ #define NV_PTPC_PRI_TPCCS_DEBUG_STATUS_FILTER_20 0x14 /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00000100 /* RWE4R */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PTPC_PRI_PE_BLKCG_CG 0x00000004 /* RWE4R */ #define NV_PTPC_PRI_PE_BLKCG_CG__PRIV_LEVEL_MASK 0x00000100 /* */ #define NV_PTPC_PRI_PE_BLKCG_CG_BLKACTIVITY_ENABLE 5:5 /* RWEVF */ #define NV_PTPC_PRI_PE_BLKCG_CG_BLKACTIVITY_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_BLKCG_CG_BLKACTIVITY_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_BLKCG_CG_BLKACTIVITY_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_BLKCG_CG_BLKACTIVITY_ERR 6:6 /* RWEVF */ #define NV_PTPC_PRI_PE_BLKCG_CG_BLKACTIVITY_ERR_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_BLKCG_CG_BLKACTIVITY_ERR_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_BLKCG_CG_BLKACTIVITY_ERR_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_DEBUG 0x00000010 /* RWE4R */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_0 0:0 /* RWEVF */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_0_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_0_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_0_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_1 1:1 /* RWEVF */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_1_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_1_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_1_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_2 2:2 /* RWEVF */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_2_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_2_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_2_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_3 3:3 /* RWEVF */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_3_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_3_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_DEBUG_SPARE_3_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_VAF 0x0000000c /* RWI4R */ #define NV_PTPC_PRI_PE_VAF_PHASE_ARB_DETERM 0:0 /* RWIVF */ #define NV_PTPC_PRI_PE_VAF_PHASE_ARB_DETERM_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_PHASE_ARB_DETERM_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_PHASE_ARB_DETERM_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_VAF_CACHE_INVAL_METHOD_EN 1:1 /* RWIVF */ #define NV_PTPC_PRI_PE_VAF_CACHE_INVAL_METHOD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_VAF_CACHE_INVAL_METHOD_EN_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_CACHE_INVAL_METHOD_EN_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_DEBUG_SPARE_2 2:2 /* RWIVF */ #define NV_PTPC_PRI_PE_VAF_DEBUG_SPARE_2_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_DEBUG_SPARE_2_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_DEBUG_SPARE_2_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_VAF_INVAL_DISABLE 3:3 /* RWIVF */ #define NV_PTPC_PRI_PE_VAF_INVAL_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_VAF_INVAL_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_INVAL_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_FAST_MODE_SWITCH 4:4 /* RWIVF */ #define NV_PTPC_PRI_PE_VAF_FAST_MODE_SWITCH_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_PE_VAF_FAST_MODE_SWITCH_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_FAST_MODE_SWITCH_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL 5:5 /* RWIVF */ #define NV_PTPC_PRI_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_CPI_FORCE_PER_TASK_CACHE_INVAL_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_WRACK_DISABLE 6:6 /* RWIVF */ #define NV_PTPC_PRI_PE_VAF_WRACK_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_VAF_WRACK_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_WRACK_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_CPI_VC_IN_CPO_OPT_MODE 7:7 /* RWIVF */ #define NV_PTPC_PRI_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_IS_BLOCKING 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_VAF_CPI_VC_IN_CPO_OPT_MODE_IS_NON_BLOCKING 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_PIN_XBAR_PORT_ID 0x00000044 /* RWE4R */ #define NV_PTPC_PRI_PE_PIN_XBAR_PORT_ID_VALUE 1:0 /* RWEVF */ #define NV_PTPC_PRI_PE_PIN_XBAR_PORT_ID_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_PIN_MIW 0x00000038 /* RWE4R */ #define NV_PTPC_PRI_PE_PIN_MIW_READ_PACKING 0:0 /* RWEVF */ #define NV_PTPC_PRI_PE_PIN_MIW_READ_PACKING_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_PIN_MIW_READ_PACKING_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_PIN_MIW_READ_PACKING_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_PE_PIN_MIW_WRITE_PACKING 1:1 /* RWEVF */ #define NV_PTPC_PRI_PE_PIN_MIW_WRITE_PACKING_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_PIN_MIW_WRITE_PACKING_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_PIN_MIW_WRITE_PACKING_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_PE_PIN_MIW_READ_CMD_HOLDOFF 4:2 /* RWEVF */ #define NV_PTPC_PRI_PE_PIN_MIW_READ_CMD_HOLDOFF_INIT 0x00000007 /* RWE-V */ #define NV_PTPC_PRI_PE_PIN_MIW_ACACHE_READ_CMD_HOLDOFF 7:5 /* RWEVF */ #define NV_PTPC_PRI_PE_PIN_MIW_ACACHE_READ_CMD_HOLDOFF_INIT 0x00000007 /* RWE-V */ #define NV_PTPC_PRI_PE_ACACHE 0x0000004c /* RWE4R */ #define NV_PTPC_PRI_PE_ACACHE_VAF_LINES 11:0 /* RWXVF */ #define NV_PTPC_PRI_PE_ACACHE_STRI_LINES 23:12 /* RWXVF */ #define NV_PTPC_PRI_PE_ACACHE_GPULL_LINES 24:24 /* RWXVF */ #define NV_PTPC_PRI_PE_ACACHE_CACHE_DISABLE 25:25 /* RWEVF */ #define NV_PTPC_PRI_PE_ACACHE_CACHE_DISABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_ACACHE_CACHE_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_ACACHE_CACHE_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_ACACHE_VAF_INVAL_DISABLE 26:26 /* RWEVF */ #define NV_PTPC_PRI_PE_ACACHE_VAF_INVAL_DISABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_ACACHE_VAF_INVAL_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_ACACHE_VAF_INVAL_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_ACACHE_STRI_INVAL_DISABLE 27:27 /* RWEVF */ #define NV_PTPC_PRI_PE_ACACHE_STRI_INVAL_DISABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_ACACHE_STRI_INVAL_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_ACACHE_STRI_INVAL_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_STRI 0x00000050 /* RWE4R */ #define NV_PTPC_PRI_PE_STRI_LRU_DISABLE 0:0 /* RWEVF */ #define NV_PTPC_PRI_PE_STRI_LRU_DISABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_STRI_LRU_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_STRI_LRU_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_STRI_INVAL_DISABLE 1:1 /* RWEVF */ #define NV_PTPC_PRI_PE_STRI_INVAL_DISABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_STRI_INVAL_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_STRI_INVAL_DISABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_STRI_LRU_KEEP_HIST_ENABLE 2:2 /* RWEVF */ #define NV_PTPC_PRI_PE_STRI_LRU_KEEP_HIST_ENABLE_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_PE_STRI_LRU_KEEP_HIST_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_STRI_LRU_KEEP_HIST_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_PM 0x00000054 /* RWE4R */ #define NV_PTPC_PRI_PE_PM_SELECT 6:0 /* RWEVF */ #define NV_PTPC_PRI_PE_PM_SELECT_STATUS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATUS_ACACHE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATUS_PIF 0x00000002 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATUS_PIN 0x00000003 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATUS_STRI 0x00000004 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATUS_TG 0x00000005 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATUS_VAF 0x00000006 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATUS_VSC 0x00000007 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CG_STATUS_ACACHE 0x00000008 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CG_STATUS_PIF 0x00000009 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CG_STATUS_PIN 0x0000000a /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CG_STATUS_STRI 0x0000000b /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CG_STATUS_TG 0x0000000c /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CG_STATUS_VAF 0x0000000d /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CG_STATUS_VSC 0x0000000e /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CG_STATUS 0x0000000f /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_BLK_ACTIVITY 0x00000010 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_WAKEUP 0x00000011 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_ACACHE_GRP_0 0x00000012 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_ACACHE_GRP_1 0x00000013 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_ACACHE_GRP_2 0x00000014 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_ACACHE_GRP_3 0x00000015 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_ACACHE_GRP_4 0x00000016 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CPO_GRP_0 0x00000017 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CPO_GRP_1 0x00000018 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PIF_GRP_0 0x00000019 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PIF_GRP_1 0x0000001a /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PIF_GRP_2 0x0000001b /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PIN_GRP_0 0x0000001c /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PIN_GRP_1 0x0000001d /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_SSYNC_GRP_0 0x0000001e /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STREAM_GRP_0 0x0000001f /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STREAM_GRP_1 0x00000020 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STREAM_GRP_2 0x00000021 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STREAM_GRP_3 0x00000022 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STRI_GRP_0 0x00000023 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_0 0x00000024 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_1 0x00000025 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_2 0x00000026 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_3 0x00000027 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_4 0x00000028 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_5 0x00000029 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_6 0x0000002a /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_7 0x0000002b /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_8 0x0000002c /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_9 0x0000002d /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_10 0x0000002e /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_11 0x0000002f /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_12 0x00000030 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_TG_GRP_13 0x00000031 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_0 0x00000032 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_1 0x00000033 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_2 0x00000034 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_3 0x00000035 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_4 0x00000036 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_5 0x00000037 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_6 0x00000038 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_7 0x00000039 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_8 0x0000003a /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_0 0x0000003b /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_1 0x0000003c /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_2 0x0000003d /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_3 0x0000003e /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_4 0x0000003f /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_5 0x00000040 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_6 0x00000041 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_7 0x00000042 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_8 0x00000043 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PVLDRDY1 0x00000044 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PVLDRDY2 0x00000045 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PVLDRDY3 0x00000046 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PVLDRDY4 0x00000047 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VALID1 0x00000048 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VALID2 0x00000049 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VALID3 0x0000004a /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PVLDRDY5 0x0000004b /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PVLDRDY6 0x0000004c /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_9 0x0000004d /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_10 0x0000004e /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VPC_GRP_11 0x0000004f /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_PG_STATUS 0x00000050 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STRI_GRP_1 0x00000051 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_9 0x00000052 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_11 0x00000053 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_12 0x00000054 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_14 0x00000055 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_15 0x00000056 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_16 0x00000057 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_17 0x00000058 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_18 0x00000059 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_19 0x0000005a /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_20 0x0000005b /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_VAF_GRP_22 0x0000005c /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STRI_GRP_2 0x0000005d /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_BA_GRP_1 0x0000005f /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATIC_PATTERN_AAA_12_GROUP 0x00000060 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_STATIC_PATTERN_555_12_GROUP 0x00000061 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_SINGLE_PASS_GRP_1 0x00000062 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_GPCID_PEID_GROUP 0x00000063 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_PM_SELECT_CTL_EN 7:7 /* RWEVF */ #define NV_PTPC_PRI_PE_PM_SELECT_CTL_EN_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_PM_SELECT_CTL_EN_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_PM_SELECT_CTL_EN_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_CACHE_INVALIDATE 0x00000058 /* RWE4R */ #define NV_PTPC_PRI_PE_CACHE_INVALIDATE_ENABLE 0:0 /* RWEVF */ #define NV_PTPC_PRI_PE_CACHE_INVALIDATE_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_CACHE_INVALIDATE_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_CACHE_INVALIDATE_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_STATUS 0x00000060 /* R--4R */ #define NV_PTPC_PRI_PE_STATUS_PE 2:0 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_PE_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_PIF 5:3 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_PIF_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_PIN 8:6 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_PIN_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_VAF 11:9 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_VAF_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_ACACHE 14:12 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_ACACHE_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_STRI 17:15 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_STRI_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_TGA 20:18 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_TGA_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_GSPILL 23:21 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_GSPILL_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_GPULL 26:24 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_GPULL_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_STATUS_VSC 29:27 /* R-EVF */ #define NV_PTPC_PRI_PE_STATUS_VSC_INIT 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_PE_PIN_CB_GLOBAL_BASE_ADDR 0x00000048 /* RWI4R */ #define NV_PTPC_PRI_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 /* RWIVF */ #define NV_PTPC_PRI_PE_PIN_CB_GLOBAL_BASE_ADDR_V_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 /* RWIVF */ #define NV_PTPC_PRI_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY 0x00000064 /* RWI4R */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_CPI 1:0 /* RWIVF */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_CPI_FIRST 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_CPI_NORMAL 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_CPI_LAST 0x00000002 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_CPI_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STRI 3:2 /* RWIVF */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STRI_FIRST 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STRI_NORMAL 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STRI_LAST 0x00000002 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STRI_INIT 0x00000002 /* RWI-V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_VPC 5:4 /* RWIVF */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_VPC_FIRST 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_VPC_NORMAL 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_VPC_LAST 0x00000002 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_VPC_INIT 0x00000002 /* RWI-V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STREAM 11:10 /* RWIVF */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STREAM_FIRST 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STREAM_NORMAL 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STREAM_LAST 0x00000002 /* RW--V */ #define NV_PTPC_PRI_PE_L2_EVICT_POLICY_STREAM_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_PE_CG 0x00000068 /* RWE4R */ #define NV_PTPC_PRI_PE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_PE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_PE_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_PE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_PE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_PE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_PE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_PE_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_PE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_PE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_PE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PTPC_PRI_PE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_PE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_PE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_PE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_PE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_PE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_PE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_PE_CG1 0x0000006C /* RWE4R */ #define NV_PTPC_PRI_PE_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_PE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_PE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_PE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_CG1_SLCG 23:1 /* RWEVF */ #define NV_PTPC_PRI_PE_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_PE_CG1_SLCG_DISABLED 0x007FFFFF /* RWE-V */ #define NV_PTPC_PRI_PE_CG1_SLCG__PROD 0x00000082 /* RW--V */ #define NV_PTPC_PRI_PE_HWW_ESR 0x00000084 /* RWE4R */ #define NV_PTPC_PRI_PE_HWW_ESR_PIF_ERR 0:0 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_PIF_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_PIF_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_PIN_ERR 1:1 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_PIN_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_PIN_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_VAF_ERR 2:2 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_VAF_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_VAF_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_ACACHE_ERR 3:3 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_ACACHE_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_ACACHE_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_STRI_ERR 4:4 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_STRI_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_STRI_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_TG_ERR 5:5 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_TG_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_TG_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_GSPILL_ERR 6:6 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_GSPILL_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_GSPILL_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_GPULL_ERR 7:7 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_GPULL_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_GPULL_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_VSC_ERR 8:8 /* R-EVF */ #define NV_PTPC_PRI_PE_HWW_ESR_VSC_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_PE_HWW_ESR_VSC_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_PE_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PTPC_PRI_PE_HWW_ESR_RESET_TASK 0x1 /* -W--T */ #define NV_PTPC_PRI_PE_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PTPC_PRI_PE_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PTPC_PRI_PE_HWW_ESR_EN_INIT 0x1 /* RWE-V */ #define NV_PTPC_PRI_PE_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_PE_HWW_ESR_EN_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_A 0x00000094 /* RW-4R */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_A__PRIV_LEVEL_MASK 0x00000100 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_A_1 9:0 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_A_1_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_A_2 19:10 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_A_2_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_A_3 29:20 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_A_3_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_B 0x00000098 /* RW-4R */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_B__PRIV_LEVEL_MASK 0x00000100 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_B_4 9:0 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_B_4_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_B_5 19:10 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_B_5_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_B_6 29:20 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_B_6_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_C 0x0000009C /* RW-4R */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_C__PRIV_LEVEL_MASK 0x00000100 /* */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_C_7 9:0 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_C_7_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_C_8 19:10 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_C_8_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_C_9 29:20 /* RWBVF */ #define NV_PTPC_PRI_PE_BLK_ACTIVITY_WEIGHTS_C_9_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_MPC 0x0000047F:0x00000400 /* RW--L */ #define NV_PTPC_PRI_MPC_VTG_DEBUG 0x00000400 /* RWI4R */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC 0:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_SINGLE_ISBE_ALLOC_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_BUNDLE_FILTER 1:1 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_BUNDLE_FILTER_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_BUNDLE_FILTER_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_SET_COUNTERS 2:2 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_SET_COUNTERS_DISABLED 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_SET_COUNTERS_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_VSB_ISBE_SHARED 4:4 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_VSB_ISBE_SHARED_DISABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_VSB_ISBE_SHARED_ENABLED 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE 5:5 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE_ENABLED 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_CYA_RESET_ISBE_BASE_DISABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE 7:6 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_FORCE_GLOBAL_CACHE_USE_SPH 0x00000002 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_OCCUPANCY_SEL 10:9 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_OCCUPANCY_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_OCCUPANCY_SEL_PIX_QUADS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_OCCUPANCY_SEL_PIX_DRAIN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_OCCUPANCY_SEL_OVERALL 0x00000002 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_OCCUPANCY_SEL_UNDEFINED 0x00000003 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_SPARE 31:11 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_DEBUG_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG 0x00000404 /* RWI4R */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SINGLE_CTA 0:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SINGLE_CTA_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SINGLE_CTA_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK 1:1 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_PIXOUT_FPW_ILOCK_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD 2:2 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_COMP_BUNDLE_HOLD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD 3:3 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_PIX_BUNDLE_HOLD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION 4:4 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_INSTRUCTION_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_DATA 5:5 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_DATA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_DATA_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_CONSTANT 6:6 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_CONSTANT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SCG_ISC_CONSTANT_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_STEERING 7:7 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_STEERING_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_STEERING_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE 9:8 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FORCE_GLOBAL_CACHE_USE_SPH 0x00000002 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_QUAD_SKEW 10:10 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_QUAD_SKEW_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_QUAD_SKEW_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID 12:11 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_COVERED 0x0000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_ALIASED 0x0000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FIRST_SAMP_CENTROID_ALWAYS 0x0000002 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW 13:13 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_CTA_SUBPARTITION_SKEW_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM 14:14 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_FORCE_PFM_PFC_WORK_TO_ONE_SM_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_2D_3DPFM_SUBTILES_MAX_IN_FLIGHT 21:15 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_2D_3DPFM_SUBTILES_MAX_IN_FLIGHT_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SPARE 31:22 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_DEBUG_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG 0x00000408 /* RWI4R */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_USE_HALF_SM 2:2 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_USE_HALF_SM_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_USE_HALF_SM_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY 5:4 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_PIX_HIGHEST 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_VTG_CREDIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_PIX_VTG_ARB_POLICY_LOOSE_PS_TILE_LOCK 0x00000002 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_BUG1693549_FIX 6:6 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_BUG1693549_FIX_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_BUG1693549_FIX_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER 7:7 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_BUG1693549_STALL_COUNTER_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING 9:8 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_15 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_63 0x00000002 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTERING_WINDOW_SIZE_1023 0x00000003 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST 10:10 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST_AGGRESSIVE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_VTG_WINDOW_ADJUST_CONSERVATIVE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST 11:11 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST_AGGRESSIVE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_PIX_WINDOW_ADJUST_CONSERVATIVE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY 13:12 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY_STALL 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_XPIPE_BUNDLE_FILTER_CNT_SAT_POLICY_NO_SQUASH_ONCE_SAT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP 14:14 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_OPEN_2D_BLOCKS_COMP_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM 15:15 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM_ENABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_2D_COMP_MUTEX_IN_SM_DISABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_SPARE 31:16 /* RWIVF */ #define NV_PTPC_PRI_MPC_WLU_DEBUG_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_PM_CTRL 0x0000040c /* RWE4R */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL 7:0 /* RWEVF */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STATUS_BLOCK 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STATUS_SUBUNIT_0 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STATUS_SUBUNIT_1 0x00000002 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PRI_PIX_OUTSTANDING 0x00000003 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PRI_VTG_OUTSTANDING_0 0x00000004 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PRI_VTG_OUTSTANDING_1 0x00000005 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STATUS_CG_PG_WAKEUP 0x00000006 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_EXT_IFC_0 0x00000007 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_EXT_IFC_1 0x00000008 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_EXT_IFC_2 0x00000009 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_EXT_IFC_3 0x0000000a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_0 0x0000000b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_1 0x0000000c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_FULL_FIFOS_2 0x0000000d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_INTERNAL_PVLD_PRDY_0 0x0000000e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_INTERNAL_PVLD_PRDY_1 0x0000000f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_0 0x00000010 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_1 0x00000011 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_2 0x00000012 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_3 0x00000013 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_4 0x00000014 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TOTAL_COUNTS_5 0x00000015 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_ATTRIBUTES_REQUESTED_DIV4 0x00000016 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIXEL_RF_ALLOCATIONS 0x00000017 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x00000018 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_VTG_THROUGHPUT_0 0x00000019 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_VTG_THROUGHPUT_1 0x0000001a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_0 0x0000001b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_1 0x0000001c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_WARP_LAUNCHES_2 0x0000001d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMPUTE_LAUNCHES 0x0000001e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x0000001f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x00000020 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x00000021 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x00000022 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x00000023 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x00000024 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_WORK_REMOVAL_0 0x00000025 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_0 0x00000026 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_1 0x00000027 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_2 0x00000028 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STALL_LIMIT_3 0x00000029 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_WLU 0x0000002a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_LAUNCH 0x0000002b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_INPUT 0x0000002c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_PIPE_STALL_TRAM 0x0000002d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_0 0x0000002e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_1 0x0000002f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_2 0x00000030 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_DRAIN_OUTSTANDING_3 0x00000031 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_STARTXY_OUTSTANDING 0x00000032 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_TRAMFILL_OUTSTANDING 0x00000033 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_RESOURCE_LIMIT_0 0x00000034 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_RESOURCE_LIMIT_1 0x00000035 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_INTERNAL_EVENTS_0 0x00000036 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_LATENCY_TRACKING_INTERNAL 0x00000037 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_0 0x00000038 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_1 0x00000039 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_2 0x0000003a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_3 0x0000003b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_4 0x0000003c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_5 0x0000003d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_6 0x0000003e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_7 0x0000003f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_8 0x00000040 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_9 0x00000041 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_10 0x00000042 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SM_RESOURCES_11 0x00000043 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_12 0x00000044 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_13 0x00000045 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_14 0x00000046 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_15 0x00000047 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMV_RESOURCES_16 0x00000048 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SM_SHADER_TYPE_ACTIVE 0x00000049 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_ALPHA_BETA_CLOCKS 0x0000004a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_0 0x0000004b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_1 0x0000004c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_2 0x0000004d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_FIFOS_STALL_3 0x0000004e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_0 0x0000004f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_1 0x00000050 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_3 0x00000051 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_TPC_RESOURCES_4 0x00000052 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x00000053 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x00000054 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x00000055 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_EXTERNAL_SCG_EVENTS 0x00000056 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_0 0x00000057 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_1 0x00000058 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_2 0x00000059 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_ACTIVE_WARP_OCCUPANCY_3 0x0000005a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_VTG_ISBE_OCCUPANCY 0x0000005b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_TRAM_OCCUPANCY 0x0000005c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMP_FSM_BLOCK_0 0x0000005d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMP_FSM_BLOCK_1 0x0000005e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMP_LAUNCH 0x0000005f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STATIC_PATTERN_123_12_GROUP 0x00000060 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_STATIC_PATTERN_EDC_12_GROUP 0x00000061 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_CILP 0x00000062 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_0 0x00000063 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_1 0x00000064 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_2 0x00000065 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PREFUNC_LATENCIES_3 0x00000066 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x00000067 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIXOUT_IF 0x00000068 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIXOUT_CANT_DRAIN_REASONS 0x00000069 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_PIX_COMP_ARB 0x0000006a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_0 0x0000006b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_1 0x0000006c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SCG_OCCUPANCY_2 0x0000006d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_ENHANCED_L1_0 0x0000006e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_ENHANCED_L1_1 0x0000006f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_INTERNAL_EVENTS_1 0x00000070 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_ARB 0x00000071 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_0 0x00000072 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_1 0x00000073 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_0 0x00000074 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_1 0x00000075 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_2 0x00000076 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_3 0x00000077 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_4 0x00000078 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_5 0x00000079 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_6 0x0000007a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_7 0x0000007b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_8 0x0000007c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_9 0x0000007d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_10 0x0000007e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_11 0x0000007f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_12 0x00000080 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_13 0x00000081 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_MESHLET_1 0x00000082 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_MESHLET_2 0x00000083 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_1 0x00000084 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_2 0x00000085 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_RMGR_DEBUG_3 0x00000086 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_WLU_ARB_DEBUG 0x00000087 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_0 0x00000088 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_1 0x00000089 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_COMPUTE_PERF_TRIAGE_2 0x0000008a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SM_PERF_RELATED 0x0000008b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_0 0x0000008c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_1 0x0000008d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_2 0x0000008e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_3 0x0000008f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_4 0x00000090 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_5 0x00000091 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_6 0x00000092 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_7 0x00000093 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_8 0x00000094 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_9 0x00000095 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_10 0x00000096 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_11 0x00000097 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_12 0x00000098 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_13 0x00000099 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_14 0x0000009a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_15 0x0000009b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_16 0x0000009c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_17 0x0000009d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_18 0x0000009e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_19 0x0000009f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_20 0x000000a0 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCG_PERF_TRIAGE_14 0x000000a1 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_21 0x000000a2 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_0 0x000000a3 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_1 0x000000a4 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_SMSCC_SPASS_2 0x000000a5 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_2 0x000000a6 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_3 0x000000a7 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_4 0x000000a8 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_GENERAL_PERF_TRIAGE_5 0x000000a9 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_0 0x000000ff /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_1 0x000000fe /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_2 0x000000fd /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_3 0x000000fc /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_4 0x000000fb /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_5 0x000000fa /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_6 0x000000f9 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_7 0x000000f8 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_8 0x000000f7 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_9 0x000000f6 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_10 0x000000f5 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_APM_GRP_11 0x000000f4 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL 15:8 /* RWEVF */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STATUS_BLOCK 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STATUS_SUBUNIT_0 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STATUS_SUBUNIT_1 0x00000002 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PRI_PIX_OUTSTANDING 0x00000003 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PRI_VTG_OUTSTANDING_0 0x00000004 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PRI_VTG_OUTSTANDING_1 0x00000005 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STATUS_CG_PG_WAKEUP 0x00000006 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_EXT_IFC_0 0x00000007 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_EXT_IFC_1 0x00000008 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_EXT_IFC_2 0x00000009 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_EXT_IFC_3 0x0000000a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_0 0x0000000b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_1 0x0000000c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_FULL_FIFOS_2 0x0000000d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_INTERNAL_PVLD_PRDY_0 0x0000000e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_INTERNAL_PVLD_PRDY_1 0x0000000f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_0 0x00000010 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_1 0x00000011 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_2 0x00000012 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_3 0x00000013 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_4 0x00000014 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TOTAL_COUNTS_5 0x00000015 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_ATTRIBUTES_REQUESTED_DIV4 0x00000016 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIXEL_RF_ALLOCATIONS 0x00000017 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x00000018 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_VTG_THROUGHPUT_0 0x00000019 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_VTG_THROUGHPUT_1 0x0000001a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_0 0x0000001b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_1 0x0000001c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_WARP_LAUNCHES_2 0x0000001d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMPUTE_LAUNCHES 0x0000001e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x0000001f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x00000020 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x00000021 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x00000022 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x00000023 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x00000024 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_WORK_REMOVAL_0 0x00000025 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_0 0x00000026 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_1 0x00000027 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_2 0x00000028 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STALL_LIMIT_3 0x00000029 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_WLU 0x0000002a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_LAUNCH 0x0000002b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_INPUT 0x0000002c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_PIPE_STALL_TRAM 0x0000002d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_0 0x0000002e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_1 0x0000002f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_2 0x00000030 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_DRAIN_OUTSTANDING_3 0x00000031 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_STARTXY_OUTSTANDING 0x00000032 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_TRAMFILL_OUTSTANDING 0x00000033 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_RESOURCE_LIMIT_0 0x00000034 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_RESOURCE_LIMIT_1 0x00000035 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_INTERNAL_EVENTS_0 0x00000036 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_LATENCY_TRACKING_INTERNAL 0x00000037 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_0 0x00000038 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_1 0x00000039 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_2 0x0000003a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_3 0x0000003b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_4 0x0000003c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_5 0x0000003d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_6 0x0000003e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_7 0x0000003f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_8 0x00000040 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_9 0x00000041 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_10 0x00000042 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SM_RESOURCES_11 0x00000043 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_12 0x00000044 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_13 0x00000045 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_14 0x00000046 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_15 0x00000047 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMV_RESOURCES_16 0x00000048 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SM_SHADER_TYPE_ACTIVE 0x00000049 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_ALPHA_BETA_CLOCKS 0x0000004a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_0 0x0000004b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_1 0x0000004c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_2 0x0000004d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_FIFOS_STALL_3 0x0000004e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_0 0x0000004f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_1 0x00000050 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_3 0x00000051 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_TPC_RESOURCES_4 0x00000052 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x00000053 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x00000054 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x00000055 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_EXTERNAL_SCG_EVENTS 0x00000056 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_0 0x00000057 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_1 0x00000058 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_2 0x00000059 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_ACTIVE_WARP_OCCUPANCY_3 0x0000005a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_VTG_ISBE_OCCUPANCY 0x0000005b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_TRAM_OCCUPANCY 0x0000005c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMP_FSM_BLOCK_0 0x0000005d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMP_FSM_BLOCK_1 0x0000005e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMP_LAUNCH 0x0000005f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STATIC_PATTERN_123_12_GROUP 0x00000060 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_STATIC_PATTERN_EDC_12_GROUP 0x00000061 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_CILP 0x00000062 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_0 0x00000063 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_1 0x00000064 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_2 0x00000065 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PREFUNC_LATENCIES_3 0x00000066 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x00000067 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIXOUT_IF 0x00000068 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIXOUT_CANT_DRAIN_REASONS 0x00000069 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_PIX_COMP_ARB 0x0000006a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_0 0x0000006b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_1 0x0000006c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SCG_OCCUPANCY_2 0x0000006d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_ENHANCED_L1_0 0x0000006e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_ENHANCED_L1_1 0x0000006f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_INTERNAL_EVENTS_1 0x00000070 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_ARB 0x00000071 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_0 0x00000072 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_1 0x00000073 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_0 0x00000074 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_1 0x00000075 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_2 0x00000076 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_3 0x00000077 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_4 0x00000078 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_5 0x00000079 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_6 0x0000007a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_7 0x0000007b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_8 0x0000007c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_9 0x0000007d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_10 0x0000007e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_11 0x0000007f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_12 0x00000080 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_13 0x00000081 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_MESHLET_1 0x00000082 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_MESHLET_2 0x00000083 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_1 0x00000084 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_2 0x00000085 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_RMGR_DEBUG_3 0x00000086 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_WLU_ARB_DEBUG 0x00000087 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_0 0x00000088 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_1 0x00000089 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_COMPUTE_PERF_TRIAGE_2 0x0000008a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SM_PERF_RELATED 0x0000008b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_0 0x0000008c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_1 0x0000008d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_2 0x0000008e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_3 0x0000008f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_4 0x00000090 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_5 0x00000091 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_6 0x00000092 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_7 0x00000093 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_8 0x00000094 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_9 0x00000095 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_10 0x00000096 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_11 0x00000097 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_12 0x00000098 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_13 0x00000099 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_14 0x0000009a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_15 0x0000009b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_16 0x0000009c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_17 0x0000009d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_18 0x0000009e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_19 0x0000009f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_20 0x000000a0 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCG_PERF_TRIAGE_14 0x000000a1 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_21 0x000000a2 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_0 0x000000a3 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_1 0x000000a4 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_SMSCC_SPASS_2 0x000000a5 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_2 0x000000a6 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_3 0x000000a7 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_4 0x000000a8 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_GENERAL_PERF_TRIAGE_5 0x000000a9 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_0 0x000000ff /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_1 0x000000fe /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_2 0x000000fd /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_3 0x000000fc /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_4 0x000000fb /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_5 0x000000fa /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_6 0x000000f9 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_7 0x000000f8 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_8 0x000000f7 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_9 0x000000f6 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_10 0x000000f5 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_APM_GRP_11 0x000000f4 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL 23:16 /* RWEVF */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STATUS_BLOCK 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STATUS_SUBUNIT_0 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STATUS_SUBUNIT_1 0x00000002 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PRI_PIX_OUTSTANDING 0x00000003 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PRI_VTG_OUTSTANDING_0 0x00000004 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PRI_VTG_OUTSTANDING_1 0x00000005 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STATUS_CG_PG_WAKEUP 0x00000006 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_EXT_IFC_0 0x00000007 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_EXT_IFC_1 0x00000008 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_EXT_IFC_2 0x00000009 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_EXT_IFC_3 0x0000000a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_0 0x0000000b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_1 0x0000000c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_FULL_FIFOS_2 0x0000000d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_INTERNAL_PVLD_PRDY_0 0x0000000e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_INTERNAL_PVLD_PRDY_1 0x0000000f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_0 0x00000010 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_1 0x00000011 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_2 0x00000012 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_3 0x00000013 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_4 0x00000014 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TOTAL_COUNTS_5 0x00000015 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_ATTRIBUTES_REQUESTED_DIV4 0x00000016 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIXEL_RF_ALLOCATIONS 0x00000017 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_NUMBER_OF_SUBTILES_PRIMS_PIXEL_WARPS 0x00000018 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_VTG_THROUGHPUT_0 0x00000019 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_VTG_THROUGHPUT_1 0x0000001a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_0 0x0000001b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_1 0x0000001c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_WARP_LAUNCHES_2 0x0000001d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMPUTE_LAUNCHES 0x0000001e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMPUTE_RF_DIV8_ALLOCATED 0x0000001f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_ACTIVE_QUADS_IN_PIX_WARPS 0x00000020 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_0 0x00000021 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_1 0x00000022 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_2 0x00000023 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_HISTOGRAM_OF_THREADS_ACTIVE_IN_WARP_3 0x00000024 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_WORK_REMOVAL_0 0x00000025 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_0 0x00000026 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_1 0x00000027 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_2 0x00000028 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STALL_LIMIT_3 0x00000029 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_WLU 0x0000002a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_LAUNCH 0x0000002b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_INPUT 0x0000002c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_PIPE_STALL_TRAM 0x0000002d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_0 0x0000002e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_1 0x0000002f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_2 0x00000030 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_DRAIN_OUTSTANDING_3 0x00000031 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_STARTXY_OUTSTANDING 0x00000032 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_TRAMFILL_OUTSTANDING 0x00000033 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_RESOURCE_LIMIT_0 0x00000034 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_RESOURCE_LIMIT_1 0x00000035 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_INTERNAL_EVENTS_0 0x00000036 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_LATENCY_TRACKING_INTERNAL 0x00000037 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_0 0x00000038 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_1 0x00000039 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_2 0x0000003a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_3 0x0000003b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_4 0x0000003c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_5 0x0000003d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_6 0x0000003e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_7 0x0000003f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_8 0x00000040 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_9 0x00000041 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_10 0x00000042 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SM_RESOURCES_11 0x00000043 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_12 0x00000044 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_13 0x00000045 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_14 0x00000046 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_15 0x00000047 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMV_RESOURCES_16 0x00000048 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SM_SHADER_TYPE_ACTIVE 0x00000049 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_ALPHA_BETA_CLOCKS 0x0000004a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_0 0x0000004b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_1 0x0000004c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_2 0x0000004d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_FIFOS_STALL_3 0x0000004e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_0 0x0000004f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_1 0x00000050 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_3 0x00000051 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_TPC_RESOURCES_4 0x00000052 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_0_2XMIO 0x00000053 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_1_2XMIO 0x00000054 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMPUTE_PIPE_DEBUG_2_2XMIO 0x00000055 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_EXTERNAL_SCG_EVENTS 0x00000056 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_0 0x00000057 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_1 0x00000058 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_2 0x00000059 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_ACTIVE_WARP_OCCUPANCY_3 0x0000005a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_VTG_ISBE_OCCUPANCY 0x0000005b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_TRAM_OCCUPANCY 0x0000005c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMP_FSM_BLOCK_0 0x0000005d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMP_FSM_BLOCK_1 0x0000005e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMP_LAUNCH 0x0000005f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STATIC_PATTERN_123_12_GROUP 0x00000060 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_STATIC_PATTERN_EDC_12_GROUP 0x00000061 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_CILP 0x00000062 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_0 0x00000063 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_1 0x00000064 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_2 0x00000065 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PREFUNC_LATENCIES_3 0x00000066 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_MPC_SCG_DRAIN_GRAPHICS_PROTOCOL 0x00000067 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIXOUT_IF 0x00000068 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIXOUT_CANT_DRAIN_REASONS 0x00000069 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_PIX_COMP_ARB 0x0000006a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_0 0x0000006b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_1 0x0000006c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SCG_OCCUPANCY_2 0x0000006d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_ENHANCED_L1_0 0x0000006e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_ENHANCED_L1_1 0x0000006f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_INTERNAL_EVENTS_1 0x00000070 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_ARB 0x00000071 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_GENERAL_PERF_TRIAGE_0 0x00000072 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_GENERAL_PERF_TRIAGE_1 0x00000073 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_0 0x00000074 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_1 0x00000075 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_2 0x00000076 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_3 0x00000077 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_4 0x00000078 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_5 0x00000079 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_6 0x0000007a /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_7 0x0000007b /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_8 0x0000007c /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_9 0x0000007d /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_10 0x0000007e /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_11 0x0000007f /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_12 0x00000080 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SMSCG_PERF_TRIAGE_13 0x00000081 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_MESHLET_1 0x00000082 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_MESHLET_2 0x00000083 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_1 0x00000084 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_2 0x00000085 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_RMGR_DEBUG_3 0x00000086 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_WLU_ARB_DEBUG 0x00000087 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_COMPUTE_PERF_TRIAGE_0 0x00000088 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_SM_PERF_RELATED 0x00000089 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_ENABLE 28:28 /* RWEVF */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM0_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_ENABLE 29:29 /* RWEVF */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_SM1_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_ENABLE 30:30 /* RWEVF */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_TPC_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PTPC_PRI_MPC_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_STATUS 0x00000410 /* R--4R */ #define NV_PTPC_PRI_MPC_STATUS_TOP_STATUS 2:0 /* R--VF */ #define NV_PTPC_PRI_MPC_STATUS_VTG_STATUS 5:3 /* R--VF */ #define NV_PTPC_PRI_MPC_STATUS_PIX_STATUS 8:6 /* R--VF */ #define NV_PTPC_PRI_MPC_STATUS_WLU_STATUS 11:9 /* R--VF */ #define NV_PTPC_PRI_MPC_STATUS_COMP_STATUS 14:12 /* R--VF */ #define NV_PTPC_PRI_MPC_STATUS_RMGR_STATUS 17:15 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS 0x00000414 /* R--4R */ #define NV_PTPC_PRI_MPC_VTG_STATUS_ALPHA_STATUS 2:0 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_BETA_STATUS 5:3 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_ISBMGR0_STATUS 8:6 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_ISBMGR1_STATUS 11:9 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_SMIO_STATUS 14:12 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_MODE 15:15 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_MODE_ALPHA 0x00000000 /* R---V */ #define NV_PTPC_PRI_MPC_VTG_STATUS_MODE_BETA 0x00000001 /* R---V */ #define NV_PTPC_PRI_MPC_VTG_STATUS_VAFA_OUTSTANDING 16:16 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_VAFB_OUTSTANDING 17:17 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_VSC_ALPHA_OUTSTANDING 20:20 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_VAF_BETA_OUTSTANDING 21:21 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_TGBFILL_OUTSTANDING 22:22 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_GSPILL_OUTSTANDING 23:23 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_VSC_BETA_OUTSTANDING 24:24 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_VSA_WARP_OUTSTANDING 25:25 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_VSB_WARP_OUTSTANDING 26:26 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_TI_WARP_OUTSTANDING 27:27 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_TS_WARP_OUTSTANDING 28:28 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_GS_WARP_OUTSTANDING 29:29 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_CBMGR_OUTSTANDING 30:30 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS 0x00000418 /* R--4R */ #define NV_PTPC_PRI_MPC_PIX_STATUS_TRAM_STATUS 2:0 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_INPUT_STATUS 5:3 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_LAUNCH_STATUS 8:6 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_OUTPUT_STATUS 11:9 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_UNEXPECTED_TRAM_DEALLOC 14:14 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_TRAMFILL_OUTSTANDING 15:15 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_START_XY_OUTSTANDING 16:16 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_PS_WARP_OUTSTANDING 17:17 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_DQUAD_UNLOAD_OUTSTANDING 18:18 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_TRAM_STATE 23:19 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_INPUT_STATE 26:24 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_2D_PIXOUT_CMD_DONE_OUTSTANDING 27:27 /* R--VF */ #define NV_PTPC_PRI_MPC_PIX_STATUS_RCVD_3D_AFTER_CONTEXT_SWITCH 29:28 /* R--VF */ #define NV_PTPC_PRI_MPC_WLU_STATUS 0x0000041c /* R--4R */ #define NV_PTPC_PRI_MPC_WLU_STATUS_VTG_STATUS 2:0 /* R--VF */ #define NV_PTPC_PRI_MPC_WLU_STATUS_PIX_STATUS 5:3 /* R--VF */ #define NV_PTPC_PRI_MPC_WLU_STATUS_COMP_STATUS 8:6 /* R--VF */ #define NV_PTPC_PRI_MPC_CYA_BUNDLE_FILTER 0x00000420 /* RWI4R */ #define NV_PTPC_PRI_MPC_CYA_BUNDLE_FILTER_START_ADDR 15:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_CYA_BUNDLE_FILTER_START_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_CYA_BUNDLE_FILTER_END_ADDR 31:16 /* RWIVF */ #define NV_PTPC_PRI_MPC_CYA_BUNDLE_FILTER_END_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK 0x00000424 /* RWI4R */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSA 4:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSA_INIT 0x00000010 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSB 9:5 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK_ALPHA_VSB_INIT 0x00000010 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK_BETA_VAF 14:10 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK_BETA_VAF_INIT 0x00000010 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK_BETA_TS 19:15 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_PREFUNC_WATERMARK_BETA_TS_INIT 0x00000010 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK 0x00000428 /* RWI4R */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_VSA 5:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_VSA_INIT 0x0000003e /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_VSB 11:6 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_VSB_INIT 0x0000003e /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_TI 17:12 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_TI_INIT 0x0000003e /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_TS 23:18 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_TS_INIT 0x0000003e /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_GS 29:24 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_MAINFUNC_WATERMARK_GS_INIT 0x0000003e /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x0000042c /* RWI4R */ #define NV_PTPC_PRI_MPC_VTG_CB_GLOBAL_BASE_ADDR_V 27:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_CB_GLOBAL_BASE_ADDR_V_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID 28:28 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_HWW_ESR 0x00000430 /* RWE4R */ #define NV_PTPC_PRI_MPC_HWW_ESR_VTG_ERR 0:0 /* R-EVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_VTG_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_VTG_ERR_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK 1:1 /* R-EVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK 2:2 /* R-EVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW 3:3 /* R-EVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION 4:4 /* R-EVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG 5:5 /* R-EVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG_NOT_PENDING 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK34_OOB_SHARED_MEM_CONFIG_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_MPC_HWW_ESR_VTG_ERR_EN 16:16 /* RWEVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_VTG_ERR_EN_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_MPC_HWW_ESR_VTG_ERR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN 17:17 /* RWEVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_GRAPHICS_WORK_EN_ENABLE 0x1 /* RWE-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN 18:18 /* RWEVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_MPC_HWW_ESR_UNEXPECTED_COMPUTE_WORK_EN_ENABLE 0x1 /* RWE-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN 19:19 /* RWEVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_MPC_HWW_ESR_COMPUTE_WORK_OVERFLOW_EN_ENABLE 0x1 /* RWE-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK19_EN 20:20 /* RWEVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK19_EN_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK19_EN_ENABLE 0x1 /* RWE-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK34_EN 21:21 /* RWEVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK34_EN_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_MPC_HWW_ESR_SKEDCHECK34_EN_ENABLE 0x1 /* RWE-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_RESET 30:30 /* RWEVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_RESET_IDLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_MPC_HWW_ESR_RESET_TRIGGER 0x1 /* RW--T */ #define NV_PTPC_PRI_MPC_HWW_ESR_INFO 0x00000434 /* R--4R */ #define NV_PTPC_PRI_MPC_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PTPC_PRI_MPC_HWW_ESR_INFO_VEID_INIT 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_VTG_WTC 0x00000438 /* RWI4R */ #define NV_PTPC_PRI_MPC_VTG_WTC_ALPHA 0:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_WTC_ALPHA_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_WTC_ALPHA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_WTC_BETA 1:1 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_WTC_BETA_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_WTC_BETA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_VTG_WTC_WATERMARK_ALPHA 12:4 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_WTC_WATERMARK_ALPHA_INIT 0x000001ff /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_WTC_WATERMARK_BETA 24:16 /* RWIVF */ #define NV_PTPC_PRI_MPC_VTG_WTC_WATERMARK_BETA_INIT 0x000001ff /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_HOLD_CNT 0x0000043c /* RWI4R */ #define NV_PTPC_PRI_MPC_PIX_HOLD_CNT_3D_WARPS 5:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_HOLD_CNT_3D_WARPS_INIT 0x00000019 /* RWI-V */ #define NV_PTPC_PRI_MPC_PIX_HOLD_CNT_3DPFM_SUBTILES 13:8 /* RWIVF */ #define NV_PTPC_PRI_MPC_PIX_HOLD_CNT_3DPFM_SUBTILES_INIT 0x00000019 /* RWI-V */ #define NV_PTPC_PRI_MPC_COMP_STATUS 0x0000044C /* R--4R */ #define NV_PTPC_PRI_MPC_COMP_STATUS_INPUT_STATUS 2:0 /* R--VF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_LAUNCH_STATUS 5:3 /* R--VF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_OUTPUT_STATUS 8:6 /* R--VF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_INPUT_STATE 12:9 /* R--VF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_CTA_IN_PROG 13:13 /* R--VF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_GOT_ALPHA_DRAIN 14:14 /* R--VF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_GOT_BETA_DRAIN 15:15 /* R--VF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_GOT_PIX_DRAIN 16:16 /* R--VF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG 20:17 /* R-IVF */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_0KB 0x00000000 /* R---V */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_8KB 0x00000001 /* R---V */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_16KB 0x00000002 /* R---V */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_32KB 0x00000003 /* R---V */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_64KB 0x00000004 /* R-I-V */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_96KB 0x00000005 /* R---V */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_100KB 0x00000006 /* R---V */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_132KB 0x00000008 /* R---V */ #define NV_PTPC_PRI_MPC_COMP_STATUS_SHM_CONFIG_164KB 0x00000009 /* R---V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG 0x00000450 /* RWI4R */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION 0:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_INSTRUCTION_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_DATA 1:1 /* RWIVF */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_DATA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_DATA_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_CONSTANT 2:2 /* RWIVF */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_CONSTANT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SCG_ISC_CONSTANT_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SMSCG_RR_ARB 3:3 /* RWIVF */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SMSCG_RR_ARB_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SMSCG_RR_ARB_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE 4:4 /* RWIVF */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_WARP_DONE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW 7:5 /* RWIVF */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_16 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_32 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_64 0x00000002 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_128 0x00000003 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_256 0x00000004 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_512 0x00000005 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_1K 0x00000006 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_CTA_REQ_COALESCER_WINDOW_DIS 0x00000007 /* RW--V */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SPARE 31:9 /* RWIVF */ #define NV_PTPC_PRI_MPC_COMP_DEBUG_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM 0x00000454 /* R--4R */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_ALPHA_MPIPEFE 3:0 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE0_PREFUNC 4:4 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE0_MAINFUNC 5:5 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE1_PREFUNC 6:6 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE1_MAINFUNC 7:7 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE2_PREFUNC 8:8 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE2_MAINFUNC 9:9 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_BETA_MPIPEFE 13:10 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE3_TGB 14:14 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE3_PREFUNC 16:15 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE3_MAINFUNC 17:17 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE4_TGB 18:18 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE4_PREFUNC 20:19 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_STAGE4_MAINFUNC 21:21 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_ISBMGR0 24:22 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_ISBMGR1 27:25 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_SMIO 30:28 /* R--VF */ #define NV_PTPC_PRI_MPC_VTG_STATUS_FSM_SMIO_FGS_ILOCK 31:31 /* R--VF */ #define NV_PTPC_PRI_MPC_OCCUPANCY 0x00000440 /* R--4R */ #define NV_PTPC_PRI_MPC_OCCUPANCY_GFX_DENOMINATOR 15:0 /* R--VF */ #define NV_PTPC_PRI_MPC_OCCUPANCY_COMPUTE_DENOMINATOR 31:16 /* R--VF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL 0x00000444 /* RWI4R */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_AVG_WINDOW 5:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_AVG_WINDOW_MIN 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_AVG_WINDOW_MAX 0x00000018 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_AVG_WINDOW_INIT 0x00000006 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_SAMPLE_DURATION 11:6 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_SAMPLE_DURATION_MIN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_SAMPLE_DURATION_MAX 0x0000003F /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_SAMPLE_DURATION_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS 17:12 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_MAX 0x00000019 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_MIN 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_IDLE_DETECT_HYS_INIT 0x00000008 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_VTG_WARP_PRIORITY_CYA 19:18 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_VTG_WARP_PRIORITY_CYA_DIS 0x00000003 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_PIX_WARP_PRIORITY_CYA 21:20 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_PIX_WARP_PRIORITY_CYA_DIS 0x00000003 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_COMP_WARP_PRIORITY_CYA 23:22 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_COMP_WARP_PRIORITY_CYA_DIS 0x00000003 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE 24:24 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE_EN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_CTA_BYPASS_SUBTILE_DIS 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_STATS_MODE 26:26 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_STATS_MODE_AVG 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_STATS_MODE_INST 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS 27:27 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS_DIS 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_IGNORE_SMSCC_QMD_FIELDS_EN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA 28:28 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA_DIS 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_STALL_FOR_LAUNCH_INPROG_CYA_EN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_SPARE 31:29 /* RWIVF */ #define NV_PTPC_PRI_MPC_SMSCG_CNTRL_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_MPC_SCG_PARAM 0x00000448 /* RWE4R */ #define NV_PTPC_PRI_MPC_SCG_PARAM_DATA 23:0 /* RWEVF */ #define NV_PTPC_PRI_MPC_SCG_PARAM_DATA_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_MPC_SCG_PARAM_INDEX 29:24 /* RWEVF */ #define NV_PTPC_PRI_MPC_SCG_PARAM_INDEX_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_MPC_SCG_PARAM_READ 30:30 /* RWEVF */ #define NV_PTPC_PRI_MPC_SCG_PARAM_READ_DONE 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_SCG_PARAM_READ_TRIGGER 0x1 /* -W--T */ #define NV_PTPC_PRI_MPC_SCG_PARAM_WRITE 31:31 /* RWEVF */ #define NV_PTPC_PRI_MPC_SCG_PARAM_WRITE_DONE 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_SCG_PARAM_WRITE_TRIGGER 0x1 /* -W--T */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_SEL 0x00000458 /* RWI4R */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_SEL_V 2:0 /* RWIVF */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_SEL_V_INIT 0x0 /* RWI-V */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_DATA_HI 0x0000045C /* R--4R */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_DATA_HI_V 31:0 /* R-EVF */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_DATA_HI_V_INIT 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_DATA_LO 0x00000460 /* R--4R */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_DATA_LO_V 31:0 /* R-EVF */ #define NV_PTPC_PRI_MPC_SCG_CLOCK_DATA_LO_V_INIT 0x0 /* R-E-V */ #define NV_PTPC_PRI_MPC_CG 0x00000470 /* RWE4R */ #define NV_PTPC_PRI_MPC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_MPC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PTPC_PRI_MPC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_MPC_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_MPC_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_MPC_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_MPC_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_STALL_CG_DLY_CNT__PROD 0x00000004 /* */ #define NV_PTPC_PRI_MPC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_MPC_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_MPC_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_MPC_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PTPC_PRI_MPC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_MPC_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_MPC_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_MPC_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_MPC_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_MPC_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_MPC_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_MPC_CG1 0x00000474 /* RWE4R */ #define NV_PTPC_PRI_MPC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_MPC_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_MPC_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_MPC_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_CG1_SLCG 4:1 /* RWEVF */ #define NV_PTPC_PRI_MPC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_MPC_CG1_SLCG_DISABLED 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_MPC_CG1_SLCG__PROD 0x0000000F /* RW--V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00000300 /* RWE4R */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PTPC_PRI_SM_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PTPC_PRI_SM_PM_CTRL 0x00000304 /* RWE4R */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL 6:0 /* RWEVF */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_STATUS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_ACTIVE_WARPS 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_ACTIVE_WARPS2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_RFA_WARP_CANT_DRAIN_OUT_OF_ORDER 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_RFA_WARP_CANT_DRAIN 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_ICC 0x00000005 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_ACTIVE_CTAS 0x00000006 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_TRAP 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SHADER_PROGRAM 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SFE_DEBUG0 0x00000009 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_PROFILER 0x0000000a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_STATIC_PATTERN0 0x0000000b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_STATIC_PATTERN1 0x0000000c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SIGDUMP_DEBUG 0x0000000d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_FULL 0x0000000e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_PS_FULL 0x0000000f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG_ACTIVE_WARPS_VTG_FULL 0x00000010 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_CILP_DEBUG 0x00000011 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG1 0x00000012 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG2 0x00000013 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG3 0x00000014 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG4 0x00000015 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG5 0x00000016 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG6 0x00000017 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG7 0x00000018 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG8 0x00000019 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG9 0x0000001a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_DEBUG10 0x0000001b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SINGLE_PASS0 0x0000001c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SINGLE_PASS1 0x0000001d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SINGLE_PASS2 0x0000001e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SINGLE_PASS3 0x0000001f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_FULL0 0x00000020 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_NMEAS 0x00000021 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SINGLE_PASS4 0x00000022 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_SINGLE_PASS5 0x00000023 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_APM_GROUP_5 0x0000007a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_APM_GROUP_4 0x0000007b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_APM_GROUP_3 0x0000007c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_APM_GROUP_2 0x0000007d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_APM_GROUP_1 0x0000007e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_APM_GROUP_0 0x0000007f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_ENABLE 7:7 /* RWEVF */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PM_CTRL_CORE_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL 14:8 /* RWEVF */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_STATUS_ACTIVITY 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_STATUS_ACTIVITY1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_ACTIVE_WARPS 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_INST_ISSUE_EXECUTED_IPC 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_REGISTER_BANK_UTIL 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_1 0x00000005 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_2 0x00000006 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_3 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_4 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_5 0x00000009 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_6 0x0000000a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_7 0x0000000b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_1 0x0000000c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_2 0x0000000d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_CANT_ISSUE_USCH_3 0x0000000e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_1 0x0000000f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_2 0x00000010 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_3 0x00000011 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_4 0x00000012 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_5 0x00000013 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_6 0x00000014 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_7 0x00000015 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_8 0x00000016 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_9 0x00000017 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_THREAD_INST_EXECUTED 0x00000018 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_IMC 0x00000019 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_TEX 0x0000001a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_PMTRIG 0x0000001b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_THREADS_LAUNCHED 0x0000001c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_LSU_WB_OPS 0x0000001d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_CANT_DISPATCH 0x0000001e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_TEX_PENDING 0x0000001f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_MIO_0 0x00000020 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_BRU 0x00000021 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_REGISTER_READ 0x00000022 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_REGISTER_READ_PART1 0x00000023 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_REGISTER_READ_PART2 0x00000024 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_UNWEIGHTED_SCH_CANT_ISSUE_1 0x00000025 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_UNWEIGHTED_SCH_CANT_ISSUE_2 0x00000026 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_IFB 0x00000027 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_TEX_WB_INST_PENDING_HIST 0x00000028 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG0 0x00000029 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG1 0x0000002a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG2 0x0000002b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG3 0x0000002c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG4 0x0000002d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG5 0x0000002e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG6 0x0000002f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG7 0x00000030 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG8 0x00000031 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG9 0x00000032 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG10 0x00000033 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG11 0x00000034 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG12 0x00000035 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SCH_DEBUG13 0x00000036 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_DEBUG0 0x00000037 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_BRU_DEBUG0 0x00000038 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_UNIFORM_DATA_DETECT 0x00000039 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DATA_ACTIVITY0 0x0000003a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DATA_ACTIVITY1 0x0000003b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_LRF_READ_0 0x0000003c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_LRF_READ_1 0x0000003d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_WARP_OFF_DECK_REASON 0x0000003e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY0 0x0000003f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY1 0x00000040 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_THREAD_OCCUPANCY2 0x00000041 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_STATIC_PATTERN0 0x00000042 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_STATIC_PATTERN1 0x00000043 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_POWER_THROTTLE 0x00000044 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_IDE_SLEEPER 0x00000045 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY 0x00000046 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY1 0x00000047 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_BLOCK_ACTIVITY2 0x00000048 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_SINGLE_PASS0 0x00000049 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_10 0x0000004a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_11 0x0000004b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_12 0x0000004c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_13 0x0000004d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_14 0x0000004e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_DISP_INST_EXECUTED_15 0x0000004f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_11 0x00000074 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_10 0x00000075 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_9 0x00000076 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_8 0x00000077 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_7 0x00000078 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_6 0x00000079 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_5 0x0000007a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_4 0x0000007b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_3 0x0000007c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_2 0x0000007d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_1 0x0000007e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_APM_GROUP_0 0x0000007f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_ENABLE 15:15 /* RWEVF */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PM_CTRL_QCTL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL 22:16 /* RWEVF */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_STATUS_0 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_STATUS_1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_STATUS_2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIO_STATUS_PART0 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIO_STATUS_PART1 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PIXOUT 0x00000005 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_IDC 0x00000006 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOP_PART0 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOP_PART1 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOP_PART2 0x00000009 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PQ_PART0 0x0000000a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PQ_PART1 0x0000000b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PQ_2 0x0000000c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PQ_3 0x0000000d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_PART0 0x0000000e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_PART1 0x0000000f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PIXOUT_2 0x00000010 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_POSTCOALESCE 0x00000011 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_IQ_FULL_PART0 0x00000012 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_IQ_FULL_PART1 0x00000013 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_TEXIO 0x00000014 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG0_PART0 0x00000015 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG1_PART0 0x00000016 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG2_PART0 0x00000017 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOP_DEBUG3_PART1 0x00000018 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG0 0x00000019 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG1 0x0000001a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG2 0x0000001b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_TEXIO_DEBUG3 0x0000001c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG0_PART0 0x0000001d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG1_PART0 0x0000001e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART0 0x0000001f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG0_PART1 0x00000020 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG1_PART1 0x00000021 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART1 0x00000022 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MIOS_DEBUG2_PART2 0x00000023 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PIXOUT_DEBUG0 0x00000024 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_MMISC_DEBUG0 0x00000025 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_STATIC_PATTERN0 0x00000026 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_STATIC_PATTERN1 0x00000027 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG1 0x00000028 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG2 0x00000029 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG3 0x0000002a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG4 0x0000002b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG5 0x0000002c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG6 0x0000002d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG7 0x0000002e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG8 0x0000002f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG9 0x00000030 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG10 0x00000031 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG11 0x00000032 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_SINGLE_PASS0 0x00000033 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_L1DATA_PART0 0x00000034 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_SINGLE_PASS_COMPUTE 0x00000035 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_T2D_PART0 0x00000036 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_T2D_PART1 0x00000037 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PMPRED0 0x00000038 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PMPRED1 0x00000039 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PMPRED2 0x0000003a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PMPRED3 0x0000003b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_SINGLE_PASS1 0x0000003c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_POSTCOALESCE2 0x0000003d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_POSTCOALESCE3 0x0000003e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_PMPRED4 0x0000003f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_DEBUG12 0x00000040 /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_APM_GROUP_5 0x0000007a /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_APM_GROUP_4 0x0000007b /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_APM_GROUP_3 0x0000007c /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_APM_GROUP_2 0x0000007d /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_APM_GROUP_1 0x0000007e /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_APM_GROUP_0 0x0000007f /* RW--V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_ENABLE 23:23 /* RWEVF */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PM_CTRL_MIO_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_CTL 0x000003E0 /* RW-4R */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_CTL__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_CTL_INDEX 1:0 /* RWBVF */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_ZERO 0 /* RWB-V */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_MIN 0 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_CTL_INDEX_MAX 2 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_DATA 0x000003E4 /* RW-4R */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_DATA__APERTURE_INDEX_OFFSET (0x000003E0 - 0x000003E4) /* */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_DATA__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_DATA_DATA 31:0 /* RWBVF */ #define NV_PTPC_PRI_SM_POWER_DIDT_WEIGHTS_DATA_DATA_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_ARCH 0x00000330 /* R--4R */ #define NV_PTPC_PRI_SM_ARCH_WARP_COUNT 7:0 /* R--UF */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MAJOR 19:16 /* R--UF */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MAJOR_5 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MAJOR_7 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MAJOR_8 0x00000008 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MINOR 15:8 /* R--UF */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MINOR_00 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MINOR_01 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MINOR_02 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MINOR_03 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MINOR_05 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MINOR_06 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_MINOR_07 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION 19:8 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_5_00 0x00000500 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_5_02 0x00000502 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_5_03 0x00000503 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_5_05 0x00000505 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_5_06 0x00000506 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_5_07 0x00000507 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_7_00 0x00000700 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_7_01 0x00000701 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_8_02 0x00000802 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_8_04 0x00000804 /* */ #define NV_PTPC_PRI_SM_ARCH_SPA_VERSION_8_06 0x00000806 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MAJOR 31:28 /* R--UF */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MAJOR_5 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MAJOR_6 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MAJOR_7 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MAJOR_8 0x00000008 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MINOR 27:20 /* R--UF */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MINOR_00 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MINOR_01 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MINOR_02 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MINOR_03 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MINOR_05 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MINOR_06 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_MINOR_07 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION 31:20 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_5_00 0x00000500 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_5_02 0x00000502 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_5_03 0x00000503 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_5_05 0x00000505 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_5_06 0x00000506 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_6_00 0x00000600 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_6_01 0x00000601 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_6_02 0x00000602 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_7_00 0x00000700 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_7_01 0x00000701 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_8_02 0x00000802 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_8_04 0x00000804 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_8_06 0x00000806 /* */ #define NV_PTPC_PRI_SM_ARCH_SM_VERSION_8_07 0x00000807 /* */ #define NV_PTPC_PRI_SM_MACHINE_ID0 0x00000334 /* RWE4R */ #define NV_PTPC_PRI_SM_MACHINE_ID0_V 31:0 /* RWEVF */ #define NV_PTPC_PRI_SM_MACHINE_ID0_V_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_CONTEXT_SAVE_ADDR 0x00000338 /* RWE4R */ #define NV_PTPC_PRI_SM_CONTEXT_SAVE_ADDR_V 31:0 /* RWEVF */ #define NV_PTPC_PRI_SM_CONTEXT_SAVE_ADDR_V_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL 0x0000033C /* RWE4R */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 /* -WEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_ICACHE_TASK 0x00000001 /* -W--T */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_ICACHE_INIT 0x00000000 /* -WE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE 1:1 /* -WEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE_TASK 0x00000001 /* -W--T */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_IDC_CCACHE_INIT 0x00000000 /* -WE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0 2:2 /* -WEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0_TASK 0x00000001 /* -W--T */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_IMM_CCACHE0_INIT 0x00000000 /* -WE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_STATE_IMC_IV 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_STATE_IMC_IV_INCLUDE_TPC_MODE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_STATE_IMC_IV_EXCLUDE_TPC_MODE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER_ENABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_FILTER_DISABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_ALL_BANKS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF 12:12 /* RWEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_CBREF_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV 13:13 /* RWEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_RTV_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_INVALIDATE_BUNDLE_VEID_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE 15:15 /* RWEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_ICC_WAKEUP_BROADCAST_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_BINDLESS_START_END 17:16 /* RWEVF */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_BINDLESS_START_END_CALCULATE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_BINDLESS_START_END_SINGLE_SECTOR 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_BINDLESS_START_END_ZERO_THREE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_CACHE_CONTROL_BINDLESS_START_END_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK 0x00000394 /* RWE4R */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_PL2_AND_PL3_ENABLED 0x0000000C /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_CTXSW_UCODE_ENABLED 0x00000076 /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL 0x00000340 /* RW-4R */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL__PRIV_LEVEL_MASK 0x00000394 /* */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_VPR_SCRUB 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_VPR_SCRUB_TASK 0x00000001 /* RW--T */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_VPR_SCRUB_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_VPR_SCRUB_DONE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS 4:4 /* R--VF */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM_PRIVATE_CONTROL_VPR_SCRUB_STATUS_DONE 0x0 /* R---V */ #define NV_PTPC_PRI_SM_FET_CONTROL 0x00000344 /* RWE4R */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT 3:0 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_TAG_PREFETCH_LIMIT_8 0x8 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH 6:4 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH_PLUS_1 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH_PLUS_2 0x2 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH_PLUS_3 0x3 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH_PLUS_4 0x4 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH_PLUS_6 0x5 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH_PLUS_8 0x6 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_ICC_PREFETCH_PLUS_10 0x7 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_0 24:24 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_0_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_0_DISABLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_1 25:25 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_1_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_1_DISABLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_2 26:26 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_2_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_2_DISABLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_3 27:27 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_3_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_3_DISABLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_4 28:28 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_4_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_4_DISABLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_5 29:29 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_5_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_5_DISABLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_6 30:30 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_6_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_6_DISABLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_7 31:31 /* RWEVF */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_7_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_FET_CONTROL_CYA_7_DISABLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED 0x00000348 /* RWI4R */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_EOS_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH 1:1 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_UPDATE_ON_ALLOC_BATCH_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_MPC_PRIORITY 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_MPC_PRIORITY_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_MPC_PRIORITY_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_MPC_PRIORITY_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_VTG_BOOST 7:7 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_VTG_BOOST_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_VTG_BOOST_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_VTG_BOOST_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_BATCH_BOOST 8:8 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_BATCH_BOOST_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_BATCH_BOOST_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_BATCH_BOOST_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST 9:9 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_CACHE_MISS_BOOST_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_SUBTILE_HOLD 11:11 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_SUBTILE_HOLD_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER 15:12 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_4 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_5 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_6 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_7 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_8 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_9 0x00000005 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_10 0x00000006 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_11 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_12 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_13 0x00000009 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_14 0x0000000a /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_15 0x0000000b /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_16 0x0000000c /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_17 0x0000000d /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_18 0x0000000e /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_INF 0x0000000f /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FAIRNESS_TIMER_INIT 0x0000000c /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS 16:16 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_CS_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS 17:17 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_PS_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG 18:18 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_AGE_ROTATION_VTG_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_CTA_AS_TILE 19:19 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_CTA_AS_TILE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_CTA_AS_TILE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_CTA_AS_TILE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR 20:20 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_EXIT_WAIT_FOR_ERRBAR_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_L0IC 21:21 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_L0IC_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_L0IC_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_L0IC_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS 22:22 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_UNLOCK_DROPPED_MISS_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL 23:23 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FULLTAG_WAKEUP_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_UNCOND_BRANCH_OPT_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_hit 25:25 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_hit_DISCARD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_hit_NO_DISCARD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_DISABLE_DISCARD_NEXT_L0IC_hit_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS 26:26 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_ALLOW_GSCHED_ON_FWD_PROGRESS_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_EXTRA_DMMA_WAIT 28:27 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_EXTRA_DMMA_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FP16_FWD_PROGRESS_WATERMK 03:02 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_FP16_FWD_PROGRESS_WATERMK_INIT 0x00000003 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_SPARE 31:29 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MACRO_SCHED_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED 0x00000350 /* RWI4R */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_SAFE_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL 3:3 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_REQ_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FWD_PROGRESS 6:4 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FWD_PROGRESS_DISABLE 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FWD_PROGRESS_INIT 0x00000002 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT 7:7 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_LONG_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_GROUP_BIT 9:9 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_GROUP_BIT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_GROUP_BIT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_GROUP_BIT_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0 10:10 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FORCE_DEPBAR_0_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL 11:11 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_GROUP_BIT_CLR_ON_STALL_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_DEFER_BLOCKING 12:12 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_DEFER_BLOCKING_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXE_COLLAPSING 13:13 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXE_COLLAPSING_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_IFB_READ_OPT 14:14 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_IFB_READ_OPT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_IFB_READ_OPT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_IFB_READ_OPT_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXTRA_MMA_S_WAIT 01:00 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXTRA_MMA_S_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXTRA_MMA_M_WAIT 16:15 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXTRA_MMA_M_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXTRA_MMA_L_WAIT 31:30 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_EXTRA_MMA_L_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_IPB_BYPASS 18:18 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_IPB_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_IPB_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_IPB_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE 19:19 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_B2B_EXIT_ON_SHADOWPIPE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16 20:20 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA16_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32 21:21 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMA32_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10 22:22 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_HMMAE8M10_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA 23:23 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IMMA8832_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA 25:25 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_BMMA_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA 26:26 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_FFMA_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A 27:27 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_IDP4A_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA 28:28 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DMMA_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA 29:29 /* RWIVF */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_SCH_MICRO_SCHED_FUSE_SLOWDOWN_JITTER_DFMA_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK 0x00000378 /* RWE4R */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PTPC_PRI_SM_ECC_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL 0x00000354 /* RWE4R */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL__PRIV_LEVEL_MASK 0x00000378 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP0_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1 1:1 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP1_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP2_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3 3:3 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP3_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP(i) (0+(i)):(0+(i)) /* */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP__SIZE_1 4 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_TASK 0x1 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_INIT 0x0 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_SCRUB_QRFDP_DONE 0x0 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS 0x00000358 /* RWE4R */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1 1:1 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP1_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP2_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3 3:3 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP3_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP1_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP2_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP3_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP0 16:16 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP0_IDLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP0_ACTIVE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP1 17:17 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP1_IDLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP1_ACTIVE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP2 18:18 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP2_IDLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP2_ACTIVE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP3 19:19 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP3_IDLE 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP3_ACTIVE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP(i) (0+(i)):(0+(i)) /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP__SIZE_1 4 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_QRFDP_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP(i) (8+(i)):(8+(i)) /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP__SIZE_1 4 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_QRFDP_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP(i) (16+(i)):(16+(i)) /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP__SIZE_1 4 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP_PASSED 0x0 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_SCRUB_QRFDP_FAILED 0x1 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 24:24 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 25:25 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 26:26 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 27:27 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_LRF_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CORRECTED_ERR_COUNT 0x0000035C /* RWE4R */ #define NV_PTPC_PRI_SM_LRF_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_UNCORRECTED_ERR_COUNT 0x00000360 /* RWE4R */ #define NV_PTPC_PRI_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_LRF_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_LRF_ECC_ADDRESS 0x00000364 /* R--4R */ #define NV_PTPC_PRI_SM_LRF_ECC_ADDRESS_INDEX 14:0 /* R-XVF */ #define NV_PTPC_PRI_SM_LRF_ECC_ADDRESS_SM_ID 14:14 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_ADDRESS_QUADRANT_ID 13:12 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_ADDRESS_QUAD_ID 11:10 /* */ #define NV_PTPC_PRI_SM_LRF_ECC_ADDRESS_BANK_ID 9:8 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL 0x00000368 /* RWE4R */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL__PRIV_LEVEL_MASK 0x00000378 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_0_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1(i) (0+(i)):(0+(i)) /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_TASK 0x1 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_INIT 0x0 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_SCRUB_EL1_DONE 0x0 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR 3:3 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS 0x0000036C /* RWE4R */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1(i) (0+(i)):(0+(i)) /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1(i) (2+(i)):(2+(i)) /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT 0x00000370 /* RWE4R */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT 0x00000374 /* RWE4R */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK 0x0000037C /* RWE4R */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL23_ENABLED 0x0000000C /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE 0x00000380 /* RW-4R */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE__PRIV_LEVEL_MASK 0x0000037C /* */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_BASE 5:0 /* RWBVF */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_BASE_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_INCR 13:8 /* RWBVF */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_STAGGER_INCR_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS 14:14 /* R-BVF */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_INACTIVE 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_STATUS_INIT 0x00000000 /* R-B-V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE 15:15 /* RWBVF */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_ISSUE_ENABLE_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_BASE 21:16 /* RWBVF */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_BASE_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_INCR 29:24 /* RWBVF */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_STAGGER_INCR_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_STATUS 30:30 /* R-BVF */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_INACTIVE 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_STATUS_INIT 0x00000000 /* R-B-V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE 31:31 /* RWBVF */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_HIPWR_THROTTLE_DISP_ENABLE_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_POWER_CTRL1 0x000003FC /* RW-4R */ #define NV_PTPC_PRI_SM_POWER_CTRL1_FMAH_THROTTLE_MIN 19:16 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_CTRL1_FMAH_THROTTLE_MIN_INIT 0x00000004 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_CTRL1_FMAH_THROTTLE_MAX 24:20 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_CTRL1_FMAH_THROTTLE_MAX_INIT 0x0000000D /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_CTRL1_FMAH_THROTTLE_INC 26:25 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_CTRL1_FMAH_THROTTLE_INC_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_CTRL1_FMAH_THROTTLE_ENABLE 27:27 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_CTRL1_FMAH_THROTTLE_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DFD_CONTROL 0x00000398 /* RWI4R */ #define NV_PTPC_PRI_SM_DFD_CONTROL_CMD 31:0 /* RWIVF */ #define NV_PTPC_PRI_SM_DFD_CONTROL_CMD_NOP 0x00 /* RWI-V */ #define NV_PTPC_PRI_SM_DFD_DATA 0x0000039C /* RWI4R */ #define NV_PTPC_PRI_SM_DFD_DATA_VALUE 31:0 /* RWIVF */ #define NV_PTPC_PRI_SM_DFD_DATA_VALUE_EMPTY 0x00 /* RWI-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL 0x000003A0 /* RWE4R */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_INCLUDE_RFA 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU 1:1 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_EXCLUDE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_INCLUDE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BLCG_INPUT_CTRL_TTU_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_0 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_1 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT 5:5 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_BR_FALLTHRU_OPT_INIT 0x1 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_6 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_6_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_6_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_6_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_7 7:7 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_7_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_7_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_7_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_8 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_8_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_8_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_8_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_9 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_9_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_9_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_9_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_10 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_10_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_10_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_10_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_11 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_11_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_11_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_11_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_12 12:12 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_12_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_12_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_12_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_13 13:13 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_13_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_13_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_13_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_14 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_14_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_14_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_14_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_15 15:15 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_15_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_15_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_SCTL_CYA_15_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_FFMA_DATAPATH 17:16 /* RWEVF */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_BUNDLE_CONFIG 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_BOTH 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_HALFCTL_CTRL_FFMA_DATAPATH_USE_FMA_LITE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL 0x000003A4 /* RWI4R */ #define NV_PTPC_PRI_SM_DISP_CTRL_COLLECTOR_REUSE 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_COLLECTOR_REUSE_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_COLLECTOR_REUSE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_2_CYCLE_COLLECTION 1:1 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_2_CYCLE_COLLECTION_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_2_CYCLE_COLLECTION_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_FTZ_NARROWS 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_FTZ_NARROWS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_FTZ_NARROWS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_FTZ_NARROWS_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_KILLED_LD_IS_NOP 3:3 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_KILLED_LD_IS_NOP_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_KILLED_LD_IS_NOP_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_KILLED_LD_IS_NOP_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_FORCE_ALLOW_GLOBAL_STORE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_COLLECTOR_FP64_REUSE 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_COLLECTOR_FP64_REUSE_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_COLLECTOR_FP64_REUSE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_FP64_PAIRING 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_FP64_PAIRING_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_FP64_PAIRING_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_DDP_RAM_REUSE 7:7 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_DDP_RAM_REUSE_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_DDP_RAM_REUSE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_PIXOUT_READ_PARALLEL 8:8 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_PIXOUT_READ_PARALLEL_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_PIXOUT_READ_PARALLEL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_TOQ_STATUS_STALL 9:9 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_TOQ_STATUS_STALL_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_TOQ_STATUS_STALL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT 10:10 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_RFDP_UNIFORM_DATA_DETECT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_RE_SUPPRESS 12:11 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_RE_SUPPRESS_ON_PT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_RE_SUPPRESS_ON_FULL_MASK 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_RE_SUPPRESS_DISABLE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_VTG_SHADER_POP 13:13 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_VTG_SHADER_POP_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_VTG_SHADER_POP_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_PIXEL_SHADER_POP 14:14 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_PIXEL_SHADER_POP_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_PIXEL_SHADER_POP_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_COMPUTE_SHADER_POP 15:15 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_COMPUTE_SHADER_POP_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_COMPUTE_SHADER_POP_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT 16:16 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_RE_SUPPRESS_FOR_WT_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_CYA1 17:17 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_CYA1_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS 18:18 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_CANCEL_REUSE_ON_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_ACTIVE_MASK_CG 19:19 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_ACTIVE_MASK_CG_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_ACTIVE_MASK_CG_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_AND_C_REUSE 20:20 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_AND_C_REUSE_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_AND_C_REUSE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_COMPUTE_SHADER_QUAD 21:21 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO 22:22 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_TTU_INST_OUTSIDE_MACRO_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO 23:23 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL_NON_TTU_INST_IN_MACRO_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL_SPARE 31:24 /* RWIVF */ #define NV_PTPC_PRI_SM_DISP_CTRL_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2 0x000003A8 /* RWE4R */ #define NV_PTPC_PRI_SM_DISP_CTRL2_PIX_PQ_WATERMARK 6:0 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_PIX_PQ_WATERMARK_MIN 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_PIX_PQ_WATERMARK_MAX 0x00000019 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_PIX_PQ_WATERMARK_INIT 0x00000019 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_SHM_PQ_WATERMARK 13:7 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_SHM_PQ_WATERMARK_MIN 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_SHM_PQ_WATERMARK_MAX 0x00000020 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_SHM_PQ_WATERMARK_INIT 0x0000001C /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_TEX_PQ_WATERMARK 20:14 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_TEX_PQ_WATERMARK_MIN 0x00000009 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_TEX_PQ_WATERMARK_MAX 0x00000018 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_TEX_PQ_WATERMARK_INIT 0x00000018 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_GRP1_PQ_WATERMARK 25:21 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_MIN 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_MAX 0x0000001F /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_GRP1_PQ_WATERMARK_INIT 0x00000014 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL 27:26 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_8_CYCLES 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_16_CYCLES 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_32_CYCLES 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_DECOUPLED_WB_DISP_STALL_INIT 0x00000002 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_AGUL_THROTTLE 28:28 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_AGUL_THROTTLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_AGUL_THROTTLE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_AGUL_THROTTLE_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY 29:29 /* -WEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY_TASK 0x00000001 /* -W--T */ #define NV_PTPC_PRI_SM_DISP_CTRL2_WAKEUP_AUX_ENTRY_INIT 0x00000000 /* -WE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_RESET_ALL_PQ 30:30 /* -WEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_RESET_ALL_PQ_TASK 0x00000001 /* -W--T */ #define NV_PTPC_PRI_SM_DISP_CTRL2_RESET_ALL_PQ_INIT 0x00000000 /* -WE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL2_SPARE 31:31 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL2_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3 0x000003C8 /* RWE4R */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_ALWAYS_ON_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_SHM 1:1 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_SHM_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK 6:2 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_MIN 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_MAX 0x0000001F /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_AGUL_THROTTLE_WATERMARK_INIT 0x00000010 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS 7:7 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_CLEAR_CREDIT_ON_RFA_STATUS_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_CLEAR_CREDIT_ON_LST_STATUS_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC 10:9 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_THRESHOLD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_EXT 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_BOTH 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_SRC_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD 12:11 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_32 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_64 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_128 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_255 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_FWD_PROGRESS_THRESHOLD_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP 13:13 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_POST_ECC_SCRUB_WAKEUP__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS 15:14 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_DISABLE_ON_ECC 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_ENABLE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_IQ_BYPASS_INIT 0x00000002 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC 16:16 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_STALL_MUFU_ON_ECC_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT 18:17 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL1 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL2 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL3 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_VAL4 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_SHARED_INSTR_STARVE_CNT_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT 19:19 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TPQ_PARTIAL_GRANT_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT 20:20 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TTU_TPQ_PARTIAL_GRANT_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY 21:21 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_TPQ_GRANT_WITH_AUX_REPLAY_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD 23:22 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL0 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_VAL3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_AGU_MIQ_THRESHOLD_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB 25:24 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_THRESHOLD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_ALWAYS 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_MULTISTEP_ARB_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ 26:26 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_ARB_UNIFIED_PQ__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD 28:27 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL0 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_VAL3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_MIOC_RF_RD_STARVE_THRESHOLD_INIT 0x00000003 /* RWE-V */ #define NV_PTPC_PRI_SM_DISP_CTRL3_SPARE 31:29 /* RWEVF */ #define NV_PTPC_PRI_SM_DISP_CTRL3_SPARE_INIT 0x00000004 /* RWE-V */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE 0x000003AC /* R--4R */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_6 6:6 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_7 7:7 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_8 8:8 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_9 9:9 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_10 10:10 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_11 11:11 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_12 12:12 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_13 13:13 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_14 14:14 /* R-XVF */ #define NV_PTPC_PRI_SM_HALFCTL_OBSERVE_CYA_15 15:15 /* R-XVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL 0x000003B0 /* RWE4R */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_0 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL 1:1 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL_BOTH 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WRITE_PRI_CTL_SELECT_ONE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE 3:2 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_NEVER 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_ON_SM_NONIDLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_PULSE_ALWAYS 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT1 7:4 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT1_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT2 11:8 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT2_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT3 15:12 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_COUNT3_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0 17:16 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG0_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1 19:18 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG1_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2 21:20 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_BLCG2_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC 23:22 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_IMC_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK 25:24 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_UNLOCK_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL 27:26 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_ICC_IVALL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL 29:28 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_WAKEUP_DATA_IVALL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_BA_BLCG_WAKEUP 31:31 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL_BA_BLCG_WAKEUP_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1 0x000003CC /* RWE4R */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH 1:0 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_CBUF_FLUSH_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET 3:2 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_L1_RESET_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT 5:4 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_SAFE_WAIT_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP 7:6 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_STALL_DISP_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER 9:8 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_ARBITER_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR 11:10 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_INJECT_MEMBAR_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4 13:12 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG4_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6 15:14 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_BLCG6_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY 17:16 /* RWEVF */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_COUNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_DEBUG_SFE_CONTROL1_WAKEUP_MIOC_PRIORITY_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL 0x000004F0 /* RWE4R */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_INDEX 3:0 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_INDEX_MIN 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_INDEX_MAX 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_TRIGGER 11:4 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_TRIGGER_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_CONTROL 30:12 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_CONTROL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_ENABLE 31:31 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_CTL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_DATA 0x000004F4 /* RWE4R */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_DATA_DATA 31:0 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_THROTTLE_DATA_DATA_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_VST_CTL 0x000004F8 /* RWE4R */ #define NV_PTPC_PRI_SM_POWER_VST_CTL_INDEX 3:0 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_VST_CTL_INDEX_MIN 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_VST_CTL_INDEX_MAX 0x0000000F /* RW--V */ #define NV_PTPC_PRI_SM_POWER_VST_CTL_CONTROL 30:4 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_VST_CTL_CONTROL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_VST_CTL_ENABLE 31:31 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_VST_CTL_ENABLE_NO 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_POWER_VST_CTL_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_POWER_VST_DATA 0x000004FC /* RWE4R */ #define NV_PTPC_PRI_SM_POWER_VST_DATA_DATA 31:0 /* RWEVF */ #define NV_PTPC_PRI_SM_POWER_VST_DATA_DATA_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL 0x000003B4 /* RWE4R */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FMAI 1:0 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FMAI_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FMAI_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FMAI_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FMAI_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FXU 3:2 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FXU_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FXU_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FXU_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FXU_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FU 5:4 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FU_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FU_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FU_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FU_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_X2X 7:6 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_X2X_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_X2X_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_X2X_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_X2X_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_RFDP 9:8 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_RFDP_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_RFDP_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_RFDP_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_RFDP_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_SFPQ_FMA64 13:12 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_SFPQ_FMA64_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_IMMA 15:14 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_IMMA_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_IMMA_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_IMMA_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_IMMA_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G0DP 17:16 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G0DP_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G1DP 19:18 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_FP16G1DP_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP 20:20 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP_USE_MIOC_WAKEUP 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_CORE2LST_WAKEUP_USE_MIOC_STATUS 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_F_PIPE 22:21 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_F_PIPE_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_M_PIPE 24:23 /* RWEVF */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_ALWAYS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_DISP_WAKEUP 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_DISP_STATUS_WAKEUP 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_WAKEUP_CONTROL_M_PIPE_ENABLED_SM_STATUS_WAKEUP 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_QUAD_BA_CONTROL 0x000003B8 /* RW-4R */ #define NV_PTPC_PRI_SM_QUAD_BA_CONTROL__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_QUAD_BA_CONTROL_INDEX 4:0 /* RWBVF */ #define NV_PTPC_PRI_SM_QUAD_BA_CONTROL_INDEX_ZERO 0 /* RWB-V */ #define NV_PTPC_PRI_SM_QUAD_BA_CONTROL_INDEX_MIN 0 /* RW--V */ #define NV_PTPC_PRI_SM_QUAD_BA_CONTROL_INDEX_MAX 22 /* RW--V */ #define NV_PTPC_PRI_SM_QUAD_BA_DATA 0x000003BC /* RW-4R */ #define NV_PTPC_PRI_SM_QUAD_BA_DATA__APERTURE_INDEX_OFFSET (0x000003B8 - 0x000003BC) /* */ #define NV_PTPC_PRI_SM_QUAD_BA_DATA__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_QUAD_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PTPC_PRI_SM_QUAD_BA_DATA_DATA_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_SFE_BA_CONTROL 0x000003C0 /* RW-4R */ #define NV_PTPC_PRI_SM_SFE_BA_CONTROL__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_SFE_BA_CONTROL_INDEX 1:0 /* RWBVF */ #define NV_PTPC_PRI_SM_SFE_BA_CONTROL_INDEX_ZERO 0 /* RWB-V */ #define NV_PTPC_PRI_SM_SFE_BA_CONTROL_INDEX_MIN 0 /* RW--V */ #define NV_PTPC_PRI_SM_SFE_BA_CONTROL_INDEX_MAX 2 /* RW--V */ #define NV_PTPC_PRI_SM_SFE_BA_DATA 0x000003C4 /* RW-4R */ #define NV_PTPC_PRI_SM_SFE_BA_DATA__APERTURE_INDEX_OFFSET (0x000003C0 - 0x000003C4) /* */ #define NV_PTPC_PRI_SM_SFE_BA_DATA__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_SFE_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PTPC_PRI_SM_SFE_BA_DATA_DATA_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_MIO_BA_CONTROL 0x000003D0 /* RW-4R */ #define NV_PTPC_PRI_SM_MIO_BA_CONTROL__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_MIO_BA_CONTROL_INDEX 3:0 /* RWBVF */ #define NV_PTPC_PRI_SM_MIO_BA_CONTROL_INDEX_ZERO 0 /* RWB-V */ #define NV_PTPC_PRI_SM_MIO_BA_CONTROL_INDEX_MIN 0 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_BA_CONTROL_INDEX_MAX 14 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_BA_DATA 0x000003D4 /* RW-4R */ #define NV_PTPC_PRI_SM_MIO_BA_DATA__APERTURE_INDEX_OFFSET (0x000003D0 - 0x000003D4) /* */ #define NV_PTPC_PRI_SM_MIO_BA_DATA__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_MIO_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PTPC_PRI_SM_MIO_BA_DATA_DATA_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_TTU_BA_CONTROL 0x00000668 /* RW-4R */ #define NV_PTPC_PRI_SM_TTU_BA_CONTROL__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_TTU_BA_CONTROL_INDEX 3:0 /* RWBVF */ #define NV_PTPC_PRI_SM_TTU_BA_CONTROL_INDEX_ZERO 0 /* RWB-V */ #define NV_PTPC_PRI_SM_TTU_BA_CONTROL_INDEX_MIN 0 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_BA_CONTROL_INDEX_MAX 13 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_BA_DATA 0x0000066C /* RW-4R */ #define NV_PTPC_PRI_SM_TTU_BA_DATA__APERTURE_INDEX_OFFSET (0x00000668 - 0x0000066C) /* */ #define NV_PTPC_PRI_SM_TTU_BA_DATA__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PTPC_PRI_SM_TTU_BA_DATA_DATA 27:0 /* RWBVF */ #define NV_PTPC_PRI_SM_TTU_BA_DATA_DATA_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_SM_BLCG_0_CG 0x00000480 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_0_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_0_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_IDLE_CG_DLY_CNT__PROD 0x00000005 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_0_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_0_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_0_CG1 0x00000484 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_0_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_0_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_0_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG1_SLCG 17:1 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_0_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_0_CG1_SLCG_DISABLED 0x0001FFFF /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_0_CG1_SLCG__PROD 0x0001FFFE /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG 0x00000488 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_1_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_1_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_IDLE_CG_DLY_CNT__PROD 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_1_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_1_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_1_CG1 0x0000048C /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_1_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_1_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_1_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG1_SLCG 31:1 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_1_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_1_CG1_SLCG_DISABLED 0x7FFFFFFF /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_1_CG1_SLCG__PROD 0x7FB8F9C2 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG 0x00000490 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_2_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_2_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_IDLE_CG_DLY_CNT__PROD 0x00000006 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_2_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_2_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_2_CG1 0x00000494 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_2_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_2_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_2_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG1_SLCG 29:1 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_2_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_2_CG1_SLCG_DISABLED 0x1FFFFFFF /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_2_CG1_SLCG__PROD 0x1CF80180 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_3_CG 0x00000498 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_3_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_3_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_3_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_3_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_3_CG1 0x0000049C /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_3_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_3_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_3_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_3_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG 0x000004A0 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_4_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_4_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_IDLE_CG_DLY_CNT__PROD 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_4_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_4_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_4_CG1 0x000004A4 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_4_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_4_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_4_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG1_SLCG 13:1 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_4_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_4_CG1_SLCG_DISABLED 0x00001FFF /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_4_CG1_SLCG__PROD 0x00001FFE /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG 0x000004A8 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_5_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_5_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_IDLE_CG_DLY_CNT__PROD 0x00000006 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_5_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_5_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_5_CG1 0x000004AC /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_5_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_5_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_5_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG1_SLCG 16:1 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_5_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_5_CG1_SLCG_DISABLED 0x0000FFFF /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_5_CG1_SLCG__PROD 0x0000FC00 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG 0x000004B0 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_6_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_6_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_IDLE_CG_DLY_CNT__PROD 0x00000005 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_6_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_6_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_SM_BLCG_6_CG1 0x000004B4 /* RWE4R */ #define NV_PTPC_PRI_SM_BLCG_6_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_6_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_6_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG1_SLCG 12:1 /* RWEVF */ #define NV_PTPC_PRI_SM_BLCG_6_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_BLCG_6_CG1_SLCG_DISABLED 0x00000FFF /* RWE-V */ #define NV_PTPC_PRI_SM_BLCG_6_CG1_SLCG__PROD 0x00000EB0 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG 0x000004E8 /* RWE4R */ #define NV_PTPC_PRI_SM_MIO_CFG_MEMBAR_WINDOW 4:0 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG_MEMBAR_WINDOW_INIT 0x00000002 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR 6:5 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X4 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X16 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X64 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_X256 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_MEMBAR_WINDOW_PRESCALAR_INIT 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG_TEX2D_CONTROL 13:12 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG_TEX2D_CONTROL_HALF0 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_TEX2D_CONTROL_HALF1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_TEX2D_CONTROL_BOTH 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_TEX2D_CONTROL_INIT 0x00000002 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D 14:14 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG_PIX_CMD_DONE_STALL_PFM3D_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG_MIOP_SPARE 23:18 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG_MIOP_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2 0x000004EC /* RWE4R */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOS_SPARE 2:0 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOS_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_PIXOUT_LOW_WATERMARK 5:3 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_PIXOUT_LOW_WATERMARK_INIT 0x00000005 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_IMC_TAG_HASH_CTRL 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_GALOIS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_NON_GALOIS 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_IMC_TAG_HASH_CTRL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL 7:7 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_INCLUDE_RFA 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_TTU_BLCG_INPUT_CTRL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_INCLUDE_RFA 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOS_BLCG_INPUT_CTRL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_INCLUDE_RFA 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_MIOP_BLCG_INPUT_CTRL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT 16:12 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_MIOS_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT 21:17 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_TEX_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT 26:22 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_OUTSTANDING_ADU_WB_REQ_COUNT_16 0x10 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_DETECT_UNIFORM_LD 27:27 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_DETECT_UNIFORM_LD_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_DETECT_UNIFORM_LD_ENABLE 0x1 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_FC_RESERVED_FOR_SUST_NUM_CYCLES 30:28 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_FC_RESERVED_FOR_SUST_NUM_CYCLES_INIT 0x00000002 /* RWE-V */ #define NV_PTPC_PRI_SM_MIO_CFG2_SUST_STEAL 31:31 /* RWEVF */ #define NV_PTPC_PRI_SM_MIO_CFG2_SUST_STEAL_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_SUST_STEAL_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_MIO_CFG2_SUST_STEAL_INIT 0x1 /* RWE-V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL 0x000003D8 /* RWI4R */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE_DISABLE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_FAST_POINT_SAMPLE_ENABLE 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP 2:1 /* RWIVF */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_DEFAULT 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_TO_CG 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_TO_CV 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_BYPASS 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_GLOBAL_GENERIC_CACHE_OP_REMAP_INIT 0x00000003 /* RWI-V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP 4:3 /* RWIVF */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_DEFAULT 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_TO_CG 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_TO_CV 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_BYPASS 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_LOCAL_CACHE_OP_REMAP_INIT 0x00000003 /* RWI-V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_TEX2SMM_ERR_RESPONSE_FORWARD_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE 7:6 /* RWIVF */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_INSTR 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_FORCE_RTZ 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_FORCE_RTNE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_FP16_ROUNDING_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE 10:8 /* RWIVF */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_X86_63_47_MATCH 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_ARM_63_48_MATCH 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_POWER_63_46_ZERO 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_POWER_63_49_ZERO 0x00000003 /* RWI-V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_ARM_55_48_MATCH 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_OOR_ADDR_CHECK_MODE_NO_CHECK 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_SPARE 18:11 /* RWIVF */ #define NV_PTPC_PRI_SM_TEXIO_CONTROL_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_PM_SAMP_CTRL 0x000003DC /* RWI4R */ #define NV_PTPC_PRI_SM_PM_SAMP_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_PM_SAMP_CTRL_ENABLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_PM_SAMP_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_PM_SAMP_CTRL_TIMER 5:1 /* RWIVF */ #define NV_PTPC_PRI_SM_PM_SAMP_CTRL_TIMER_INIT 0x00000005 /* RWI-V */ #define NV_PTPC_PRI_SM_CONFIG 0x00000608 /* RWE4R */ #define NV_PTPC_PRI_SM_CONFIG_TPC_ID 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_CONFIG_TPC_ID_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL 0x0000060C /* R--4R */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SM0_ERROR 0:0 /* R-IVF */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SM0_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SM0_ERROR_PENDING 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SM1_ERROR 1:1 /* R-IVF */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SM1_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SM1_ERROR_PENDING 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SMC_ERROR 2:2 /* R-IVF */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SMC_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM_TPC_ESR_SM_SEL_SMC_ERROR_PENDING 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x00000610 /* RWI4R */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM_NO_REPORT 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_VAT_ALARM_REPORT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED_NO_REPORT 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_CORRECTED_REPORT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED_NO_REPORT 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_REPORT_MASK_ECC_UNCORRECTED_REPORT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR 0x00000614 /* RWI4R */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_VAT_ALARM 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_VAT_ALARM_NOT_PENDING 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_VAT_ALARM_PENDING 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_ECC_CORRECTED 4:4 /* R-IVF */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_ECC_CORRECTED_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_ECC_CORRECTED_PENDING 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED 5:5 /* R-IVF */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM_HWW_GLOBAL_ESR_ECC_UNCORRECTED_PENDING 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_CBU_CNTRL 0x00000618 /* RWI4R */ #define NV_PTPC_PRI_SM_CBU_CNTRL_NANOSLEEP_MIN 3:0 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_NANOSLEEP_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_NANOSLEEP_MAX 7:4 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_NANOSLEEP_MAX_INIT 0x0000000f /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_YIELD_NOP_CNT 15:8 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_YIELD_NOP_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD 16:16 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_PESSIMISTIC_YIELD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_FORCE_ALIASED 17:17 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_FORCE_ALIASED_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_FORCE_ALIASED_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP 18:18 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_CYA_DISABLE_OPT_TOP_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_BSSY_REPLACE_MASK 19:19 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_BSSY_REPLACE_MASK_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_BSSY_REPLACE_MASK_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD 20:20 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_BSYNC_EMPTY_STACK_YIELD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER 21:21 /* RWIVF */ #define NV_PTPC_PRI_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_CNTRL_ELECTION_RELEASE_BARRIER__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL 0x000003F0 /* RWI4R */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SECTOR_PROMOTE_GLOBAL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SKIP_READ 1:1 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SKIP_READ_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SKIP_READ_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SKIP_READ_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_HASH_LG 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_HASH_LG_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_HASH_LG_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_HASH_LG_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_HASH_TEX 3:3 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_HASH_TEX_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_HASH_TEX_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_HASH_TEX_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_L1_ATOMIC 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_L1_ATOMIC_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_L1_ATOMIC_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_L1_ATOMIC_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD 5:5 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_2D 6:6 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_2D_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_2D_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_2D_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_LOCAL 7:7 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_LOCAL_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_LOCAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_LOCAL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_GLOBAL 8:8 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_GLOBAL_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_GLOBAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_GLOBAL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_TEX 9:9 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_TEX_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_TEX_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_TEX_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST 10:10 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_CTRL 10:5 /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_CTRL_EN_NONE 0x00000000 /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CACHE_CTRL_EN_ALL 0x0000003f /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT 11:11 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SCRUBBER_READY_COUNT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE 12:12 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_SURFACE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL 13:13 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_GLOBAL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL 14:14 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_WRITE_ALLOC_LOCAL_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_DUAL_LOD_SERIAL 15:15 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_DUAL_LOD_SERIAL_AUTO 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_DUAL_LOD_SERIAL_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN 16:16 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_REPLACEMENT_ALLOC_RANK_EU_AS_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN 17:17 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_REPLACEMENT_HIT_RANK_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_LG_THROTTLE_T2D 22:18 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_LG_THROTTLE_T2D_INIT 0x00000010 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_LG_THROTTLE_DSLOT 27:23 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_LG_THROTTLE_DSLOT_INIT 0x00000008 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR 28:28 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_ALWAYS_CUT_COLLECTOR_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR 29:29 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_SURFACE_CUT_COLLECTOR_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_RESET_L1_ON_LEAK 30:30 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_RESET_L1_ON_LEAK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM 31:31 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL_CLEAR_EV_LONG_ON_3DPFM_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2 0x000003F4 /* RWI4R */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_RED 0:0 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_RED_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_RED_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_RED_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS 1:1 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOM_CAS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOM 2:2 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOM_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOM_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOM_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_LG 3:3 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_LG_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_LG_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_LG_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_SURFACE 4:4 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_SURFACE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_SURFACE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_SURFACE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL 4:0 /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL_EN_NONE 0x00000000 /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CONCAT_ATOMIC_CTRL_EN_ALL 0x0000001f /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN 5:5 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LG_WR_COALESCE_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN 6:6 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LG_RD_COALESCE_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN 7:7 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_SU_WR_COALESCE_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN 8:8 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_SU_RD_COALESCE_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN 9:9 /* RWIUF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_TEX_RD_COALESCE_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_COALESCE_EN_CTRL 9:5 /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_COALESCE_EN_CTRL_EN_NONE 0x00000000 /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_COALESCE_EN_CTRL_EN_ALL 0x0000001f /* */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN 10:10 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_LIFE_EXTN_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LATFIFO_DEPTH_DIV4 18:11 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_LATFIFO_DEPTH_DIV4_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_TIMEOUT 22:19 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_TIMEOUT_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR 23:23 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_X2K 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_X16K 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_TIMEOUT_PRESCALAR_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK_ENABLE 0x00000001 /* RW--T */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_DSLOT_LEAK__PROD 0x00000001 /* RW--T */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR 25:25 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR_ENABLE 0x00000001 /* RW--T */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_REFCOUNTER_ERR__PROD 0x00000001 /* RW--T */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK 26:26 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DETECT_L1MISS_LEAK_ENABLE 0x00000001 /* RW--T */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN 27:27 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_STORE_COALESCE_GAP_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_COALESCE_FLUSH 28:28 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_COALESCE_FLUSH_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_COALESCE_FLUSH_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_NO_EVICT_LONG 29:29 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_NO_EVICT_LONG_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_NO_EVICT_LONG_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_NO_EVICT_LONG_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_LD_COMMIT 30:30 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_CBUF_LD_COMMIT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DBE_PRTY_CYA 31:31 /* RWIVF */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DBE_PRTY_CYA_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DBE_PRTY_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1TAG_CTRL2_DBE_PRTY_CYA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL 0x000003F8 /* RWI4R */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_LG_THROTTLE_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE 1:1 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_MAIN_COLLECTOR_LOOK_AHEAD_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_LOOK_AHEAD_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE 3:3 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_PAIRING_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_HOLDING_BUFFER_BYPASS_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_STALL_GNIC_REQUESTS_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_STALL_4Q_REQUESTS_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE 9:9 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TEX_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE 10:10 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_TCR_TEX_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE 11:11 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TCR_READ_PARTIAL_SECTOR_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SM_READ_STARVATION_THRESHOLD_COUNT 14:12 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SM_READ_STARVATION_THRESHOLD_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SM_READ_STALL_TEX_TCR_NUM_CYCLES 17:15 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SM_READ_STALL_TEX_TCR_NUM_CYCLES_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TEX_READ_STARVATION_THRESHOLD_COUNT 20:18 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TEX_READ_STARVATION_THRESHOLD_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TEX_READ_STALL_TCR_NUM_CYCLES 23:21 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TEX_READ_STALL_TCR_NUM_CYCLES_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIDE_COLLECTOR_FAST_BDI_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TTU_READ_STARVATION_THRESHOLD_COUNT 27:25 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TTU_READ_STARVATION_THRESHOLD_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TTU_READ_STALL_TEX_TCR_NUM_CYCLES 30:28 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_TTU_READ_STALL_TEX_TCR_NUM_CYCLES_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE 31:31 /* RWIVF */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_L1DATA_CTRL_SIMULTANEOUS_MEMORY_ACCESS_PE_TTU_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_ADDRESS 0x0000061C /* R--4R */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_ADDRESS_INDEX 17:0 /* R-XVF */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_ADDRESS_SUBBANK_ID 16:15 /* */ #define NV_PTPC_PRI_SM_L1_DATA_ECC_ADDRESS_BANK_ID 14:10 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL 0x00000620 /* RWE4R */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL__PRIV_LEVEL_MASK 0x00000378 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_0_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1(i) (0+(i)):(0+(i)) /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_TASK 0x1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_INIT 0x0 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_EL1_DONE 0x0 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR 3:3 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF 4:4 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_PIXPRF_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO 5:5 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CONTROL_SCRUB_MISS_FIFO_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS 0x00000624 /* RWE4R */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1(i) (0+(i)):(0+(i)) /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1(i) (2+(i)):(2+(i)) /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_EL1_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF 4:4 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_PIXPRF_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO 5:5 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_MISS_FIFO_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_PIXPRF_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO 7:7 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_MISS_FIFO_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT 0x00000628 /* RWE4R */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT 0x0000062C /* RWE4R */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS 0x00000630 /* R--4R */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_SM_ID 15:15 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_STRUCT 14:13 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_STRUCT_EL1 0x0 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_STRUCT_PIXPRF 0x1 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_STRUCT_MISS_FIFO_T2D 0x2 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_STRUCT_MISS_FIFO_W2D 0x3 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_EL1_BANK_ID 7:6 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_EL1_SET_ID 5:0 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_BANK_ID 7:6 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_SET_ID 5:0 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_PIXPRF_SM_ID 15:15 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_PIXPRF_STRUCT 14:13 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_PIXPRF_BANK_ID 9:8 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_PIXPRF_ROW 6:0 /* */ #define NV_PTPC_PRI_SM_L1_TAG_ECC_ADDRESS_MISS_FIFO_SUBFIFO 12:10 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL 0x00000634 /* RWE4R */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL__PRIV_LEVEL_MASK 0x00000378 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM0_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM0_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM(i) (0+(i)):(0+(i)) /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_TASK 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_INIT 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_WARP_SM_DONE 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM(i) (2+(i)):(2+(i)) /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_TASK 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_INIT 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_SCRUB_BARRIER_SM_DONE 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS 0x00000638 /* RWE4R */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0 4:4 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM0_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM(i) (0+(i)):(0+(i)) /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_WARP_SM_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM(i) (2+(i)):(2+(i)) /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_BARRIER_SM_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM(i) (4+(i)):(4+(i)) /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_WARP_SM_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM(i) (6+(i)):(6+(i)) /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM__SIZE_1 1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM_NOT_PENDING 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_BARRIER_SM_PENDING 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_CBU_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_CORRECTED_ERR_COUNT 0x0000063C /* RWE4R */ #define NV_PTPC_PRI_SM_CBU_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_UNCORRECTED_ERR_COUNT 0x00000640 /* RWE4R */ #define NV_PTPC_PRI_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_CBU_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_CBU_ECC_ADDRESS 0x00000644 /* R--4R */ #define NV_PTPC_PRI_SM_CBU_ECC_ADDRESS_INDEX 12:0 /* R-XVF */ #define NV_PTPC_PRI_SM_CBU_ECC_ADDRESS_SM_ID 12:12 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_ADDRESS_STRUCT 11:11 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_ADDRESS_STRUCT_WARP 0x0 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_ADDRESS_STRUCT_BARRIER 0x1 /* */ #define NV_PTPC_PRI_SM_CBU_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL 0x00000648 /* RWE4R */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL__PRIV_LEVEL_MASK 0x00000378 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_SCRUB_L1_DATA_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS 0x0000064C /* RWE4R */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_L1_DATA_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA 6:6 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_L1_DATA_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CORRECTED_ERR_COUNT 0x00000650 /* RWE4R */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT 0x00000654 /* RWE4R */ #define NV_PTPC_PRI_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS 0x00000658 /* R--4R */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS_STRUCT 16:16 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS_STRUCT_L1 0x1 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS_SUBSTRUCT 14:14 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS_SUBSTRUCT_DATA 0x0 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS_QUAD_ID 13:12 /* */ #define NV_PTPC_PRI_SM_ICACHE_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL 0x00000384 /* RWE4R */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL__PRIV_LEVEL_MASK 0x00000378 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_DATA_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE 1:1 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_L0IC_PREDECODE_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_SCRUB_URF_DATA_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR 30:30 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR 31:31 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x1 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS 0x00000388 /* RWE4R */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_DATA_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE 1:1 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_L0IC_PREDECODE_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA 2:2 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_URF_DATA_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA 8:8 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_DATA_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE 9:9 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_L0IC_PREDECODE_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA 10:10 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_URF_DATA_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 24:24 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 25:25 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 26:26 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 27:27 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PTPC_PRI_SM_RAMS_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CORRECTED_ERR_COUNT 0x0000038C /* RWE4R */ #define NV_PTPC_PRI_SM_RAMS_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT 0x00000390 /* RWE4R */ #define NV_PTPC_PRI_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS 0x0000034C /* R--4R */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS_SM_ID 17:17 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS_STRUCT 16:14 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS_STRUCT_L0IC_DATA 0x0 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS_STRUCT_L0IC_PREDECODE 0x1 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS_URF_DATA 0x2 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS_QUAD_ID 13:12 /* */ #define NV_PTPC_PRI_SM_RAMS_ECC_ADDRESS_ROW 10:0 /* */ #define NV_PTPC_PRI_SM_TTU_CTRL 0x0000065C /* RWI4R */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0_USE_TAG 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0_USE_TAG_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0_USE_TAG_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0_USE_TAG_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0_TAG_USE_SM_ID 1:1 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0_TAG_USE_SM_ID_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0_TAG_USE_SM_ID_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0_TAG_USE_SM_ID_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0TC_SLOW_REQUEST 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0TC_SLOW_REQUEST_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0TC_SLOW_REQUEST_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0TC_SLOW_REQUEST_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TIF_PER_SM_TICKET 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_TIF_PER_SM_TICKET_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TIF_PER_SM_TICKET_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TIF_PER_SM_TICKET_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD 6:5 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_4 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_8 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_16 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_EARLY_RAY_RTN_THRESHOLD_INIT 0x00000002 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION 7:7 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RCT_SHEAR_TRANSFORM_PRECISION_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD 9:8 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_CNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_STARVATION_THRESHOLD_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS 10:10 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RAY_ALLOC_COUNT_ACTV_RAYS__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE 11:11 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TCKT_CLR_WAIT_ON_HPIPE_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY 12:12 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_HIGH_PRIORITY_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD 14:13 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_CNT3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_L0CC_REQ_STARVATION_THRESHOLD_INIT 0x00000002 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID 15:15 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_MEMARB_L1C_HASH_USE_SM_ID_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT 16:16 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RTT_TRIANGLE_PAIR_SUPPORT_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE 19:17 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_VAL4 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TOP_STACK_LIM_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE 22:20 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_VAL4 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_BOT_STACK_LIM_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK 23:23 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RMU_RAY_ACTV_ERROR_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_TIF_GREEDY_TCKT_ALLOCATE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_MEMARB_L1C_HASH 25:25 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_MEMARB_L1C_HASH_CHOICE0 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_MEMARB_L1C_HASH_CHOICE1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_MEMARB_L1C_HASH_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RCT_FRA_SUPPORT 26:26 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_RCT_FRA_SUPPORT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RCT_FRA_SUPPORT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL_RCT_FRA_SUPPORT_INIT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL_SPARE 31:27 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2 0x00000660 /* RWI4R */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_TCKT_ON_RFA_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS 1:1 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_RAY_ON_RFA_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_CLR_L0_ON_RFA_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT 4:4 /* -WIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT_TASK 0x00000001 /* -W--T */ #define NV_PTPC_PRI_SM_TTU_CTRL2_FORCE_TTU_TIMEOUT_INIT 0x00000000 /* -WI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC1_WATERMARK 7:5 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC1_WATERMARK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC1_WATERMARK_MIN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC1_WATERMARK_MAX 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC1_WATERMARK_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC2_WATERMARK 11:8 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC2_WATERMARK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC2_WATERMARK_MIN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC2_WATERMARK_MAX 0x0000000F /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC2_WATERMARK_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC3_WATERMARK 15:12 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC3_WATERMARK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC3_WATERMARK_MIN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC3_WATERMARK_MAX 0x0000000F /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC3_WATERMARK_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC4_WATERMARK 19:16 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC4_WATERMARK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC4_WATERMARK_MIN 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC4_WATERMARK_MAX 0x0000000F /* RW--V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_RESRC4_WATERMARK_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_CTRL2_SPARE 31:20 /* RWIVF */ #define NV_PTPC_PRI_SM_TTU_CTRL2_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL 0x00000664 /* RWE4R */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL 6:0 /* RWEVF */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP10 0x0000000a /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP11 0x0000000b /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP12 0x0000000c /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP13 0x0000000d /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP14 0x0000000e /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP15 0x0000000f /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP16 0x00000010 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP17 0x00000011 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP18 0x00000012 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP19 0x00000013 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP20 0x00000014 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP21 0x00000015 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP22 0x00000016 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP23 0x00000017 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP24 0x00000018 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_DBG0 0x00000019 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_DBG1 0x0000001a /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_DBG2 0x0000001b /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_SINGLE_PASS0 0x0000001c /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_SINGLE_PASS1 0x0000001d /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_STATIC_PATTERN0 0x0000001e /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_STATIC_PATTERN1 0x0000001f /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_SIGDUMP_DEBUG 0x00000020 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP25 0x00000021 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP26 0x00000022 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP27 0x00000023 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP28 0x00000024 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP29 0x00000025 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP30 0x00000026 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP31 0x00000027 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP32 0x00000028 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_GRP33 0x00000029 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_APM_GROUP_7 0x00000078 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_APM_GROUP_6 0x00000079 /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_APM_GROUP_5 0x0000007a /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_APM_GROUP_4 0x0000007b /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_APM_GROUP_3 0x0000007c /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_APM_GROUP_2 0x0000007d /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_APM_GROUP_1 0x0000007e /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_APM_GROUP_0 0x0000007f /* RW--V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_ENABLE 7:7 /* RWEVF */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_TTU_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_STATUS 0x00000670 /* R--4R */ #define NV_PTPC_PRI_SM_STATUS_SFE 2:0 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_SFE_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SFE_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SFE_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SFE_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SFE_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SFE_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SFE_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL0 5:3 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_SCTL0_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL0_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL0_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL0_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL0_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL0_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL0_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL1 8:6 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_SCTL1_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL1_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL1_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL1_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL1_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL1_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_SCTL1_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C0 11:9 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_L1C0_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C0_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C0_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C0_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C0_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C0_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C0_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C1 14:12 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_L1C1_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C1_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C1_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C1_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C1_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C1_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_L1C1_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM0 17:15 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_TEXAM0_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM0_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM0_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM0_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM0_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM0_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM0_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM1 20:18 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_TEXAM1_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM1_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM1_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM1_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM1_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM1_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXAM1_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF0 23:21 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_TEXDF0_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF0_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF0_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF0_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF0_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF0_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF0_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF1 26:24 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_TEXDF1_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF1_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF1_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF1_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF1_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF1_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TEXDF1_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TTU 29:27 /* R-XVF */ #define NV_PTPC_PRI_SM_STATUS_TTU_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TTU_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TTU_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TTU_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TTU_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TTU_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_STATUS_TTU_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS 0x00000674 /* R--4R */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA0 2:0 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA0_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA0_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA0_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA0_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA0_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA0_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA0_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA1 5:3 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA1_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA1_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA1_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA1_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA1_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA1_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_RFA1_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_SMGR 8:6 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_SMGR_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_SMGR_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_SMGR_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_SMGR_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_SMGR_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_SMGR_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_SMGR_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_MMISC 11:9 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_MMISC_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_MMISC_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_MMISC_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_MMISC_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_MMISC_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_MMISC_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_MMISC_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PFET 14:12 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_PFET_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PFET_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PFET_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PFET_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PFET_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PFET_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PFET_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_ICC 17:15 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_ICC_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_ICC_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_ICC_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_ICC_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_ICC_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_ICC_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_ICC_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_GIF 20:18 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_GIF_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_GIF_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_GIF_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_GIF_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_GIF_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_GIF_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_GIF_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER0 23:21 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER0_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER0_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER0_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER0_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER0_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER0_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER0_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER1 26:24 /* R-XVF */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER1_EMPTY 0x00000000 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER1_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER1_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER1_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER1_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER1_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_SM_SFE_STATUS_PROFILER1_HAULTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_SM_TEX_CTRL 0x00000214 /* RWE4R */ #define NV_PTPC_PRI_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL 0:0 /* RWEVF */ #define NV_PTPC_PRI_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_INCLUDE_RFA 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TEX_CTRL_TEXAM_BLCG_INPUT_CTRL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL 1:1 /* RWEVF */ #define NV_PTPC_PRI_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_EXCLUDE_RFA 0x00000000 /* RW--V */ #define NV_PTPC_PRI_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_INCLUDE_RFA 0x00000001 /* RW--V */ #define NV_PTPC_PRI_SM_TEX_CTRL_TEXDF_BLCG_INPUT_CTRL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SM_TEX_CTRL_SPARE 31:2 /* RWEVF */ #define NV_PTPC_PRI_SM_TEX_CTRL_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_SMS_DBGR_STATUS0 0x00000680 /* R--4R */ #define NV_PTPC_PRI_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE_FALSE 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_DBGR_STATUS0_SM_IN_TRAP_MODE_TRUE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_DBGR_STATUS0_LOCKED_DOWN 4:4 /* R-XVF */ #define NV_PTPC_PRI_SMS_DBGR_STATUS0_LOCKED_DOWN_FALSE 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_DBGR_STATUS0_LOCKED_DOWN_TRUE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0 0x00000684 /* RWI4R */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_DEBUGGER_MODE 0:0 /* RWIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_DEBUGGER_MODE_ON 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE 3:3 /* RWIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW 10:7 /* RWIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW_256 0x8 /* RWI-V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW 14:11 /* RWIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW_INIT 0x3 /* RWI-V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP 24:24 /* RWIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE 28:28 /* RWIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT 29:29 /* -WIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_TASK 0x1 /* -W--T */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_INIT 0x0 /* -WI-V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_RUN_TRIGGER 30:30 /* -WIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_RUN_TRIGGER_TASK 0x1 /* -W--T */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_RUN_TRIGGER_TASK_INIT 0x0 /* -WI-V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_STOP_TRIGGER 31:31 /* RWIVF */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_DBGR_WARP_VALID_MASK_0 0x00000688 /* R--4R */ #define NV_PTPC_PRI_SMS_DBGR_WARP_VALID_MASK_0_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_DBGR_WARP_VALID_MASK_1 0x0000068c /* R--4R */ #define NV_PTPC_PRI_SMS_DBGR_WARP_VALID_MASK_1_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_DBGR_BPT_PAUSE_MASK_0 0x00000690 /* RW-4R */ #define NV_PTPC_PRI_SMS_DBGR_BPT_PAUSE_MASK_0_V 31:0 /* RWXVF */ #define NV_PTPC_PRI_SMS_DBGR_BPT_PAUSE_MASK_1 0x00000694 /* RW-4R */ #define NV_PTPC_PRI_SMS_DBGR_BPT_PAUSE_MASK_1_V 31:0 /* RWXVF */ #define NV_PTPC_PRI_SMS_DBGR_BPT_TRAP_MASK_0 0x00000698 /* R--4R */ #define NV_PTPC_PRI_SMS_DBGR_BPT_TRAP_MASK_0_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_DBGR_BPT_TRAP_MASK_1 0x0000069c /* R--4R */ #define NV_PTPC_PRI_SMS_DBGR_BPT_TRAP_MASK_1_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0 0x000006a0 /* R--4R */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0_LO_VALUE 31:0 /* R-IUF */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0_LO_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0_TEX_IDX 19:0 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0_COMPONENTS 26:20 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0_VA_IN_PAGE 24:20 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0_REQ_TYPE 27:27 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0_REQ_TYPE_SURFTEX 0x0 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_0_REQ_TYPE_LG 0x1 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1 0x000006a4 /* R--4R */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1_HI_VALUE 31:0 /* R-IUF */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1_HI_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1_D_SLOT_ID 9:0 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1_MASK_ROTATE_RIGHT 11:10 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1_MEMORY_LAYOUT 12:12 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1_SZ_SWAP 15:13 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1_KIND 23:16 /* */ #define NV_PTPC_PRI_SMS_HWW_ESR_ADDR_1_APERTURE 25:24 /* */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK 0x000006a8 /* RWI4R */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT 24:24 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT 25:25 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK 26:26 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE 27:27 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_REPORT_MASK_ARRIVE_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK 0x000006ac /* RWI4R */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA 12:12 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR 0x000006b0 /* RWI4R */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR 15:0 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_NONE 0x0000 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_API_STACK_ERROR 0x0002 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_PC 0x0005 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_PC_OVERFLOW 0x0006 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_REG 0x0008 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_ENCODING 0x0009 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_PARAM 0x000b /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_OOR_REG 0x000d /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_OOR_ADDR 0x000e /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_MISALIGNED_ADDR 0x000f /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_INVALID_ADDR_SPACE 0x0010 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_INVALID_CONST_ADDR_LDC 0x0012 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_MMU_FAULT 0x0017 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_TEX_FORMAT 0x0018 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_TEX_LAYOUT 0x0019 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_MMU_NACK 0x0020 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ERROR_ARRIVE 0x0021 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_WARP_ID 23:16 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_WARP_ID_INIT 0x00 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE 27:24 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_NONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_OVERFLOW_ADDR 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_OVERFLOW_ADDR 0x2 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_WINDOW_BTWN_HI_LO 0x3 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_LOCAL_WINDOW_BTWN_HI_LO 0x4 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_GLOBAL_MISALIGN_ADDR 0x5 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_LOCAL_MISALIGN_ADDR 0x6 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_SURF_OOR_ADDR 0x7 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_FAULT 0x8 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_FORMAT 0x9 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_LAYOUT 0xa /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_NACK 0xb /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_SHARED_OVERFLOW_ADDR 0xc /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_SHARED_MISALIGN_ADDR 0xd /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_ADDR_ERROR_TYPE_INIT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR 0x000006b4 /* RWI4R */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_BPT_INT 4:4 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_BPT_INT_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_BPT_INT_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_BPT_PAUSE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_ERROR_IN_TRAP_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_POISON_DATA 12:12 /* R-IVF */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_POISON_DATA_NOT_PENDING 0x0 /* R-I-V */ #define NV_PTPC_PRI_SMS_HWW_GLOBAL_ESR_POISON_DATA_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_PC 0x000006b8 /* R--4R */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_PC_VALUE 31:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_PC_HI 0x000006bc /* R--4R */ #define NV_PTPC_PRI_SMS_HWW_WARP_ESR_PC_HI_VALUE 31:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE 0x000006c0 /* RWI4R */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_SUBP0 5:0 /* RWIVF */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_SUBP0_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_SUBP1 11:6 /* RWIVF */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_SUBP1_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_SUBP2 17:12 /* RWIVF */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_SUBP2_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_SUBP3 23:18 /* RWIVF */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_SUBP3_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_CORE 25:24 /* RWIVF */ #define NV_PTPC_PRI_SMS_PM_SAMP_STATE_CORE_INIT 0x0 /* R-I-V */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET 0x000006e0 /* R--4R */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_SR64_PREEMPTION_SAVE 0:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_SR64_PREEMPTION_RESTORE 1:1 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_0 24:24 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_1 25:25 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_2 26:26 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_3 27:27 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_4 28:28 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_5 29:29 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_6 30:30 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_7 31:31 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_8 22:22 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_ESR_FET_OBSERVE_CYA_9 23:23 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS 0x000006e4 /* R--4R */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH 2:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_SCH_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP 5:3 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_DISP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC 8:6 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTUALLY_QUIESCENT 0x7 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU 11:9 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_CBU_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC 14:12 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_MIOC_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP 17:15 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_SCTL_SUBUNIT_STATUS_TRAP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS 0x000006e8 /* R--4R */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP 2:0 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA 5:3 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1DATA_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG 8:6 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS 11:9 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_FAULTED 0x6 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_HAULTED 0x7 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT 14:12 /* R-XVF */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_HALTED 0x6 /* R---V */ #define NV_PTPC_PRI_SMS_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_FAULTEDED 0x7 /* R---V */ #define NV_PTPC_PRI_SMS_HWW_ESR_INFO 0x000006ec /* R--4R */ #define NV_PTPC_PRI_SMS_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PTPC_PRI_SMS_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PTPC_PRI_SM0_DBGR_STATUS0 0x00000700 /* R--4R */ #define NV_PTPC_PRI_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE_FALSE 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_DBGR_STATUS0_SM_IN_TRAP_MODE_TRUE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_DBGR_STATUS0_LOCKED_DOWN 4:4 /* R-XVF */ #define NV_PTPC_PRI_SM0_DBGR_STATUS0_LOCKED_DOWN_FALSE 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_DBGR_STATUS0_LOCKED_DOWN_TRUE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0 0x00000704 /* RWI4R */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_DEBUGGER_MODE 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_DEBUGGER_MODE_ON 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE 3:3 /* RWIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW 10:7 /* RWIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW_256 0x8 /* RWI-V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW 14:11 /* RWIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW_INIT 0x3 /* RWI-V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE 28:28 /* RWIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT 29:29 /* -WIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_TASK 0x1 /* -W--T */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_INIT 0x0 /* -WI-V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_RUN_TRIGGER 30:30 /* -WIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_RUN_TRIGGER_TASK 0x1 /* -W--T */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_RUN_TRIGGER_TASK_INIT 0x0 /* -WI-V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_STOP_TRIGGER 31:31 /* RWIVF */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_DBGR_WARP_VALID_MASK_0 0x00000708 /* R--4R */ #define NV_PTPC_PRI_SM0_DBGR_WARP_VALID_MASK_0_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_DBGR_WARP_VALID_MASK_1 0x0000070c /* R--4R */ #define NV_PTPC_PRI_SM0_DBGR_WARP_VALID_MASK_1_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_DBGR_BPT_PAUSE_MASK_0 0x00000710 /* RW-4R */ #define NV_PTPC_PRI_SM0_DBGR_BPT_PAUSE_MASK_0_V 31:0 /* RWXVF */ #define NV_PTPC_PRI_SM0_DBGR_BPT_PAUSE_MASK_1 0x00000714 /* RW-4R */ #define NV_PTPC_PRI_SM0_DBGR_BPT_PAUSE_MASK_1_V 31:0 /* RWXVF */ #define NV_PTPC_PRI_SM0_DBGR_BPT_TRAP_MASK_0 0x00000718 /* R--4R */ #define NV_PTPC_PRI_SM0_DBGR_BPT_TRAP_MASK_0_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_DBGR_BPT_TRAP_MASK_1 0x0000071c /* R--4R */ #define NV_PTPC_PRI_SM0_DBGR_BPT_TRAP_MASK_1_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0 0x00000720 /* R--4R */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0_LO_VALUE 31:0 /* R-IUF */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0_LO_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0_TEX_IDX 19:0 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0_COMPONENTS 26:20 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0_VA_IN_PAGE 24:20 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0_REQ_TYPE 27:27 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0_REQ_TYPE_SURFTEX 0x0 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_0_REQ_TYPE_LG 0x1 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1 0x00000724 /* R--4R */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1_HI_VALUE 31:0 /* R-IUF */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1_HI_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1_D_SLOT_ID 9:0 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1_MASK_ROTATE_RIGHT 11:10 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1_MEMORY_LAYOUT 12:12 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1_SZ_SWAP 15:13 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1_KIND 23:16 /* */ #define NV_PTPC_PRI_SM0_HWW_ESR_ADDR_1_APERTURE 25:24 /* */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK 0x00000728 /* RWI4R */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT 25:25 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK 26:26 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE 27:27 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_REPORT_MASK_ARRIVE_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK 0x0000072c /* RWI4R */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA 12:12 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR 0x00000730 /* RWI4R */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR 15:0 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_NONE 0x0000 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_API_STACK_ERROR 0x0002 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_PC 0x0005 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_PC_OVERFLOW 0x0006 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_REG 0x0008 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_ENCODING 0x0009 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_PARAM 0x000b /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_OOR_REG 0x000d /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_OOR_ADDR 0x000e /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_MISALIGNED_ADDR 0x000f /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_INVALID_ADDR_SPACE 0x0010 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_INVALID_CONST_ADDR_LDC 0x0012 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_MMU_FAULT 0x0017 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_TEX_FORMAT 0x0018 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_TEX_LAYOUT 0x0019 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_MMU_NACK 0x0020 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ERROR_ARRIVE 0x0021 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_WARP_ID 23:16 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_WARP_ID_INIT 0x00 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE 27:24 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_NONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_OVERFLOW_ADDR 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_OVERFLOW_ADDR 0x2 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_WINDOW_BTWN_HI_LO 0x3 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_LOCAL_WINDOW_BTWN_HI_LO 0x4 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_GLOBAL_MISALIGN_ADDR 0x5 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_LOCAL_MISALIGN_ADDR 0x6 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_SURF_OOR_ADDR 0x7 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_FAULT 0x8 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_FORMAT 0x9 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_LAYOUT 0xa /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_NACK 0xb /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_SHARED_OVERFLOW_ADDR 0xc /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_SHARED_MISALIGN_ADDR 0xd /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_ADDR_ERROR_TYPE_INIT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR 0x00000734 /* RWI4R */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_BPT_INT 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_BPT_INT_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_BPT_INT_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_BPT_PAUSE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_ERROR_IN_TRAP_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_POISON_DATA 12:12 /* R-IVF */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_POISON_DATA_NOT_PENDING 0x0 /* R-I-V */ #define NV_PTPC_PRI_SM0_HWW_GLOBAL_ESR_POISON_DATA_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_PC 0x00000738 /* R--4R */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_PC_VALUE 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_PC_HI 0x0000073c /* R--4R */ #define NV_PTPC_PRI_SM0_HWW_WARP_ESR_PC_HI_VALUE 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE 0x00000740 /* RWI4R */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_SUBP0 5:0 /* RWIVF */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_SUBP0_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_SUBP1 11:6 /* RWIVF */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_SUBP1_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_SUBP2 17:12 /* RWIVF */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_SUBP2_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_SUBP3 23:18 /* RWIVF */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_SUBP3_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_CORE 25:24 /* RWIVF */ #define NV_PTPC_PRI_SM0_PM_SAMP_STATE_CORE_INIT 0x0 /* R-I-V */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET 0x00000760 /* R--4R */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_SR64_PREEMPTION_SAVE 0:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_SR64_PREEMPTION_RESTORE 1:1 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_0 24:24 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_1 25:25 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_2 26:26 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_3 27:27 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_4 28:28 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_5 29:29 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_6 30:30 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_7 31:31 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_8 22:22 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_ESR_FET_OBSERVE_CYA_9 23:23 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS 0x00000764 /* R--4R */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH 2:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_SCH_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP 5:3 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_DISP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC 8:6 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTUALLY_QUIESCENT 0x7 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU 11:9 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_CBU_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC 14:12 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_MIOC_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP 17:15 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_SCTL_SUBUNIT_STATUS_TRAP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS 0x00000768 /* R--4R */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP 2:0 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA 5:3 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1DATA_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG 8:6 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS 11:9 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_FAULTED 0x6 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_HAULTED 0x7 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT 14:12 /* R-XVF */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_HALTED 0x6 /* R---V */ #define NV_PTPC_PRI_SM0_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_FAULTEDED 0x7 /* R---V */ #define NV_PTPC_PRI_SM0_HWW_ESR_INFO 0x0000076c /* R--4R */ #define NV_PTPC_PRI_SM0_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PTPC_PRI_SM0_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PTPC_PRI_SM1_DBGR_STATUS0 0x00000780 /* R--4R */ #define NV_PTPC_PRI_SM1_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_DBGR_STATUS0_SM_IN_TRAP_MODE_FALSE 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_DBGR_STATUS0_SM_IN_TRAP_MODE_TRUE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_DBGR_STATUS0_LOCKED_DOWN 4:4 /* R-XVF */ #define NV_PTPC_PRI_SM1_DBGR_STATUS0_LOCKED_DOWN_FALSE 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_DBGR_STATUS0_LOCKED_DOWN_TRUE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0 0x00000784 /* RWI4R */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_DEBUGGER_MODE 0:0 /* RWIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_DEBUGGER_MODE_ON 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_SINGLE_STEP_MODE 3:3 /* RWIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW 10:7 /* RWIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_TRAP_COALLESCE_WINDOW_256 0x8 /* RWI-V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW 14:11 /* RWIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_TRAP_DEGLITCH_WINDOW_INIT 0x3 /* RWI-V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_ENABLE_ERROR_IN_TRAP_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE 28:28 /* RWIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_STOP_IS_NOT_MASKABLE_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT 29:29 /* -WIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_TASK 0x1 /* -W--T */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_SKIP_IDLE_WARP_DETECT_INIT 0x0 /* -WI-V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_RUN_TRIGGER 30:30 /* -WIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_RUN_TRIGGER_TASK 0x1 /* -W--T */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_RUN_TRIGGER_TASK_INIT 0x0 /* -WI-V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_STOP_TRIGGER 31:31 /* RWIVF */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_DBGR_WARP_VALID_MASK_0 0x00000788 /* R--4R */ #define NV_PTPC_PRI_SM1_DBGR_WARP_VALID_MASK_0_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_DBGR_WARP_VALID_MASK_1 0x0000078c /* R--4R */ #define NV_PTPC_PRI_SM1_DBGR_WARP_VALID_MASK_1_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_DBGR_BPT_PAUSE_MASK_0 0x00000790 /* RW-4R */ #define NV_PTPC_PRI_SM1_DBGR_BPT_PAUSE_MASK_0_V 31:0 /* RWXVF */ #define NV_PTPC_PRI_SM1_DBGR_BPT_PAUSE_MASK_1 0x00000794 /* RW-4R */ #define NV_PTPC_PRI_SM1_DBGR_BPT_PAUSE_MASK_1_V 31:0 /* RWXVF */ #define NV_PTPC_PRI_SM1_DBGR_BPT_TRAP_MASK_0 0x00000798 /* R--4R */ #define NV_PTPC_PRI_SM1_DBGR_BPT_TRAP_MASK_0_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_DBGR_BPT_TRAP_MASK_1 0x0000079c /* R--4R */ #define NV_PTPC_PRI_SM1_DBGR_BPT_TRAP_MASK_1_V 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0 0x000007a0 /* R--4R */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0_LO_VALUE 31:0 /* R-IUF */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0_LO_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0_TEX_IDX 19:0 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0_COMPONENTS 26:20 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0_VA_IN_PAGE 24:20 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0_REQ_TYPE 27:27 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0_REQ_TYPE_SURFTEX 0x0 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_0_REQ_TYPE_LG 0x1 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1 0x000007a4 /* R--4R */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1_HI_VALUE 31:0 /* R-IUF */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1_HI_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1_D_SLOT_ID 9:0 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1_MASK_ROTATE_RIGHT 11:10 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1_MEMORY_LAYOUT 12:12 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1_SZ_SWAP 15:13 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1_KIND 23:16 /* */ #define NV_PTPC_PRI_SM1_HWW_ESR_ADDR_1_APERTURE 25:24 /* */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK 0x000007a8 /* RWI4R */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_OOR_REG_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT 24:24 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_TEX_FORMAT_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT 25:25 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_TEX_LAYOUT_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MMU_NACK 26:26 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_MMU_NACK_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ARRIVE 27:27 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ARRIVE_REPORT 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_REPORT_MASK_ARRIVE_NO_REPORT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK 0x000007ac /* RWI4R */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_ERROR_IN_TRAP_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA 12:12 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_NO_REPORT 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_REPORT_MASK_POISON_DATA_REPORT 0x1 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR 0x000007b0 /* RWI4R */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR 15:0 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_NONE 0x0000 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_API_STACK_ERROR 0x0002 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_MISALIGNED_PC 0x0005 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_PC_OVERFLOW 0x0006 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_MISALIGNED_REG 0x0008 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_ENCODING 0x0009 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_ILLEGAL_INSTR_PARAM 0x000b /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_OOR_REG 0x000d /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_OOR_ADDR 0x000e /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_MISALIGNED_ADDR 0x000f /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_INVALID_ADDR_SPACE 0x0010 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_INVALID_CONST_ADDR_LDC 0x0012 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_MMU_FAULT 0x0017 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_TEX_FORMAT 0x0018 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_TEX_LAYOUT 0x0019 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_MMU_NACK 0x0020 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ERROR_ARRIVE 0x0021 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_WARP_ID 23:16 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_WARP_ID_INIT 0x00 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE 27:24 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_NONE 0x0 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_OVERFLOW_ADDR 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_OVERFLOW_ADDR 0x2 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_EXP_LOCAL_WINDOW_BTWN_HI_LO 0x3 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_GENERIC_LOCAL_WINDOW_BTWN_HI_LO 0x4 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_GLOBAL_MISALIGN_ADDR 0x5 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_LOCAL_MISALIGN_ADDR 0x6 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_SURF_OOR_ADDR 0x7 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_FAULT 0x8 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_FORMAT 0x9 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_TEX_LAYOUT 0xa /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_MMU_NACK 0xb /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_OOR_SHARED_OVERFLOW_ADDR 0xc /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_SHARED_MISALIGN_ADDR 0xd /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_ADDR_ERROR_TYPE_INIT 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR 0x000007b4 /* RWI4R */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS 2:2 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_BPT_INT 4:4 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_BPT_INT_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_BPT_INT_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_BPT_PAUSE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_ERROR_IN_TRAP 8:8 /* RWIVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_ERROR_IN_TRAP_NOT_PENDING 0x0 /* RWI-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_ERROR_IN_TRAP_PENDING 0x1 /* RW--V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_POISON_DATA 12:12 /* R-IVF */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_POISON_DATA_NOT_PENDING 0x0 /* R-I-V */ #define NV_PTPC_PRI_SM1_HWW_GLOBAL_ESR_POISON_DATA_PENDING 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_PC 0x000007b8 /* R--4R */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_PC_VALUE 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_PC_HI 0x000007bc /* R--4R */ #define NV_PTPC_PRI_SM1_HWW_WARP_ESR_PC_HI_VALUE 31:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE 0x000007c0 /* RWI4R */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_SUBP0 5:0 /* RWIVF */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_SUBP0_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_SUBP1 11:6 /* RWIVF */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_SUBP1_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_SUBP2 17:12 /* RWIVF */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_SUBP2_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_SUBP3 23:18 /* RWIVF */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_SUBP3_INIT 0x00 /* R-I-V */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_CORE 25:24 /* RWIVF */ #define NV_PTPC_PRI_SM1_PM_SAMP_STATE_CORE_INIT 0x0 /* R-I-V */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET 0x000007e0 /* R--4R */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_SR64_PREEMPTION_SAVE 0:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_SR64_PREEMPTION_RESTORE 1:1 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_0 24:24 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_1 25:25 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_2 26:26 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_3 27:27 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_4 28:28 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_5 29:29 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_6 30:30 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_7 31:31 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_8 22:22 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_ESR_FET_OBSERVE_CYA_9 23:23 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS 0x000007e4 /* R--4R */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_SCH 2:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_SCH_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_SCH_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_SCH_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_SCH_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_DISP 5:3 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_DISP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_DISP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_DISP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_DISP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_IMC 8:6 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_IMC_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_IMC_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_IMC_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_IMC_ACTUALLY_QUIESCENT 0x7 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_CBU 11:9 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_CBU_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_CBU_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_CBU_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_CBU_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_MIOC 14:12 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_MIOC_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_MIOC_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_MIOC_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_MIOC_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_TRAP 17:15 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_TRAP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_TRAP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_TRAP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_SCTL_SUBUNIT_STATUS_TRAP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS 0x000007e8 /* R--4R */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_MIOP 2:0 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_MIOP_PIXOUT_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1DATA 5:3 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1DATA_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1DATA_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1DATA_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1DATA_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1TAG 8:6 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1TAG_MIOP_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1MISS 11:9 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_FAULTED 0x6 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_L1MISS_L1TAG_HAULTED 0x7 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_PIXOUT 14:12 /* R-XVF */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_PAUSED 0x2 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_HALTED 0x6 /* R---V */ #define NV_PTPC_PRI_SM1_INFO_L1C_SUBUNIT_STATUS_PIXOUT_L1MISS_FAULTEDED 0x7 /* R---V */ #define NV_PTPC_PRI_SM1_HWW_ESR_INFO 0x000007ec /* R--4R */ #define NV_PTPC_PRI_SM1_HWW_ESR_INFO_VEID 5:0 /* R-EVF */ #define NV_PTPC_PRI_SM1_HWW_ESR_INFO_VEID_INIT 0x00 /* R-E-V */ #define NV_PTPC_PRI_TEX_IN_DBG 0x00000200 /* RWI4R */ #define NV_PTPC_PRI_TEX_IN_DBG_HEADER_TAGMODE 0:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_HEADER_TAGMODE_AUTO 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_HEADER_TAGMODE_MISS 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_SAMPLER_TAGMODE 1:1 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_SAMPLER_TAGMODE_AUTO 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_SAMPLER_TAGMODE_MISS 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FORCE_INVALIDATE 10:10 /* -WIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FORCE_INVALIDATE_RESET 0x00000000 /* -WI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FORCE_INVALIDATE_ACTIVE 0x00000001 /* -W--T */ #define NV_PTPC_PRI_TEX_IN_DBG_TSL1_ENTRIES 15:12 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_TSL1_ENTRIES_FULL 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_ZERO_OFFSET_OPT 16:16 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_ZERO_OFFSET_OPT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_ZERO_OFFSET_OPT_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D 18:18 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_INVAL_3D_TSL1_ON_TEX_IN_2D_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 19:19 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH 20:20 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH_ENABLED 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_SURFACE_USE_FAST_POINT_SAMPLE_PATH_DISABLED 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM 21:21 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_SNORM_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN 22:22 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_FP16_RETURN_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY 23:23 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_ARRAY_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER 24:24 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_MIP_FILTER_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR 25:25 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_BORDER_COLOR_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT 26:26 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_CACHE_LAYOUT_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER 27:27 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_1D_BUFFER_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP 28:28 /* RWIVF */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP_DISABLE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_IN_DBG_FAST_POINT_SAMPLE_VETO_COLOR_KEY_OP_ENABLE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_LOD_DBG 0x00000204 /* RWI4R */ #define NV_PTPC_PRI_TEX_LOD_DBG_CUBEMAP_ANISO 0:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_LOD_DBG_CUBEMAP_ANISO_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_LOD_DBG_CUBEMAP_ANISO_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_LOD_DBG_CUBESEAM_ANISO 1:1 /* RWIVF */ #define NV_PTPC_PRI_TEX_LOD_DBG_CUBESEAM_ANISO_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_LOD_DBG_CUBESEAM_ANISO_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_LOD_DBG_UNOPT_LOD_CLAMP 2:2 /* RWIVF */ #define NV_PTPC_PRI_TEX_LOD_DBG_UNOPT_LOD_CLAMP_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_LOD_DBG_UNOPT_LOD_CLAMP_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_TXL 3:3 /* RWIVF */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_TXL_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_TXL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_TXB 4:4 /* RWIVF */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_TXB_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_TXB_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_LC 5:5 /* RWIVF */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_LC_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_LOD_DBG_SERIALIZE_LC_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_DBG 0x00000208 /* RWI4R */ #define NV_PTPC_PRI_TEX_SAMP_DBG_NOP_OPT 0:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_SAMP_DBG_NOP_OPT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_NOP_OPT_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_SAMPSTAT 3:3 /* RWIVF */ #define NV_PTPC_PRI_TEX_SAMP_DBG_SAMPSTAT_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_SAMPSTAT_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_UNOPT_LOD_SPREAD 4:4 /* RWIVF */ #define NV_PTPC_PRI_TEX_SAMP_DBG_UNOPT_LOD_SPREAD_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_UNOPT_LOD_SPREAD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_COMPATIBILITY_PRECISION 5:5 /* RWIVF */ #define NV_PTPC_PRI_TEX_SAMP_DBG_COMPATIBILITY_PRECISION_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_COMPATIBILITY_PRECISION_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_FILTER_64B 7:6 /* RWIVF */ #define NV_PTPC_PRI_TEX_SAMP_DBG_FILTER_64B_FULL_SPEED 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_FILTER_64B_HALF_SPEED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_FILTER_64B_ANISO_HALF_SPEED 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_W_WEIGHT_CG_OPT 9:9 /* RWIVF */ #define NV_PTPC_PRI_TEX_SAMP_DBG_W_WEIGHT_CG_OPT_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_DBG_W_WEIGHT_CG_OPT_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_PM_CTRL 0x000002B0 /* RWE4R */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL 6:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP10 0x0000000a /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP11 0x0000000b /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP12 0x0000000c /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP13 0x0000000d /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP14 0x0000000e /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP15 0x0000000f /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP16 0x00000010 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP17 0x00000011 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP18 0x00000012 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP19 0x00000013 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP20 0x00000014 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP21 0x00000015 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP22 0x00000016 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP23 0x00000017 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP24 0x00000018 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP25 0x00000019 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP26 0x0000001a /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP27 0x0000001b /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_SINGLE_PASS0 0x0000001c /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_SINGLE_PASS_COMPUTE 0x0000001d /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_STATIC_PATTERN0 0x0000001e /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_STATIC_PATTERN1 0x0000001f /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_SINGLE_PASS1 0x00000020 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_GRP28 0x00000021 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_APM_GROUP_7 0x00000078 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_APM_GROUP_6 0x00000079 /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_APM_GROUP_5 0x0000007a /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_APM_GROUP_4 0x0000007b /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_APM_GROUP_3 0x0000007c /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_APM_GROUP_2 0x0000007d /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_APM_GROUP_1 0x0000007e /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_APM_GROUP_0 0x0000007f /* RW--V */ #define NV_PTPC_PRI_TEX_PM_CTRL_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_PM_CTRL_ENABLE 7:7 /* RWEVF */ #define NV_PTPC_PRI_TEX_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_X_DBG 0x0000020C /* RWI4R */ #define NV_PTPC_PRI_TEX_X_DBG_SUBSET_PICK 3:2 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SUBSET_PICK_AUTO 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_SUBSET_PICK_ZERO 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_X_DBG_SUBSET_PICK_ZERO_TO_ONE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_1B 5:4 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_1B_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_2B 7:6 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_2B_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_4B 9:8 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_4B_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_8B 11:10 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_8B_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_12B 13:12 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_12B_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_16B 15:14 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_16B_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_DXT1 17:16 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_DXT1_INIT 0x00000002 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_DXT2 19:18 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_SETFUNC_DXT2_INIT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_T2D_COMPRESSION 20:20 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_T2D_COMPRESSION_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_X_DBG_T2D_COMPRESSION_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_X_DBG_RLAT_DEPTH_DIV8 26:21 /* RWIVF */ #define NV_PTPC_PRI_TEX_X_DBG_RLAT_DEPTH_DIV8_FULL 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_W_DBG 0x00000210 /* RWI4R */ #define NV_PTPC_PRI_TEX_W_DBG_LATFIFO_DEPTH_DIV4 7:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_W_DBG_LATFIFO_DEPTH_DIV4_FULL 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG 0x0000021C /* RWI4R */ #define NV_PTPC_PRI_TEX_D_DBG_ROWCOL_SERIAL 8:8 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_ROWCOL_SERIAL_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_ROWCOL_SERIAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_BANK_SERIAL 9:9 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_BANK_SERIAL_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_BANK_SERIAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_CONVERT_NEAREST_AS_TLD 11:11 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_CONVERT_NEAREST_AS_TLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_CONVERT_NEAREST_AS_TLD_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_CONVERT_NEAREST_AS_TLD__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_FILTER_64B 13:12 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_FILTER_64B_FULL_SPEED 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_FILTER_64B_HALF_SPEED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_FILTER_64B_ANISO_HALF_SPEED 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD 14:14 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_COMPUTE_CONVERT_NEAREST_AS_TLD_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_CACHE_QUIET_READ 15:15 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_CACHE_QUIET_READ_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_CACHE_QUIET_READ_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_OVERRIDE 17:17 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_OVERRIDE_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_IDLE_EN 18:18 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_IDLE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_IDLE_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_STALL_EN 19:19 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_STALL_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_SLCG_STALL_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_D_DBG_LG_EXPAND_BILERP 20:20 /* RWIVF */ #define NV_PTPC_PRI_TEX_D_DBG_LG_EXPAND_BILERP_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_D_DBG_LG_EXPAND_BILERP_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x000002CC /* RWE4R */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PTPC_PRI_TEX_M_DBG 0x00000220 /* RWI4R */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK 0:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRN_SUBP_OLDEST_BLOCK_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP_DRNLOCK 1:1 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP_DRNLOCK_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP_DRNLOCK_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP2_BOOST 2:2 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP2_BOOST_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP2_BOOST_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP3_BOOST 3:3 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP3_BOOST_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP3_BOOST_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP4_RECYCLE 4:4 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP4_RECYCLE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_CP4_RECYCLE_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT 7:5 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_NONE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_2 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_8 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_16 0x00000003 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_24 0x00000004 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_32 0x00000005 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_64 0x00000006 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_DRNGRP_WAVE_LIMIT_128 0x00000007 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_FB_SECTOR_SERIAL 8:8 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_FB_SECTOR_SERIAL_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_FB_SECTOR_SERIAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_READ_PACKING_EN 9:9 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_READ_PACKING_EN_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_READ_PACKING_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_ONLY_ONE_FB_REQ 10:10 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_ONLY_ONE_FB_REQ_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_ONLY_ONE_FB_REQ_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_L1TAG_DESC_EVICT_LAST 11:11 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_L1TAG_DESC_EVICT_LAST_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_L1TAG_DESC_EVICT_LAST_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_INJECT_MEMBAR_PRIORITY 12:12 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_INJECT_MEMBAR_PRIORITY_HIGH 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_INJECT_MEMBAR_PRIORITY_NORMAL 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_FB_STENCIL_SERIAL 13:13 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_FB_STENCIL_SERIAL_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_FB_STENCIL_SERIAL_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU 14:14 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_L1TAG_CTRL_CACHE_TTU_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_WRITE_CONCAT_EN 15:15 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_WRITE_CONCAT_EN_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_WRITE_CONCAT_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS 16:16 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_MEMBAR_SYNC_IN_L1MISS_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_NACK_RESP 17:17 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_NACK_RESP_KILL_ALL_BUT_MEMBAR_CORRECT 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_NACK_RESP_KILL_ALL_CORRECT 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_SCO_GPU_AS_STRONG 18:18 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_SCO_GPU_AS_STRONG_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_SCO_GPU_AS_STRONG_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE 20:19 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_OUT_OF_ORD 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_TEXLG_LH 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_TEXLG_TQ01 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_OOOT2D_TQ_ALLOC_MODE_IN_ORDER 0x00000003 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_FPS_TEXTLD_AS_SURF 21:21 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_FPS_TEXTLD_AS_SURF_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_FPS_TEXTLD_AS_SURF_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_GNIC_POISON_IGNORE 22:22 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_GNIC_POISON_IGNORE_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_GNIC_POISON_IGNORE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_OVERRIDE 23:23 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_OVERRIDE_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_IDLE_EN 24:24 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_IDLE_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_IDLE_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_STALL_EN 25:25 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_STALL_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_SLCG_STALL_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_READ_CMD_HOLDOFF 30:26 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_READ_CMD_HOLDOFF_ZERO 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG_MIW_READ_CMD_HOLDOFF_INIT 0x00000007 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG2 0x0000023C /* RWI4R */ #define NV_PTPC_PRI_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK 23:4 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK_DEFAULT 0x0003718d /* RWI-V */ #define NV_PTPC_PRI_TEX_M_DBG2_L1TAG_DESC_INVERT_MASK_GA100 0x0003718d /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG2_MIW_PAUSED_OVERRIDE 31:31 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_DBG2_MIW_PAUSED_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_M_DBG2_MIW_PAUSED_OVERRIDE_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_ROUTING 0x000002C4 /* RWI4R */ #define NV_PTPC_PRI_TEX_M_ROUTING_SEL 1:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_M_ROUTING_SEL_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_ROUTING_SEL_PIPE0 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_M_ROUTING_SEL_PIPE1 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_M_ROUTING_SEL__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE 0x000002C8 /* RWI4R */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_LG 0:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_LG_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_LG_ENABLE 0x00000001 /* RW--T */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX 1:1 /* RWIVF */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_TEX_ENABLE 0x00000001 /* RW--T */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1 2:2 /* RWIVF */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_RESET_L1_ENABLE 0x00000001 /* RW--T */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH 3:3 /* RWIVF */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_T_DBG2_L1_DATA_INVALIDATE_CBUF_FLUSH_ENABLE 0x00000001 /* RW--T */ #define NV_PTPC_PRI_TEX_F_DBG 0x00000230 /* RWI4R */ #define NV_PTPC_PRI_TEX_F_DBG_MADD_64B_LANA_CYA 0:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_F_DBG_MADD_64B_LANA_CYA_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_F_DBG_MADD_64B_LANA_CYA_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_F_DBG_FP16_ROUNDING_MODE 3:2 /* RWIVF */ #define NV_PTPC_PRI_TEX_F_DBG_FP16_ROUNDING_MODE_INSTR 0x00000000 /* RWI-V */ #define NV_PTPC_PRI_TEX_F_DBG_FP16_ROUNDING_MODE_FORCE_RTZ 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_F_DBG_FP16_ROUNDING_MODE_FORCE_RTNE 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_F_DBG_PS_BYPASS 4:4 /* RWIVF */ #define NV_PTPC_PRI_TEX_F_DBG_PS_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_F_DBG_PS_BYPASS_ENABLE 0x00000001 /* RWI-V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS 0x00000238 /* R--4R */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIN 10:8 /* R-XVF */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIN_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_F 13:11 /* R-XVF */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_F_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_F_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_F_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_F_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_F_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_D 16:14 /* R-XVF */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_D_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_D_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_D_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_D_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_D_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TM 19:17 /* R-XVF */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TM_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TM_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TM_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TM_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TM_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_X 22:20 /* R-XVF */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_X_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_X_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_X_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_X_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_X_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIO 25:23 /* R-XVF */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_TEXIO_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_W 28:26 /* R-XVF */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_W_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_W_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_W_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_W_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_W_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_MIPB 31:29 /* R-XVF */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_MIPB_EMPTY 0x0 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_MIPB_ACTIVE 0x1 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_MIPB_QUIESCENT 0x3 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_MIPB_STALLED 0x5 /* R---V */ #define NV_PTPC_PRI_TEX_M_TEX_SUBUNITS_STATUS_MIPB_HALTED 0x7 /* R---V */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_INDEX 0x000002A8 /* RW-4R */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_INDEX__PRIV_LEVEL_MASK 0x000002CC /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_INDEX_INDEX 7:0 /* RWBVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_INDEX_INDEX_ZERO 0 /* RWB-V */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_INDEX_INDEX_MIN 0 /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_INDEX_INDEX_MAX 23 /* RW--V */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_DATA 0x000002AC /* RW-4R */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_DATA__PRIV_LEVEL_MASK 0x000002CC /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_DATA__APERTURE_INDEX_OFFSET (0x000002A8 - 0x000002AC) /* */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_DATA_DATA 27:0 /* RWBVF */ #define NV_PTPC_PRI_TEX_M_BLK_ACT_DATA_DATA_INIT 0x00000000 /* RWB-V */ #define NV_PTPC_PRI_TEX_RM_CB_0 0x00000600 /* RWI4R */ #define NV_PTPC_PRI_TEX_RM_CB_0_BASE_ADDR_43_12 31:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_RM_CB_0_BASE_ADDR_43_12_INIT 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_RM_CB_1 0x00000604 /* RWI4R */ #define NV_PTPC_PRI_TEX_RM_CB_1_SIZE_DIV_128B 20:0 /* RWIVF */ #define NV_PTPC_PRI_TEX_RM_CB_1_SIZE_DIV_128B_INIT 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_RM_CB_1_SIZE_DIV_128B_GRANULARITY 0x80 /* RW--V */ #define NV_PTPC_PRI_TEX_RM_CB_1_BASE_ADDR_48_44 28:24 /* RWIVF */ #define NV_PTPC_PRI_TEX_RM_CB_1_BASE_ADDR_48_44_INIT 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_RM_CB_1_LTC_CLASS 30:30 /* RWIVF */ #define NV_PTPC_PRI_TEX_RM_CB_1_LTC_CLASS_PASS_THRU 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_RM_CB_1_LTC_CLASS_EVICT_LAST 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_RM_CB_1_VALID 31:31 /* RWIVF */ #define NV_PTPC_PRI_TEX_RM_CB_1_VALID_FALSE 0x0 /* RWI-V */ #define NV_PTPC_PRI_TEX_RM_CB_1_VALID_TRUE 0x1 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG 0x00000240 /* RWE4R */ #define NV_PTPC_PRI_TEX_IN_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_IN_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IN_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_IN_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IN_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_IN_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IN_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_IN_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_TEX_IN_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_IN_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IN_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_IN_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IN_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_IN_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IN_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_IN_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_IN_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IN_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_IN_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IN_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IN_CG1 0x00000244 /* RWE4R */ #define NV_PTPC_PRI_TEX_IN_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_IN_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IN_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG1_SLCG 3:1 /* RWEVF */ #define NV_PTPC_PRI_TEX_IN_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IN_CG1_SLCG_DISABLED 0x00000007 /* RWE-V */ #define NV_PTPC_PRI_TEX_IN_CG1_SLCG__PROD 0x00000004 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG 0x00000248 /* RWE4R */ #define NV_PTPC_PRI_TEX_SAMP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_SAMP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_SAMP_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_SAMP_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_SAMP_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_SAMP_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_SAMP_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_SAMP_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_SAMP_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_SAMP_CG1 0x0000024C /* RWE4R */ #define NV_PTPC_PRI_TEX_SAMP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_SAMP_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_SAMP_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG1_SLCG 8:1 /* RWEVF */ #define NV_PTPC_PRI_TEX_SAMP_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_SAMP_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */ #define NV_PTPC_PRI_TEX_SAMP_CG1_SLCG__PROD 0x000000FC /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG 0x00000250 /* RWE4R */ #define NV_PTPC_PRI_TEX_X_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_X_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_X_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_X_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_X_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_X_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_X_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_X_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_TEX_X_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_X_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_X_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_X_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_X_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_X_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_X_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_X_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_X_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_X_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_X_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_X_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_X_CG1 0x00000254 /* RWE4R */ #define NV_PTPC_PRI_TEX_X_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_X_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_X_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG1_SLCG 5:1 /* RWEVF */ #define NV_PTPC_PRI_TEX_X_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_X_CG1_SLCG_DISABLED 0x0000001F /* RWE-V */ #define NV_PTPC_PRI_TEX_X_CG1_SLCG__PROD 0x0000001E /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG 0x00000258 /* RWE4R */ #define NV_PTPC_PRI_TEX_W_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_W_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_W_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_W_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_W_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_W_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_W_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_W_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_TEX_W_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_W_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_W_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_W_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_W_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_W_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_W_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_W_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_W_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_W_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_W_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_W_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_W_CG1 0x0000025C /* RWE4R */ #define NV_PTPC_PRI_TEX_W_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_W_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_W_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG1_SLCG 3:1 /* RWEVF */ #define NV_PTPC_PRI_TEX_W_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_W_CG1_SLCG_DISABLED 0x00000007 /* RWE-V */ #define NV_PTPC_PRI_TEX_W_CG1_SLCG__PROD 0x00000006 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG 0x00000260 /* RWE4R */ #define NV_PTPC_PRI_TEX_D_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_D_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_D_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_D_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_D_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_D_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_D_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_D_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_TEX_D_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_D_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_D_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_D_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_D_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_D_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_D_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_D_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_D_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_D_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_D_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_D_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_D_CG1 0x00000264 /* RWE4R */ #define NV_PTPC_PRI_TEX_D_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_D_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_D_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG1_SLCG 8:1 /* RWEVF */ #define NV_PTPC_PRI_TEX_D_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_D_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */ #define NV_PTPC_PRI_TEX_D_CG1_SLCG__PROD 0x000000D3 /* RW--V */ #define NV_PTPC_PRI_TEX_IO_CG 0x00000268 /* RWE4R */ #define NV_PTPC_PRI_TEX_IO_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_IO_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IO_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_IO_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_IO_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IO_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IO_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IO_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_IO_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IO_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_IO_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_TEX_IO_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_IO_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IO_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IO_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IO_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_IO_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IO_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_IO_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IO_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_IO_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_IO_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IO_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_IO_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_IO_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_IO_CG1 0x0000026C /* RWE4R */ #define NV_PTPC_PRI_TEX_IO_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_IO_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_IO_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_IO_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG 0x00000278 /* RWE4R */ #define NV_PTPC_PRI_TEX_F_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_F_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_F_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_F_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_F_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_F_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_F_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_F_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_TEX_F_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_F_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_F_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_F_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_F_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_F_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_F_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_F_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_F_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_F_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_F_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_F_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_F_CG1 0x0000027C /* RWE4R */ #define NV_PTPC_PRI_TEX_F_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_F_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_F_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG1_SLCG 5:1 /* RWEVF */ #define NV_PTPC_PRI_TEX_F_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_F_CG1_SLCG_DISABLED 0x0000001F /* RWE-V */ #define NV_PTPC_PRI_TEX_F_CG1_SLCG__PROD 0x0000001E /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG 0x00000280 /* RWE4R */ #define NV_PTPC_PRI_TEX_MIPB_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_MIPB_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_MIPB_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_MIPB_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_MIPB_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_MIPB_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_MIPB_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_MIPB_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_MIPB_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_MIPB_CG1 0x00000284 /* RWE4R */ #define NV_PTPC_PRI_TEX_MIPB_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_MIPB_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_MIPB_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG1_SLCG 3:1 /* RWEVF */ #define NV_PTPC_PRI_TEX_MIPB_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_MIPB_CG1_SLCG_DISABLED 0x00000007 /* RWE-V */ #define NV_PTPC_PRI_TEX_MIPB_CG1_SLCG__PROD 0x00000006 /* RW--V */ #define NV_PTPC_PRI_TEX_AM_CG 0x00000270 /* RWE4R */ #define NV_PTPC_PRI_TEX_AM_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_AM_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_AM_CG_IDLE_CG_DLY_CNT__PROD 0x00000005 /* RW--V */ #define NV_PTPC_PRI_TEX_AM_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_AM_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_AM_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_AM_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_AM_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_AM_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_AM_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_AM_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_STALL_CG_DLY_CNT__PROD 0x00000005 /* */ #define NV_PTPC_PRI_TEX_AM_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_AM_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_AM_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_AM_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_AM_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_AM_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_AM_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_AM_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_AM_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_AM_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_AM_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_AM_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_AM_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_AM_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_AM_CG1 0x00000274 /* RWE4R */ #define NV_PTPC_PRI_TEX_AM_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_AM_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_AM_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_AM_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_DF_CG 0x00000288 /* RWE4R */ #define NV_PTPC_PRI_TEX_DF_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_DF_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_DF_CG_IDLE_CG_DLY_CNT__PROD 0x00000005 /* RW--V */ #define NV_PTPC_PRI_TEX_DF_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PTPC_PRI_TEX_DF_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_DF_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_DF_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_DF_CG_STATE_CG_EN 7:7 /* */ #define NV_PTPC_PRI_TEX_DF_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_DF_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PTPC_PRI_TEX_DF_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_STALL_CG_DLY_CNT__PROD 0x00000005 /* */ #define NV_PTPC_PRI_TEX_DF_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PTPC_PRI_TEX_DF_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_DF_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_DF_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_DF_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PTPC_PRI_TEX_DF_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_DF_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PTPC_PRI_TEX_DF_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_DF_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PTPC_PRI_TEX_DF_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_EN 28:28 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PTPC_PRI_TEX_DF_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_DF_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_HALT_CG_EN 31:31 /* */ #define NV_PTPC_PRI_TEX_DF_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PTPC_PRI_TEX_DF_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PTPC_PRI_TEX_DF_CG1 0x0000028C /* RWE4R */ #define NV_PTPC_PRI_TEX_DF_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PTPC_PRI_TEX_DF_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_TEX_DF_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_TEX_DF_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PTPC_PRI_CAU 0x000001ff:0x00000180 /* RW--L */ #define NV_PTPC_PRI_CAU_CONTROL(i) (0x00000180+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_CONTROL__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_CONTROL_MODE 0:0 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_MODE_DISABLED 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_MODE_STREAMING 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_AGGREGATE_SCTL 2:2 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_AGGREGATE_SCTL_DISABLED 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_AGGREGATE_SCTL_ENABLED 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE 4:4 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE_DISABLED 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_TRIGGER_ENABLE_T_PULSE_ENABLED 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES 8:5 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_DISABLED 0x0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_1K 0x1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_2K 0x2 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_4K 0x3 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_8K 0x4 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_16K 0x5 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_32K 0x6 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_64K 0x7 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_128K 0x8 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_256K 0x9 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_512K 0xA /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_1024K 0xB /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_2048K 0xC /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_4096K 0xD /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_8192K 0xE /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TIMEBASE_CYCLES_16384K 0xF /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER 9:9 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER_DISABLED 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_TRIGGER_ENABLE_PMA_TRIGGER_ENABLED 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES 14:12 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_DISABLED 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_1K 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_4K 2 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_16K 3 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_64K 4 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_256K 5 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_1024K 6 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_TIMEOUT_CYCLES_4096K 7 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_KEEP_RECORD 15:15 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_KEEP_RECORD_DISABLED 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_QUIESCENT_KEEP_RECORD_ENABLED 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_COREMIO 16:16 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_COREMIO_DISABLE 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_COREMIO_ENABLE 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL0 17:17 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL0_DISABLE 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL0_ENABLE 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL1 18:18 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL1_DISABLE 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL1_ENABLE 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL2 19:19 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL2_DISABLE 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL2_ENABLE 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL3 20:20 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL3_DISABLE 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROL_INPUT_SCTL3_ENABLE 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROL_TRIG_SKIP_COUNT 31:22 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROL_TRIG_SKIP_COUNT_ZERO 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CTXSW(i) (0x00000184+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_CTXSW__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_CTXSW_MODE 0:0 /* RWEUF */ #define NV_PTPC_PRI_CAU_CTXSW_MODE_DISABLED 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CTXSW_MODE_ENABLED 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CTXSW_TIMER 1:1 /* RWEUF */ #define NV_PTPC_PRI_CAU_CTXSW_TIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_CTXSW_TIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PTPC_PRI_CAU_PERFMONID(i) (0x00000188+(i)*64) /* RW-4A */ #define NV_PTPC_PRI_CAU_PERFMONID__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_PERFMONID_PERFMONID 10:0 /* RWXUF */ #define NV_PTPC_PRI_CAU_PERFMONID_PERFMONID_INIT 0 /* RW--V */ #define NV_PTPC_PRI_CAU_CYCLECNT_LSB(i) (0x0000018C+(i)*64) /* RW-4A */ #define NV_PTPC_PRI_CAU_CYCLECNT_LSB__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_CYCLECNT_LSB_COUNT 31:0 /* RWXUF */ #define NV_PTPC_PRI_CAU_CYCLECNT_MSB(i) (0x00000190+(i)*64) /* RW-4A */ #define NV_PTPC_PRI_CAU_CYCLECNT_MSB__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_CYCLECNT_MSB_COUNT 7:0 /* RWXUF */ #define NV_PTPC_PRI_CAU_TOTAL_TRIG_RCV(i) (0x00000194+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_TOTAL_TRIG_RCV__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PTPC_PRI_CAU_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_TRIG_STATE(i) (0x000001B8+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_TRIG_STATE__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_TRIG_STATE_INCR_COUNT 9:0 /* RWEUF */ #define NV_PTPC_PRI_CAU_TRIG_STATE_INCR_COUNT_ZERO 0x000 /* RWE-V */ #define NV_PTPC_PRI_CAU_STATE(i) (0x00000198+(i)*64) /* R--4A */ #define NV_PTPC_PRI_CAU_STATE__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_STATE_SAMPLECNT 8:0 /* R-XUF */ #define NV_PTPC_PRI_CAU_STATE_DELAY 9:9 /* R-XUF */ #define NV_PTPC_PRI_CAU_STATE_PER_SMPC_OVERFLOW 14:10 /* R-XUF */ #define NV_PTPC_PRI_CAU_STATE_PER_SMPC_QUIESCENT_TIMEOUT 19:15 /* R-XUF */ #define NV_PTPC_PRI_CAU_STATE_PER_SMPC_SPURIOUS_SM_DATA 24:20 /* R-XUF */ #define NV_PTPC_PRI_CAU_ENGINESTATUS(i) (0x0000019C+(i)*64) /* R--4A */ #define NV_PTPC_PRI_CAU_ENGINESTATUS__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PTPC_PRI_CAU_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PTPC_PRI_CAU_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PTPC_PRI_CAU_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PTPC_PRI_CAU_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PTPC_PRI_CAU_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PTPC_PRI_CAU_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PTPC_PRI_CAU_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PTPC_PRI_CAU_CG2_SLCG(i) (0x000001A0+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_CG2_SLCG__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_CG2_SLCG_ENABLE 0:0 /* RWEVF */ #define NV_PTPC_PRI_CAU_CG2_SLCG_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CG2_SLCG_ENABLE_ENABLED 0x1 /* RW--V */ #define NV_PTPC_PRI_CAU_CG2_SLCG_ENABLE_DISABLED 0x0 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROLB(i) (0x000001A4+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_CONTROLB__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_CONTROLB_FLUSH_RECORD 0:0 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROLB_FLUSH_RECORD_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROLB_FLUSH_RECORD_DOIT 1 /* RW--V */ #define NV_PTPC_PRI_CAU_CONTROLB_SOFT_RESET 1:1 /* RWEUF */ #define NV_PTPC_PRI_CAU_CONTROLB_SOFT_RESET_INIT 0 /* RWE-V */ #define NV_PTPC_PRI_CAU_CONTROLB_SOFT_RESET_DOIT 1 /* RW--V */ #define NV_PTPC_PRI_CAU_DATA_GEN(i) (0x000001A8+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_DATA_GEN__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_DATA_GEN_ENABLE 0:0 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_CAU_DATA_GEN_SINGLE_DP 1:1 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_SINGLE_DP_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_CAU_DATA_GEN_TRIGGER_MODE 3:2 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_TRIGGER_MODE_IGNORE_PMA_TRIGGER 0x0 /* RW--V */ #define NV_PTPC_PRI_CAU_DATA_GEN_TRIGGER_MODE_ONLY_PMA_TRIGGER 0x2 /* RW--V */ #define NV_PTPC_PRI_CAU_DATA_GEN_TRIGGER_MODE_ONLY_TPULSE_TRIGGER 0x3 /* RW--V */ #define NV_PTPC_PRI_CAU_DATA_GEN_TRIGGER_MODE_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_CAU_DATA_GEN_MODE 6:4 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_MODE_ZEROS 0x0 /* RW--V */ #define NV_PTPC_PRI_CAU_DATA_GEN_MODE_COUNT_UP 0x1 /* RW--V */ #define NV_PTPC_PRI_CAU_DATA_GEN_MODE_COUNT_DOWN 0x2 /* RW--V */ #define NV_PTPC_PRI_CAU_DATA_GEN_MODE_RANDOM 0x3 /* RW--V */ #define NV_PTPC_PRI_CAU_DATA_GEN_MODE_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_CAU_DATA_GEN_OVERFLOW_ENABLE 7:7 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_OVERFLOW_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_CAU_DATA_GEN_MODE_SEED 15:8 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_MODE_SEED_INIT 0x00 /* RWE-V */ #define NV_PTPC_PRI_CAU_DATA_GEN_NUM_TRIGGERS 22:16 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_NUM_TRIGGERS_INIT 0x00 /* RWE-V */ #define NV_PTPC_PRI_CAU_DATA_GEN_DWORDS 23:23 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_DWORDS_INIT 0x0 /* RWE-V */ #define NV_PTPC_PRI_CAU_DATA_GEN_TRIGGER_DELAY 31:24 /* RWEVF */ #define NV_PTPC_PRI_CAU_DATA_GEN_TRIGGER_DELAY_INIT 0x00 /* RWE-V */ #define NV_PTPC_PRI_CAU_PM(i) (0x000001AC+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_PM__SIZE_1 1 /* */ #define NV_PTPC_PRI_CAU_PM_SELECT 4:0 /* RWEVF */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_STATUS 0x00000000 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP0 0x00000001 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP1 0x00000002 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP2 0x00000003 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP3 0x00000004 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP4 0x00000005 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP5 0x00000006 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP6 0x00000007 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP7 0x00000008 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP8 0x00000009 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_SM_GRP9 0x0000000a /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE0_PMM_GRP0 0x0000000b /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_STATUS 0x00000010 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP0 0x00000011 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP1 0x00000012 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP2 0x00000013 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP3 0x00000014 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP4 0x00000015 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP5 0x00000016 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP6 0x00000017 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP7 0x00000018 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP8 0x00000019 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_SM_GRP9 0x0000001a /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_SLICE1_PMM_GRP0 0x0000001b /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_PM_SELECT_CTL_EN 8:8 /* RWEVF */ #define NV_PTPC_PRI_CAU_PM_SELECT_CTL_EN_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_PM_SELECT_CTL_EN_TRUE 0x00000001 /* RW--V */ #define NV_PTPC_PRI_CAU_PM_SELECT_CTL_EN_FALSE 0x00000000 /* RW--V */ #define NV_PTPC_PRI_CAU_DEBUG(i) (0x000001B0+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_DEBUG__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_DEBUG_TOTAL_RECORDS_SENT 31:0 /* RWEUF */ #define NV_PTPC_PRI_CAU_DEBUG_TOTAL_RECORDS_SENT_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_DEBUG2(i) (0x000001B4+(i)*64) /* RWE4A */ #define NV_PTPC_PRI_CAU_DEBUG2__SIZE_1 2 /* */ #define NV_PTPC_PRI_CAU_DEBUG2_TOTAL_DROPPED_TRIGGERS 3:0 /* RWEUF */ #define NV_PTPC_PRI_CAU_DEBUG2_TOTAL_DROPPED_TRIGGERS_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_DEBUG2_TOTAL_T_PULSE_TRIGGERS 7:4 /* RWEUF */ #define NV_PTPC_PRI_CAU_DEBUG2_TOTAL_T_PULSE_TRIGGERS_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_DEBUG2_TOTAL_OVERFLOW 11:8 /* RWEUF */ #define NV_PTPC_PRI_CAU_DEBUG2_TOTAL_OVERFLOW_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_DEBUG2_TOTAL_CTXSW_FREEZE 15:12 /* RWEUF */ #define NV_PTPC_PRI_CAU_DEBUG2_TOTAL_CTXSW_FREEZE_INIT 0x00000000 /* RWE-V */ #define NV_PTPC_PRI_CAU_DEBUG2_CYA_REGS 31:16 /* RWEUF */ #define NV_PTPC_PRI_CAU_DEBUG2_CYA_REGS_INIT 0x00000000 /* RWE-V */ #endif // __ga102_dev_tpc_h__