/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2015-2021 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

#ifndef __ga102_dev_perf_addendum_h__
#define __ga102_dev_perf_addendum_h__

// DO NOT EDIT THIS FILE - it is produced by the regaccess whitelist generation process

//
// see bug 1585129, open to address where HW does not fully specify the NV_PERF range across
// all chiplets, we are doing a WAR in the manuals parsing to generate this new addendum
// header that transforms the regs to proper arrays so the generic additions of regs
// here will work in the whitelist
//



#define NV_PERF_PMMSYS_FT0_INPUTSEL_RM(i,j) (((0x00260000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_FT0_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_FT0_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_FT1_INPUTSEL_RM(i,j) (((0x00260004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_FT1_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_FT1_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_FT2_INPUTSEL_RM(i,j) (((0x00260008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_FT2_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_FT2_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_FT3_INPUTSEL_RM(i,j) (((0x0026000C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_FT3_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_FT3_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_FT4_INPUTSEL_RM(i,j) (((0x00260010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_FT4_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_FT4_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_FT5_INPUTSEL_RM(i,j) (((0x00260014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_FT5_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_FT5_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CNTR0_INC_RM(i,j) (((0x00260020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CNTR0_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CNTR0_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CNTR1_INC_RM(i,j) (((0x00260024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CNTR1_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CNTR1_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CNTR2_INC_RM(i,j) (((0x00260028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CNTR2_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CNTR2_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CNTR3_INC_RM(i,j) (((0x0026002C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CNTR3_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CNTR3_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CNTR4_INC_RM(i,j) (((0x00260030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CNTR4_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CNTR4_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CNTR5_INC_RM(i,j) (((0x00260034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CNTR5_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CNTR5_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_TRIG0_SEL_RM(i,j) (((0x00260040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_TRIG0_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_TRIG0_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_TRIG0_OP_RM(i,j) (((0x00260044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_TRIG0_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_TRIG0_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_TRIG1_SEL_RM(i,j) (((0x00260048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_TRIG1_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_TRIG1_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_TRIG1_OP_RM(i,j) (((0x0026004C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_TRIG1_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_TRIG1_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_EVENT_SEL_RM(i,j) (((0x00260050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_EVENT_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_EVENT_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_EVENT_OP_RM(i,j) (((0x00260054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_EVENT_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_EVENT_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SAMPLE_SEL_RM(i,j) (((0x00260058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SAMPLE_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SAMPLE_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SAMPLE_OP_RM(i,j) (((0x0026005C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SAMPLE_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SAMPLE_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SETFLAG_OP_RM(i,j) (((0x00260060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SETFLAG_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SETFLAG_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CLRFLAG_OP_RM(i,j) (((0x00260064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLRFLAG_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CLRFLAG_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SELECTMUX_RM(i,j) (((0x00260068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SELECTMUX_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SELECTMUX_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_ENGINE_SEL_RM(i,j) (((0x0026006C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_ENGINE_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_ENGINE_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_ELAPSED_RM(i,j) (((0x00260070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_ELAPSED_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_ELAPSED_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_MODEC5CNT_RM(i,j) (((0x00260074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_MODEC5CNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_MODEC5CNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CYCLECNT_RM(i,j) (((0x00260078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CYCLECNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CYCLECNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_MODEC6CNT_RM(i,j) (((0x0026007C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_MODEC6CNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_MODEC6CNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_EVENTCNT_RM(i,j) (((0x00260080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_EVENTCNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_EVENTCNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_DFD_CNT_UPPER_RM(i,j) (((0x00260084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_DFD_CNT_UPPER_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_DFD_CNT_UPPER_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_THRESHCNT_RM(i,j) (((0x00260088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_THRESHCNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_THRESHCNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_TRIGGERCNT_RM(i,j) (((0x0026008C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_TRIGGERCNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_TRIGGERCNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SAMPLECNT_RM(i,j) (((0x00260090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SAMPLECNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SAMPLECNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_THRESHOLD_RM(i,j) (((0x00260098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_THRESHOLD_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_THRESHOLD_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CONTROL_RM(i,j) (((0x0026009C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CONTROL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CONTROL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RELEASE_RM(i,j) (((0x002600A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RELEASE_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RELEASE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWCNT0_RM(i,j) (((0x002600A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWCNT0_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWCNT0_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWCNT1_RM(i,j) (((0x002600A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWCNT1_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWCNT1_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWCNT2_RM(i,j) (((0x002600AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWCNT2_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWCNT2_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWCNT3_RM(i,j) (((0x002600B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWCNT3_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWCNT3_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWCNT4_RM(i,j) (((0x002600B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWCNT4_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWCNT4_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWCNT5_RM(i,j) (((0x002600B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWCNT5_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWCNT5_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWCNT6_RM(i,j) (((0x002600BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWCNT6_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWCNT6_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWCNT7_RM(i,j) (((0x002600C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWCNT7_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWCNT7_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_RAWSMPLCNT_RM(i,j) (((0x002600C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_RAWSMPLCNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_RAWSMPLCNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_ENGINESTATUS_RM(i,j) (((0x002600C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_ENGINESTATUS_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_ENGINESTATUS_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_WBSKEW0_RM(i,j) (((0x002600CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_WBSKEW0_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_WBSKEW0_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_WBSKEW1_RM(i,j) (((0x002600D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_WBSKEW1_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_WBSKEW1_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_WBSKEW2_RM(i,j) (((0x002600D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_WBSKEW2_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_WBSKEW2_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_WBSKEW_CHAIN0_RM(i,j) (((0x002600D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_WBSKEW_CHAIN0_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_WBSKEW_CHAIN0_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_WBSKEW_CHAIN1_RM(i,j) (((0x002600DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_WBSKEW_CHAIN1_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_WBSKEW_CHAIN1_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_STARTEXPERIMENT_RM(i,j) (((0x002600E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_STARTEXPERIMENT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_STARTEXPERIMENT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CTXSW0_RM(i,j) (((0x002600E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CTXSW0_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CTXSW0_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CTXSW1_RM(i,j) (((0x002600E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CTXSW1_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CTXSW1_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_WATCHBUSDEBUG_RM(i,j) (((0x002600EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_WATCHBUSDEBUG_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_WATCHBUSDEBUG_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_DEBUG_RM(i,j) (((0x002600F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_DEBUG_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_DEBUG_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_DAISY_DISABLE_RM(i,j) (((0x002600FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_DAISY_DISABLE_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_DAISY_DISABLE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CONTROLB_RM(i,j) (((0x00260108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CONTROLB_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CONTROLB_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CONTROLC_RM(i,j) (((0x00260110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CONTROLC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CONTROLC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CONTROLD_RM(i,j) (((0x00260120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CONTROLD_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CONTROLD_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_PERFMONID_RM(i,j) (((0x00260128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_PERFMONID_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_PERFMONID_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CTXSW2_RM(i,j) (((0x00260114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CTXSW2_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CTXSW2_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CTXSW3_RM(i,j) (((0x00260118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CTXSW3_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CTXSW3_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CTXSW4_RM(i,j) (((0x0026011C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CTXSW4_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CTXSW4_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_TOTAL_TRIG_RCV_RM(i,j) (((0x00260124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_TOTAL_TRIG_RCV_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_TOTAL_TRIG_RCV_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_FLAG_BIT_TIMER_RM(i,j) (((0x00260130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_FLAG_BIT_TIMER_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_FLAG_BIT_TIMER_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_RM(i) ((0x00248000)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_RECORD_GRANT_RM(i) ((0x00248004)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_RECORD_GRANT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00248008)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024800C)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_GLOBAL_CTXSW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_ENGINESTATUS_RM(i) ((0x00248010)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_ENGINESTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_PERFMONSTATUS_RM(i) ((0x00248014)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_PERFMONSTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_CG2_RM(i) ((0x00248018)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_CG2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_RECORD_DEBUG_RM(i) ((0x0024801C)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_RECORD_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_HS_RECORD_DEBUG_RM(i) ((0x00248154)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_HS_RECORD_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYSROUTER_HS_CONFIG_RM(i) ((0x00248150)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMSYSROUTER_HS_CONFIG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL_RM(i,j) (((0x00260100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_RM(i) ((0x00262900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_RM(i) ((0x00262700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_RM(i) ((0x00262500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_RM(i) ((0x00262300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_RM(i) ((0x00262100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15_RM(i) ((0x00261F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL14_RM(i) ((0x00261D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL14_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL13_RM(i) ((0x00261B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL13_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL12_RM(i) ((0x00261900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL12_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL11_RM(i) ((0x00261700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL11_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL10_RM(i) ((0x00261500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL10_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL9_RM(i) ((0x00261300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL9_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_RM(i) ((0x00261100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL7_RM(i) ((0x00260F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL7_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL6_RM(i) ((0x00260D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL6_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL5_RM(i) ((0x00260B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL5_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL4_RM(i) ((0x00260900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL3_RM(i) ((0x00260700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL2_RM(i) ((0x00260500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_RM(i) ((0x00260300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL0_RM(i) ((0x00260100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL_RM(i,j) (((0x00260000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL_RM(i,j) (((0x00260004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL_RM(i,j) (((0x00260008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL_RM(i,j) (((0x0026000C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL_RM(i,j) (((0x00260010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL_RM(i,j) (((0x00260014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR0_INC_RM(i,j) (((0x00260020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CNTR0_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR0_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR1_INC_RM(i,j) (((0x00260024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CNTR1_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR1_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR2_INC_RM(i,j) (((0x00260028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CNTR2_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR2_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR3_INC_RM(i,j) (((0x0026002C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CNTR3_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR3_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR4_INC_RM(i,j) (((0x00260030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CNTR4_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR4_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR5_INC_RM(i,j) (((0x00260034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CNTR5_INC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CNTR5_INC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIG0_SEL_RM(i,j) (((0x00260040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_TRIG0_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIG0_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIG0_OP_RM(i,j) (((0x00260044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_TRIG0_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIG0_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIG1_SEL_RM(i,j) (((0x00260048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_TRIG1_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIG1_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIG1_OP_RM(i,j) (((0x0026004C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_TRIG1_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIG1_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_EVENT_SEL_RM(i,j) (((0x00260050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_EVENT_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_EVENT_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_EVENT_OP_RM(i,j) (((0x00260054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_EVENT_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_EVENT_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL_RM(i,j) (((0x00260058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_RM(i,j) (((0x0026005C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_RM(i,j) (((0x00260060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_RM(i,j) (((0x00260064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_SELECTMUX_RM(i,j) (((0x00260068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_SELECTMUX_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_SELECTMUX_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_ENGINE_SEL_RM(i,j) (((0x0026006C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_ENGINE_SEL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_ENGINE_SEL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_ELAPSED_RM(i,j) (((0x00260070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_ELAPSED_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_ELAPSED_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_MODEC5CNT_RM(i,j) (((0x00260074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_MODEC5CNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_MODEC5CNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CYCLECNT_RM(i,j) (((0x00260078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CYCLECNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CYCLECNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_MODEC6CNT_RM(i,j) (((0x0026007C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_MODEC6CNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_MODEC6CNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_EVENTCNT_RM(i,j) (((0x00260080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_EVENTCNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_EVENTCNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER_RM(i,j) (((0x00260084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_THRESHCNT_RM(i,j) (((0x00260088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_THRESHCNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_THRESHCNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIGGERCNT_RM(i,j) (((0x0026008C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_TRIGGERCNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_TRIGGERCNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_SAMPLECNT_RM(i,j) (((0x00260090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_SAMPLECNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_SAMPLECNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_THRESHOLD_RM(i,j) (((0x00260098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_THRESHOLD_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_THRESHOLD_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CONTROL_RM(i,j) (((0x0026009C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CONTROL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CONTROL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RELEASE_RM(i,j) (((0x002600A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RELEASE_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RELEASE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT0_RM(i,j) (((0x002600A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWCNT0_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT0_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT1_RM(i,j) (((0x002600A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWCNT1_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT1_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT2_RM(i,j) (((0x002600AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWCNT2_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT2_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT3_RM(i,j) (((0x002600B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWCNT3_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT3_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT4_RM(i,j) (((0x002600B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWCNT4_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT4_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT5_RM(i,j) (((0x002600B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWCNT5_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT5_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT6_RM(i,j) (((0x002600BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWCNT6_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT6_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT7_RM(i,j) (((0x002600C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWCNT7_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWCNT7_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWSMPLCNT_RM(i,j) (((0x002600C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_RAWSMPLCNT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_RAWSMPLCNT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_RM(i,j) (((0x002600C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW0_RM(i,j) (((0x002600CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_WBSKEW0_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW0_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW1_RM(i,j) (((0x002600D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_WBSKEW1_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW1_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW2_RM(i,j) (((0x002600D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_WBSKEW2_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW2_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_RM(i,j) (((0x002600D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_RM(i,j) (((0x002600DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_STARTEXPERIMENT_RM(i,j) (((0x002600E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_STARTEXPERIMENT_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_STARTEXPERIMENT_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW0_RM(i,j) (((0x002600E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CTXSW0_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW0_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW1_RM(i,j) (((0x002600E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CTXSW1_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW1_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_RM(i,j) (((0x002600EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_DEBUG_RM(i,j) (((0x002600F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_DEBUG_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_DEBUG_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_DAISY_DISABLE_RM(i,j) (((0x002600FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_DAISY_DISABLE_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_DAISY_DISABLE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CONTROLB_RM(i,j) (((0x00260108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CONTROLB_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CONTROLB_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CONTROLC_RM(i,j) (((0x00260110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CONTROLC_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CONTROLC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CONTROLD_RM(i,j) (((0x00260120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CONTROLD_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CONTROLD_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_PERFMONID_RM(i,j) (((0x00260128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_PERFMONID_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_PERFMONID_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW2_RM(i,j) (((0x00260114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CTXSW2_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW2_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW3_RM(i,j) (((0x00260118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CTXSW3_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW3_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW4_RM(i,j) (((0x0026011C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CTXSW4_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CTXSW4_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_TOTAL_TRIG_RCV_RM(i,j) (((0x00260124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_TOTAL_TRIG_RCV_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_TOTAL_TRIG_RCV_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_RM(i,j) (((0x00260130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_RM(i) ((0x00248000)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_GRANT_RM(i) ((0x00248004)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_GRANT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00248008)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024800C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_RM(i) ((0x00248010)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_RM(i) ((0x00248014)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_CG2_RM(i) ((0x00248018)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_CG2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG_RM(i) ((0x0024801C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00248154)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_RM(i) ((0x00248150)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL_RM(i,j) (((0x00260100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL_RM__SIZE_1 21 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_RM(i) ((0x00262900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_RM(i) ((0x00262700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_RM(i) ((0x00262500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_RM(i) ((0x00262300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_RM(i) ((0x00262100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15_RM(i) ((0x00261F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL14_RM(i) ((0x00261D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL14_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL13_RM(i) ((0x00261B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL13_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL12_RM(i) ((0x00261900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL12_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL11_RM(i) ((0x00261700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL11_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL10_RM(i) ((0x00261500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL10_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL9_RM(i) ((0x00261300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL9_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_RM(i) ((0x00261100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL7_RM(i) ((0x00260F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL7_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL6_RM(i) ((0x00260D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL6_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL5_RM(i) ((0x00260B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL5_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL4_RM(i) ((0x00260900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL3_RM(i) ((0x00260700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL2_RM(i) ((0x00260500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_RM(i) ((0x00260300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL0_RM(i) ((0x00260100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT0_INPUTSEL_RM(i) ((0x00251000)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT0_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT1_INPUTSEL_RM(i) ((0x00251004)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT1_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT2_INPUTSEL_RM(i) ((0x00251008)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT2_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT3_INPUTSEL_RM(i) ((0x0025100C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT3_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT4_INPUTSEL_RM(i) ((0x00251010)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT4_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT5_INPUTSEL_RM(i) ((0x00251014)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT5_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_RM(i) ((0x00251020)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_RM(i) ((0x00251024)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_RM(i) ((0x00251028)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_RM(i) ((0x0025102C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_RM(i) ((0x00251030)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_RM(i) ((0x00251034)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_SEL_RM(i) ((0x00251040)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_RM(i) ((0x00251044)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_SEL_RM(i) ((0x00251048)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_RM(i) ((0x0025104C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_SEL_RM(i) ((0x00251050)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_RM(i) ((0x00251054)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_SEL_RM(i) ((0x00251058)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_RM(i) ((0x0025105C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_RM(i) ((0x00251060)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_RM(i) ((0x00251064)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX_RM(i) ((0x00251068)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINE_SEL_RM(i) ((0x0025106C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINE_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ELAPSED_RM(i) ((0x00251070)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ELAPSED_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC5CNT_RM(i) ((0x00251074)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC5CNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CYCLECNT_RM(i) ((0x00251078)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CYCLECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC6CNT_RM(i) ((0x0025107C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC6CNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENTCNT_RM(i) ((0x00251080)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENTCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DFD_CNT_UPPER_RM(i) ((0x00251084)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DFD_CNT_UPPER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHCNT_RM(i) ((0x00251088)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIGGERCNT_RM(i) ((0x0025108C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLECNT_RM(i) ((0x00251090)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHOLD_RM(i) ((0x00251098)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHOLD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_RM(i) ((0x0025109C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RELEASE_RM(i) ((0x002510A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RELEASE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT0_RM(i) ((0x002510A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT1_RM(i) ((0x002510A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT2_RM(i) ((0x002510AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT3_RM(i) ((0x002510B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT4_RM(i) ((0x002510B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT5_RM(i) ((0x002510B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT5_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT6_RM(i) ((0x002510BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT6_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT7_RM(i) ((0x002510C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT7_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWSMPLCNT_RM(i) ((0x002510C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWSMPLCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_RM(i) ((0x002510C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_RM(i) ((0x002510CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_RM(i) ((0x002510D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW2_RM(i) ((0x002510D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_RM(i) ((0x002510D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_RM(i) ((0x002510DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_STARTEXPERIMENT_RM(i) ((0x002510E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_STARTEXPERIMENT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_RM(i) ((0x002510E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_RM(i) ((0x002510E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_RM(i) ((0x002510EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DEBUG_RM(i) ((0x002510F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DAISY_DISABLE_RM(i) ((0x002510FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DAISY_DISABLE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_RM(i) ((0x00251108)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_RM(i) ((0x00251110)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLD_RM(i) ((0x00251120)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_PERFMONID_RM(i) ((0x00251128)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_PERFMONID_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW2_RM(i) ((0x00251114)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW3_RM(i) ((0x00251118)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW4_RM(i) ((0x0025111C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TOTAL_TRIG_RCV_RM(i) ((0x00251124)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TOTAL_TRIG_RCV_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER_RM(i) ((0x00251130)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLAMP_CYA_CONTROL_RM(i) ((0x00251100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLAMP_CYA_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT0_INPUTSEL_RM(i) ((0x00251200)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT0_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT1_INPUTSEL_RM(i) ((0x00251204)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT1_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT2_INPUTSEL_RM(i) ((0x00251208)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT2_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT3_INPUTSEL_RM(i) ((0x0025120C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT3_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT4_INPUTSEL_RM(i) ((0x00251210)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT4_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT5_INPUTSEL_RM(i) ((0x00251214)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FT5_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_RM(i) ((0x00251220)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_RM(i) ((0x00251224)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_RM(i) ((0x00251228)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_RM(i) ((0x0025122C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_RM(i) ((0x00251230)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_RM(i) ((0x00251234)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_SEL_RM(i) ((0x00251240)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_RM(i) ((0x00251244)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_SEL_RM(i) ((0x00251248)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_RM(i) ((0x0025124C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_SEL_RM(i) ((0x00251250)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_RM(i) ((0x00251254)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_SEL_RM(i) ((0x00251258)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_RM(i) ((0x0025125C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_RM(i) ((0x00251260)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_RM(i) ((0x00251264)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX_RM(i) ((0x00251268)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINE_SEL_RM(i) ((0x0025126C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINE_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_ELAPSED_RM(i) ((0x00251270)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_ELAPSED_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC5CNT_RM(i) ((0x00251274)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC5CNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CYCLECNT_RM(i) ((0x00251278)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CYCLECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC6CNT_RM(i) ((0x0025127C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC6CNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENTCNT_RM(i) ((0x00251280)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENTCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_DFD_CNT_UPPER_RM(i) ((0x00251284)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_DFD_CNT_UPPER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHCNT_RM(i) ((0x00251288)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIGGERCNT_RM(i) ((0x0025128C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLECNT_RM(i) ((0x00251290)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHOLD_RM(i) ((0x00251298)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHOLD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_RM(i) ((0x0025129C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RELEASE_RM(i) ((0x002512A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RELEASE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT0_RM(i) ((0x002512A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT1_RM(i) ((0x002512A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT2_RM(i) ((0x002512AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT3_RM(i) ((0x002512B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT4_RM(i) ((0x002512B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT5_RM(i) ((0x002512B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT5_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT6_RM(i) ((0x002512BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT6_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT7_RM(i) ((0x002512C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT7_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWSMPLCNT_RM(i) ((0x002512C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWSMPLCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_RM(i) ((0x002512C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_RM(i) ((0x002512CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_RM(i) ((0x002512D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW2_RM(i) ((0x002512D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_RM(i) ((0x002512D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_RM(i) ((0x002512DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_STARTEXPERIMENT_RM(i) ((0x002512E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_STARTEXPERIMENT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_RM(i) ((0x002512E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_RM(i) ((0x002512E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_RM(i) ((0x002512EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_DEBUG_RM(i) ((0x002512F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_DAISY_DISABLE_RM(i) ((0x002512FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_DAISY_DISABLE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_RM(i) ((0x00251308)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_RM(i) ((0x00251310)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLD_RM(i) ((0x00251320)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_PERFMONID_RM(i) ((0x00251328)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_PERFMONID_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW2_RM(i) ((0x00251314)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW3_RM(i) ((0x00251318)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW4_RM(i) ((0x0025131C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TOTAL_TRIG_RCV_RM(i) ((0x00251324)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_TOTAL_TRIG_RCV_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER_RM(i) ((0x00251330)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CLAMP_CYA_CONTROL_RM(i) ((0x00251300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLRX_CLAMP_CYA_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT0_INPUTSEL_RM(i) ((0x00251400)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT0_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT1_INPUTSEL_RM(i) ((0x00251404)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT1_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT2_INPUTSEL_RM(i) ((0x00251408)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT2_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT3_INPUTSEL_RM(i) ((0x0025140C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT3_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT4_INPUTSEL_RM(i) ((0x00251410)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT4_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT5_INPUTSEL_RM(i) ((0x00251414)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT5_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_RM(i) ((0x00251420)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_RM(i) ((0x00251424)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_RM(i) ((0x00251428)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_RM(i) ((0x0025142C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_RM(i) ((0x00251430)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_RM(i) ((0x00251434)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_SEL_RM(i) ((0x00251440)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_RM(i) ((0x00251444)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_SEL_RM(i) ((0x00251448)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_RM(i) ((0x0025144C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_SEL_RM(i) ((0x00251450)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_RM(i) ((0x00251454)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_SEL_RM(i) ((0x00251458)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_RM(i) ((0x0025145C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_RM(i) ((0x00251460)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_RM(i) ((0x00251464)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX_RM(i) ((0x00251468)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINE_SEL_RM(i) ((0x0025146C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINE_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_ELAPSED_RM(i) ((0x00251470)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_ELAPSED_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC5CNT_RM(i) ((0x00251474)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC5CNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CYCLECNT_RM(i) ((0x00251478)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CYCLECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC6CNT_RM(i) ((0x0025147C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC6CNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENTCNT_RM(i) ((0x00251480)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENTCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_DFD_CNT_UPPER_RM(i) ((0x00251484)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_DFD_CNT_UPPER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHCNT_RM(i) ((0x00251488)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIGGERCNT_RM(i) ((0x0025148C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLECNT_RM(i) ((0x00251490)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHOLD_RM(i) ((0x00251498)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHOLD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_RM(i) ((0x0025149C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RELEASE_RM(i) ((0x002514A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RELEASE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT0_RM(i) ((0x002514A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT1_RM(i) ((0x002514A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT2_RM(i) ((0x002514AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT3_RM(i) ((0x002514B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT4_RM(i) ((0x002514B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT5_RM(i) ((0x002514B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT5_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT6_RM(i) ((0x002514BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT6_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT7_RM(i) ((0x002514C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT7_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWSMPLCNT_RM(i) ((0x002514C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWSMPLCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_RM(i) ((0x002514C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_RM(i) ((0x002514CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_RM(i) ((0x002514D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW2_RM(i) ((0x002514D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_RM(i) ((0x002514D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_RM(i) ((0x002514DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_STARTEXPERIMENT_RM(i) ((0x002514E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_STARTEXPERIMENT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_RM(i) ((0x002514E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_RM(i) ((0x002514E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_RM(i) ((0x002514EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_DEBUG_RM(i) ((0x002514F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_DAISY_DISABLE_RM(i) ((0x002514FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_DAISY_DISABLE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_RM(i) ((0x00251508)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_RM(i) ((0x00251510)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLD_RM(i) ((0x00251520)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_PERFMONID_RM(i) ((0x00251528)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_PERFMONID_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW2_RM(i) ((0x00251514)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW3_RM(i) ((0x00251518)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW4_RM(i) ((0x0025151C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TOTAL_TRIG_RCV_RM(i) ((0x00251524)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_TOTAL_TRIG_RCV_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER_RM(i) ((0x00251530)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLAMP_CYA_CONTROL_RM(i) ((0x00251500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLAMP_CYA_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT0_INPUTSEL_RM(i) ((0x00251600)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT0_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT1_INPUTSEL_RM(i) ((0x00251604)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT1_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT2_INPUTSEL_RM(i) ((0x00251608)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT2_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT3_INPUTSEL_RM(i) ((0x0025160C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT3_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT4_INPUTSEL_RM(i) ((0x00251610)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT4_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT5_INPUTSEL_RM(i) ((0x00251614)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FT5_INPUTSEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_RM(i) ((0x00251620)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_RM(i) ((0x00251624)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_RM(i) ((0x00251628)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_RM(i) ((0x0025162C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_RM(i) ((0x00251630)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_RM(i) ((0x00251634)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_SEL_RM(i) ((0x00251640)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_RM(i) ((0x00251644)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_SEL_RM(i) ((0x00251648)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_RM(i) ((0x0025164C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_SEL_RM(i) ((0x00251650)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_RM(i) ((0x00251654)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_SEL_RM(i) ((0x00251658)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_RM(i) ((0x0025165C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_RM(i) ((0x00251660)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_RM(i) ((0x00251664)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX_RM(i) ((0x00251668)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINE_SEL_RM(i) ((0x0025166C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINE_SEL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_ELAPSED_RM(i) ((0x00251670)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_ELAPSED_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC5CNT_RM(i) ((0x00251674)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC5CNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CYCLECNT_RM(i) ((0x00251678)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CYCLECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC6CNT_RM(i) ((0x0025167C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC6CNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENTCNT_RM(i) ((0x00251680)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENTCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_DFD_CNT_UPPER_RM(i) ((0x00251684)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_DFD_CNT_UPPER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHCNT_RM(i) ((0x00251688)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIGGERCNT_RM(i) ((0x0025168C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLECNT_RM(i) ((0x00251690)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHOLD_RM(i) ((0x00251698)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHOLD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_RM(i) ((0x0025169C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RELEASE_RM(i) ((0x002516A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RELEASE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT0_RM(i) ((0x002516A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT1_RM(i) ((0x002516A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT2_RM(i) ((0x002516AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT3_RM(i) ((0x002516B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT4_RM(i) ((0x002516B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT5_RM(i) ((0x002516B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT5_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT6_RM(i) ((0x002516BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT6_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT7_RM(i) ((0x002516C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT7_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWSMPLCNT_RM(i) ((0x002516C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWSMPLCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_RM(i) ((0x002516C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_RM(i) ((0x002516CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_RM(i) ((0x002516D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW2_RM(i) ((0x002516D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_RM(i) ((0x002516D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_RM(i) ((0x002516DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_STARTEXPERIMENT_RM(i) ((0x002516E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_STARTEXPERIMENT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_RM(i) ((0x002516E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_RM(i) ((0x002516E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_RM(i) ((0x002516EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_DEBUG_RM(i) ((0x002516F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_DAISY_DISABLE_RM(i) ((0x002516FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_DAISY_DISABLE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_RM(i) ((0x00251708)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_RM(i) ((0x00251710)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLD_RM(i) ((0x00251720)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_PERFMONID_RM(i) ((0x00251728)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_PERFMONID_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW2_RM(i) ((0x00251714)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW3_RM(i) ((0x00251718)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW3_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW4_RM(i) ((0x0025171C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW4_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TOTAL_TRIG_RCV_RM(i) ((0x00251724)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_TOTAL_TRIG_RCV_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER_RM(i) ((0x00251730)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CLAMP_CYA_CONTROL_RM(i) ((0x00251700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMSYS_SYSGS_NVLTX_CLAMP_CYA_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMMFBP_FT0_INPUTSEL_RM(i,j) (((0x00200000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FT0_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FT0_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FT1_INPUTSEL_RM(i,j) (((0x00200004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FT1_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FT1_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FT2_INPUTSEL_RM(i,j) (((0x00200008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FT2_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FT2_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FT3_INPUTSEL_RM(i,j) (((0x0020000C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FT3_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FT3_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FT4_INPUTSEL_RM(i,j) (((0x00200010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FT4_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FT4_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FT5_INPUTSEL_RM(i,j) (((0x00200014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FT5_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FT5_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CNTR0_INC_RM(i,j) (((0x00200020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CNTR0_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CNTR0_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CNTR1_INC_RM(i,j) (((0x00200024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CNTR1_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CNTR1_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CNTR2_INC_RM(i,j) (((0x00200028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CNTR2_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CNTR2_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CNTR3_INC_RM(i,j) (((0x0020002C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CNTR3_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CNTR3_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CNTR4_INC_RM(i,j) (((0x00200030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CNTR4_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CNTR4_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CNTR5_INC_RM(i,j) (((0x00200034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CNTR5_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CNTR5_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_TRIG0_SEL_RM(i,j) (((0x00200040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_TRIG0_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_TRIG0_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_TRIG0_OP_RM(i,j) (((0x00200044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_TRIG0_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_TRIG0_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_TRIG1_SEL_RM(i,j) (((0x00200048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_TRIG1_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_TRIG1_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_TRIG1_OP_RM(i,j) (((0x0020004C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_TRIG1_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_TRIG1_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_EVENT_SEL_RM(i,j) (((0x00200050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_EVENT_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_EVENT_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_EVENT_OP_RM(i,j) (((0x00200054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_EVENT_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_EVENT_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_SAMPLE_SEL_RM(i,j) (((0x00200058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_SAMPLE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_SAMPLE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_SAMPLE_OP_RM(i,j) (((0x0020005C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_SAMPLE_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_SAMPLE_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_SETFLAG_OP_RM(i,j) (((0x00200060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_SETFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_SETFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CLRFLAG_OP_RM(i,j) (((0x00200064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLRFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CLRFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_SELECTMUX_RM(i,j) (((0x00200068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_SELECTMUX_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_SELECTMUX_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_ENGINE_SEL_RM(i,j) (((0x0020006C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_ENGINE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_ENGINE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_ELAPSED_RM(i,j) (((0x00200070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_ELAPSED_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_ELAPSED_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_MODEC5CNT_RM(i,j) (((0x00200074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_MODEC5CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_MODEC5CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CYCLECNT_RM(i,j) (((0x00200078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CYCLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CYCLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_MODEC6CNT_RM(i,j) (((0x0020007C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_MODEC6CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_MODEC6CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_EVENTCNT_RM(i,j) (((0x00200080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_EVENTCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_EVENTCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_DFD_CNT_UPPER_RM(i,j) (((0x00200084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_DFD_CNT_UPPER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_DFD_CNT_UPPER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_THRESHCNT_RM(i,j) (((0x00200088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_THRESHCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_THRESHCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_TRIGGERCNT_RM(i,j) (((0x0020008C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_TRIGGERCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_TRIGGERCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_SAMPLECNT_RM(i,j) (((0x00200090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_SAMPLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_SAMPLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_THRESHOLD_RM(i,j) (((0x00200098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_THRESHOLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_THRESHOLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CONTROL_RM(i,j) (((0x0020009C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RELEASE_RM(i,j) (((0x002000A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RELEASE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RELEASE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWCNT0_RM(i,j) (((0x002000A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWCNT0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWCNT0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWCNT1_RM(i,j) (((0x002000A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWCNT1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWCNT1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWCNT2_RM(i,j) (((0x002000AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWCNT2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWCNT2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWCNT3_RM(i,j) (((0x002000B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWCNT3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWCNT3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWCNT4_RM(i,j) (((0x002000B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWCNT4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWCNT4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWCNT5_RM(i,j) (((0x002000B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWCNT5_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWCNT5_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWCNT6_RM(i,j) (((0x002000BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWCNT6_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWCNT6_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWCNT7_RM(i,j) (((0x002000C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWCNT7_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWCNT7_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_RAWSMPLCNT_RM(i,j) (((0x002000C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_RAWSMPLCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_RAWSMPLCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_ENGINESTATUS_RM(i,j) (((0x002000C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_ENGINESTATUS_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_ENGINESTATUS_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_WBSKEW0_RM(i,j) (((0x002000CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_WBSKEW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_WBSKEW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_WBSKEW1_RM(i,j) (((0x002000D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_WBSKEW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_WBSKEW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_WBSKEW2_RM(i,j) (((0x002000D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_WBSKEW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_WBSKEW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_WBSKEW_CHAIN0_RM(i,j) (((0x002000D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_WBSKEW_CHAIN0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_WBSKEW_CHAIN0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_WBSKEW_CHAIN1_RM(i,j) (((0x002000DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_WBSKEW_CHAIN1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_WBSKEW_CHAIN1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_STARTEXPERIMENT_RM(i,j) (((0x002000E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_STARTEXPERIMENT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_STARTEXPERIMENT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CTXSW0_RM(i,j) (((0x002000E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CTXSW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CTXSW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CTXSW1_RM(i,j) (((0x002000E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CTXSW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CTXSW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_WATCHBUSDEBUG_RM(i,j) (((0x002000EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_WATCHBUSDEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_WATCHBUSDEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_DEBUG_RM(i,j) (((0x002000F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_DEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_DEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_DAISY_DISABLE_RM(i,j) (((0x002000FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_DAISY_DISABLE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_DAISY_DISABLE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CONTROLB_RM(i,j) (((0x00200108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CONTROLB_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CONTROLB_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CONTROLC_RM(i,j) (((0x00200110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CONTROLC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CONTROLC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CONTROLD_RM(i,j) (((0x00200120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CONTROLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CONTROLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_PERFMONID_RM(i,j) (((0x00200128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_PERFMONID_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_PERFMONID_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CTXSW2_RM(i,j) (((0x00200114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CTXSW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CTXSW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CTXSW3_RM(i,j) (((0x00200118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CTXSW3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CTXSW3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CTXSW4_RM(i,j) (((0x0020011C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CTXSW4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CTXSW4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_TOTAL_TRIG_RCV_RM(i,j) (((0x00200124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_TOTAL_TRIG_RCV_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_TOTAL_TRIG_RCV_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FLAG_BIT_TIMER_RM(i,j) (((0x00200130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FLAG_BIT_TIMER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FLAG_BIT_TIMER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_RM(i) ((0x00246000)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_RECORD_GRANT_RM(i) ((0x00246004)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_RECORD_GRANT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00246008)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024600C)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_GLOBAL_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_ENGINESTATUS_RM(i) ((0x00246010)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_PERFMONSTATUS_RM(i) ((0x00246014)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_PERFMONSTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_CG2_RM(i) ((0x00246018)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_CG2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_RECORD_DEBUG_RM(i) ((0x0024601C)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_HS_RECORD_DEBUG_RM(i) ((0x00246154)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_HS_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBPROUTER_HS_CONFIG_RM(i) ((0x00246150)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMFBPROUTER_HS_CONFIG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL_RM(i,j) (((0x00200100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL11_RM(i) ((0x00201700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL11_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL10_RM(i) ((0x00201500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL10_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL9_RM(i) ((0x00201300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL9_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL8_RM(i) ((0x00201100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL8_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL7_RM(i) ((0x00200F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL6_RM(i) ((0x00200D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL5_RM(i) ((0x00200B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL4_RM(i) ((0x00200900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL3_RM(i) ((0x00200700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL2_RM(i) ((0x00200500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL1_RM(i) ((0x00200300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0_RM(i) ((0x00200100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL_RM(i,j) (((0x00200000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL_RM(i,j) (((0x00200004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL_RM(i,j) (((0x00200008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL_RM(i,j) (((0x0020000C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL_RM(i,j) (((0x00200010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL_RM(i,j) (((0x00200014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR0_INC_RM(i,j) (((0x00200020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CNTR0_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR0_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR1_INC_RM(i,j) (((0x00200024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CNTR1_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR1_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR2_INC_RM(i,j) (((0x00200028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CNTR2_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR2_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR3_INC_RM(i,j) (((0x0020002C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CNTR3_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR3_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR4_INC_RM(i,j) (((0x00200030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CNTR4_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR4_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR5_INC_RM(i,j) (((0x00200034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CNTR5_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CNTR5_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIG0_SEL_RM(i,j) (((0x00200040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_TRIG0_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIG0_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIG0_OP_RM(i,j) (((0x00200044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_TRIG0_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIG0_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIG1_SEL_RM(i,j) (((0x00200048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_TRIG1_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIG1_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIG1_OP_RM(i,j) (((0x0020004C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_TRIG1_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIG1_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_EVENT_SEL_RM(i,j) (((0x00200050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_EVENT_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_EVENT_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_EVENT_OP_RM(i,j) (((0x00200054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_EVENT_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_EVENT_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL_RM(i,j) (((0x00200058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_RM(i,j) (((0x0020005C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_RM(i,j) (((0x00200060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_RM(i,j) (((0x00200064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_SELECTMUX_RM(i,j) (((0x00200068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_SELECTMUX_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_SELECTMUX_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_ENGINE_SEL_RM(i,j) (((0x0020006C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_ENGINE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_ENGINE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_ELAPSED_RM(i,j) (((0x00200070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_ELAPSED_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_ELAPSED_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_MODEC5CNT_RM(i,j) (((0x00200074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_MODEC5CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_MODEC5CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CYCLECNT_RM(i,j) (((0x00200078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CYCLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CYCLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_MODEC6CNT_RM(i,j) (((0x0020007C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_MODEC6CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_MODEC6CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_EVENTCNT_RM(i,j) (((0x00200080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_EVENTCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_EVENTCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER_RM(i,j) (((0x00200084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_THRESHCNT_RM(i,j) (((0x00200088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_THRESHCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_THRESHCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIGGERCNT_RM(i,j) (((0x0020008C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_TRIGGERCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_TRIGGERCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_SAMPLECNT_RM(i,j) (((0x00200090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_SAMPLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_SAMPLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_THRESHOLD_RM(i,j) (((0x00200098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_THRESHOLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_THRESHOLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CONTROL_RM(i,j) (((0x0020009C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RELEASE_RM(i,j) (((0x002000A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RELEASE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RELEASE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT0_RM(i,j) (((0x002000A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWCNT0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT1_RM(i,j) (((0x002000A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWCNT1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT2_RM(i,j) (((0x002000AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWCNT2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT3_RM(i,j) (((0x002000B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWCNT3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT4_RM(i,j) (((0x002000B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWCNT4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT5_RM(i,j) (((0x002000B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWCNT5_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT5_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT6_RM(i,j) (((0x002000BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWCNT6_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT6_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT7_RM(i,j) (((0x002000C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWCNT7_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWCNT7_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWSMPLCNT_RM(i,j) (((0x002000C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_RAWSMPLCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_RAWSMPLCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_RM(i,j) (((0x002000C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW0_RM(i,j) (((0x002000CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_WBSKEW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW1_RM(i,j) (((0x002000D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_WBSKEW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW2_RM(i,j) (((0x002000D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_WBSKEW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_RM(i,j) (((0x002000D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_RM(i,j) (((0x002000DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_STARTEXPERIMENT_RM(i,j) (((0x002000E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_STARTEXPERIMENT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_STARTEXPERIMENT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW0_RM(i,j) (((0x002000E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CTXSW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW1_RM(i,j) (((0x002000E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CTXSW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_RM(i,j) (((0x002000EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_DEBUG_RM(i,j) (((0x002000F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_DEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_DEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_DAISY_DISABLE_RM(i,j) (((0x002000FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_DAISY_DISABLE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_DAISY_DISABLE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CONTROLB_RM(i,j) (((0x00200108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CONTROLB_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CONTROLB_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CONTROLC_RM(i,j) (((0x00200110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CONTROLC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CONTROLC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CONTROLD_RM(i,j) (((0x00200120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CONTROLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CONTROLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_PERFMONID_RM(i,j) (((0x00200128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_PERFMONID_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_PERFMONID_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW2_RM(i,j) (((0x00200114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CTXSW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW3_RM(i,j) (((0x00200118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CTXSW3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW4_RM(i,j) (((0x0020011C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CTXSW4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CTXSW4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_TOTAL_TRIG_RCV_RM(i,j) (((0x00200124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_TOTAL_TRIG_RCV_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_TOTAL_TRIG_RCV_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_RM(i,j) (((0x00200130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_RM(i) ((0x00246000)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_GRANT_RM(i) ((0x00246004)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_GRANT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00246008)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024600C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_RM(i) ((0x00246010)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_PERFMONSTATUS_RM(i) ((0x00246014)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_PERFMONSTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_CG2_RM(i) ((0x00246018)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_CG2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG_RM(i) ((0x0024601C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00246154)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_RM(i) ((0x00246150)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL_RM(i,j) (((0x00200100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL11_RM(i) ((0x00201700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL11_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL10_RM(i) ((0x00201500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL10_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL9_RM(i) ((0x00201300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL9_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL8_RM(i) ((0x00201100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL8_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL7_RM(i) ((0x00200F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL6_RM(i) ((0x00200D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL5_RM(i) ((0x00200B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL4_RM(i) ((0x00200900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL3_RM(i) ((0x00200700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL2_RM(i) ((0x00200500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL1_RM(i) ((0x00200300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0_RM(i) ((0x00200100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL_RM(i,j) (((0x00204000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL_RM(i,j) (((0x00204004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL_RM(i,j) (((0x00204008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL_RM(i,j) (((0x0020400C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL_RM(i,j) (((0x00204010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL_RM(i,j) (((0x00204014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR0_INC_RM(i,j) (((0x00204020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CNTR0_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR0_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR1_INC_RM(i,j) (((0x00204024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CNTR1_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR1_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR2_INC_RM(i,j) (((0x00204028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CNTR2_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR2_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR3_INC_RM(i,j) (((0x0020402C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CNTR3_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR3_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR4_INC_RM(i,j) (((0x00204030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CNTR4_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR4_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR5_INC_RM(i,j) (((0x00204034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CNTR5_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CNTR5_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIG0_SEL_RM(i,j) (((0x00204040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_TRIG0_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIG0_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIG0_OP_RM(i,j) (((0x00204044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_TRIG0_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIG0_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIG1_SEL_RM(i,j) (((0x00204048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_TRIG1_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIG1_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIG1_OP_RM(i,j) (((0x0020404C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_TRIG1_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIG1_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_EVENT_SEL_RM(i,j) (((0x00204050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_EVENT_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_EVENT_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_EVENT_OP_RM(i,j) (((0x00204054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_EVENT_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_EVENT_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL_RM(i,j) (((0x00204058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_RM(i,j) (((0x0020405C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_RM(i,j) (((0x00204060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_RM(i,j) (((0x00204064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_SELECTMUX_RM(i,j) (((0x00204068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_SELECTMUX_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_SELECTMUX_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_ENGINE_SEL_RM(i,j) (((0x0020406C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_ENGINE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_ENGINE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_ELAPSED_RM(i,j) (((0x00204070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_ELAPSED_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_ELAPSED_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_MODEC5CNT_RM(i,j) (((0x00204074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_MODEC5CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_MODEC5CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CYCLECNT_RM(i,j) (((0x00204078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CYCLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CYCLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_MODEC6CNT_RM(i,j) (((0x0020407C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_MODEC6CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_MODEC6CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_EVENTCNT_RM(i,j) (((0x00204080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_EVENTCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_EVENTCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER_RM(i,j) (((0x00204084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_THRESHCNT_RM(i,j) (((0x00204088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_THRESHCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_THRESHCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIGGERCNT_RM(i,j) (((0x0020408C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_TRIGGERCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_TRIGGERCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_SAMPLECNT_RM(i,j) (((0x00204090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_SAMPLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_SAMPLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_THRESHOLD_RM(i,j) (((0x00204098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_THRESHOLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_THRESHOLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CONTROL_RM(i,j) (((0x0020409C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RELEASE_RM(i,j) (((0x002040A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RELEASE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RELEASE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT0_RM(i,j) (((0x002040A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWCNT0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT1_RM(i,j) (((0x002040A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWCNT1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT2_RM(i,j) (((0x002040AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWCNT2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT3_RM(i,j) (((0x002040B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWCNT3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT4_RM(i,j) (((0x002040B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWCNT4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT5_RM(i,j) (((0x002040B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWCNT5_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT5_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT6_RM(i,j) (((0x002040BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWCNT6_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT6_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT7_RM(i,j) (((0x002040C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWCNT7_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWCNT7_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWSMPLCNT_RM(i,j) (((0x002040C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_RAWSMPLCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_RAWSMPLCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_RM(i,j) (((0x002040C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW0_RM(i,j) (((0x002040CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_WBSKEW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW1_RM(i,j) (((0x002040D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_WBSKEW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW2_RM(i,j) (((0x002040D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_WBSKEW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_RM(i,j) (((0x002040D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_RM(i,j) (((0x002040DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_STARTEXPERIMENT_RM(i,j) (((0x002040E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_STARTEXPERIMENT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_STARTEXPERIMENT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW0_RM(i,j) (((0x002040E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CTXSW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW1_RM(i,j) (((0x002040E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CTXSW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_RM(i,j) (((0x002040EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_DEBUG_RM(i,j) (((0x002040F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_DEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_DEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_DAISY_DISABLE_RM(i,j) (((0x002040FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_DAISY_DISABLE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_DAISY_DISABLE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CONTROLB_RM(i,j) (((0x00204108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CONTROLB_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CONTROLB_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CONTROLC_RM(i,j) (((0x00204110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CONTROLC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CONTROLC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CONTROLD_RM(i,j) (((0x00204120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CONTROLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CONTROLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_PERFMONID_RM(i,j) (((0x00204128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_PERFMONID_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_PERFMONID_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW2_RM(i,j) (((0x00204114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CTXSW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW3_RM(i,j) (((0x00204118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CTXSW3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW4_RM(i,j) (((0x0020411C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CTXSW4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CTXSW4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_TOTAL_TRIG_RCV_RM(i,j) (((0x00204124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_TOTAL_TRIG_RCV_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_TOTAL_TRIG_RCV_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_RM(i,j) (((0x00204130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_RM(i) ((0x00246200)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_GRANT_RM(i) ((0x00246204)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_GRANT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00246208)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024620C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_RM(i) ((0x00246210)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_PERFMONSTATUS_RM(i) ((0x00246214)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_PERFMONSTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_CG2_RM(i) ((0x00246218)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_CG2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG_RM(i) ((0x0024621C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00246354)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_RM(i) ((0x00246350)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL_RM(i,j) (((0x00204100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL11_RM(i) ((0x00205700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL11_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL10_RM(i) ((0x00205500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL10_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL9_RM(i) ((0x00205300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL9_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL8_RM(i) ((0x00205100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL8_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL7_RM(i) ((0x00204F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL6_RM(i) ((0x00204D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL5_RM(i) ((0x00204B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL4_RM(i) ((0x00204900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL3_RM(i) ((0x00204700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL2_RM(i) ((0x00204500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL1_RM(i) ((0x00204300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0_RM(i) ((0x00204100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL_RM(i,j) (((0x00208000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL_RM(i,j) (((0x00208004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL_RM(i,j) (((0x00208008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL_RM(i,j) (((0x0020800C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL_RM(i,j) (((0x00208010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL_RM(i,j) (((0x00208014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR0_INC_RM(i,j) (((0x00208020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CNTR0_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR0_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR1_INC_RM(i,j) (((0x00208024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CNTR1_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR1_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR2_INC_RM(i,j) (((0x00208028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CNTR2_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR2_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR3_INC_RM(i,j) (((0x0020802C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CNTR3_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR3_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR4_INC_RM(i,j) (((0x00208030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CNTR4_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR4_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR5_INC_RM(i,j) (((0x00208034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CNTR5_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CNTR5_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIG0_SEL_RM(i,j) (((0x00208040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_TRIG0_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIG0_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIG0_OP_RM(i,j) (((0x00208044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_TRIG0_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIG0_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIG1_SEL_RM(i,j) (((0x00208048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_TRIG1_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIG1_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIG1_OP_RM(i,j) (((0x0020804C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_TRIG1_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIG1_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_EVENT_SEL_RM(i,j) (((0x00208050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_EVENT_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_EVENT_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_EVENT_OP_RM(i,j) (((0x00208054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_EVENT_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_EVENT_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL_RM(i,j) (((0x00208058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_RM(i,j) (((0x0020805C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_RM(i,j) (((0x00208060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_RM(i,j) (((0x00208064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_SELECTMUX_RM(i,j) (((0x00208068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_SELECTMUX_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_SELECTMUX_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_ENGINE_SEL_RM(i,j) (((0x0020806C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_ENGINE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_ENGINE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_ELAPSED_RM(i,j) (((0x00208070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_ELAPSED_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_ELAPSED_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_MODEC5CNT_RM(i,j) (((0x00208074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_MODEC5CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_MODEC5CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CYCLECNT_RM(i,j) (((0x00208078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CYCLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CYCLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_MODEC6CNT_RM(i,j) (((0x0020807C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_MODEC6CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_MODEC6CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_EVENTCNT_RM(i,j) (((0x00208080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_EVENTCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_EVENTCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER_RM(i,j) (((0x00208084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_THRESHCNT_RM(i,j) (((0x00208088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_THRESHCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_THRESHCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIGGERCNT_RM(i,j) (((0x0020808C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_TRIGGERCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_TRIGGERCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_SAMPLECNT_RM(i,j) (((0x00208090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_SAMPLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_SAMPLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_THRESHOLD_RM(i,j) (((0x00208098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_THRESHOLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_THRESHOLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CONTROL_RM(i,j) (((0x0020809C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RELEASE_RM(i,j) (((0x002080A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RELEASE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RELEASE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT0_RM(i,j) (((0x002080A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWCNT0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT1_RM(i,j) (((0x002080A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWCNT1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT2_RM(i,j) (((0x002080AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWCNT2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT3_RM(i,j) (((0x002080B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWCNT3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT4_RM(i,j) (((0x002080B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWCNT4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT5_RM(i,j) (((0x002080B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWCNT5_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT5_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT6_RM(i,j) (((0x002080BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWCNT6_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT6_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT7_RM(i,j) (((0x002080C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWCNT7_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWCNT7_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWSMPLCNT_RM(i,j) (((0x002080C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_RAWSMPLCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_RAWSMPLCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_RM(i,j) (((0x002080C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW0_RM(i,j) (((0x002080CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_WBSKEW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW1_RM(i,j) (((0x002080D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_WBSKEW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW2_RM(i,j) (((0x002080D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_WBSKEW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_RM(i,j) (((0x002080D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_RM(i,j) (((0x002080DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_STARTEXPERIMENT_RM(i,j) (((0x002080E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_STARTEXPERIMENT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_STARTEXPERIMENT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW0_RM(i,j) (((0x002080E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CTXSW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW1_RM(i,j) (((0x002080E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CTXSW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_RM(i,j) (((0x002080EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_DEBUG_RM(i,j) (((0x002080F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_DEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_DEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_DAISY_DISABLE_RM(i,j) (((0x002080FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_DAISY_DISABLE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_DAISY_DISABLE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CONTROLB_RM(i,j) (((0x00208108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CONTROLB_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CONTROLB_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CONTROLC_RM(i,j) (((0x00208110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CONTROLC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CONTROLC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CONTROLD_RM(i,j) (((0x00208120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CONTROLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CONTROLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_PERFMONID_RM(i,j) (((0x00208128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_PERFMONID_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_PERFMONID_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW2_RM(i,j) (((0x00208114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CTXSW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW3_RM(i,j) (((0x00208118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CTXSW3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW4_RM(i,j) (((0x0020811C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CTXSW4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CTXSW4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_TOTAL_TRIG_RCV_RM(i,j) (((0x00208124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_TOTAL_TRIG_RCV_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_TOTAL_TRIG_RCV_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_RM(i,j) (((0x00208130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_RM(i) ((0x00246400)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_GRANT_RM(i) ((0x00246404)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_GRANT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00246408)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024640C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_RM(i) ((0x00246410)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_PERFMONSTATUS_RM(i) ((0x00246414)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_PERFMONSTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_CG2_RM(i) ((0x00246418)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_CG2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG_RM(i) ((0x0024641C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00246554)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_RM(i) ((0x00246550)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL_RM(i,j) (((0x00208100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL11_RM(i) ((0x00209700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL11_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL10_RM(i) ((0x00209500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL10_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL9_RM(i) ((0x00209300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL9_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL8_RM(i) ((0x00209100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL8_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL7_RM(i) ((0x00208F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL6_RM(i) ((0x00208D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL5_RM(i) ((0x00208B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL4_RM(i) ((0x00208900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL3_RM(i) ((0x00208700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL2_RM(i) ((0x00208500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL1_RM(i) ((0x00208300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0_RM(i) ((0x00208100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL_RM(i,j) (((0x0020C000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL_RM(i,j) (((0x0020C004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL_RM(i,j) (((0x0020C008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL_RM(i,j) (((0x0020C00C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL_RM(i,j) (((0x0020C010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL_RM(i,j) (((0x0020C014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR0_INC_RM(i,j) (((0x0020C020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CNTR0_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR0_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR1_INC_RM(i,j) (((0x0020C024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CNTR1_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR1_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR2_INC_RM(i,j) (((0x0020C028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CNTR2_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR2_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR3_INC_RM(i,j) (((0x0020C02C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CNTR3_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR3_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR4_INC_RM(i,j) (((0x0020C030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CNTR4_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR4_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR5_INC_RM(i,j) (((0x0020C034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CNTR5_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CNTR5_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIG0_SEL_RM(i,j) (((0x0020C040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_TRIG0_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIG0_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIG0_OP_RM(i,j) (((0x0020C044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_TRIG0_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIG0_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIG1_SEL_RM(i,j) (((0x0020C048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_TRIG1_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIG1_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIG1_OP_RM(i,j) (((0x0020C04C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_TRIG1_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIG1_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_EVENT_SEL_RM(i,j) (((0x0020C050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_EVENT_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_EVENT_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_EVENT_OP_RM(i,j) (((0x0020C054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_EVENT_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_EVENT_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL_RM(i,j) (((0x0020C058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_RM(i,j) (((0x0020C05C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_RM(i,j) (((0x0020C060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_RM(i,j) (((0x0020C064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_SELECTMUX_RM(i,j) (((0x0020C068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_SELECTMUX_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_SELECTMUX_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_ENGINE_SEL_RM(i,j) (((0x0020C06C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_ENGINE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_ENGINE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_ELAPSED_RM(i,j) (((0x0020C070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_ELAPSED_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_ELAPSED_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_MODEC5CNT_RM(i,j) (((0x0020C074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_MODEC5CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_MODEC5CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CYCLECNT_RM(i,j) (((0x0020C078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CYCLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CYCLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_MODEC6CNT_RM(i,j) (((0x0020C07C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_MODEC6CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_MODEC6CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_EVENTCNT_RM(i,j) (((0x0020C080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_EVENTCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_EVENTCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER_RM(i,j) (((0x0020C084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_THRESHCNT_RM(i,j) (((0x0020C088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_THRESHCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_THRESHCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIGGERCNT_RM(i,j) (((0x0020C08C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_TRIGGERCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_TRIGGERCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_SAMPLECNT_RM(i,j) (((0x0020C090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_SAMPLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_SAMPLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_THRESHOLD_RM(i,j) (((0x0020C098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_THRESHOLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_THRESHOLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CONTROL_RM(i,j) (((0x0020C09C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RELEASE_RM(i,j) (((0x0020C0A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RELEASE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RELEASE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT0_RM(i,j) (((0x0020C0A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWCNT0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT1_RM(i,j) (((0x0020C0A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWCNT1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT2_RM(i,j) (((0x0020C0AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWCNT2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT3_RM(i,j) (((0x0020C0B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWCNT3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT4_RM(i,j) (((0x0020C0B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWCNT4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT5_RM(i,j) (((0x0020C0B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWCNT5_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT5_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT6_RM(i,j) (((0x0020C0BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWCNT6_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT6_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT7_RM(i,j) (((0x0020C0C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWCNT7_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWCNT7_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWSMPLCNT_RM(i,j) (((0x0020C0C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_RAWSMPLCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_RAWSMPLCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_RM(i,j) (((0x0020C0C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW0_RM(i,j) (((0x0020C0CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_WBSKEW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW1_RM(i,j) (((0x0020C0D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_WBSKEW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW2_RM(i,j) (((0x0020C0D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_WBSKEW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_RM(i,j) (((0x0020C0D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_RM(i,j) (((0x0020C0DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_STARTEXPERIMENT_RM(i,j) (((0x0020C0E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_STARTEXPERIMENT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_STARTEXPERIMENT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW0_RM(i,j) (((0x0020C0E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CTXSW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW1_RM(i,j) (((0x0020C0E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CTXSW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_RM(i,j) (((0x0020C0EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_DEBUG_RM(i,j) (((0x0020C0F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_DEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_DEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_DAISY_DISABLE_RM(i,j) (((0x0020C0FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_DAISY_DISABLE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_DAISY_DISABLE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CONTROLB_RM(i,j) (((0x0020C108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CONTROLB_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CONTROLB_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CONTROLC_RM(i,j) (((0x0020C110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CONTROLC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CONTROLC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CONTROLD_RM(i,j) (((0x0020C120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CONTROLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CONTROLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_PERFMONID_RM(i,j) (((0x0020C128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_PERFMONID_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_PERFMONID_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW2_RM(i,j) (((0x0020C114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CTXSW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW3_RM(i,j) (((0x0020C118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CTXSW3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW4_RM(i,j) (((0x0020C11C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CTXSW4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CTXSW4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_TOTAL_TRIG_RCV_RM(i,j) (((0x0020C124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_TOTAL_TRIG_RCV_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_TOTAL_TRIG_RCV_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_RM(i,j) (((0x0020C130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_RM(i) ((0x00246600)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_GRANT_RM(i) ((0x00246604)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_GRANT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00246608)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024660C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_RM(i) ((0x00246610)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_PERFMONSTATUS_RM(i) ((0x00246614)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_PERFMONSTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_CG2_RM(i) ((0x00246618)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_CG2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG_RM(i) ((0x0024661C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00246754)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_RM(i) ((0x00246750)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL_RM(i,j) (((0x0020C100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL11_RM(i) ((0x0020D700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL11_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL10_RM(i) ((0x0020D500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL10_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL9_RM(i) ((0x0020D300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL9_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL8_RM(i) ((0x0020D100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL8_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL7_RM(i) ((0x0020CF00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL6_RM(i) ((0x0020CD00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL5_RM(i) ((0x0020CB00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL4_RM(i) ((0x0020C900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL3_RM(i) ((0x0020C700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL2_RM(i) ((0x0020C500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL1_RM(i) ((0x0020C300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0_RM(i) ((0x0020C100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL_RM(i,j) (((0x00210000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL_RM(i,j) (((0x00210004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL_RM(i,j) (((0x00210008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL_RM(i,j) (((0x0021000C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL_RM(i,j) (((0x00210010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL_RM(i,j) (((0x00210014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR0_INC_RM(i,j) (((0x00210020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CNTR0_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR0_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR1_INC_RM(i,j) (((0x00210024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CNTR1_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR1_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR2_INC_RM(i,j) (((0x00210028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CNTR2_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR2_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR3_INC_RM(i,j) (((0x0021002C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CNTR3_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR3_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR4_INC_RM(i,j) (((0x00210030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CNTR4_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR4_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR5_INC_RM(i,j) (((0x00210034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CNTR5_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CNTR5_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIG0_SEL_RM(i,j) (((0x00210040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_TRIG0_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIG0_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIG0_OP_RM(i,j) (((0x00210044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_TRIG0_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIG0_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIG1_SEL_RM(i,j) (((0x00210048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_TRIG1_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIG1_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIG1_OP_RM(i,j) (((0x0021004C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_TRIG1_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIG1_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_EVENT_SEL_RM(i,j) (((0x00210050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_EVENT_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_EVENT_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_EVENT_OP_RM(i,j) (((0x00210054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_EVENT_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_EVENT_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL_RM(i,j) (((0x00210058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_RM(i,j) (((0x0021005C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_RM(i,j) (((0x00210060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_RM(i,j) (((0x00210064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_SELECTMUX_RM(i,j) (((0x00210068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_SELECTMUX_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_SELECTMUX_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_ENGINE_SEL_RM(i,j) (((0x0021006C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_ENGINE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_ENGINE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_ELAPSED_RM(i,j) (((0x00210070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_ELAPSED_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_ELAPSED_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_MODEC5CNT_RM(i,j) (((0x00210074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_MODEC5CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_MODEC5CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CYCLECNT_RM(i,j) (((0x00210078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CYCLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CYCLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_MODEC6CNT_RM(i,j) (((0x0021007C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_MODEC6CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_MODEC6CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_EVENTCNT_RM(i,j) (((0x00210080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_EVENTCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_EVENTCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER_RM(i,j) (((0x00210084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_THRESHCNT_RM(i,j) (((0x00210088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_THRESHCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_THRESHCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIGGERCNT_RM(i,j) (((0x0021008C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_TRIGGERCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_TRIGGERCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_SAMPLECNT_RM(i,j) (((0x00210090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_SAMPLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_SAMPLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_THRESHOLD_RM(i,j) (((0x00210098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_THRESHOLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_THRESHOLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CONTROL_RM(i,j) (((0x0021009C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RELEASE_RM(i,j) (((0x002100A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RELEASE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RELEASE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT0_RM(i,j) (((0x002100A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWCNT0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT1_RM(i,j) (((0x002100A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWCNT1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT2_RM(i,j) (((0x002100AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWCNT2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT3_RM(i,j) (((0x002100B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWCNT3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT4_RM(i,j) (((0x002100B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWCNT4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT5_RM(i,j) (((0x002100B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWCNT5_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT5_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT6_RM(i,j) (((0x002100BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWCNT6_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT6_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT7_RM(i,j) (((0x002100C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWCNT7_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWCNT7_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWSMPLCNT_RM(i,j) (((0x002100C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_RAWSMPLCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_RAWSMPLCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_RM(i,j) (((0x002100C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW0_RM(i,j) (((0x002100CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_WBSKEW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW1_RM(i,j) (((0x002100D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_WBSKEW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW2_RM(i,j) (((0x002100D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_WBSKEW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_RM(i,j) (((0x002100D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_RM(i,j) (((0x002100DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_STARTEXPERIMENT_RM(i,j) (((0x002100E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_STARTEXPERIMENT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_STARTEXPERIMENT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW0_RM(i,j) (((0x002100E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CTXSW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW1_RM(i,j) (((0x002100E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CTXSW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_RM(i,j) (((0x002100EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_DEBUG_RM(i,j) (((0x002100F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_DEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_DEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_DAISY_DISABLE_RM(i,j) (((0x002100FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_DAISY_DISABLE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_DAISY_DISABLE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CONTROLB_RM(i,j) (((0x00210108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CONTROLB_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CONTROLB_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CONTROLC_RM(i,j) (((0x00210110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CONTROLC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CONTROLC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CONTROLD_RM(i,j) (((0x00210120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CONTROLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CONTROLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_PERFMONID_RM(i,j) (((0x00210128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_PERFMONID_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_PERFMONID_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW2_RM(i,j) (((0x00210114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CTXSW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW3_RM(i,j) (((0x00210118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CTXSW3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW4_RM(i,j) (((0x0021011C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CTXSW4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CTXSW4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_TOTAL_TRIG_RCV_RM(i,j) (((0x00210124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_TOTAL_TRIG_RCV_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_TOTAL_TRIG_RCV_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_RM(i,j) (((0x00210130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_RM(i) ((0x00246800)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_GRANT_RM(i) ((0x00246804)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_GRANT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00246808)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024680C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_RM(i) ((0x00246810)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_PERFMONSTATUS_RM(i) ((0x00246814)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_PERFMONSTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_CG2_RM(i) ((0x00246818)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_CG2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG_RM(i) ((0x0024681C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00246954)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_RM(i) ((0x00246950)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL_RM(i,j) (((0x00210100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL11_RM(i) ((0x00211700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL11_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL10_RM(i) ((0x00211500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL10_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL9_RM(i) ((0x00211300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL9_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL8_RM(i) ((0x00211100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL8_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL7_RM(i) ((0x00210F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL6_RM(i) ((0x00210D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL5_RM(i) ((0x00210B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL4_RM(i) ((0x00210900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL3_RM(i) ((0x00210700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL2_RM(i) ((0x00210500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL1_RM(i) ((0x00210300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0_RM(i) ((0x00210100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL_RM(i,j) (((0x00214000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL_RM(i,j) (((0x00214004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL_RM(i,j) (((0x00214008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL_RM(i,j) (((0x0021400C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL_RM(i,j) (((0x00214010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL_RM(i,j) (((0x00214014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR0_INC_RM(i,j) (((0x00214020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CNTR0_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR0_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR1_INC_RM(i,j) (((0x00214024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CNTR1_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR1_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR2_INC_RM(i,j) (((0x00214028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CNTR2_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR2_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR3_INC_RM(i,j) (((0x0021402C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CNTR3_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR3_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR4_INC_RM(i,j) (((0x00214030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CNTR4_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR4_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR5_INC_RM(i,j) (((0x00214034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CNTR5_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CNTR5_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIG0_SEL_RM(i,j) (((0x00214040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_TRIG0_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIG0_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIG0_OP_RM(i,j) (((0x00214044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_TRIG0_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIG0_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIG1_SEL_RM(i,j) (((0x00214048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_TRIG1_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIG1_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIG1_OP_RM(i,j) (((0x0021404C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_TRIG1_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIG1_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_EVENT_SEL_RM(i,j) (((0x00214050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_EVENT_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_EVENT_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_EVENT_OP_RM(i,j) (((0x00214054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_EVENT_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_EVENT_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL_RM(i,j) (((0x00214058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_RM(i,j) (((0x0021405C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_RM(i,j) (((0x00214060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_RM(i,j) (((0x00214064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_SELECTMUX_RM(i,j) (((0x00214068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_SELECTMUX_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_SELECTMUX_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_ENGINE_SEL_RM(i,j) (((0x0021406C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_ENGINE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_ENGINE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_ELAPSED_RM(i,j) (((0x00214070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_ELAPSED_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_ELAPSED_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_MODEC5CNT_RM(i,j) (((0x00214074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_MODEC5CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_MODEC5CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CYCLECNT_RM(i,j) (((0x00214078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CYCLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CYCLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_MODEC6CNT_RM(i,j) (((0x0021407C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_MODEC6CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_MODEC6CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_EVENTCNT_RM(i,j) (((0x00214080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_EVENTCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_EVENTCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER_RM(i,j) (((0x00214084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_THRESHCNT_RM(i,j) (((0x00214088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_THRESHCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_THRESHCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIGGERCNT_RM(i,j) (((0x0021408C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_TRIGGERCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_TRIGGERCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_SAMPLECNT_RM(i,j) (((0x00214090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_SAMPLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_SAMPLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_THRESHOLD_RM(i,j) (((0x00214098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_THRESHOLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_THRESHOLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CONTROL_RM(i,j) (((0x0021409C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RELEASE_RM(i,j) (((0x002140A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RELEASE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RELEASE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT0_RM(i,j) (((0x002140A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWCNT0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT1_RM(i,j) (((0x002140A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWCNT1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT2_RM(i,j) (((0x002140AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWCNT2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT3_RM(i,j) (((0x002140B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWCNT3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT4_RM(i,j) (((0x002140B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWCNT4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT5_RM(i,j) (((0x002140B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWCNT5_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT5_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT6_RM(i,j) (((0x002140BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWCNT6_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT6_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT7_RM(i,j) (((0x002140C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWCNT7_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWCNT7_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWSMPLCNT_RM(i,j) (((0x002140C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_RAWSMPLCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_RAWSMPLCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_RM(i,j) (((0x002140C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW0_RM(i,j) (((0x002140CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_WBSKEW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW1_RM(i,j) (((0x002140D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_WBSKEW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW2_RM(i,j) (((0x002140D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_WBSKEW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_RM(i,j) (((0x002140D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_RM(i,j) (((0x002140DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_STARTEXPERIMENT_RM(i,j) (((0x002140E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_STARTEXPERIMENT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_STARTEXPERIMENT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW0_RM(i,j) (((0x002140E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CTXSW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW1_RM(i,j) (((0x002140E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CTXSW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_RM(i,j) (((0x002140EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_DEBUG_RM(i,j) (((0x002140F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_DEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_DEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_DAISY_DISABLE_RM(i,j) (((0x002140FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_DAISY_DISABLE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_DAISY_DISABLE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CONTROLB_RM(i,j) (((0x00214108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CONTROLB_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CONTROLB_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CONTROLC_RM(i,j) (((0x00214110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CONTROLC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CONTROLC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CONTROLD_RM(i,j) (((0x00214120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CONTROLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CONTROLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_PERFMONID_RM(i,j) (((0x00214128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_PERFMONID_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_PERFMONID_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW2_RM(i,j) (((0x00214114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CTXSW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW3_RM(i,j) (((0x00214118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CTXSW3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW4_RM(i,j) (((0x0021411C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CTXSW4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CTXSW4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_TOTAL_TRIG_RCV_RM(i,j) (((0x00214124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_TOTAL_TRIG_RCV_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_TOTAL_TRIG_RCV_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_RM(i,j) (((0x00214130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_RM(i) ((0x00246A00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_GRANT_RM(i) ((0x00246A04)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_GRANT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00246A08)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CTXSW0_RM(i) ((0x00246A0C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_RM(i) ((0x00246A10)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_PERFMONSTATUS_RM(i) ((0x00246A14)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_PERFMONSTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_CG2_RM(i) ((0x00246A18)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_CG2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG_RM(i) ((0x00246A1C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00246B54)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_RM(i) ((0x00246B50)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL_RM(i,j) (((0x00214100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL11_RM(i) ((0x00215700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL11_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL10_RM(i) ((0x00215500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL10_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL9_RM(i) ((0x00215300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL9_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL8_RM(i) ((0x00215100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL8_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL7_RM(i) ((0x00214F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL6_RM(i) ((0x00214D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL5_RM(i) ((0x00214B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL4_RM(i) ((0x00214900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL3_RM(i) ((0x00214700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL2_RM(i) ((0x00214500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL1_RM(i) ((0x00214300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0_RM(i) ((0x00214100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT0_INPUTSEL_RM(i) ((0x00250800)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT0_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT1_INPUTSEL_RM(i) ((0x00250804)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT1_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT2_INPUTSEL_RM(i) ((0x00250808)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT2_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT3_INPUTSEL_RM(i) ((0x0025080C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT3_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT4_INPUTSEL_RM(i) ((0x00250810)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT4_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT5_INPUTSEL_RM(i) ((0x00250814)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FT5_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_RM(i) ((0x00250820)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_RM(i) ((0x00250824)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_RM(i) ((0x00250828)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_RM(i) ((0x0025082C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_RM(i) ((0x00250830)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_RM(i) ((0x00250834)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_SEL_RM(i) ((0x00250840)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_RM(i) ((0x00250844)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_SEL_RM(i) ((0x00250848)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_RM(i) ((0x0025084C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_SEL_RM(i) ((0x00250850)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_RM(i) ((0x00250854)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_SEL_RM(i) ((0x00250858)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_RM(i) ((0x0025085C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_RM(i) ((0x00250860)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_RM(i) ((0x00250864)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX_RM(i) ((0x00250868)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINE_SEL_RM(i) ((0x0025086C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINE_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_ELAPSED_RM(i) ((0x00250870)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_ELAPSED_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC5CNT_RM(i) ((0x00250874)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC5CNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CYCLECNT_RM(i) ((0x00250878)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CYCLECNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC6CNT_RM(i) ((0x0025087C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC6CNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_EVENTCNT_RM(i) ((0x00250880)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_EVENTCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_DFD_CNT_UPPER_RM(i) ((0x00250884)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_DFD_CNT_UPPER_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHCNT_RM(i) ((0x00250888)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIGGERCNT_RM(i) ((0x0025088C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLECNT_RM(i) ((0x00250890)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLECNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHOLD_RM(i) ((0x00250898)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHOLD_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_RM(i) ((0x0025089C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RELEASE_RM(i) ((0x002508A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RELEASE_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT0_RM(i) ((0x002508A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT1_RM(i) ((0x002508A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT2_RM(i) ((0x002508AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT3_RM(i) ((0x002508B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT4_RM(i) ((0x002508B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT5_RM(i) ((0x002508B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT6_RM(i) ((0x002508BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT7_RM(i) ((0x002508C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWSMPLCNT_RM(i) ((0x002508C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_RAWSMPLCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_RM(i) ((0x002508C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_RM(i) ((0x002508CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_RM(i) ((0x002508D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW2_RM(i) ((0x002508D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_RM(i) ((0x002508D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_RM(i) ((0x002508DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_STARTEXPERIMENT_RM(i) ((0x002508E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_STARTEXPERIMENT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_RM(i) ((0x002508E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_RM(i) ((0x002508E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_RM(i) ((0x002508EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_DEBUG_RM(i) ((0x002508F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_DAISY_DISABLE_RM(i) ((0x002508FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_DAISY_DISABLE_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_RM(i) ((0x00250908)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_RM(i) ((0x00250910)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLD_RM(i) ((0x00250920)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLD_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_PERFMONID_RM(i) ((0x00250928)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_PERFMONID_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW2_RM(i) ((0x00250914)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW3_RM(i) ((0x00250918)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW4_RM(i) ((0x0025091C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TOTAL_TRIG_RCV_RM(i) ((0x00250924)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_TOTAL_TRIG_RCV_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER_RM(i) ((0x00250930)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CLAMP_CYA_CONTROL_RM(i) ((0x00250900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPA_CLAMP_CYA_CONTROL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT0_INPUTSEL_RM(i) ((0x00250A00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT0_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT1_INPUTSEL_RM(i) ((0x00250A04)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT1_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT2_INPUTSEL_RM(i) ((0x00250A08)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT2_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT3_INPUTSEL_RM(i) ((0x00250A0C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT3_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT4_INPUTSEL_RM(i) ((0x00250A10)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT4_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT5_INPUTSEL_RM(i) ((0x00250A14)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FT5_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_RM(i) ((0x00250A20)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_RM(i) ((0x00250A24)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_RM(i) ((0x00250A28)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_RM(i) ((0x00250A2C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_RM(i) ((0x00250A30)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_RM(i) ((0x00250A34)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_SEL_RM(i) ((0x00250A40)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_RM(i) ((0x00250A44)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_SEL_RM(i) ((0x00250A48)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_RM(i) ((0x00250A4C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_SEL_RM(i) ((0x00250A50)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_RM(i) ((0x00250A54)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_SEL_RM(i) ((0x00250A58)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_RM(i) ((0x00250A5C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_RM(i) ((0x00250A60)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_RM(i) ((0x00250A64)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX_RM(i) ((0x00250A68)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINE_SEL_RM(i) ((0x00250A6C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINE_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_ELAPSED_RM(i) ((0x00250A70)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_ELAPSED_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC5CNT_RM(i) ((0x00250A74)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC5CNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CYCLECNT_RM(i) ((0x00250A78)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CYCLECNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC6CNT_RM(i) ((0x00250A7C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC6CNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENTCNT_RM(i) ((0x00250A80)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENTCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_DFD_CNT_UPPER_RM(i) ((0x00250A84)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_DFD_CNT_UPPER_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHCNT_RM(i) ((0x00250A88)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIGGERCNT_RM(i) ((0x00250A8C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLECNT_RM(i) ((0x00250A90)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLECNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHOLD_RM(i) ((0x00250A98)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHOLD_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_RM(i) ((0x00250A9C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RELEASE_RM(i) ((0x00250AA0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RELEASE_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT0_RM(i) ((0x00250AA4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT1_RM(i) ((0x00250AA8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT2_RM(i) ((0x00250AAC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT3_RM(i) ((0x00250AB0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT4_RM(i) ((0x00250AB4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT5_RM(i) ((0x00250AB8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT6_RM(i) ((0x00250ABC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT7_RM(i) ((0x00250AC0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWSMPLCNT_RM(i) ((0x00250AC4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWSMPLCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_RM(i) ((0x00250AC8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_RM(i) ((0x00250ACC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_RM(i) ((0x00250AD0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW2_RM(i) ((0x00250AD4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_RM(i) ((0x00250AD8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_RM(i) ((0x00250ADC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_STARTEXPERIMENT_RM(i) ((0x00250AE0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_STARTEXPERIMENT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_RM(i) ((0x00250AE4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_RM(i) ((0x00250AE8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_RM(i) ((0x00250AEC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_DEBUG_RM(i) ((0x00250AF8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_DAISY_DISABLE_RM(i) ((0x00250AFC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_DAISY_DISABLE_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_RM(i) ((0x00250B08)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_RM(i) ((0x00250B10)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLD_RM(i) ((0x00250B20)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLD_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_PERFMONID_RM(i) ((0x00250B28)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_PERFMONID_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW2_RM(i) ((0x00250B14)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW3_RM(i) ((0x00250B18)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW4_RM(i) ((0x00250B1C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TOTAL_TRIG_RCV_RM(i) ((0x00250B24)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_TOTAL_TRIG_RCV_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER_RM(i) ((0x00250B30)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CLAMP_CYA_CONTROL_RM(i) ((0x00250B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_FBPAS_CLAMP_CYA_CONTROL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT0_INPUTSEL_RM(i) ((0x00250C00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT0_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT1_INPUTSEL_RM(i) ((0x00250C04)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT1_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT2_INPUTSEL_RM(i) ((0x00250C08)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT2_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT3_INPUTSEL_RM(i) ((0x00250C0C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT3_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT4_INPUTSEL_RM(i) ((0x00250C10)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT4_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT5_INPUTSEL_RM(i) ((0x00250C14)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FT5_INPUTSEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_RM(i) ((0x00250C20)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_RM(i) ((0x00250C24)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_RM(i) ((0x00250C28)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_RM(i) ((0x00250C2C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_RM(i) ((0x00250C30)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_RM(i) ((0x00250C34)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_SEL_RM(i) ((0x00250C40)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_RM(i) ((0x00250C44)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_SEL_RM(i) ((0x00250C48)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_RM(i) ((0x00250C4C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_SEL_RM(i) ((0x00250C50)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_RM(i) ((0x00250C54)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_SEL_RM(i) ((0x00250C58)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_RM(i) ((0x00250C5C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_RM(i) ((0x00250C60)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_RM(i) ((0x00250C64)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX_RM(i) ((0x00250C68)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINE_SEL_RM(i) ((0x00250C6C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINE_SEL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_ELAPSED_RM(i) ((0x00250C70)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_ELAPSED_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC5CNT_RM(i) ((0x00250C74)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC5CNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CYCLECNT_RM(i) ((0x00250C78)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CYCLECNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC6CNT_RM(i) ((0x00250C7C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC6CNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_EVENTCNT_RM(i) ((0x00250C80)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_EVENTCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_DFD_CNT_UPPER_RM(i) ((0x00250C84)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_DFD_CNT_UPPER_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHCNT_RM(i) ((0x00250C88)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIGGERCNT_RM(i) ((0x00250C8C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLECNT_RM(i) ((0x00250C90)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLECNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHOLD_RM(i) ((0x00250C98)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHOLD_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_RM(i) ((0x00250C9C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RELEASE_RM(i) ((0x00250CA0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RELEASE_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT0_RM(i) ((0x00250CA4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT1_RM(i) ((0x00250CA8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT2_RM(i) ((0x00250CAC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT3_RM(i) ((0x00250CB0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT4_RM(i) ((0x00250CB4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT5_RM(i) ((0x00250CB8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT6_RM(i) ((0x00250CBC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT7_RM(i) ((0x00250CC0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWSMPLCNT_RM(i) ((0x00250CC4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_RAWSMPLCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_RM(i) ((0x00250CC8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_RM(i) ((0x00250CCC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_RM(i) ((0x00250CD0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW2_RM(i) ((0x00250CD4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_RM(i) ((0x00250CD8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_RM(i) ((0x00250CDC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_STARTEXPERIMENT_RM(i) ((0x00250CE0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_STARTEXPERIMENT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_RM(i) ((0x00250CE4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_RM(i) ((0x00250CE8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_RM(i) ((0x00250CEC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_DEBUG_RM(i) ((0x00250CF8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_DAISY_DISABLE_RM(i) ((0x00250CFC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_DAISY_DISABLE_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_RM(i) ((0x00250D08)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_RM(i) ((0x00250D10)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLD_RM(i) ((0x00250D20)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLD_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_PERFMONID_RM(i) ((0x00250D28)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_PERFMONID_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW2_RM(i) ((0x00250D14)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW3_RM(i) ((0x00250D18)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW4_RM(i) ((0x00250D1C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TOTAL_TRIG_RCV_RM(i) ((0x00250D24)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_TOTAL_TRIG_RCV_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER_RM(i) ((0x00250D30)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CLAMP_CYA_CONTROL_RM(i) ((0x00250D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPGS_LTCS_CLAMP_CYA_CONTROL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL_RM(i,j) (((0x0027C000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL_RM(i,j) (((0x0027C004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL_RM(i,j) (((0x0027C008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL_RM(i,j) (((0x0027C00C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL_RM(i,j) (((0x0027C010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL_RM(i,j) (((0x0027C014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR0_INC_RM(i,j) (((0x0027C020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CNTR0_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR0_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR1_INC_RM(i,j) (((0x0027C024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CNTR1_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR1_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR2_INC_RM(i,j) (((0x0027C028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CNTR2_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR2_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR3_INC_RM(i,j) (((0x0027C02C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CNTR3_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR3_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR4_INC_RM(i,j) (((0x0027C030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CNTR4_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR4_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR5_INC_RM(i,j) (((0x0027C034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CNTR5_INC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CNTR5_INC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIG0_SEL_RM(i,j) (((0x0027C040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_TRIG0_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIG0_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIG0_OP_RM(i,j) (((0x0027C044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_TRIG0_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIG0_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIG1_SEL_RM(i,j) (((0x0027C048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_TRIG1_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIG1_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIG1_OP_RM(i,j) (((0x0027C04C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_TRIG1_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIG1_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_EVENT_SEL_RM(i,j) (((0x0027C050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_EVENT_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_EVENT_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_EVENT_OP_RM(i,j) (((0x0027C054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_EVENT_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_EVENT_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL_RM(i,j) (((0x0027C058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_RM(i,j) (((0x0027C05C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_RM(i,j) (((0x0027C060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_RM(i,j) (((0x0027C064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_SELECTMUX_RM(i,j) (((0x0027C068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_SELECTMUX_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_SELECTMUX_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_ENGINE_SEL_RM(i,j) (((0x0027C06C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_ENGINE_SEL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_ENGINE_SEL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_ELAPSED_RM(i,j) (((0x0027C070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_ELAPSED_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_ELAPSED_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_MODEC5CNT_RM(i,j) (((0x0027C074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_MODEC5CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_MODEC5CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CYCLECNT_RM(i,j) (((0x0027C078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CYCLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CYCLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_MODEC6CNT_RM(i,j) (((0x0027C07C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_MODEC6CNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_MODEC6CNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_EVENTCNT_RM(i,j) (((0x0027C080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_EVENTCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_EVENTCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER_RM(i,j) (((0x0027C084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_THRESHCNT_RM(i,j) (((0x0027C088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_THRESHCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_THRESHCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIGGERCNT_RM(i,j) (((0x0027C08C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_TRIGGERCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_TRIGGERCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_SAMPLECNT_RM(i,j) (((0x0027C090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_SAMPLECNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_SAMPLECNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_THRESHOLD_RM(i,j) (((0x0027C098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_THRESHOLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_THRESHOLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CONTROL_RM(i,j) (((0x0027C09C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RELEASE_RM(i,j) (((0x0027C0A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RELEASE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RELEASE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT0_RM(i,j) (((0x0027C0A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWCNT0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT1_RM(i,j) (((0x0027C0A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWCNT1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT2_RM(i,j) (((0x0027C0AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWCNT2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT3_RM(i,j) (((0x0027C0B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWCNT3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT4_RM(i,j) (((0x0027C0B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWCNT4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT5_RM(i,j) (((0x0027C0B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWCNT5_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT5_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT6_RM(i,j) (((0x0027C0BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWCNT6_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT6_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT7_RM(i,j) (((0x0027C0C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWCNT7_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWCNT7_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWSMPLCNT_RM(i,j) (((0x0027C0C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_RAWSMPLCNT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_RAWSMPLCNT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_RM(i,j) (((0x0027C0C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW0_RM(i,j) (((0x0027C0CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_WBSKEW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW1_RM(i,j) (((0x0027C0D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_WBSKEW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW2_RM(i,j) (((0x0027C0D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_WBSKEW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_RM(i,j) (((0x0027C0D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_RM(i,j) (((0x0027C0DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_STARTEXPERIMENT_RM(i,j) (((0x0027C0E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_STARTEXPERIMENT_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_STARTEXPERIMENT_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW0_RM(i,j) (((0x0027C0E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CTXSW0_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW0_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW1_RM(i,j) (((0x0027C0E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CTXSW1_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW1_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_RM(i,j) (((0x0027C0EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_DEBUG_RM(i,j) (((0x0027C0F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_DEBUG_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_DEBUG_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_DAISY_DISABLE_RM(i,j) (((0x0027C0FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_DAISY_DISABLE_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_DAISY_DISABLE_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CONTROLB_RM(i,j) (((0x0027C108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CONTROLB_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CONTROLB_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CONTROLC_RM(i,j) (((0x0027C110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CONTROLC_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CONTROLC_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CONTROLD_RM(i,j) (((0x0027C120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CONTROLD_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CONTROLD_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_PERFMONID_RM(i,j) (((0x0027C128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_PERFMONID_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_PERFMONID_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW2_RM(i,j) (((0x0027C114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CTXSW2_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW2_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW3_RM(i,j) (((0x0027C118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CTXSW3_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW3_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW4_RM(i,j) (((0x0027C11C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CTXSW4_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CTXSW4_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_TOTAL_TRIG_RCV_RM(i,j) (((0x0027C124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_TOTAL_TRIG_RCV_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_TOTAL_TRIG_RCV_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_RM(i,j) (((0x0027C130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_RM(i) ((0x00251A00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_RECORD_GRANT_RM(i) ((0x00251A04)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_RECORD_GRANT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00251A08)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CTXSW0_RM(i) ((0x00251A0C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CTXSW0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_RM(i) ((0x00251A10)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_PERFMONSTATUS_RM(i) ((0x00251A14)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_PERFMONSTATUS_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_CG2_RM(i) ((0x00251A18)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_CG2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG_RM(i) ((0x00251A1C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_HS_RECORD_DEBUG_RM(i) ((0x00251B54)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_HS_RECORD_DEBUG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_RM(i) ((0x00251B50)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL_RM(i,j) (((0x0027C100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL_RM__SIZE_1 12 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL_RM__SIZE_2 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL11_RM(i) ((0x0027D700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL11_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL10_RM(i) ((0x0027D500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL10_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL9_RM(i) ((0x0027D300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL9_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL8_RM(i) ((0x0027D100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL8_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL7_RM(i) ((0x0027CF00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL7_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL6_RM(i) ((0x0027CD00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL6_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL5_RM(i) ((0x0027CB00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL5_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL4_RM(i) ((0x0027C900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL4_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL3_RM(i) ((0x0027C700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL3_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL2_RM(i) ((0x0027C500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL2_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL1_RM(i) ((0x0027C300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL1_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0_RM(i) ((0x0027C100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0_RM__SIZE_1 6 /*       */
#define NV_PERF_PMMGPC_FT0_INPUTSEL_RM(i,j) (((0x00180000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_FT1_INPUTSEL_RM(i,j) (((0x00180004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_FT2_INPUTSEL_RM(i,j) (((0x00180008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_FT3_INPUTSEL_RM(i,j) (((0x0018000C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_FT4_INPUTSEL_RM(i,j) (((0x00180010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_FT5_INPUTSEL_RM(i,j) (((0x00180014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CNTR0_INC_RM(i,j) (((0x00180020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CNTR1_INC_RM(i,j) (((0x00180024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CNTR2_INC_RM(i,j) (((0x00180028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CNTR3_INC_RM(i,j) (((0x0018002C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CNTR4_INC_RM(i,j) (((0x00180030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CNTR5_INC_RM(i,j) (((0x00180034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_TRIG0_SEL_RM(i,j) (((0x00180040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_TRIG0_OP_RM(i,j) (((0x00180044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_TRIG1_SEL_RM(i,j) (((0x00180048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_TRIG1_OP_RM(i,j) (((0x0018004C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_EVENT_SEL_RM(i,j) (((0x00180050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_EVENT_OP_RM(i,j) (((0x00180054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_SAMPLE_SEL_RM(i,j) (((0x00180058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_SAMPLE_OP_RM(i,j) (((0x0018005C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_SETFLAG_OP_RM(i,j) (((0x00180060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CLRFLAG_OP_RM(i,j) (((0x00180064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_SELECTMUX_RM(i,j) (((0x00180068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_ENGINE_SEL_RM(i,j) (((0x0018006C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_ELAPSED_RM(i,j) (((0x00180070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_MODEC5CNT_RM(i,j) (((0x00180074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CYCLECNT_RM(i,j) (((0x00180078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_MODEC6CNT_RM(i,j) (((0x0018007C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_EVENTCNT_RM(i,j) (((0x00180080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_DFD_CNT_UPPER_RM(i,j) (((0x00180084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_THRESHCNT_RM(i,j) (((0x00180088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_TRIGGERCNT_RM(i,j) (((0x0018008C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_SAMPLECNT_RM(i,j) (((0x00180090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_THRESHOLD_RM(i,j) (((0x00180098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CONTROL_RM(i,j) (((0x0018009C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RELEASE_RM(i,j) (((0x001800A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWCNT0_RM(i,j) (((0x001800A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWCNT1_RM(i,j) (((0x001800A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWCNT2_RM(i,j) (((0x001800AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWCNT3_RM(i,j) (((0x001800B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWCNT4_RM(i,j) (((0x001800B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWCNT5_RM(i,j) (((0x001800B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWCNT6_RM(i,j) (((0x001800BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWCNT7_RM(i,j) (((0x001800C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_RAWSMPLCNT_RM(i,j) (((0x001800C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_ENGINESTATUS_RM(i,j) (((0x001800C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_WBSKEW0_RM(i,j) (((0x001800CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_WBSKEW1_RM(i,j) (((0x001800D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_WBSKEW2_RM(i,j) (((0x001800D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_WBSKEW_CHAIN0_RM(i,j) (((0x001800D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_WBSKEW_CHAIN1_RM(i,j) (((0x001800DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_STARTEXPERIMENT_RM(i,j) (((0x001800E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CTXSW0_RM(i,j) (((0x001800E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CTXSW1_RM(i,j) (((0x001800E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_WATCHBUSDEBUG_RM(i,j) (((0x001800EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_DEBUG_RM(i,j) (((0x001800F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_DAISY_DISABLE_RM(i,j) (((0x001800FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CONTROLB_RM(i,j) (((0x00180108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CONTROLC_RM(i,j) (((0x00180110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CONTROLD_RM(i,j) (((0x00180120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_PERFMONID_RM(i,j) (((0x00180128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CTXSW2_RM(i,j) (((0x00180114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CTXSW3_RM(i,j) (((0x00180118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CTXSW4_RM(i,j) (((0x0018011C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_TOTAL_TRIG_RCV_RM(i,j) (((0x00180124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_FLAG_BIT_TIMER_RM(i,j) (((0x00180130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_RM(i) ((0x00244000)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_RECORD_GRANT_RM(i) ((0x00244004)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00244008)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024400C)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_ENGINESTATUS_RM(i) ((0x00244010)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_PERFMONSTATUS_RM(i) ((0x00244014)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_CG2_RM(i) ((0x00244018)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_RECORD_DEBUG_RM(i) ((0x0024401C)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_HS_RECORD_DEBUG_RM(i) ((0x00244154)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPCROUTER_HS_CONFIG_RM(i) ((0x00244150)+((i)*0x200)) /* RW-4A */
#define NV_PERF_PMMGPCROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL_RM(i,j) (((0x00180100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21_RM(i) ((0x00182B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20_RM(i) ((0x00182900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19_RM(i) ((0x00182700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18_RM(i) ((0x00182500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17_RM(i) ((0x00182300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16_RM(i) ((0x00182100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15_RM(i) ((0x00181F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14_RM(i) ((0x00181D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_RM(i) ((0x00181B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_RM(i) ((0x00181900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_RM(i) ((0x00181700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_RM(i) ((0x00181500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_RM(i) ((0x00181300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_RM(i) ((0x00181100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_RM(i) ((0x00180F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_RM(i) ((0x00180D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_RM(i) ((0x00180B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_RM(i) ((0x00180900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_RM(i) ((0x00180700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_RM(i) ((0x00180500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_RM(i) ((0x00180300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_RM(i) ((0x00180100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL_RM(i,j) (((0x00180000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL_RM(i,j) (((0x00180004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL_RM(i,j) (((0x00180008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL_RM(i,j) (((0x0018000C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL_RM(i,j) (((0x00180010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL_RM(i,j) (((0x00180014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR0_INC_RM(i,j) (((0x00180020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR1_INC_RM(i,j) (((0x00180024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR2_INC_RM(i,j) (((0x00180028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR3_INC_RM(i,j) (((0x0018002C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR4_INC_RM(i,j) (((0x00180030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR5_INC_RM(i,j) (((0x00180034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIG0_SEL_RM(i,j) (((0x00180040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIG0_OP_RM(i,j) (((0x00180044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIG1_SEL_RM(i,j) (((0x00180048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIG1_OP_RM(i,j) (((0x0018004C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_EVENT_SEL_RM(i,j) (((0x00180050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_EVENT_OP_RM(i,j) (((0x00180054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL_RM(i,j) (((0x00180058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_RM(i,j) (((0x0018005C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_RM(i,j) (((0x00180060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_RM(i,j) (((0x00180064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_SELECTMUX_RM(i,j) (((0x00180068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_ENGINE_SEL_RM(i,j) (((0x0018006C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_ELAPSED_RM(i,j) (((0x00180070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_MODEC5CNT_RM(i,j) (((0x00180074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CYCLECNT_RM(i,j) (((0x00180078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_MODEC6CNT_RM(i,j) (((0x0018007C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_EVENTCNT_RM(i,j) (((0x00180080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER_RM(i,j) (((0x00180084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_THRESHCNT_RM(i,j) (((0x00180088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIGGERCNT_RM(i,j) (((0x0018008C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_SAMPLECNT_RM(i,j) (((0x00180090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_THRESHOLD_RM(i,j) (((0x00180098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CONTROL_RM(i,j) (((0x0018009C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RELEASE_RM(i,j) (((0x001800A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT0_RM(i,j) (((0x001800A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT1_RM(i,j) (((0x001800A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT2_RM(i,j) (((0x001800AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT3_RM(i,j) (((0x001800B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT4_RM(i,j) (((0x001800B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT5_RM(i,j) (((0x001800B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT6_RM(i,j) (((0x001800BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT7_RM(i,j) (((0x001800C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWSMPLCNT_RM(i,j) (((0x001800C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_RM(i,j) (((0x001800C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW0_RM(i,j) (((0x001800CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW1_RM(i,j) (((0x001800D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW2_RM(i,j) (((0x001800D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_RM(i,j) (((0x001800D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_RM(i,j) (((0x001800DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_STARTEXPERIMENT_RM(i,j) (((0x001800E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW0_RM(i,j) (((0x001800E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW1_RM(i,j) (((0x001800E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_RM(i,j) (((0x001800EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_DEBUG_RM(i,j) (((0x001800F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_DAISY_DISABLE_RM(i,j) (((0x001800FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CONTROLB_RM(i,j) (((0x00180108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CONTROLC_RM(i,j) (((0x00180110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CONTROLD_RM(i,j) (((0x00180120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_PERFMONID_RM(i,j) (((0x00180128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW2_RM(i,j) (((0x00180114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW3_RM(i,j) (((0x00180118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW4_RM(i,j) (((0x0018011C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_TOTAL_TRIG_RCV_RM(i,j) (((0x00180124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_RM(i,j) (((0x00180130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_RM(i) ((0x00244000)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_GRANT_RM(i) ((0x00244004)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00244008)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024400C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_RM(i) ((0x00244010)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_PERFMONSTATUS_RM(i) ((0x00244014)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_CG2_RM(i) ((0x00244018)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG_RM(i) ((0x0024401C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00244154)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_RM(i) ((0x00244150)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL_RM(i,j) (((0x00180100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21_RM(i) ((0x00182B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20_RM(i) ((0x00182900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19_RM(i) ((0x00182700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18_RM(i) ((0x00182500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17_RM(i) ((0x00182300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16_RM(i) ((0x00182100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15_RM(i) ((0x00181F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14_RM(i) ((0x00181D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_RM(i) ((0x00181B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_RM(i) ((0x00181900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_RM(i) ((0x00181700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_RM(i) ((0x00181500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_RM(i) ((0x00181300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_RM(i) ((0x00181100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_RM(i) ((0x00180F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_RM(i) ((0x00180D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_RM(i) ((0x00180B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_RM(i) ((0x00180900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_RM(i) ((0x00180700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_RM(i) ((0x00180500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_RM(i) ((0x00180300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_RM(i) ((0x00180100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL_RM(i,j) (((0x00184000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL_RM(i,j) (((0x00184004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL_RM(i,j) (((0x00184008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL_RM(i,j) (((0x0018400C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL_RM(i,j) (((0x00184010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL_RM(i,j) (((0x00184014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR0_INC_RM(i,j) (((0x00184020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR1_INC_RM(i,j) (((0x00184024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR2_INC_RM(i,j) (((0x00184028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR3_INC_RM(i,j) (((0x0018402C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR4_INC_RM(i,j) (((0x00184030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR5_INC_RM(i,j) (((0x00184034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIG0_SEL_RM(i,j) (((0x00184040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIG0_OP_RM(i,j) (((0x00184044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIG1_SEL_RM(i,j) (((0x00184048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIG1_OP_RM(i,j) (((0x0018404C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_EVENT_SEL_RM(i,j) (((0x00184050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_EVENT_OP_RM(i,j) (((0x00184054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL_RM(i,j) (((0x00184058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_RM(i,j) (((0x0018405C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_RM(i,j) (((0x00184060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_RM(i,j) (((0x00184064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_SELECTMUX_RM(i,j) (((0x00184068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_ENGINE_SEL_RM(i,j) (((0x0018406C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_ELAPSED_RM(i,j) (((0x00184070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_MODEC5CNT_RM(i,j) (((0x00184074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CYCLECNT_RM(i,j) (((0x00184078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_MODEC6CNT_RM(i,j) (((0x0018407C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_EVENTCNT_RM(i,j) (((0x00184080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER_RM(i,j) (((0x00184084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_THRESHCNT_RM(i,j) (((0x00184088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIGGERCNT_RM(i,j) (((0x0018408C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_SAMPLECNT_RM(i,j) (((0x00184090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_THRESHOLD_RM(i,j) (((0x00184098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CONTROL_RM(i,j) (((0x0018409C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RELEASE_RM(i,j) (((0x001840A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT0_RM(i,j) (((0x001840A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT1_RM(i,j) (((0x001840A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT2_RM(i,j) (((0x001840AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT3_RM(i,j) (((0x001840B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT4_RM(i,j) (((0x001840B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT5_RM(i,j) (((0x001840B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT6_RM(i,j) (((0x001840BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT7_RM(i,j) (((0x001840C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWSMPLCNT_RM(i,j) (((0x001840C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_RM(i,j) (((0x001840C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW0_RM(i,j) (((0x001840CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW1_RM(i,j) (((0x001840D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW2_RM(i,j) (((0x001840D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_RM(i,j) (((0x001840D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_RM(i,j) (((0x001840DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_STARTEXPERIMENT_RM(i,j) (((0x001840E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW0_RM(i,j) (((0x001840E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW1_RM(i,j) (((0x001840E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_RM(i,j) (((0x001840EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_DEBUG_RM(i,j) (((0x001840F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_DAISY_DISABLE_RM(i,j) (((0x001840FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CONTROLB_RM(i,j) (((0x00184108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CONTROLC_RM(i,j) (((0x00184110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CONTROLD_RM(i,j) (((0x00184120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_PERFMONID_RM(i,j) (((0x00184128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW2_RM(i,j) (((0x00184114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW3_RM(i,j) (((0x00184118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW4_RM(i,j) (((0x0018411C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_TOTAL_TRIG_RCV_RM(i,j) (((0x00184124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_RM(i,j) (((0x00184130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_RM(i) ((0x00244200)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_GRANT_RM(i) ((0x00244204)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00244208)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024420C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_RM(i) ((0x00244210)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_PERFMONSTATUS_RM(i) ((0x00244214)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_CG2_RM(i) ((0x00244218)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG_RM(i) ((0x0024421C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00244354)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_RM(i) ((0x00244350)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL_RM(i,j) (((0x00184100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21_RM(i) ((0x00186B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20_RM(i) ((0x00186900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19_RM(i) ((0x00186700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18_RM(i) ((0x00186500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17_RM(i) ((0x00186300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16_RM(i) ((0x00186100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15_RM(i) ((0x00185F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14_RM(i) ((0x00185D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_RM(i) ((0x00185B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_RM(i) ((0x00185900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_RM(i) ((0x00185700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_RM(i) ((0x00185500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_RM(i) ((0x00185300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_RM(i) ((0x00185100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_RM(i) ((0x00184F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_RM(i) ((0x00184D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_RM(i) ((0x00184B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_RM(i) ((0x00184900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_RM(i) ((0x00184700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_RM(i) ((0x00184500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_RM(i) ((0x00184300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_RM(i) ((0x00184100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL_RM(i,j) (((0x00188000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL_RM(i,j) (((0x00188004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL_RM(i,j) (((0x00188008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL_RM(i,j) (((0x0018800C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL_RM(i,j) (((0x00188010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL_RM(i,j) (((0x00188014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR0_INC_RM(i,j) (((0x00188020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR1_INC_RM(i,j) (((0x00188024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR2_INC_RM(i,j) (((0x00188028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR3_INC_RM(i,j) (((0x0018802C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR4_INC_RM(i,j) (((0x00188030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR5_INC_RM(i,j) (((0x00188034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIG0_SEL_RM(i,j) (((0x00188040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIG0_OP_RM(i,j) (((0x00188044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIG1_SEL_RM(i,j) (((0x00188048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIG1_OP_RM(i,j) (((0x0018804C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_EVENT_SEL_RM(i,j) (((0x00188050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_EVENT_OP_RM(i,j) (((0x00188054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL_RM(i,j) (((0x00188058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_RM(i,j) (((0x0018805C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_RM(i,j) (((0x00188060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_RM(i,j) (((0x00188064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_SELECTMUX_RM(i,j) (((0x00188068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_ENGINE_SEL_RM(i,j) (((0x0018806C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_ELAPSED_RM(i,j) (((0x00188070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_MODEC5CNT_RM(i,j) (((0x00188074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CYCLECNT_RM(i,j) (((0x00188078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_MODEC6CNT_RM(i,j) (((0x0018807C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_EVENTCNT_RM(i,j) (((0x00188080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER_RM(i,j) (((0x00188084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_THRESHCNT_RM(i,j) (((0x00188088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIGGERCNT_RM(i,j) (((0x0018808C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_SAMPLECNT_RM(i,j) (((0x00188090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_THRESHOLD_RM(i,j) (((0x00188098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CONTROL_RM(i,j) (((0x0018809C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RELEASE_RM(i,j) (((0x001880A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT0_RM(i,j) (((0x001880A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT1_RM(i,j) (((0x001880A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT2_RM(i,j) (((0x001880AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT3_RM(i,j) (((0x001880B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT4_RM(i,j) (((0x001880B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT5_RM(i,j) (((0x001880B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT6_RM(i,j) (((0x001880BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT7_RM(i,j) (((0x001880C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWSMPLCNT_RM(i,j) (((0x001880C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_RM(i,j) (((0x001880C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW0_RM(i,j) (((0x001880CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW1_RM(i,j) (((0x001880D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW2_RM(i,j) (((0x001880D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_RM(i,j) (((0x001880D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_RM(i,j) (((0x001880DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_STARTEXPERIMENT_RM(i,j) (((0x001880E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW0_RM(i,j) (((0x001880E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW1_RM(i,j) (((0x001880E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_RM(i,j) (((0x001880EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_DEBUG_RM(i,j) (((0x001880F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_DAISY_DISABLE_RM(i,j) (((0x001880FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CONTROLB_RM(i,j) (((0x00188108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CONTROLC_RM(i,j) (((0x00188110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CONTROLD_RM(i,j) (((0x00188120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_PERFMONID_RM(i,j) (((0x00188128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW2_RM(i,j) (((0x00188114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW3_RM(i,j) (((0x00188118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW4_RM(i,j) (((0x0018811C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_TOTAL_TRIG_RCV_RM(i,j) (((0x00188124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_RM(i,j) (((0x00188130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_RM(i) ((0x00244400)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_GRANT_RM(i) ((0x00244404)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00244408)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024440C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_RM(i) ((0x00244410)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_PERFMONSTATUS_RM(i) ((0x00244414)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_CG2_RM(i) ((0x00244418)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG_RM(i) ((0x0024441C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00244554)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_RM(i) ((0x00244550)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL_RM(i,j) (((0x00188100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21_RM(i) ((0x0018AB00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20_RM(i) ((0x0018A900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19_RM(i) ((0x0018A700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18_RM(i) ((0x0018A500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17_RM(i) ((0x0018A300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16_RM(i) ((0x0018A100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15_RM(i) ((0x00189F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14_RM(i) ((0x00189D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_RM(i) ((0x00189B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_RM(i) ((0x00189900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_RM(i) ((0x00189700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_RM(i) ((0x00189500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_RM(i) ((0x00189300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_RM(i) ((0x00189100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_RM(i) ((0x00188F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_RM(i) ((0x00188D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_RM(i) ((0x00188B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_RM(i) ((0x00188900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_RM(i) ((0x00188700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_RM(i) ((0x00188500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_RM(i) ((0x00188300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_RM(i) ((0x00188100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL_RM(i,j) (((0x0018C000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL_RM(i,j) (((0x0018C004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL_RM(i,j) (((0x0018C008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL_RM(i,j) (((0x0018C00C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL_RM(i,j) (((0x0018C010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL_RM(i,j) (((0x0018C014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR0_INC_RM(i,j) (((0x0018C020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR1_INC_RM(i,j) (((0x0018C024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR2_INC_RM(i,j) (((0x0018C028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR3_INC_RM(i,j) (((0x0018C02C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR4_INC_RM(i,j) (((0x0018C030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR5_INC_RM(i,j) (((0x0018C034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIG0_SEL_RM(i,j) (((0x0018C040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIG0_OP_RM(i,j) (((0x0018C044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIG1_SEL_RM(i,j) (((0x0018C048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIG1_OP_RM(i,j) (((0x0018C04C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_EVENT_SEL_RM(i,j) (((0x0018C050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_EVENT_OP_RM(i,j) (((0x0018C054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL_RM(i,j) (((0x0018C058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_RM(i,j) (((0x0018C05C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_RM(i,j) (((0x0018C060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_RM(i,j) (((0x0018C064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_SELECTMUX_RM(i,j) (((0x0018C068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_ENGINE_SEL_RM(i,j) (((0x0018C06C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_ELAPSED_RM(i,j) (((0x0018C070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_MODEC5CNT_RM(i,j) (((0x0018C074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CYCLECNT_RM(i,j) (((0x0018C078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_MODEC6CNT_RM(i,j) (((0x0018C07C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_EVENTCNT_RM(i,j) (((0x0018C080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER_RM(i,j) (((0x0018C084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_THRESHCNT_RM(i,j) (((0x0018C088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIGGERCNT_RM(i,j) (((0x0018C08C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_SAMPLECNT_RM(i,j) (((0x0018C090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_THRESHOLD_RM(i,j) (((0x0018C098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CONTROL_RM(i,j) (((0x0018C09C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RELEASE_RM(i,j) (((0x0018C0A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT0_RM(i,j) (((0x0018C0A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT1_RM(i,j) (((0x0018C0A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT2_RM(i,j) (((0x0018C0AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT3_RM(i,j) (((0x0018C0B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT4_RM(i,j) (((0x0018C0B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT5_RM(i,j) (((0x0018C0B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT6_RM(i,j) (((0x0018C0BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT7_RM(i,j) (((0x0018C0C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWSMPLCNT_RM(i,j) (((0x0018C0C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_RM(i,j) (((0x0018C0C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW0_RM(i,j) (((0x0018C0CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW1_RM(i,j) (((0x0018C0D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW2_RM(i,j) (((0x0018C0D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_RM(i,j) (((0x0018C0D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_RM(i,j) (((0x0018C0DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_STARTEXPERIMENT_RM(i,j) (((0x0018C0E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW0_RM(i,j) (((0x0018C0E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW1_RM(i,j) (((0x0018C0E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_RM(i,j) (((0x0018C0EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_DEBUG_RM(i,j) (((0x0018C0F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_DAISY_DISABLE_RM(i,j) (((0x0018C0FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CONTROLB_RM(i,j) (((0x0018C108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CONTROLC_RM(i,j) (((0x0018C110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CONTROLD_RM(i,j) (((0x0018C120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_PERFMONID_RM(i,j) (((0x0018C128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW2_RM(i,j) (((0x0018C114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW3_RM(i,j) (((0x0018C118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW4_RM(i,j) (((0x0018C11C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_TOTAL_TRIG_RCV_RM(i,j) (((0x0018C124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_RM(i,j) (((0x0018C130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_RM(i) ((0x00244600)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_GRANT_RM(i) ((0x00244604)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00244608)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024460C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_RM(i) ((0x00244610)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_PERFMONSTATUS_RM(i) ((0x00244614)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_CG2_RM(i) ((0x00244618)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG_RM(i) ((0x0024461C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00244754)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_RM(i) ((0x00244750)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL_RM(i,j) (((0x0018C100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21_RM(i) ((0x0018EB00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20_RM(i) ((0x0018E900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19_RM(i) ((0x0018E700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18_RM(i) ((0x0018E500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17_RM(i) ((0x0018E300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16_RM(i) ((0x0018E100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15_RM(i) ((0x0018DF00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14_RM(i) ((0x0018DD00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_RM(i) ((0x0018DB00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_RM(i) ((0x0018D900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_RM(i) ((0x0018D700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_RM(i) ((0x0018D500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_RM(i) ((0x0018D300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_RM(i) ((0x0018D100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_RM(i) ((0x0018CF00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_RM(i) ((0x0018CD00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_RM(i) ((0x0018CB00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_RM(i) ((0x0018C900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_RM(i) ((0x0018C700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_RM(i) ((0x0018C500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_RM(i) ((0x0018C300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_RM(i) ((0x0018C100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL_RM(i,j) (((0x00190000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL_RM(i,j) (((0x00190004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL_RM(i,j) (((0x00190008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL_RM(i,j) (((0x0019000C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL_RM(i,j) (((0x00190010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL_RM(i,j) (((0x00190014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR0_INC_RM(i,j) (((0x00190020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR1_INC_RM(i,j) (((0x00190024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR2_INC_RM(i,j) (((0x00190028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR3_INC_RM(i,j) (((0x0019002C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR4_INC_RM(i,j) (((0x00190030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR5_INC_RM(i,j) (((0x00190034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIG0_SEL_RM(i,j) (((0x00190040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIG0_OP_RM(i,j) (((0x00190044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIG1_SEL_RM(i,j) (((0x00190048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIG1_OP_RM(i,j) (((0x0019004C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_EVENT_SEL_RM(i,j) (((0x00190050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_EVENT_OP_RM(i,j) (((0x00190054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL_RM(i,j) (((0x00190058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_RM(i,j) (((0x0019005C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_RM(i,j) (((0x00190060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_RM(i,j) (((0x00190064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_SELECTMUX_RM(i,j) (((0x00190068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_ENGINE_SEL_RM(i,j) (((0x0019006C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_ELAPSED_RM(i,j) (((0x00190070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_MODEC5CNT_RM(i,j) (((0x00190074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CYCLECNT_RM(i,j) (((0x00190078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_MODEC6CNT_RM(i,j) (((0x0019007C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_EVENTCNT_RM(i,j) (((0x00190080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER_RM(i,j) (((0x00190084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_THRESHCNT_RM(i,j) (((0x00190088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIGGERCNT_RM(i,j) (((0x0019008C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_SAMPLECNT_RM(i,j) (((0x00190090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_THRESHOLD_RM(i,j) (((0x00190098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CONTROL_RM(i,j) (((0x0019009C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RELEASE_RM(i,j) (((0x001900A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT0_RM(i,j) (((0x001900A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT1_RM(i,j) (((0x001900A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT2_RM(i,j) (((0x001900AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT3_RM(i,j) (((0x001900B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT4_RM(i,j) (((0x001900B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT5_RM(i,j) (((0x001900B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT6_RM(i,j) (((0x001900BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT7_RM(i,j) (((0x001900C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWSMPLCNT_RM(i,j) (((0x001900C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_RM(i,j) (((0x001900C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW0_RM(i,j) (((0x001900CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW1_RM(i,j) (((0x001900D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW2_RM(i,j) (((0x001900D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_RM(i,j) (((0x001900D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_RM(i,j) (((0x001900DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_STARTEXPERIMENT_RM(i,j) (((0x001900E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW0_RM(i,j) (((0x001900E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW1_RM(i,j) (((0x001900E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_RM(i,j) (((0x001900EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_DEBUG_RM(i,j) (((0x001900F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_DAISY_DISABLE_RM(i,j) (((0x001900FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CONTROLB_RM(i,j) (((0x00190108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CONTROLC_RM(i,j) (((0x00190110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CONTROLD_RM(i,j) (((0x00190120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_PERFMONID_RM(i,j) (((0x00190128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW2_RM(i,j) (((0x00190114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW3_RM(i,j) (((0x00190118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW4_RM(i,j) (((0x0019011C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_TOTAL_TRIG_RCV_RM(i,j) (((0x00190124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_RM(i,j) (((0x00190130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_RM(i) ((0x00244800)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_GRANT_RM(i) ((0x00244804)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00244808)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CTXSW0_RM(i) ((0x0024480C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_RM(i) ((0x00244810)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_PERFMONSTATUS_RM(i) ((0x00244814)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_CG2_RM(i) ((0x00244818)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG_RM(i) ((0x0024481C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00244954)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_RM(i) ((0x00244950)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL_RM(i,j) (((0x00190100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21_RM(i) ((0x00192B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20_RM(i) ((0x00192900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19_RM(i) ((0x00192700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18_RM(i) ((0x00192500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17_RM(i) ((0x00192300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16_RM(i) ((0x00192100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15_RM(i) ((0x00191F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14_RM(i) ((0x00191D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_RM(i) ((0x00191B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_RM(i) ((0x00191900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_RM(i) ((0x00191700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_RM(i) ((0x00191500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_RM(i) ((0x00191300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_RM(i) ((0x00191100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_RM(i) ((0x00190F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_RM(i) ((0x00190D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_RM(i) ((0x00190B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_RM(i) ((0x00190900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_RM(i) ((0x00190700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_RM(i) ((0x00190500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_RM(i) ((0x00190300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_RM(i) ((0x00190100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL_RM(i,j) (((0x00194000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL_RM(i,j) (((0x00194004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL_RM(i,j) (((0x00194008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL_RM(i,j) (((0x0019400C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL_RM(i,j) (((0x00194010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL_RM(i,j) (((0x00194014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR0_INC_RM(i,j) (((0x00194020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR1_INC_RM(i,j) (((0x00194024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR2_INC_RM(i,j) (((0x00194028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR3_INC_RM(i,j) (((0x0019402C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR4_INC_RM(i,j) (((0x00194030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR5_INC_RM(i,j) (((0x00194034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIG0_SEL_RM(i,j) (((0x00194040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIG0_OP_RM(i,j) (((0x00194044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIG1_SEL_RM(i,j) (((0x00194048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIG1_OP_RM(i,j) (((0x0019404C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_EVENT_SEL_RM(i,j) (((0x00194050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_EVENT_OP_RM(i,j) (((0x00194054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL_RM(i,j) (((0x00194058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_RM(i,j) (((0x0019405C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_RM(i,j) (((0x00194060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_RM(i,j) (((0x00194064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_SELECTMUX_RM(i,j) (((0x00194068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_ENGINE_SEL_RM(i,j) (((0x0019406C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_ELAPSED_RM(i,j) (((0x00194070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_MODEC5CNT_RM(i,j) (((0x00194074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CYCLECNT_RM(i,j) (((0x00194078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_MODEC6CNT_RM(i,j) (((0x0019407C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_EVENTCNT_RM(i,j) (((0x00194080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER_RM(i,j) (((0x00194084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_THRESHCNT_RM(i,j) (((0x00194088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIGGERCNT_RM(i,j) (((0x0019408C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_SAMPLECNT_RM(i,j) (((0x00194090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_THRESHOLD_RM(i,j) (((0x00194098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CONTROL_RM(i,j) (((0x0019409C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RELEASE_RM(i,j) (((0x001940A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT0_RM(i,j) (((0x001940A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT1_RM(i,j) (((0x001940A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT2_RM(i,j) (((0x001940AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT3_RM(i,j) (((0x001940B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT4_RM(i,j) (((0x001940B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT5_RM(i,j) (((0x001940B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT6_RM(i,j) (((0x001940BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT7_RM(i,j) (((0x001940C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWSMPLCNT_RM(i,j) (((0x001940C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_RM(i,j) (((0x001940C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW0_RM(i,j) (((0x001940CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW1_RM(i,j) (((0x001940D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW2_RM(i,j) (((0x001940D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_RM(i,j) (((0x001940D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_RM(i,j) (((0x001940DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_STARTEXPERIMENT_RM(i,j) (((0x001940E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW0_RM(i,j) (((0x001940E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW1_RM(i,j) (((0x001940E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_RM(i,j) (((0x001940EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_DEBUG_RM(i,j) (((0x001940F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_DAISY_DISABLE_RM(i,j) (((0x001940FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CONTROLB_RM(i,j) (((0x00194108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CONTROLC_RM(i,j) (((0x00194110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CONTROLD_RM(i,j) (((0x00194120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_PERFMONID_RM(i,j) (((0x00194128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW2_RM(i,j) (((0x00194114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW3_RM(i,j) (((0x00194118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW4_RM(i,j) (((0x0019411C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_TOTAL_TRIG_RCV_RM(i,j) (((0x00194124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_RM(i,j) (((0x00194130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_RM(i) ((0x00244A00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_GRANT_RM(i) ((0x00244A04)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00244A08)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CTXSW0_RM(i) ((0x00244A0C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_RM(i) ((0x00244A10)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_PERFMONSTATUS_RM(i) ((0x00244A14)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_CG2_RM(i) ((0x00244A18)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG_RM(i) ((0x00244A1C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00244B54)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_RM(i) ((0x00244B50)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL_RM(i,j) (((0x00194100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21_RM(i) ((0x00196B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20_RM(i) ((0x00196900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19_RM(i) ((0x00196700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18_RM(i) ((0x00196500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17_RM(i) ((0x00196300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16_RM(i) ((0x00196100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15_RM(i) ((0x00195F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14_RM(i) ((0x00195D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_RM(i) ((0x00195B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_RM(i) ((0x00195900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_RM(i) ((0x00195700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_RM(i) ((0x00195500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_RM(i) ((0x00195300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_RM(i) ((0x00195100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_RM(i) ((0x00194F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_RM(i) ((0x00194D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_RM(i) ((0x00194B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_RM(i) ((0x00194900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_RM(i) ((0x00194700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_RM(i) ((0x00194500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_RM(i) ((0x00194300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_RM(i) ((0x00194100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL_RM(i,j) (((0x00198000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL_RM(i,j) (((0x00198004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL_RM(i,j) (((0x00198008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL_RM(i,j) (((0x0019800C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL_RM(i,j) (((0x00198010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL_RM(i,j) (((0x00198014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR0_INC_RM(i,j) (((0x00198020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR1_INC_RM(i,j) (((0x00198024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR2_INC_RM(i,j) (((0x00198028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR3_INC_RM(i,j) (((0x0019802C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR4_INC_RM(i,j) (((0x00198030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR5_INC_RM(i,j) (((0x00198034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIG0_SEL_RM(i,j) (((0x00198040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIG0_OP_RM(i,j) (((0x00198044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIG1_SEL_RM(i,j) (((0x00198048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIG1_OP_RM(i,j) (((0x0019804C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_EVENT_SEL_RM(i,j) (((0x00198050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_EVENT_OP_RM(i,j) (((0x00198054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL_RM(i,j) (((0x00198058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_RM(i,j) (((0x0019805C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_RM(i,j) (((0x00198060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_RM(i,j) (((0x00198064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_SELECTMUX_RM(i,j) (((0x00198068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_ENGINE_SEL_RM(i,j) (((0x0019806C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_ELAPSED_RM(i,j) (((0x00198070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_MODEC5CNT_RM(i,j) (((0x00198074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CYCLECNT_RM(i,j) (((0x00198078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_MODEC6CNT_RM(i,j) (((0x0019807C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_EVENTCNT_RM(i,j) (((0x00198080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER_RM(i,j) (((0x00198084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_THRESHCNT_RM(i,j) (((0x00198088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIGGERCNT_RM(i,j) (((0x0019808C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_SAMPLECNT_RM(i,j) (((0x00198090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_THRESHOLD_RM(i,j) (((0x00198098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CONTROL_RM(i,j) (((0x0019809C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RELEASE_RM(i,j) (((0x001980A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT0_RM(i,j) (((0x001980A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT1_RM(i,j) (((0x001980A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT2_RM(i,j) (((0x001980AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT3_RM(i,j) (((0x001980B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT4_RM(i,j) (((0x001980B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT5_RM(i,j) (((0x001980B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT6_RM(i,j) (((0x001980BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT7_RM(i,j) (((0x001980C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWSMPLCNT_RM(i,j) (((0x001980C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_RM(i,j) (((0x001980C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW0_RM(i,j) (((0x001980CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW1_RM(i,j) (((0x001980D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW2_RM(i,j) (((0x001980D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_RM(i,j) (((0x001980D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_RM(i,j) (((0x001980DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_STARTEXPERIMENT_RM(i,j) (((0x001980E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW0_RM(i,j) (((0x001980E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW1_RM(i,j) (((0x001980E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_RM(i,j) (((0x001980EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_DEBUG_RM(i,j) (((0x001980F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_DAISY_DISABLE_RM(i,j) (((0x001980FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CONTROLB_RM(i,j) (((0x00198108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CONTROLC_RM(i,j) (((0x00198110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CONTROLD_RM(i,j) (((0x00198120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_PERFMONID_RM(i,j) (((0x00198128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW2_RM(i,j) (((0x00198114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW3_RM(i,j) (((0x00198118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW4_RM(i,j) (((0x0019811C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_TOTAL_TRIG_RCV_RM(i,j) (((0x00198124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_RM(i,j) (((0x00198130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_RM(i) ((0x00244C00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_GRANT_RM(i) ((0x00244C04)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00244C08)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CTXSW0_RM(i) ((0x00244C0C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_RM(i) ((0x00244C10)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_PERFMONSTATUS_RM(i) ((0x00244C14)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_CG2_RM(i) ((0x00244C18)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG_RM(i) ((0x00244C1C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_HS_RECORD_DEBUG_RM(i) ((0x00244D54)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_RM(i) ((0x00244D50)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL_RM(i,j) (((0x00198100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21_RM(i) ((0x0019AB00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20_RM(i) ((0x0019A900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19_RM(i) ((0x0019A700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18_RM(i) ((0x0019A500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17_RM(i) ((0x0019A300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16_RM(i) ((0x0019A100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15_RM(i) ((0x00199F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14_RM(i) ((0x00199D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_RM(i) ((0x00199B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_RM(i) ((0x00199900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_RM(i) ((0x00199700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_RM(i) ((0x00199500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_RM(i) ((0x00199300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_RM(i) ((0x00199100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_RM(i) ((0x00198F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_RM(i) ((0x00198D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_RM(i) ((0x00198B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_RM(i) ((0x00198900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_RM(i) ((0x00198700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_RM(i) ((0x00198500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_RM(i) ((0x00198300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_RM(i) ((0x00198100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT0_INPUTSEL_RM(i) ((0x00250000)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT0_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT1_INPUTSEL_RM(i) ((0x00250004)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT1_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT2_INPUTSEL_RM(i) ((0x00250008)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT2_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT3_INPUTSEL_RM(i) ((0x0025000C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT3_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT4_INPUTSEL_RM(i) ((0x00250010)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT4_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT5_INPUTSEL_RM(i) ((0x00250014)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT5_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_RM(i) ((0x00250020)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_RM(i) ((0x00250024)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_RM(i) ((0x00250028)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_RM(i) ((0x0025002C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_RM(i) ((0x00250030)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_RM(i) ((0x00250034)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_SEL_RM(i) ((0x00250040)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_RM(i) ((0x00250044)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_SEL_RM(i) ((0x00250048)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_RM(i) ((0x0025004C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_SEL_RM(i) ((0x00250050)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_RM(i) ((0x00250054)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_SEL_RM(i) ((0x00250058)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_RM(i) ((0x0025005C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_RM(i) ((0x00250060)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_RM(i) ((0x00250064)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX_RM(i) ((0x00250068)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINE_SEL_RM(i) ((0x0025006C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINE_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ELAPSED_RM(i) ((0x00250070)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ELAPSED_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC5CNT_RM(i) ((0x00250074)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC5CNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CYCLECNT_RM(i) ((0x00250078)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CYCLECNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC6CNT_RM(i) ((0x0025007C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC6CNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENTCNT_RM(i) ((0x00250080)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENTCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DFD_CNT_UPPER_RM(i) ((0x00250084)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DFD_CNT_UPPER_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHCNT_RM(i) ((0x00250088)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIGGERCNT_RM(i) ((0x0025008C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLECNT_RM(i) ((0x00250090)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLECNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHOLD_RM(i) ((0x00250098)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHOLD_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_RM(i) ((0x0025009C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RELEASE_RM(i) ((0x002500A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RELEASE_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT0_RM(i) ((0x002500A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT1_RM(i) ((0x002500A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT2_RM(i) ((0x002500AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT3_RM(i) ((0x002500B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT4_RM(i) ((0x002500B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT5_RM(i) ((0x002500B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT6_RM(i) ((0x002500BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT7_RM(i) ((0x002500C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWSMPLCNT_RM(i) ((0x002500C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWSMPLCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_RM(i) ((0x002500C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_RM(i) ((0x002500CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_RM(i) ((0x002500D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW2_RM(i) ((0x002500D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_RM(i) ((0x002500D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_RM(i) ((0x002500DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_STARTEXPERIMENT_RM(i) ((0x002500E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_STARTEXPERIMENT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_RM(i) ((0x002500E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_RM(i) ((0x002500E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_RM(i) ((0x002500EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DEBUG_RM(i) ((0x002500F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DAISY_DISABLE_RM(i) ((0x002500FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DAISY_DISABLE_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_RM(i) ((0x00250108)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_RM(i) ((0x00250110)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLD_RM(i) ((0x00250120)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLD_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_PERFMONID_RM(i) ((0x00250128)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_PERFMONID_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW2_RM(i) ((0x00250114)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW3_RM(i) ((0x00250118)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW4_RM(i) ((0x0025011C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TOTAL_TRIG_RCV_RM(i) ((0x00250124)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TOTAL_TRIG_RCV_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER_RM(i) ((0x00250130)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLAMP_CYA_CONTROL_RM(i) ((0x00250100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLAMP_CYA_CONTROL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT0_INPUTSEL_RM(i) ((0x00250200)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT0_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT1_INPUTSEL_RM(i) ((0x00250204)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT1_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT2_INPUTSEL_RM(i) ((0x00250208)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT2_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT3_INPUTSEL_RM(i) ((0x0025020C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT3_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT4_INPUTSEL_RM(i) ((0x00250210)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT4_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT5_INPUTSEL_RM(i) ((0x00250214)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT5_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_RM(i) ((0x00250220)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_RM(i) ((0x00250224)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_RM(i) ((0x00250228)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_RM(i) ((0x0025022C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_RM(i) ((0x00250230)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_RM(i) ((0x00250234)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_SEL_RM(i) ((0x00250240)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_RM(i) ((0x00250244)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_SEL_RM(i) ((0x00250248)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_RM(i) ((0x0025024C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_SEL_RM(i) ((0x00250250)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_RM(i) ((0x00250254)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_SEL_RM(i) ((0x00250258)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_RM(i) ((0x0025025C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_RM(i) ((0x00250260)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_RM(i) ((0x00250264)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX_RM(i) ((0x00250268)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINE_SEL_RM(i) ((0x0025026C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINE_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ELAPSED_RM(i) ((0x00250270)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ELAPSED_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC5CNT_RM(i) ((0x00250274)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC5CNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CYCLECNT_RM(i) ((0x00250278)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CYCLECNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC6CNT_RM(i) ((0x0025027C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC6CNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENTCNT_RM(i) ((0x00250280)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENTCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DFD_CNT_UPPER_RM(i) ((0x00250284)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DFD_CNT_UPPER_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHCNT_RM(i) ((0x00250288)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIGGERCNT_RM(i) ((0x0025028C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLECNT_RM(i) ((0x00250290)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLECNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHOLD_RM(i) ((0x00250298)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHOLD_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_RM(i) ((0x0025029C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RELEASE_RM(i) ((0x002502A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RELEASE_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT0_RM(i) ((0x002502A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT1_RM(i) ((0x002502A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT2_RM(i) ((0x002502AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT3_RM(i) ((0x002502B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT4_RM(i) ((0x002502B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT5_RM(i) ((0x002502B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT6_RM(i) ((0x002502BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT7_RM(i) ((0x002502C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWSMPLCNT_RM(i) ((0x002502C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWSMPLCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_RM(i) ((0x002502C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_RM(i) ((0x002502CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_RM(i) ((0x002502D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW2_RM(i) ((0x002502D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_RM(i) ((0x002502D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_RM(i) ((0x002502DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_STARTEXPERIMENT_RM(i) ((0x002502E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_STARTEXPERIMENT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_RM(i) ((0x002502E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_RM(i) ((0x002502E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_RM(i) ((0x002502EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DEBUG_RM(i) ((0x002502F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DAISY_DISABLE_RM(i) ((0x002502FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DAISY_DISABLE_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_RM(i) ((0x00250308)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_RM(i) ((0x00250310)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLD_RM(i) ((0x00250320)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLD_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_PERFMONID_RM(i) ((0x00250328)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_PERFMONID_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW2_RM(i) ((0x00250314)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW3_RM(i) ((0x00250318)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW4_RM(i) ((0x0025031C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TOTAL_TRIG_RCV_RM(i) ((0x00250324)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TOTAL_TRIG_RCV_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER_RM(i) ((0x00250330)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLAMP_CYA_CONTROL_RM(i) ((0x00250300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLAMP_CYA_CONTROL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT0_INPUTSEL_RM(i) ((0x00250400)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT0_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT1_INPUTSEL_RM(i) ((0x00250404)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT1_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT2_INPUTSEL_RM(i) ((0x00250408)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT2_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT3_INPUTSEL_RM(i) ((0x0025040C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT3_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT4_INPUTSEL_RM(i) ((0x00250410)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT4_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT5_INPUTSEL_RM(i) ((0x00250414)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT5_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_RM(i) ((0x00250420)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_RM(i) ((0x00250424)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_RM(i) ((0x00250428)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_RM(i) ((0x0025042C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_RM(i) ((0x00250430)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_RM(i) ((0x00250434)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_SEL_RM(i) ((0x00250440)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_RM(i) ((0x00250444)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_SEL_RM(i) ((0x00250448)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_RM(i) ((0x0025044C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_SEL_RM(i) ((0x00250450)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_RM(i) ((0x00250454)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_SEL_RM(i) ((0x00250458)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_RM(i) ((0x0025045C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_RM(i) ((0x00250460)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_RM(i) ((0x00250464)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX_RM(i) ((0x00250468)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINE_SEL_RM(i) ((0x0025046C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINE_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ELAPSED_RM(i) ((0x00250470)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ELAPSED_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC5CNT_RM(i) ((0x00250474)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC5CNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CYCLECNT_RM(i) ((0x00250478)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CYCLECNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC6CNT_RM(i) ((0x0025047C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC6CNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENTCNT_RM(i) ((0x00250480)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENTCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DFD_CNT_UPPER_RM(i) ((0x00250484)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DFD_CNT_UPPER_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHCNT_RM(i) ((0x00250488)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIGGERCNT_RM(i) ((0x0025048C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLECNT_RM(i) ((0x00250490)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLECNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHOLD_RM(i) ((0x00250498)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHOLD_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_RM(i) ((0x0025049C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RELEASE_RM(i) ((0x002504A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RELEASE_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT0_RM(i) ((0x002504A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT1_RM(i) ((0x002504A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT2_RM(i) ((0x002504AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT3_RM(i) ((0x002504B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT4_RM(i) ((0x002504B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT5_RM(i) ((0x002504B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT6_RM(i) ((0x002504BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT7_RM(i) ((0x002504C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWSMPLCNT_RM(i) ((0x002504C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWSMPLCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_RM(i) ((0x002504C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_RM(i) ((0x002504CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_RM(i) ((0x002504D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW2_RM(i) ((0x002504D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_RM(i) ((0x002504D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_RM(i) ((0x002504DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_STARTEXPERIMENT_RM(i) ((0x002504E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_STARTEXPERIMENT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_RM(i) ((0x002504E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_RM(i) ((0x002504E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_RM(i) ((0x002504EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DEBUG_RM(i) ((0x002504F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DAISY_DISABLE_RM(i) ((0x002504FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DAISY_DISABLE_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_RM(i) ((0x00250508)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_RM(i) ((0x00250510)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLD_RM(i) ((0x00250520)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLD_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_PERFMONID_RM(i) ((0x00250528)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_PERFMONID_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW2_RM(i) ((0x00250514)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW3_RM(i) ((0x00250518)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW4_RM(i) ((0x0025051C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TOTAL_TRIG_RCV_RM(i) ((0x00250524)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TOTAL_TRIG_RCV_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER_RM(i) ((0x00250530)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLAMP_CYA_CONTROL_RM(i) ((0x00250500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLAMP_CYA_CONTROL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT0_INPUTSEL_RM(i) ((0x00250600)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT0_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT1_INPUTSEL_RM(i) ((0x00250604)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT1_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT2_INPUTSEL_RM(i) ((0x00250608)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT2_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT3_INPUTSEL_RM(i) ((0x0025060C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT3_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT4_INPUTSEL_RM(i) ((0x00250610)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT4_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT5_INPUTSEL_RM(i) ((0x00250614)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_FT5_INPUTSEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_RM(i) ((0x00250620)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_RM(i) ((0x00250624)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_RM(i) ((0x00250628)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_RM(i) ((0x0025062C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_RM(i) ((0x00250630)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_RM(i) ((0x00250634)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_SEL_RM(i) ((0x00250640)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_RM(i) ((0x00250644)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_SEL_RM(i) ((0x00250648)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_RM(i) ((0x0025064C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_SEL_RM(i) ((0x00250650)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_RM(i) ((0x00250654)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_SEL_RM(i) ((0x00250658)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_RM(i) ((0x0025065C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_RM(i) ((0x00250660)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_RM(i) ((0x00250664)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX_RM(i) ((0x00250668)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_ENGINE_SEL_RM(i) ((0x0025066C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_ENGINE_SEL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_ELAPSED_RM(i) ((0x00250670)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_ELAPSED_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_MODEC5CNT_RM(i) ((0x00250674)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_MODEC5CNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CYCLECNT_RM(i) ((0x00250678)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CYCLECNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_MODEC6CNT_RM(i) ((0x0025067C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_MODEC6CNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_EVENTCNT_RM(i) ((0x00250680)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_EVENTCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_DFD_CNT_UPPER_RM(i) ((0x00250684)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_DFD_CNT_UPPER_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_THRESHCNT_RM(i) ((0x00250688)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_THRESHCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIGGERCNT_RM(i) ((0x0025068C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_TRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLECNT_RM(i) ((0x00250690)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLECNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_THRESHOLD_RM(i) ((0x00250698)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_THRESHOLD_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_RM(i) ((0x0025069C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RELEASE_RM(i) ((0x002506A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RELEASE_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT0_RM(i) ((0x002506A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT1_RM(i) ((0x002506A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT2_RM(i) ((0x002506AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT3_RM(i) ((0x002506B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT4_RM(i) ((0x002506B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT5_RM(i) ((0x002506B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT6_RM(i) ((0x002506BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT7_RM(i) ((0x002506C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWSMPLCNT_RM(i) ((0x002506C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_RAWSMPLCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_RM(i) ((0x002506C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_RM(i) ((0x002506CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_RM(i) ((0x002506D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW2_RM(i) ((0x002506D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_RM(i) ((0x002506D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_RM(i) ((0x002506DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_STARTEXPERIMENT_RM(i) ((0x002506E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_STARTEXPERIMENT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_RM(i) ((0x002506E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_RM(i) ((0x002506E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_RM(i) ((0x002506EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_DEBUG_RM(i) ((0x002506F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_DAISY_DISABLE_RM(i) ((0x002506FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_DAISY_DISABLE_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_RM(i) ((0x00250708)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_RM(i) ((0x00250710)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLD_RM(i) ((0x00250720)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLD_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_PERFMONID_RM(i) ((0x00250728)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_PERFMONID_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW2_RM(i) ((0x00250714)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW3_RM(i) ((0x00250718)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW4_RM(i) ((0x0025071C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_TOTAL_TRIG_RCV_RM(i) ((0x00250724)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_TOTAL_TRIG_RCV_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER_RM(i) ((0x00250730)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCGS_ROP_CLAMP_CYA_CONTROL_RM(i) ((0x00250700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCGS_ROP_CLAMP_CYA_CONTROL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL_RM(i,j) (((0x00278000+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL_RM(i,j) (((0x00278004+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL_RM(i,j) (((0x00278008+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL_RM(i,j) (((0x0027800C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL_RM(i,j) (((0x00278010+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL_RM(i,j) (((0x00278014+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR0_INC_RM(i,j) (((0x00278020+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CNTR0_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR0_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR1_INC_RM(i,j) (((0x00278024+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CNTR1_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR1_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR2_INC_RM(i,j) (((0x00278028+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CNTR2_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR2_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR3_INC_RM(i,j) (((0x0027802C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CNTR3_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR3_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR4_INC_RM(i,j) (((0x00278030+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CNTR4_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR4_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR5_INC_RM(i,j) (((0x00278034+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CNTR5_INC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CNTR5_INC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIG0_SEL_RM(i,j) (((0x00278040+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_TRIG0_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIG0_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIG0_OP_RM(i,j) (((0x00278044+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_TRIG0_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIG0_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIG1_SEL_RM(i,j) (((0x00278048+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_TRIG1_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIG1_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIG1_OP_RM(i,j) (((0x0027804C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_TRIG1_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIG1_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_EVENT_SEL_RM(i,j) (((0x00278050+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_EVENT_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_EVENT_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_EVENT_OP_RM(i,j) (((0x00278054+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_EVENT_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_EVENT_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL_RM(i,j) (((0x00278058+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_RM(i,j) (((0x0027805C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_RM(i,j) (((0x00278060+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_RM(i,j) (((0x00278064+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_SELECTMUX_RM(i,j) (((0x00278068+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_SELECTMUX_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_SELECTMUX_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_ENGINE_SEL_RM(i,j) (((0x0027806C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_ENGINE_SEL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_ENGINE_SEL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_ELAPSED_RM(i,j) (((0x00278070+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_ELAPSED_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_ELAPSED_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_MODEC5CNT_RM(i,j) (((0x00278074+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_MODEC5CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_MODEC5CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CYCLECNT_RM(i,j) (((0x00278078+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CYCLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CYCLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_MODEC6CNT_RM(i,j) (((0x0027807C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_MODEC6CNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_MODEC6CNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_EVENTCNT_RM(i,j) (((0x00278080+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_EVENTCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_EVENTCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER_RM(i,j) (((0x00278084+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_THRESHCNT_RM(i,j) (((0x00278088+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_THRESHCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_THRESHCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIGGERCNT_RM(i,j) (((0x0027808C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_TRIGGERCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_TRIGGERCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_SAMPLECNT_RM(i,j) (((0x00278090+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_SAMPLECNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_SAMPLECNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_THRESHOLD_RM(i,j) (((0x00278098+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_THRESHOLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_THRESHOLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CONTROL_RM(i,j) (((0x0027809C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RELEASE_RM(i,j) (((0x002780A0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RELEASE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RELEASE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT0_RM(i,j) (((0x002780A4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWCNT0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT1_RM(i,j) (((0x002780A8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWCNT1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT2_RM(i,j) (((0x002780AC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWCNT2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT3_RM(i,j) (((0x002780B0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWCNT3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT4_RM(i,j) (((0x002780B4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWCNT4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT5_RM(i,j) (((0x002780B8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWCNT5_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT5_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT6_RM(i,j) (((0x002780BC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWCNT6_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT6_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT7_RM(i,j) (((0x002780C0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWCNT7_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWCNT7_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWSMPLCNT_RM(i,j) (((0x002780C4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_RAWSMPLCNT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_RAWSMPLCNT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_RM(i,j) (((0x002780C8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW0_RM(i,j) (((0x002780CC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_WBSKEW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW1_RM(i,j) (((0x002780D0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_WBSKEW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW2_RM(i,j) (((0x002780D4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_WBSKEW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_RM(i,j) (((0x002780D8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_RM(i,j) (((0x002780DC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_STARTEXPERIMENT_RM(i,j) (((0x002780E0+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_STARTEXPERIMENT_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_STARTEXPERIMENT_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW0_RM(i,j) (((0x002780E4+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CTXSW0_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW0_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW1_RM(i,j) (((0x002780E8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CTXSW1_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW1_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_RM(i,j) (((0x002780EC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_DEBUG_RM(i,j) (((0x002780F8+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_DEBUG_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_DEBUG_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_DAISY_DISABLE_RM(i,j) (((0x002780FC+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_DAISY_DISABLE_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_DAISY_DISABLE_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CONTROLB_RM(i,j) (((0x00278108+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CONTROLB_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CONTROLB_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CONTROLC_RM(i,j) (((0x00278110+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CONTROLC_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CONTROLC_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CONTROLD_RM(i,j) (((0x00278120+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CONTROLD_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CONTROLD_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_PERFMONID_RM(i,j) (((0x00278128+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_PERFMONID_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_PERFMONID_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW2_RM(i,j) (((0x00278114+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CTXSW2_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW2_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW3_RM(i,j) (((0x00278118+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CTXSW3_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW3_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW4_RM(i,j) (((0x0027811C+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CTXSW4_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CTXSW4_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_TOTAL_TRIG_RCV_RM(i,j) (((0x00278124+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_TOTAL_TRIG_RCV_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_TOTAL_TRIG_RCV_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_RM(i,j) (((0x00278130+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_RM(i) ((0x00251800)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_RECORD_GRANT_RM(i) ((0x00251804)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_RECORD_GRANT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_PMMTRIGGERCNT_RM(i) ((0x00251808)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_PMMTRIGGERCNT_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CTXSW0_RM(i) ((0x0025180C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CTXSW0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_RM(i) ((0x00251810)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_PERFMONSTATUS_RM(i) ((0x00251814)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_PERFMONSTATUS_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_CG2_RM(i) ((0x00251818)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_CG2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG_RM(i) ((0x0025181C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_HS_RECORD_DEBUG_RM(i) ((0x00251954)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_HS_RECORD_DEBUG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_RM(i) ((0x00251950)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL_RM(i,j) (((0x00278100+(i)*0x00000200))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL_RM__SIZE_1 22 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL_RM__SIZE_2 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21_RM(i) ((0x0027AB00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20_RM(i) ((0x0027A900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19_RM(i) ((0x0027A700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18_RM(i) ((0x0027A500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17_RM(i) ((0x0027A300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16_RM(i) ((0x0027A100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15_RM(i) ((0x00279F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14_RM(i) ((0x00279D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_RM(i) ((0x00279B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_RM(i) ((0x00279900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_RM(i) ((0x00279700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_RM(i) ((0x00279500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_RM(i) ((0x00279300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_RM(i) ((0x00279100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_RM(i) ((0x00278F00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_RM(i) ((0x00278D00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_RM(i) ((0x00278B00)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_RM(i) ((0x00278900)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_RM(i) ((0x00278700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_RM(i) ((0x00278500)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_RM(i) ((0x00278300)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_RM__SIZE_1 7 /*       */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_RM(i) ((0x00278100)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_RM__SIZE_1 7 /*       */
#define NV_PERF_PMASYS_CONTROL_RM(i) ((0x0024A000)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_PULSE_TIMEBASESET_RM(i) ((0x0024A698)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_PULSE_TIMEBASESET_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_PULSE_TIMEBASECNT_RM(i) ((0x0024A69C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_PULSE_TIMEBASECNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_DEBUG_RM(i) ((0x0024A614)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_TRIGGER_GLOBAL_RM(i) ((0x0024A008)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_TRIGGER_GLOBAL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_HS_INFO_RM(i) ((0x0024A00C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_HS_INFO_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_HS_DEBUG_RM(i) ((0x0024A618)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_HS_DEBUG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_START_RM(i) ((0x0024A6D0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_START_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_STARTB_RM(i) ((0x24A6D4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_STARTB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_START_RM(i) ((0x0024A6D8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_START_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_STARTB_RM(i) ((0x24A6DC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_STARTB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_START_RM(i) ((0x0024A6E0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_START_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_STARTB_RM(i) ((0x24A6E4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_STARTB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_RM(i) ((0x0024A65C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_START_MASKB_RM(i) ((0x24A660)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_START_MASKB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_RM(i) ((0x0024A664)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_START_MASKB_RM(i) ((0x24A668)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_START_MASKB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_RM(i) ((0x0024A66C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_START_MASKB_RM(i) ((0x24A670)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_START_MASKB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_STOP_RM(i) ((0x0024A6E8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_STOP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_STOPB_RM(i) ((0x24A6EC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_STOPB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_STOP_RM(i) ((0x0024A6F0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_STOP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_STOPB_RM(i) ((0x24A6F4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_STOPB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_STOP_RM(i) ((0x0024A6F8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_STOP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_STOPB_RM(i) ((0x24A6FC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_STOPB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_RM(i) ((0x0024A674)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASKB_RM(i) ((0x24A678)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASKB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_RM(i) ((0x0024A67C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASKB_RM(i) ((0x24A680)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASKB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_RM(i) ((0x0024A684)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASKB_RM(i) ((0x24A688)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASKB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_RM(i) ((0x0024A700)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_STATUSB_RM(i) ((0x24A704)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_STATUSB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_RM(i) ((0x0024A708)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_STATUSB_RM(i) ((0x24A70C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_STATUSB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_RM(i) ((0x0024A710)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_STATUSB_RM(i) ((0x24A714)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_STATUSB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_ENGINE_STATUS_START_RM(i) ((0x0024A600)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_ENGINE_STATUS_START_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_ENGINE_STATUS_STARTB_RM(i) ((0x24A604)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_ENGINE_STATUS_STARTB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_ENGINE_STATUS_STOP_RM(i) ((0x0024A608)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_ENGINE_STATUS_STOP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_ENGINE_STATUS_STOPB_RM(i) ((0x24A60C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_ENGINE_STATUS_STOPB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_RM(i) ((0x0024A68C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_RM(i) ((0x0024A690)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CONTROLB_RM(i) ((0x0024A070)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CONTROLB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_RM(i) ((0x0024A010)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_TRIGGER_MASK_SECURE1_RM(i) ((0x24A014)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_TRIGGER_MASK_SECURE1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_RM(i,j) (((0x0024A730+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_RM(i,j) (((0x0024A638+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_OUTBASE_RM(i,j) (((0x0024A644+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_OUTBASE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_OUTBASE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_RM(i,j) (((0x0024A648+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_OUTSIZE_RM(i,j) (((0x0024A64C+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_OUTSIZE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_OUTSIZE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_HEAD_RM(i,j) (((0x0024A650+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_MEM_HEAD_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_HEAD_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_RM(i,j) (((0x0024A654+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_BUMP_RM(i,j) (((0x0024A624+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_MEM_BUMP_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_BUMP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_RM(i,j) (((0x0024A658+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CTXSW_RM(i,j) (((0x0024A734+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_CTXSW_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CTXSW_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_GFID_RM(i,j) (((0x0024A634+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_GFID_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_GFID_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGERCNT_RM(i) ((0x0024A718)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGERCNT_RM(i) ((0x0024A71C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGERCNT_RM(i) ((0x0024A720)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_ENGINESTATUS_RM(i) ((0x0024A75C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_ENGINESTATUS_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_RM(i) ((0x0024A6A0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODEB_RM(i) ((0x24A6A4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODEB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_RM(i) ((0x0024A6B8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODEB_RM(i) ((0x24A6BC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODEB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_RM(i) ((0x0024A6A8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODEB_RM(i) ((0x24A6AC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODEB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_RM(i) ((0x0024A6C0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODEB_RM(i) ((0x24A6C4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODEB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_RM(i) ((0x0024A6B0)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODEB_RM(i) ((0x24A6B4)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODEB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_RM(i) ((0x0024A6C8)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODEB_RM(i) ((0x24A6CC)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODEB_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_RM(i) ((0x0024A040)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0_RM(i) ((0x0024A020)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_RM(i) ((0x0024A024)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CG2_RM(i) ((0x0024A044)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CG2_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_PRIV_LEVEL_MASK_RM(i) ((0x0024A038)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_PRIV_LEVEL_MASK_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CONTROLREG_RM(i) ((0x0024A03C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CONTROLREG_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_PMCONTROL_RM(i) ((0x0024A08C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_PMCONTROL_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_RECORD_REQUEST_GPC_RM(i,j) (((0x0024A200+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_REQUEST_GPC_RM__SIZE_1 16 /*       */
#define NV_PERF_PMASYS_RECORD_REQUEST_GPC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_RECORD_REQUEST_FBP_RM(i,j) (((0x0024A280+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_REQUEST_FBP_RM__SIZE_1 16 /*       */
#define NV_PERF_PMASYS_RECORD_REQUEST_FBP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_RECORD_REQUEST_SYS_RM(i,j) (((0x0024A300+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_REQUEST_SYS_RM__SIZE_1 16 /*       */
#define NV_PERF_PMASYS_RECORD_REQUEST_SYS_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_RECORD_DATA_GPC_RM(i,j) (((0x0024A400+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_DATA_GPC_RM__SIZE_1 16 /*       */
#define NV_PERF_PMASYS_RECORD_DATA_GPC_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_RECORD_DATA_FBP_RM(i,j) (((0x0024A480+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_DATA_FBP_RM__SIZE_1 16 /*       */
#define NV_PERF_PMASYS_RECORD_DATA_FBP_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_RECORD_DATA_SYS_RM(i,j) (((0x0024A500+(i)*4))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_DATA_SYS_RM__SIZE_1 16 /*       */
#define NV_PERF_PMASYS_RECORD_DATA_SYS_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_RECORD_START_TRIGGERCNT_RM(i) ((0x0024A724)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_START_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_RECORD_STOP_TRIGGERCNT_RM(i) ((0x0024A728)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_STOP_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_RECORD_TOTAL_TRIGGERCNT_RM(i) ((0x0024A72C)+((i)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_RECORD_TOTAL_TRIGGERCNT_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_RM(i,j) (((0x0024A610+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_SECURE_RM(i,j) (((0x0024A61C+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_SECURE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_SECURE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_RM(i,j) (((0x0024A640+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_RM(i,j) (((0x0024A620+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_RM(i,j) (((0x0024A628+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RM(i,j) (((0x0024A694+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_RM(i,j) (((0x0024A62C+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CTXSW_CONTROL_FIRMWARE_RM(i,j) (((0x0024A630+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CTXSW_CONTROL_FIRMWARE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CTXSW_CONTROL_FIRMWARE_RM__SIZE_2 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_RM(i,j) (((0x0024A63C+(i)*0x180))+((j)*0x4000)) /* RW-4A */
#define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_RM__SIZE_1 1 /*       */
#define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_RM__SIZE_2 1 /*       */

#endif // __ga102_dev_perf_addendum_h__