/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_perf_h__ #define __ga102_dev_perf_h__ /* This file is autogenerated. Do not edit */ #define NV_PERF_PMMSYS_PERDOMAIN_OFFSET 0x00000200 /* */ #define NV_PERF_PMMSYS 0x00263FFF:0x00260000 /* RW--D */ #define NV_PERF_PMMSYSROUTER 0x002481FF:0x00248000 /* RW--D */ #define NV_PERF_PMMSYSROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMSYS_FT0_INPUTSEL(i) (0x00260000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_FT0_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_FT1_INPUTSEL(i) (0x00260004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_FT1_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_FT2_INPUTSEL(i) (0x00260008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_FT2_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_FT3_INPUTSEL(i) (0x0026000C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_FT3_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_FT4_INPUTSEL(i) (0x00260010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_FT4_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_FT5_INPUTSEL(i) (0x00260014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_FT5_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR0_INC(i) (0x00260020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CNTR0_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC(i) (0x00260024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CNTR1_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC(i) (0x00260028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CNTR2_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC(i) (0x0026002C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CNTR3_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC(i) (0x00260030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CNTR4_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC(i) (0x00260034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CNTR5_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_TRIG0_SEL(i) (0x00260040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_TRIG0_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_TRIG0_OP(i) (0x00260044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_TRIG0_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG1_SEL(i) (0x00260048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_TRIG1_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_TRIG1_OP(i) (0x0026004C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_TRIG1_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_EVENT_SEL(i) (0x00260050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_EVENT_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_EVENT_OP(i) (0x00260054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_EVENT_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SAMPLE_SEL(i) (0x00260058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SAMPLE_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SAMPLE_OP(i) (0x0026005C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SAMPLE_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SETFLAG_OP(i) (0x00260060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SETFLAG_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CLRFLAG_OP(i) (0x00260064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CLRFLAG_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SELECTMUX(i) (0x00260068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMSYS_SELECTMUX__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMSYS_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMSYS_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMSYS_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMSYS_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMSYS_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMSYS_ENGINE_SEL(i) (0x0026006C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_ENGINE_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMSYS_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_ELAPSED(i) (0x00260070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_ELAPSED__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_MODEC5CNT(i) (0x00260074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_MODEC5CNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CYCLECNT(i) (0x00260078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CYCLECNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_MODEC6CNT(i) (0x0026007C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_MODEC6CNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_EVENTCNT(i) (0x00260080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_EVENTCNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_DFD_CNT_UPPER(i) (0x00260084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_DFD_CNT_UPPER__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_THRESHCNT(i) (0x00260088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_THRESHCNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_TRIGGERCNT(i) (0x0026008C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_TRIGGERCNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SAMPLECNT(i) (0x00260090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SAMPLECNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_THRESHOLD(i) (0x00260098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_THRESHOLD__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMSYS_CONTROL(i) (0x0026009C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CONTROL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMSYS_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMSYS_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMSYS_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_RELEASE(i) (0x002600A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RELEASE__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMSYS_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT0(i) (0x002600A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWCNT0__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT1(i) (0x002600A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWCNT1__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT2(i) (0x002600AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWCNT2__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT3(i) (0x002600B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWCNT3__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT4(i) (0x002600B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWCNT4__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT5(i) (0x002600B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWCNT5__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT6(i) (0x002600BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWCNT6__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWCNT7(i) (0x002600C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWCNT7__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_RAWSMPLCNT(i) (0x002600C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_RAWSMPLCNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMSYS_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_ENGINESTATUS(i) (0x002600C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_ENGINESTATUS__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMSYS_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMSYS_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMSYS_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMSYS_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMSYS_WBSKEW0(i) (0x002600CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_WBSKEW0__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW1(i) (0x002600D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_WBSKEW1__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW2(i) (0x002600D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_WBSKEW2__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0(i) (0x002600D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1(i) (0x002600DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMSYS_STARTEXPERIMENT(i) (0x002600E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_STARTEXPERIMENT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_CTXSW0(i) (0x002600E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CTXSW0__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1(i) (0x002600E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CTXSW1__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG(i) (0x002600EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMSYS_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_DEBUG(i) (0x002600F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_DEBUG__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMSYS_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMSYS_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMSYS_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMSYS_DAISY_DISABLE(i) (0x002600FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_DAISY_DISABLE__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMSYS_CONTROLB(i) (0x00260108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CONTROLB__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMSYS_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMSYS_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMSYS_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMSYS_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLC(i) (0x00260110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CONTROLC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLD(i) (0x00260120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CONTROLD__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMSYS_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_PERFMONID(i) (0x00260128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_PERFMONID__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMSYS_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CTXSW2(i) (0x00260114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CTXSW2__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW3(i) (0x00260118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CTXSW3__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMSYS_CTXSW4(i) (0x0026011C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CTXSW4__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMSYS_TOTAL_TRIG_RCV(i) (0x00260124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_TOTAL_TRIG_RCV__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_FLAG_BIT_TIMER(i) (0x00260130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_FLAG_BIT_TIMER__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMSYS_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL 0x00248000 /* RW-4R */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMSYSROUTER_RECORD_GRANT 0x00248004 /* -W-4R */ #define NV_PERF_PMMSYSROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMSYSROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMSYSROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_PMMTRIGGERCNT 0x00248008 /* RW-4R */ #define NV_PERF_PMMSYSROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CTXSW0 0x0024800C /* R-E4R */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMSYSROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS 0x00248010 /* RW-4R */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMSYSROUTER_PERFMONSTATUS 0x00248014 /* R--4R */ #define NV_PERF_PMMSYSROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMSYSROUTER_CG2 0x00248018 /* RW-4R */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMSYSROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMSYSROUTER_RECORD_DEBUG 0x0024801C /* RW-4R */ #define NV_PERF_PMMSYSROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMSYSROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMSYSROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMSYSROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMSYSROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMSYSROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMSYSROUTER_HS_RECORD_DEBUG 0x00248154 /* RW-4R */ #define NV_PERF_PMMSYSROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMSYSROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMSYSROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMSYSROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMSYSROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMSYSROUTER_HS_CONFIG 0x00248150 /* RW-4R */ #define NV_PERF_PMMSYSROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMSYSROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMSYSROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMSYSROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMSYSROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMSYSROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL(i) (0x00260100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20 0x00262900 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_CXBAR_CQPM 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_MXBAR_CS_REQ0 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_MXBAR_CS_RSP0 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_WXBAR_CS_XSU 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_WXBAR_CSPM 4:4 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19 0x00262700 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_CE4 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_CE5 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_CESHIM 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_ESC0 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_ESC1 4:4 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_EXT 5:5 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_PMA 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_SYS_PRI_HUB 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18 0x00262500 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_HSHUB1_EG 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_HSHUB1_IG 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_HSHUB1_RR 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_CE0 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_CE1 4:4 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_HUBMMU 5:5 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_PD 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_PDB 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_RSTR2D 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17 0x00262300 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_CE2 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_CE3 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_DS 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_HSHUB_EG 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_HSHUB_IG 4:4 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_HSHUB_RR 5:5 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_HSHUBMMU 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_FBHUB 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_PMMSYS_ROUTER 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_PWR 9:9 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_SCC 10:10 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_SMCARB 11:11 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_SSYNC 12:12 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16 0x00262100 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_CWD0 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_FE 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_FECS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_FECS 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15 0x00261F00 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15_FE 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15_ESC0 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15_SKED0 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL14 0x00261D00 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL14_PWR 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL13 0x00261B00 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL13_XP 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL13_XVE 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL12 0x00261900 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL12_NVLDL3 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL12_NVLTLC3_TX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL11 0x00261700 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL11_NVLDL2 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL11_NVLTLC2_TX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL10 0x00261500 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL10_NVLDL1 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL10_NVLTLC1_TX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL9 0x00261300 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL9_NVLDL0 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL9_NVLTLC0_TX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8 0x00261100 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_NVLTLC0_SYS 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_NVLTLC1_SYS 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_NVLTLC2_SYS 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_NVLTLC3_SYS 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL7 0x00260F00 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL7_NVLDL3_RX 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL7_NVLTLC3_RX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL6 0x00260D00 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL6_NVLDL2_RX 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL6_NVLTLC2_RX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL5 0x00260B00 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL5_NVLDL1_RX 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL5_NVLTLC1_RX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL4 0x00260900 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL4_NVLDL0_RX 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL4_NVLTLC0_RX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL3 0x00260700 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL3_IOCTRL0_SYS 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL3_NVLIPT0_SYS 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL2 0x00260500 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL2_NVDEC1 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL2_NVENC0 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1 0x00260300 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_GSP 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_NVDEC0 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_OFA 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_SEC 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL0 0x00260100 /* RW-4R */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL0_EXT 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL0_XVE 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0 0x00263FFF:0x00260000 /* RW--D */ #define NV_PERF_PMMSYS_SYS0ROUTER 0x002481FF:0x00248000 /* RW--D */ #define NV_PERF_PMMSYS_SYS0ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL(i) (0x00260000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL(i) (0x00260004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL(i) (0x00260008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL(i) (0x0026000C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL(i) (0x00260010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL(i) (0x00260014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC(i) (0x00260020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC(i) (0x00260024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC(i) (0x00260028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC(i) (0x0026002C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC(i) (0x00260030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC(i) (0x00260034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_TRIG0_SEL(i) (0x00260040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_TRIG0_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP(i) (0x00260044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG1_SEL(i) (0x00260048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_TRIG1_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP(i) (0x0026004C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_EVENT_SEL(i) (0x00260050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_EVENT_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP(i) (0x00260054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL(i) (0x00260058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP(i) (0x0026005C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP(i) (0x00260060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP(i) (0x00260064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SELECTMUX(i) (0x00260068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMSYS_SYS0_SELECTMUX__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_ENGINE_SEL(i) (0x0026006C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_ENGINE_SEL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_ELAPSED(i) (0x00260070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_ELAPSED__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_MODEC5CNT(i) (0x00260074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_MODEC5CNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CYCLECNT(i) (0x00260078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CYCLECNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_MODEC6CNT(i) (0x0026007C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_MODEC6CNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_EVENTCNT(i) (0x00260080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_EVENTCNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER(i) (0x00260084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_THRESHCNT(i) (0x00260088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_THRESHCNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_TRIGGERCNT(i) (0x0026008C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_TRIGGERCNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_SAMPLECNT(i) (0x00260090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_SAMPLECNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_THRESHOLD(i) (0x00260098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_THRESHOLD__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMSYS_SYS0_CONTROL(i) (0x0026009C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CONTROL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_RELEASE(i) (0x002600A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RELEASE__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMSYS_SYS0_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT0(i) (0x002600A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWCNT0__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT1(i) (0x002600A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWCNT1__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT2(i) (0x002600AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWCNT2__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT3(i) (0x002600B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWCNT3__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT4(i) (0x002600B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWCNT4__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT5(i) (0x002600B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWCNT5__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT6(i) (0x002600BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWCNT6__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWCNT7(i) (0x002600C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWCNT7__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_RAWSMPLCNT(i) (0x002600C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_RAWSMPLCNT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS(i) (0x002600C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0(i) (0x002600CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1(i) (0x002600D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW2(i) (0x002600D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_WBSKEW2__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0(i) (0x002600D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1(i) (0x002600DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_STARTEXPERIMENT(i) (0x002600E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_STARTEXPERIMENT__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYS0_CTXSW0(i) (0x002600E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CTXSW0__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1(i) (0x002600E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CTXSW1__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG(i) (0x002600EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYS0_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYS0_DEBUG(i) (0x002600F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_DEBUG__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMSYS_SYS0_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMSYS_SYS0_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMSYS_SYS0_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMSYS_SYS0_DAISY_DISABLE(i) (0x002600FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_DAISY_DISABLE__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB(i) (0x00260108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CONTROLB__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC(i) (0x00260110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CONTROLC__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLD(i) (0x00260120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CONTROLD__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_PERFMONID(i) (0x00260128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_PERFMONID__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CTXSW2(i) (0x00260114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CTXSW2__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW3(i) (0x00260118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CTXSW3__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CTXSW4(i) (0x0026011C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CTXSW4__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_TOTAL_TRIG_RCV(i) (0x00260124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_TOTAL_TRIG_RCV__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER(i) (0x00260130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL 0x00248000 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_GRANT 0x00248004 /* -W-4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_PMMTRIGGERCNT 0x00248008 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CTXSW0 0x0024800C /* R-E4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS 0x00248010 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS 0x00248014 /* R--4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2 0x00248018 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG 0x0024801C /* RW-4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_RECORD_DEBUG 0x00248154 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG 0x00248150 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYS0ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL(i) (0x00260100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL__SIZE_1 21 /* */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20 0x00262900 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_CXBAR_CQPM 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_MXBAR_CS_REQ0 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_MXBAR_CS_RSP0 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_WXBAR_CS_XSU 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_WXBAR_CSPM 4:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19 0x00262700 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_CE4 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_CE5 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_CESHIM 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_ESC0 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_ESC1 4:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_EXT 5:5 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_PMA 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_SYS_PRI_HUB 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18 0x00262500 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_HSHUB1_EG 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_HSHUB1_IG 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_HSHUB1_RR 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_CE0 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_CE1 4:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_HUBMMU 5:5 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_PD 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_PDB 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_RSTR2D 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17 0x00262300 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_CE2 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_CE3 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_DS 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_HSHUB_EG 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_HSHUB_IG 4:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_HSHUB_RR 5:5 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_HSHUBMMU 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_FBHUB 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_PMMSYS_ROUTER 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_PWR 9:9 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_SCC 10:10 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_SMCARB 11:11 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_SSYNC 12:12 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16 0x00262100 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_CWD0 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_FE 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_FECS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_FECS 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15 0x00261F00 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15_FE 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15_ESC0 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15_SKED0 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL14 0x00261D00 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL14_PWR 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL13 0x00261B00 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL13_XP 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL13_XVE 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL12 0x00261900 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL12_NVLDL3 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL12_NVLTLC3_TX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL11 0x00261700 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL11_NVLDL2 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL11_NVLTLC2_TX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL10 0x00261500 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL10_NVLDL1 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL10_NVLTLC1_TX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL9 0x00261300 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL9_NVLDL0 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL9_NVLTLC0_TX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8 0x00261100 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_NVLTLC0_SYS 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_NVLTLC1_SYS 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_NVLTLC2_SYS 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_NVLTLC3_SYS 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL7 0x00260F00 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL7_NVLDL3_RX 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL7_NVLTLC3_RX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL6 0x00260D00 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL6_NVLDL2_RX 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL6_NVLTLC2_RX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL5 0x00260B00 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL5_NVLDL1_RX 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL5_NVLTLC1_RX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL4 0x00260900 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL4_NVLDL0_RX 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL4_NVLTLC0_RX 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL3 0x00260700 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL3_IOCTRL0_SYS 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL3_NVLIPT0_SYS 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL2 0x00260500 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL2_NVDEC1 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL2_NVENC0 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1 0x00260300 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_GSP 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_NVDEC0 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_OFA 2:2 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_SEC 3:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL0 0x00260100 /* RW-4R */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL0_EXT 0:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL0_XVE 1:1 /* RWXUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYS0_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL 0x002511FF:0x00251000 /* RW--D */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT0_INPUTSEL 0x00251000 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT1_INPUTSEL 0x00251004 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT2_INPUTSEL 0x00251008 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT3_INPUTSEL 0x0025100C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT4_INPUTSEL 0x00251010 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT5_INPUTSEL 0x00251014 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC 0x00251020 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC 0x00251024 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC 0x00251028 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC 0x0025102C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC 0x00251030 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC 0x00251034 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_SEL 0x00251040 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP 0x00251044 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_SEL 0x00251048 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP 0x0025104C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_SEL 0x00251050 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP 0x00251054 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_SEL 0x00251058 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP 0x0025105C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP 0x00251060 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP 0x00251064 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX 0x00251068 /* R--4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINE_SEL 0x0025106C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ELAPSED 0x00251070 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC5CNT 0x00251074 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CYCLECNT 0x00251078 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC6CNT 0x0025107C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENTCNT 0x00251080 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DFD_CNT_UPPER 0x00251084 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHCNT 0x00251088 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIGGERCNT 0x0025108C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLECNT 0x00251090 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHOLD 0x00251098 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL 0x0025109C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RELEASE 0x002510A0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT0 0x002510A4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT1 0x002510A8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT2 0x002510AC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT3 0x002510B0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT4 0x002510B4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT5 0x002510B8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT6 0x002510BC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT7 0x002510C0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWSMPLCNT 0x002510C4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS 0x002510C8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0 0x002510CC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1 0x002510D0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW2 0x002510D4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0 0x002510D8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1 0x002510DC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_STARTEXPERIMENT 0x002510E0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0 0x002510E4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1 0x002510E8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG 0x002510EC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DEBUG 0x002510F8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DAISY_DISABLE 0x002510FC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB 0x00251108 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC 0x00251110 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLD 0x00251120 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_PERFMONID 0x00251128 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW2 0x00251114 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW3 0x00251118 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW4 0x0025111C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TOTAL_TRIG_RCV 0x00251124 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER 0x00251130 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLAMP_CYA_CONTROL 0x00251100 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLCTRL_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX 0x002513FF:0x00251200 /* RW--D */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT0_INPUTSEL 0x00251200 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT1_INPUTSEL 0x00251204 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT2_INPUTSEL 0x00251208 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT3_INPUTSEL 0x0025120C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT4_INPUTSEL 0x00251210 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT5_INPUTSEL 0x00251214 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC 0x00251220 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC 0x00251224 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC 0x00251228 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC 0x0025122C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC 0x00251230 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC 0x00251234 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_SEL 0x00251240 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP 0x00251244 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_SEL 0x00251248 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP 0x0025124C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_SEL 0x00251250 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP 0x00251254 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_SEL 0x00251258 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP 0x0025125C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP 0x00251260 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP 0x00251264 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX 0x00251268 /* R--4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINE_SEL 0x0025126C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ELAPSED 0x00251270 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC5CNT 0x00251274 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CYCLECNT 0x00251278 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC6CNT 0x0025127C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENTCNT 0x00251280 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DFD_CNT_UPPER 0x00251284 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHCNT 0x00251288 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIGGERCNT 0x0025128C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLECNT 0x00251290 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHOLD 0x00251298 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL 0x0025129C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RELEASE 0x002512A0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT0 0x002512A4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT1 0x002512A8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT2 0x002512AC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT3 0x002512B0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT4 0x002512B4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT5 0x002512B8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT6 0x002512BC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT7 0x002512C0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWSMPLCNT 0x002512C4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS 0x002512C8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0 0x002512CC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1 0x002512D0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW2 0x002512D4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0 0x002512D8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1 0x002512DC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_STARTEXPERIMENT 0x002512E0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0 0x002512E4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1 0x002512E8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG 0x002512EC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DEBUG 0x002512F8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DAISY_DISABLE 0x002512FC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB 0x00251308 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC 0x00251310 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLD 0x00251320 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_PERFMONID 0x00251328 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW2 0x00251314 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW3 0x00251318 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW4 0x0025131C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TOTAL_TRIG_RCV 0x00251324 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER 0x00251330 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLAMP_CYA_CONTROL 0x00251300 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLRX_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS 0x002515FF:0x00251400 /* RW--D */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT0_INPUTSEL 0x00251400 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT1_INPUTSEL 0x00251404 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT2_INPUTSEL 0x00251408 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT3_INPUTSEL 0x0025140C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT4_INPUTSEL 0x00251410 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT5_INPUTSEL 0x00251414 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC 0x00251420 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC 0x00251424 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC 0x00251428 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC 0x0025142C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC 0x00251430 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC 0x00251434 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_SEL 0x00251440 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP 0x00251444 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_SEL 0x00251448 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP 0x0025144C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_SEL 0x00251450 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP 0x00251454 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_SEL 0x00251458 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP 0x0025145C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP 0x00251460 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP 0x00251464 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX 0x00251468 /* R--4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINE_SEL 0x0025146C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ELAPSED 0x00251470 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC5CNT 0x00251474 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CYCLECNT 0x00251478 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC6CNT 0x0025147C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENTCNT 0x00251480 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DFD_CNT_UPPER 0x00251484 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHCNT 0x00251488 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIGGERCNT 0x0025148C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLECNT 0x00251490 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHOLD 0x00251498 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL 0x0025149C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RELEASE 0x002514A0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT0 0x002514A4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT1 0x002514A8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT2 0x002514AC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT3 0x002514B0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT4 0x002514B4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT5 0x002514B8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT6 0x002514BC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT7 0x002514C0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWSMPLCNT 0x002514C4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS 0x002514C8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0 0x002514CC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1 0x002514D0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW2 0x002514D4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0 0x002514D8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1 0x002514DC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_STARTEXPERIMENT 0x002514E0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0 0x002514E4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1 0x002514E8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG 0x002514EC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DEBUG 0x002514F8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DAISY_DISABLE 0x002514FC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB 0x00251508 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC 0x00251510 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLD 0x00251520 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_PERFMONID 0x00251528 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW2 0x00251514 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW3 0x00251518 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW4 0x0025151C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TOTAL_TRIG_RCV 0x00251524 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER 0x00251530 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLAMP_CYA_CONTROL 0x00251500 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLSYS_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX 0x002517FF:0x00251600 /* RW--D */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT0_INPUTSEL 0x00251600 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT1_INPUTSEL 0x00251604 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT2_INPUTSEL 0x00251608 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT3_INPUTSEL 0x0025160C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT4_INPUTSEL 0x00251610 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT5_INPUTSEL 0x00251614 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC 0x00251620 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC 0x00251624 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC 0x00251628 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC 0x0025162C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC 0x00251630 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC 0x00251634 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_SEL 0x00251640 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP 0x00251644 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_SEL 0x00251648 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP 0x0025164C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_SEL 0x00251650 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP 0x00251654 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_SEL 0x00251658 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP 0x0025165C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP 0x00251660 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP 0x00251664 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX 0x00251668 /* R--4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINE_SEL 0x0025166C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ELAPSED 0x00251670 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC5CNT 0x00251674 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CYCLECNT 0x00251678 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC6CNT 0x0025167C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENTCNT 0x00251680 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DFD_CNT_UPPER 0x00251684 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHCNT 0x00251688 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIGGERCNT 0x0025168C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLECNT 0x00251690 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHOLD 0x00251698 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL 0x0025169C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RELEASE 0x002516A0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT0 0x002516A4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT1 0x002516A8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT2 0x002516AC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT3 0x002516B0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT4 0x002516B4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT5 0x002516B8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT6 0x002516BC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT7 0x002516C0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWSMPLCNT 0x002516C4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS 0x002516C8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0 0x002516CC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1 0x002516D0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW2 0x002516D4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0 0x002516D8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1 0x002516DC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_STARTEXPERIMENT 0x002516E0 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0 0x002516E4 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1 0x002516E8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG 0x002516EC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DEBUG 0x002516F8 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DAISY_DISABLE 0x002516FC /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB 0x00251708 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC 0x00251710 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLD 0x00251720 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_PERFMONID 0x00251728 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW2 0x00251714 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW3 0x00251718 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW4 0x0025171C /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TOTAL_TRIG_RCV 0x00251724 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER 0x00251730 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLAMP_CYA_CONTROL 0x00251700 /* RW-4R */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMSYS_SYSGS_NVLTX_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_PERDOMAIN_OFFSET 0x00000200 /* */ #define NV_PERF_PMMFBP 0x00203FFF:0x00200000 /* RW--D */ #define NV_PERF_PMMFBPROUTER 0x002461FF:0x00246000 /* RW--D */ #define NV_PERF_PMMFBPROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMFBP_FT0_INPUTSEL(i) (0x00200000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FT0_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FT1_INPUTSEL(i) (0x00200004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FT1_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FT2_INPUTSEL(i) (0x00200008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FT2_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FT3_INPUTSEL(i) (0x0020000C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FT3_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FT4_INPUTSEL(i) (0x00200010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FT4_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FT5_INPUTSEL(i) (0x00200014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FT5_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR0_INC(i) (0x00200020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CNTR0_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC(i) (0x00200024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CNTR1_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC(i) (0x00200028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CNTR2_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC(i) (0x0020002C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CNTR3_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC(i) (0x00200030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CNTR4_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC(i) (0x00200034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CNTR5_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_TRIG0_SEL(i) (0x00200040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_TRIG0_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_TRIG0_OP(i) (0x00200044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_TRIG0_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG1_SEL(i) (0x00200048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_TRIG1_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_TRIG1_OP(i) (0x0020004C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_TRIG1_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_EVENT_SEL(i) (0x00200050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_EVENT_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_EVENT_OP(i) (0x00200054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_EVENT_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SAMPLE_SEL(i) (0x00200058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_SAMPLE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_SAMPLE_OP(i) (0x0020005C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_SAMPLE_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SETFLAG_OP(i) (0x00200060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_SETFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CLRFLAG_OP(i) (0x00200064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CLRFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SELECTMUX(i) (0x00200068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMFBP_SELECTMUX__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_ENGINE_SEL(i) (0x0020006C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_ENGINE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_ELAPSED(i) (0x00200070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_ELAPSED__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_MODEC5CNT(i) (0x00200074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_MODEC5CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CYCLECNT(i) (0x00200078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CYCLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_MODEC6CNT(i) (0x0020007C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_MODEC6CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_EVENTCNT(i) (0x00200080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_EVENTCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_DFD_CNT_UPPER(i) (0x00200084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_DFD_CNT_UPPER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_THRESHCNT(i) (0x00200088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_THRESHCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_TRIGGERCNT(i) (0x0020008C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_TRIGGERCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_SAMPLECNT(i) (0x00200090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_SAMPLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_THRESHOLD(i) (0x00200098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_THRESHOLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_CONTROL(i) (0x0020009C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_RELEASE(i) (0x002000A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RELEASE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT0(i) (0x002000A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWCNT0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT1(i) (0x002000A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWCNT1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT2(i) (0x002000AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWCNT2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT3(i) (0x002000B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWCNT3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT4(i) (0x002000B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWCNT4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT5(i) (0x002000B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWCNT5__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT6(i) (0x002000BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWCNT6__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWCNT7(i) (0x002000C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWCNT7__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_RAWSMPLCNT(i) (0x002000C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_RAWSMPLCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_ENGINESTATUS(i) (0x002000C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_ENGINESTATUS__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_WBSKEW0(i) (0x002000CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_WBSKEW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW1(i) (0x002000D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_WBSKEW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW2(i) (0x002000D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_WBSKEW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0(i) (0x002000D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1(i) (0x002000DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_STARTEXPERIMENT(i) (0x002000E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_STARTEXPERIMENT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_CTXSW0(i) (0x002000E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CTXSW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1(i) (0x002000E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CTXSW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG(i) (0x002000EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_DEBUG(i) (0x002000F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_DEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_DAISY_DISABLE(i) (0x002000FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_DAISY_DISABLE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_CONTROLB(i) (0x00200108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CONTROLB__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLC(i) (0x00200110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CONTROLC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLD(i) (0x00200120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CONTROLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_PERFMONID(i) (0x00200128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_PERFMONID__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CTXSW2(i) (0x00200114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CTXSW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW3(i) (0x00200118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CTXSW3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_CTXSW4(i) (0x0020011C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CTXSW4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_TOTAL_TRIG_RCV(i) (0x00200124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_TOTAL_TRIG_RCV__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FLAG_BIT_TIMER(i) (0x00200130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FLAG_BIT_TIMER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL 0x00246000 /* RW-4R */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBPROUTER_RECORD_GRANT 0x00246004 /* -W-4R */ #define NV_PERF_PMMFBPROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMFBPROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBPROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_PMMTRIGGERCNT 0x00246008 /* RW-4R */ #define NV_PERF_PMMFBPROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CTXSW0 0x0024600C /* R-E4R */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMFBPROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS 0x00246010 /* RW-4R */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBPROUTER_PERFMONSTATUS 0x00246014 /* R--4R */ #define NV_PERF_PMMFBPROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMFBPROUTER_CG2 0x00246018 /* RW-4R */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMFBPROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMFBPROUTER_RECORD_DEBUG 0x0024601C /* RW-4R */ #define NV_PERF_PMMFBPROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMFBPROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBPROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBPROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBPROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMFBPROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMFBPROUTER_HS_RECORD_DEBUG 0x00246154 /* RW-4R */ #define NV_PERF_PMMFBPROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBPROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBPROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBPROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMFBPROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMFBPROUTER_HS_CONFIG 0x00246150 /* RW-4R */ #define NV_PERF_PMMFBPROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMFBPROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMFBPROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMFBPROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMFBPROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMFBPROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL(i) (0x00200100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL11 0x00201700 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL11_LTC1_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL10 0x00201500 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL10_LTC1_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL9 0x00201300 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL9_LTC1_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL8 0x00201100 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL8_LTC1_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL7 0x00200F00 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL7_LTC0_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL6 0x00200D00 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL6_LTC0_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL5 0x00200B00 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL5_LTC0_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL4 0x00200900 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL4_LTC0_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL3 0x00200700 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL3_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL2 0x00200500 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL2_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL1 0x00200300 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL1_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0 0x00200100 /* RW-4R */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0_LTC0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0_LTC1 1:1 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0_PMMFBP_ROUTER 2:2 /* RWXUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0 0x00203FFF:0x00200000 /* RW--D */ #define NV_PERF_PMMFBP_FBP0ROUTER 0x002461FF:0x00246000 /* RW--D */ #define NV_PERF_PMMFBP_FBP0ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL(i) (0x00200000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL(i) (0x00200004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL(i) (0x00200008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL(i) (0x0020000C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL(i) (0x00200010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL(i) (0x00200014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC(i) (0x00200020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC(i) (0x00200024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC(i) (0x00200028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC(i) (0x0020002C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC(i) (0x00200030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC(i) (0x00200034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_TRIG0_SEL(i) (0x00200040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_TRIG0_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP(i) (0x00200044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG1_SEL(i) (0x00200048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_TRIG1_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP(i) (0x0020004C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_EVENT_SEL(i) (0x00200050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_EVENT_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP(i) (0x00200054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL(i) (0x00200058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP(i) (0x0020005C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP(i) (0x00200060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP(i) (0x00200064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SELECTMUX(i) (0x00200068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMFBP_FBP0_SELECTMUX__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_ENGINE_SEL(i) (0x0020006C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_ENGINE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_ELAPSED(i) (0x00200070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_ELAPSED__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_MODEC5CNT(i) (0x00200074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_MODEC5CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CYCLECNT(i) (0x00200078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CYCLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_MODEC6CNT(i) (0x0020007C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_MODEC6CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_EVENTCNT(i) (0x00200080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_EVENTCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER(i) (0x00200084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_THRESHCNT(i) (0x00200088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_THRESHCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_TRIGGERCNT(i) (0x0020008C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_TRIGGERCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_SAMPLECNT(i) (0x00200090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_SAMPLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_THRESHOLD(i) (0x00200098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_THRESHOLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBP0_CONTROL(i) (0x0020009C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_RELEASE(i) (0x002000A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RELEASE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP0_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT0(i) (0x002000A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWCNT0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT1(i) (0x002000A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWCNT1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT2(i) (0x002000AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWCNT2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT3(i) (0x002000B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWCNT3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT4(i) (0x002000B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWCNT4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT5(i) (0x002000B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWCNT5__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT6(i) (0x002000BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWCNT6__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWCNT7(i) (0x002000C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWCNT7__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_RAWSMPLCNT(i) (0x002000C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_RAWSMPLCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS(i) (0x002000C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0(i) (0x002000CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1(i) (0x002000D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW2(i) (0x002000D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_WBSKEW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0(i) (0x002000D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1(i) (0x002000DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_STARTEXPERIMENT(i) (0x002000E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_STARTEXPERIMENT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP0_CTXSW0(i) (0x002000E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CTXSW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1(i) (0x002000E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CTXSW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG(i) (0x002000EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP0_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP0_DEBUG(i) (0x002000F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_DEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBP0_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBP0_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBP0_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBP0_DAISY_DISABLE(i) (0x002000FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_DAISY_DISABLE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB(i) (0x00200108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CONTROLB__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC(i) (0x00200110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CONTROLC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLD(i) (0x00200120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CONTROLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_PERFMONID(i) (0x00200128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_PERFMONID__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CTXSW2(i) (0x00200114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CTXSW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW3(i) (0x00200118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CTXSW3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CTXSW4(i) (0x0020011C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CTXSW4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_TOTAL_TRIG_RCV(i) (0x00200124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_TOTAL_TRIG_RCV__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER(i) (0x00200130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL 0x00246000 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_GRANT 0x00246004 /* -W-4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_PMMTRIGGERCNT 0x00246008 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CTXSW0 0x0024600C /* R-E4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS 0x00246010 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_PERFMONSTATUS 0x00246014 /* R--4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2 0x00246018 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMFBP_FBP0ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG 0x0024601C /* RW-4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_RECORD_DEBUG 0x00246154 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG 0x00246150 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP0ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL(i) (0x00200100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL11 0x00201700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL11_LTC1_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL10 0x00201500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL10_LTC1_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL9 0x00201300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL9_LTC1_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL8 0x00201100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL8_LTC1_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL7 0x00200F00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL7_LTC0_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL6 0x00200D00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL6_LTC0_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL5 0x00200B00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL5_LTC0_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL4 0x00200900 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL4_LTC0_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL3 0x00200700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL3_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL2 0x00200500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL2_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL1 0x00200300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL1_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0 0x00200100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0_LTC0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0_LTC1 1:1 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0_PMMFBP_ROUTER 2:2 /* RWXUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP0_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1 0x00207FFF:0x00204000 /* RW--D */ #define NV_PERF_PMMFBP_FBP1ROUTER 0x002463FF:0x00246200 /* RW--D */ #define NV_PERF_PMMFBP_FBP1ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL(i) (0x00204000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL(i) (0x00204004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL(i) (0x00204008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL(i) (0x0020400C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL(i) (0x00204010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL(i) (0x00204014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC(i) (0x00204020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC(i) (0x00204024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC(i) (0x00204028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC(i) (0x0020402C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC(i) (0x00204030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC(i) (0x00204034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_TRIG0_SEL(i) (0x00204040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_TRIG0_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP(i) (0x00204044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG1_SEL(i) (0x00204048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_TRIG1_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP(i) (0x0020404C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_EVENT_SEL(i) (0x00204050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_EVENT_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP(i) (0x00204054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL(i) (0x00204058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP(i) (0x0020405C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP(i) (0x00204060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP(i) (0x00204064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SELECTMUX(i) (0x00204068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMFBP_FBP1_SELECTMUX__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_ENGINE_SEL(i) (0x0020406C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_ENGINE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_ELAPSED(i) (0x00204070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_ELAPSED__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_MODEC5CNT(i) (0x00204074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_MODEC5CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CYCLECNT(i) (0x00204078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CYCLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_MODEC6CNT(i) (0x0020407C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_MODEC6CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_EVENTCNT(i) (0x00204080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_EVENTCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER(i) (0x00204084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_THRESHCNT(i) (0x00204088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_THRESHCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_TRIGGERCNT(i) (0x0020408C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_TRIGGERCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_SAMPLECNT(i) (0x00204090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_SAMPLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_THRESHOLD(i) (0x00204098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_THRESHOLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBP1_CONTROL(i) (0x0020409C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_RELEASE(i) (0x002040A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RELEASE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP1_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT0(i) (0x002040A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWCNT0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT1(i) (0x002040A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWCNT1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT2(i) (0x002040AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWCNT2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT3(i) (0x002040B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWCNT3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT4(i) (0x002040B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWCNT4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT5(i) (0x002040B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWCNT5__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT6(i) (0x002040BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWCNT6__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWCNT7(i) (0x002040C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWCNT7__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_RAWSMPLCNT(i) (0x002040C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_RAWSMPLCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS(i) (0x002040C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0(i) (0x002040CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1(i) (0x002040D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW2(i) (0x002040D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_WBSKEW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0(i) (0x002040D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1(i) (0x002040DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_STARTEXPERIMENT(i) (0x002040E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_STARTEXPERIMENT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP1_CTXSW0(i) (0x002040E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CTXSW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1(i) (0x002040E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CTXSW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG(i) (0x002040EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP1_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP1_DEBUG(i) (0x002040F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_DEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBP1_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBP1_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBP1_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBP1_DAISY_DISABLE(i) (0x002040FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_DAISY_DISABLE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB(i) (0x00204108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CONTROLB__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC(i) (0x00204110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CONTROLC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLD(i) (0x00204120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CONTROLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_PERFMONID(i) (0x00204128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_PERFMONID__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CTXSW2(i) (0x00204114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CTXSW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW3(i) (0x00204118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CTXSW3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CTXSW4(i) (0x0020411C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CTXSW4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_TOTAL_TRIG_RCV(i) (0x00204124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_TOTAL_TRIG_RCV__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER(i) (0x00204130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL 0x00246200 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_GRANT 0x00246204 /* -W-4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_PMMTRIGGERCNT 0x00246208 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CTXSW0 0x0024620C /* R-E4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS 0x00246210 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_PERFMONSTATUS 0x00246214 /* R--4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2 0x00246218 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMFBP_FBP1ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG 0x0024621C /* RW-4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_RECORD_DEBUG 0x00246354 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG 0x00246350 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP1ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL(i) (0x00204100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL11 0x00205700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL11_LTC1_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL10 0x00205500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL10_LTC1_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL9 0x00205300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL9_LTC1_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL8 0x00205100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL8_LTC1_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL7 0x00204F00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL7_LTC0_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL6 0x00204D00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL6_LTC0_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL5 0x00204B00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL5_LTC0_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL4 0x00204900 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL4_LTC0_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL3 0x00204700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL3_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL2 0x00204500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL2_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL1 0x00204300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL1_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0 0x00204100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0_LTC0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0_LTC1 1:1 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0_PMMFBP_ROUTER 2:2 /* RWXUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP1_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2 0x0020BFFF:0x00208000 /* RW--D */ #define NV_PERF_PMMFBP_FBP2ROUTER 0x002465FF:0x00246400 /* RW--D */ #define NV_PERF_PMMFBP_FBP2ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL(i) (0x00208000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL(i) (0x00208004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL(i) (0x00208008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL(i) (0x0020800C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL(i) (0x00208010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL(i) (0x00208014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC(i) (0x00208020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC(i) (0x00208024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC(i) (0x00208028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC(i) (0x0020802C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC(i) (0x00208030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC(i) (0x00208034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_TRIG0_SEL(i) (0x00208040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_TRIG0_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP(i) (0x00208044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG1_SEL(i) (0x00208048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_TRIG1_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP(i) (0x0020804C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_EVENT_SEL(i) (0x00208050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_EVENT_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP(i) (0x00208054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL(i) (0x00208058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP(i) (0x0020805C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP(i) (0x00208060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP(i) (0x00208064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SELECTMUX(i) (0x00208068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMFBP_FBP2_SELECTMUX__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_ENGINE_SEL(i) (0x0020806C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_ENGINE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_ELAPSED(i) (0x00208070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_ELAPSED__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_MODEC5CNT(i) (0x00208074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_MODEC5CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CYCLECNT(i) (0x00208078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CYCLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_MODEC6CNT(i) (0x0020807C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_MODEC6CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_EVENTCNT(i) (0x00208080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_EVENTCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER(i) (0x00208084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_THRESHCNT(i) (0x00208088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_THRESHCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_TRIGGERCNT(i) (0x0020808C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_TRIGGERCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_SAMPLECNT(i) (0x00208090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_SAMPLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_THRESHOLD(i) (0x00208098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_THRESHOLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBP2_CONTROL(i) (0x0020809C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_RELEASE(i) (0x002080A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RELEASE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP2_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT0(i) (0x002080A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWCNT0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT1(i) (0x002080A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWCNT1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT2(i) (0x002080AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWCNT2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT3(i) (0x002080B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWCNT3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT4(i) (0x002080B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWCNT4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT5(i) (0x002080B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWCNT5__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT6(i) (0x002080BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWCNT6__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWCNT7(i) (0x002080C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWCNT7__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_RAWSMPLCNT(i) (0x002080C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_RAWSMPLCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS(i) (0x002080C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0(i) (0x002080CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1(i) (0x002080D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW2(i) (0x002080D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_WBSKEW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0(i) (0x002080D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1(i) (0x002080DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_STARTEXPERIMENT(i) (0x002080E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_STARTEXPERIMENT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP2_CTXSW0(i) (0x002080E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CTXSW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1(i) (0x002080E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CTXSW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG(i) (0x002080EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP2_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP2_DEBUG(i) (0x002080F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_DEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBP2_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBP2_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBP2_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBP2_DAISY_DISABLE(i) (0x002080FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_DAISY_DISABLE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB(i) (0x00208108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CONTROLB__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC(i) (0x00208110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CONTROLC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLD(i) (0x00208120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CONTROLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_PERFMONID(i) (0x00208128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_PERFMONID__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CTXSW2(i) (0x00208114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CTXSW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW3(i) (0x00208118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CTXSW3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CTXSW4(i) (0x0020811C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CTXSW4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_TOTAL_TRIG_RCV(i) (0x00208124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_TOTAL_TRIG_RCV__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER(i) (0x00208130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL 0x00246400 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_GRANT 0x00246404 /* -W-4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_PMMTRIGGERCNT 0x00246408 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CTXSW0 0x0024640C /* R-E4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS 0x00246410 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_PERFMONSTATUS 0x00246414 /* R--4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2 0x00246418 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMFBP_FBP2ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG 0x0024641C /* RW-4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_RECORD_DEBUG 0x00246554 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG 0x00246550 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP2ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL(i) (0x00208100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL11 0x00209700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL11_LTC1_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL10 0x00209500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL10_LTC1_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL9 0x00209300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL9_LTC1_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL8 0x00209100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL8_LTC1_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL7 0x00208F00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL7_LTC0_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL6 0x00208D00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL6_LTC0_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL5 0x00208B00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL5_LTC0_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL4 0x00208900 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL4_LTC0_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL3 0x00208700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL3_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL2 0x00208500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL2_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL1 0x00208300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL1_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0 0x00208100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0_LTC0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0_LTC1 1:1 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0_PMMFBP_ROUTER 2:2 /* RWXUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP2_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3 0x0020FFFF:0x0020C000 /* RW--D */ #define NV_PERF_PMMFBP_FBP3ROUTER 0x002467FF:0x00246600 /* RW--D */ #define NV_PERF_PMMFBP_FBP3ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL(i) (0x0020C000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL(i) (0x0020C004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL(i) (0x0020C008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL(i) (0x0020C00C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL(i) (0x0020C010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL(i) (0x0020C014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC(i) (0x0020C020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC(i) (0x0020C024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC(i) (0x0020C028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC(i) (0x0020C02C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC(i) (0x0020C030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC(i) (0x0020C034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_TRIG0_SEL(i) (0x0020C040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_TRIG0_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP(i) (0x0020C044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG1_SEL(i) (0x0020C048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_TRIG1_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP(i) (0x0020C04C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_EVENT_SEL(i) (0x0020C050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_EVENT_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP(i) (0x0020C054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL(i) (0x0020C058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP(i) (0x0020C05C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP(i) (0x0020C060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP(i) (0x0020C064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SELECTMUX(i) (0x0020C068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMFBP_FBP3_SELECTMUX__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_ENGINE_SEL(i) (0x0020C06C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_ENGINE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_ELAPSED(i) (0x0020C070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_ELAPSED__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_MODEC5CNT(i) (0x0020C074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_MODEC5CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CYCLECNT(i) (0x0020C078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CYCLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_MODEC6CNT(i) (0x0020C07C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_MODEC6CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_EVENTCNT(i) (0x0020C080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_EVENTCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER(i) (0x0020C084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_THRESHCNT(i) (0x0020C088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_THRESHCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_TRIGGERCNT(i) (0x0020C08C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_TRIGGERCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_SAMPLECNT(i) (0x0020C090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_SAMPLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_THRESHOLD(i) (0x0020C098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_THRESHOLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBP3_CONTROL(i) (0x0020C09C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_RELEASE(i) (0x0020C0A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RELEASE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP3_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT0(i) (0x0020C0A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWCNT0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT1(i) (0x0020C0A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWCNT1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT2(i) (0x0020C0AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWCNT2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT3(i) (0x0020C0B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWCNT3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT4(i) (0x0020C0B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWCNT4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT5(i) (0x0020C0B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWCNT5__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT6(i) (0x0020C0BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWCNT6__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWCNT7(i) (0x0020C0C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWCNT7__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_RAWSMPLCNT(i) (0x0020C0C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_RAWSMPLCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS(i) (0x0020C0C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0(i) (0x0020C0CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1(i) (0x0020C0D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW2(i) (0x0020C0D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_WBSKEW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0(i) (0x0020C0D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1(i) (0x0020C0DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_STARTEXPERIMENT(i) (0x0020C0E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_STARTEXPERIMENT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP3_CTXSW0(i) (0x0020C0E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CTXSW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1(i) (0x0020C0E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CTXSW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG(i) (0x0020C0EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP3_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP3_DEBUG(i) (0x0020C0F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_DEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBP3_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBP3_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBP3_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBP3_DAISY_DISABLE(i) (0x0020C0FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_DAISY_DISABLE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB(i) (0x0020C108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CONTROLB__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC(i) (0x0020C110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CONTROLC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLD(i) (0x0020C120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CONTROLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_PERFMONID(i) (0x0020C128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_PERFMONID__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CTXSW2(i) (0x0020C114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CTXSW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW3(i) (0x0020C118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CTXSW3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CTXSW4(i) (0x0020C11C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CTXSW4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_TOTAL_TRIG_RCV(i) (0x0020C124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_TOTAL_TRIG_RCV__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER(i) (0x0020C130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL 0x00246600 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_GRANT 0x00246604 /* -W-4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_PMMTRIGGERCNT 0x00246608 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CTXSW0 0x0024660C /* R-E4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS 0x00246610 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_PERFMONSTATUS 0x00246614 /* R--4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2 0x00246618 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMFBP_FBP3ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG 0x0024661C /* RW-4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_RECORD_DEBUG 0x00246754 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG 0x00246750 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP3ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL(i) (0x0020C100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL11 0x0020D700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL11_LTC1_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL10 0x0020D500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL10_LTC1_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL9 0x0020D300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL9_LTC1_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL8 0x0020D100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL8_LTC1_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL7 0x0020CF00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL7_LTC0_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL6 0x0020CD00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL6_LTC0_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL5 0x0020CB00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL5_LTC0_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL4 0x0020C900 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL4_LTC0_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL3 0x0020C700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL3_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL2 0x0020C500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL2_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL1 0x0020C300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL1_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0 0x0020C100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0_LTC0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0_LTC1 1:1 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0_PMMFBP_ROUTER 2:2 /* RWXUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP3_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4 0x00213FFF:0x00210000 /* RW--D */ #define NV_PERF_PMMFBP_FBP4ROUTER 0x002469FF:0x00246800 /* RW--D */ #define NV_PERF_PMMFBP_FBP4ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL(i) (0x00210000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL(i) (0x00210004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL(i) (0x00210008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL(i) (0x0021000C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL(i) (0x00210010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL(i) (0x00210014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC(i) (0x00210020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC(i) (0x00210024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC(i) (0x00210028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC(i) (0x0021002C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC(i) (0x00210030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC(i) (0x00210034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_TRIG0_SEL(i) (0x00210040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_TRIG0_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP(i) (0x00210044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG1_SEL(i) (0x00210048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_TRIG1_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP(i) (0x0021004C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_EVENT_SEL(i) (0x00210050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_EVENT_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP(i) (0x00210054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL(i) (0x00210058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP(i) (0x0021005C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP(i) (0x00210060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP(i) (0x00210064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SELECTMUX(i) (0x00210068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMFBP_FBP4_SELECTMUX__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_ENGINE_SEL(i) (0x0021006C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_ENGINE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_ELAPSED(i) (0x00210070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_ELAPSED__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_MODEC5CNT(i) (0x00210074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_MODEC5CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CYCLECNT(i) (0x00210078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CYCLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_MODEC6CNT(i) (0x0021007C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_MODEC6CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_EVENTCNT(i) (0x00210080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_EVENTCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER(i) (0x00210084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_THRESHCNT(i) (0x00210088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_THRESHCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_TRIGGERCNT(i) (0x0021008C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_TRIGGERCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_SAMPLECNT(i) (0x00210090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_SAMPLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_THRESHOLD(i) (0x00210098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_THRESHOLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBP4_CONTROL(i) (0x0021009C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_RELEASE(i) (0x002100A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RELEASE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP4_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT0(i) (0x002100A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWCNT0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT1(i) (0x002100A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWCNT1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT2(i) (0x002100AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWCNT2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT3(i) (0x002100B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWCNT3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT4(i) (0x002100B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWCNT4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT5(i) (0x002100B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWCNT5__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT6(i) (0x002100BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWCNT6__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWCNT7(i) (0x002100C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWCNT7__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_RAWSMPLCNT(i) (0x002100C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_RAWSMPLCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS(i) (0x002100C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0(i) (0x002100CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1(i) (0x002100D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW2(i) (0x002100D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_WBSKEW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0(i) (0x002100D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1(i) (0x002100DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_STARTEXPERIMENT(i) (0x002100E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_STARTEXPERIMENT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP4_CTXSW0(i) (0x002100E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CTXSW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1(i) (0x002100E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CTXSW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG(i) (0x002100EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP4_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP4_DEBUG(i) (0x002100F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_DEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBP4_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBP4_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBP4_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBP4_DAISY_DISABLE(i) (0x002100FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_DAISY_DISABLE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB(i) (0x00210108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CONTROLB__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC(i) (0x00210110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CONTROLC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLD(i) (0x00210120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CONTROLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_PERFMONID(i) (0x00210128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_PERFMONID__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CTXSW2(i) (0x00210114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CTXSW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW3(i) (0x00210118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CTXSW3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CTXSW4(i) (0x0021011C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CTXSW4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_TOTAL_TRIG_RCV(i) (0x00210124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_TOTAL_TRIG_RCV__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER(i) (0x00210130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL 0x00246800 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_GRANT 0x00246804 /* -W-4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_PMMTRIGGERCNT 0x00246808 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CTXSW0 0x0024680C /* R-E4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS 0x00246810 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_PERFMONSTATUS 0x00246814 /* R--4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2 0x00246818 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMFBP_FBP4ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG 0x0024681C /* RW-4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_RECORD_DEBUG 0x00246954 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG 0x00246950 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP4ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL(i) (0x00210100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL11 0x00211700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL11_LTC1_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL10 0x00211500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL10_LTC1_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL9 0x00211300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL9_LTC1_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL8 0x00211100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL8_LTC1_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL7 0x00210F00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL7_LTC0_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL6 0x00210D00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL6_LTC0_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL5 0x00210B00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL5_LTC0_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL4 0x00210900 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL4_LTC0_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL3 0x00210700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL3_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL2 0x00210500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL2_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL1 0x00210300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL1_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0 0x00210100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0_LTC0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0_LTC1 1:1 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0_PMMFBP_ROUTER 2:2 /* RWXUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP4_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5 0x00217FFF:0x00214000 /* RW--D */ #define NV_PERF_PMMFBP_FBP5ROUTER 0x00246BFF:0x00246A00 /* RW--D */ #define NV_PERF_PMMFBP_FBP5ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL(i) (0x00214000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL(i) (0x00214004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL(i) (0x00214008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL(i) (0x0021400C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL(i) (0x00214010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL(i) (0x00214014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC(i) (0x00214020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC(i) (0x00214024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC(i) (0x00214028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC(i) (0x0021402C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC(i) (0x00214030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC(i) (0x00214034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_TRIG0_SEL(i) (0x00214040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_TRIG0_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP(i) (0x00214044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG1_SEL(i) (0x00214048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_TRIG1_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP(i) (0x0021404C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_EVENT_SEL(i) (0x00214050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_EVENT_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP(i) (0x00214054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL(i) (0x00214058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP(i) (0x0021405C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP(i) (0x00214060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP(i) (0x00214064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SELECTMUX(i) (0x00214068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMFBP_FBP5_SELECTMUX__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_ENGINE_SEL(i) (0x0021406C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_ENGINE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_ELAPSED(i) (0x00214070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_ELAPSED__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_MODEC5CNT(i) (0x00214074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_MODEC5CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CYCLECNT(i) (0x00214078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CYCLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_MODEC6CNT(i) (0x0021407C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_MODEC6CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_EVENTCNT(i) (0x00214080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_EVENTCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER(i) (0x00214084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_THRESHCNT(i) (0x00214088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_THRESHCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_TRIGGERCNT(i) (0x0021408C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_TRIGGERCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_SAMPLECNT(i) (0x00214090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_SAMPLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_THRESHOLD(i) (0x00214098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_THRESHOLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBP5_CONTROL(i) (0x0021409C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_RELEASE(i) (0x002140A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RELEASE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP5_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT0(i) (0x002140A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWCNT0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT1(i) (0x002140A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWCNT1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT2(i) (0x002140AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWCNT2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT3(i) (0x002140B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWCNT3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT4(i) (0x002140B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWCNT4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT5(i) (0x002140B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWCNT5__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT6(i) (0x002140BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWCNT6__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWCNT7(i) (0x002140C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWCNT7__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_RAWSMPLCNT(i) (0x002140C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_RAWSMPLCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS(i) (0x002140C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0(i) (0x002140CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1(i) (0x002140D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW2(i) (0x002140D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_WBSKEW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0(i) (0x002140D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1(i) (0x002140DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_STARTEXPERIMENT(i) (0x002140E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_STARTEXPERIMENT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP5_CTXSW0(i) (0x002140E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CTXSW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1(i) (0x002140E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CTXSW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG(i) (0x002140EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP5_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP5_DEBUG(i) (0x002140F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_DEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBP5_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBP5_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBP5_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBP5_DAISY_DISABLE(i) (0x002140FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_DAISY_DISABLE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB(i) (0x00214108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CONTROLB__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC(i) (0x00214110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CONTROLC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLD(i) (0x00214120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CONTROLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_PERFMONID(i) (0x00214128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_PERFMONID__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CTXSW2(i) (0x00214114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CTXSW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW3(i) (0x00214118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CTXSW3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CTXSW4(i) (0x0021411C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CTXSW4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_TOTAL_TRIG_RCV(i) (0x00214124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_TOTAL_TRIG_RCV__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER(i) (0x00214130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL 0x00246A00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_GRANT 0x00246A04 /* -W-4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_PMMTRIGGERCNT 0x00246A08 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CTXSW0 0x00246A0C /* R-E4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS 0x00246A10 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_PERFMONSTATUS 0x00246A14 /* R--4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2 0x00246A18 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMFBP_FBP5ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG 0x00246A1C /* RW-4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_RECORD_DEBUG 0x00246B54 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG 0x00246B50 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBP5ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL(i) (0x00214100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL11 0x00215700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL11_LTC1_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL10 0x00215500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL10_LTC1_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL9 0x00215300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL9_LTC1_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL8 0x00215100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL8_LTC1_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL7 0x00214F00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL7_LTC0_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL6 0x00214D00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL6_LTC0_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL5 0x00214B00 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL5_LTC0_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL4 0x00214900 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL4_LTC0_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL3 0x00214700 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL3_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL2 0x00214500 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL2_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL1 0x00214300 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL1_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0 0x00214100 /* RW-4R */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0_LTC0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0_LTC1 1:1 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0_PMMFBP_ROUTER 2:2 /* RWXUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBP5_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA 0x002509FF:0x00250800 /* RW--D */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT0_INPUTSEL 0x00250800 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT1_INPUTSEL 0x00250804 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT2_INPUTSEL 0x00250808 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT3_INPUTSEL 0x0025080C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT4_INPUTSEL 0x00250810 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT5_INPUTSEL 0x00250814 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC 0x00250820 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC 0x00250824 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC 0x00250828 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC 0x0025082C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC 0x00250830 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC 0x00250834 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_SEL 0x00250840 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP 0x00250844 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_SEL 0x00250848 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP 0x0025084C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_SEL 0x00250850 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP 0x00250854 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_SEL 0x00250858 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP 0x0025085C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP 0x00250860 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP 0x00250864 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX 0x00250868 /* R--4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINE_SEL 0x0025086C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ELAPSED 0x00250870 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC5CNT 0x00250874 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CYCLECNT 0x00250878 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC6CNT 0x0025087C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENTCNT 0x00250880 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DFD_CNT_UPPER 0x00250884 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHCNT 0x00250888 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIGGERCNT 0x0025088C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLECNT 0x00250890 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHOLD 0x00250898 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL 0x0025089C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RELEASE 0x002508A0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT0 0x002508A4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT1 0x002508A8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT2 0x002508AC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT3 0x002508B0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT4 0x002508B4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT5 0x002508B8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT6 0x002508BC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT7 0x002508C0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWSMPLCNT 0x002508C4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS 0x002508C8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0 0x002508CC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1 0x002508D0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW2 0x002508D4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0 0x002508D8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1 0x002508DC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_STARTEXPERIMENT 0x002508E0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0 0x002508E4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1 0x002508E8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG 0x002508EC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DEBUG 0x002508F8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DAISY_DISABLE 0x002508FC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB 0x00250908 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC 0x00250910 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLD 0x00250920 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_PERFMONID 0x00250928 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW2 0x00250914 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW3 0x00250918 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW4 0x0025091C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TOTAL_TRIG_RCV 0x00250924 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER 0x00250930 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLAMP_CYA_CONTROL 0x00250900 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPA_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS 0x00250BFF:0x00250A00 /* RW--D */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT0_INPUTSEL 0x00250A00 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT1_INPUTSEL 0x00250A04 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT2_INPUTSEL 0x00250A08 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT3_INPUTSEL 0x00250A0C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT4_INPUTSEL 0x00250A10 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT5_INPUTSEL 0x00250A14 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC 0x00250A20 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC 0x00250A24 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC 0x00250A28 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC 0x00250A2C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC 0x00250A30 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC 0x00250A34 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_SEL 0x00250A40 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP 0x00250A44 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_SEL 0x00250A48 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP 0x00250A4C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_SEL 0x00250A50 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP 0x00250A54 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_SEL 0x00250A58 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP 0x00250A5C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP 0x00250A60 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP 0x00250A64 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX 0x00250A68 /* R--4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINE_SEL 0x00250A6C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ELAPSED 0x00250A70 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC5CNT 0x00250A74 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CYCLECNT 0x00250A78 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC6CNT 0x00250A7C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENTCNT 0x00250A80 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DFD_CNT_UPPER 0x00250A84 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHCNT 0x00250A88 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIGGERCNT 0x00250A8C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLECNT 0x00250A90 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHOLD 0x00250A98 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL 0x00250A9C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RELEASE 0x00250AA0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT0 0x00250AA4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT1 0x00250AA8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT2 0x00250AAC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT3 0x00250AB0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT4 0x00250AB4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT5 0x00250AB8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT6 0x00250ABC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT7 0x00250AC0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWSMPLCNT 0x00250AC4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS 0x00250AC8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0 0x00250ACC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1 0x00250AD0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW2 0x00250AD4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0 0x00250AD8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1 0x00250ADC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_STARTEXPERIMENT 0x00250AE0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0 0x00250AE4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1 0x00250AE8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG 0x00250AEC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DEBUG 0x00250AF8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DAISY_DISABLE 0x00250AFC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB 0x00250B08 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC 0x00250B10 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLD 0x00250B20 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_PERFMONID 0x00250B28 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW2 0x00250B14 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW3 0x00250B18 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW4 0x00250B1C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TOTAL_TRIG_RCV 0x00250B24 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER 0x00250B30 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLAMP_CYA_CONTROL 0x00250B00 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_FBPAS_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS 0x00250DFF:0x00250C00 /* RW--D */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT0_INPUTSEL 0x00250C00 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT1_INPUTSEL 0x00250C04 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT2_INPUTSEL 0x00250C08 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT3_INPUTSEL 0x00250C0C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT4_INPUTSEL 0x00250C10 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT5_INPUTSEL 0x00250C14 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC 0x00250C20 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC 0x00250C24 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC 0x00250C28 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC 0x00250C2C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC 0x00250C30 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC 0x00250C34 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_SEL 0x00250C40 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP 0x00250C44 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_SEL 0x00250C48 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP 0x00250C4C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_SEL 0x00250C50 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP 0x00250C54 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_SEL 0x00250C58 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP 0x00250C5C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP 0x00250C60 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP 0x00250C64 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX 0x00250C68 /* R--4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINE_SEL 0x00250C6C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ELAPSED 0x00250C70 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC5CNT 0x00250C74 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CYCLECNT 0x00250C78 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC6CNT 0x00250C7C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENTCNT 0x00250C80 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DFD_CNT_UPPER 0x00250C84 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHCNT 0x00250C88 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIGGERCNT 0x00250C8C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLECNT 0x00250C90 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHOLD 0x00250C98 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL 0x00250C9C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RELEASE 0x00250CA0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT0 0x00250CA4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT1 0x00250CA8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT2 0x00250CAC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT3 0x00250CB0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT4 0x00250CB4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT5 0x00250CB8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT6 0x00250CBC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT7 0x00250CC0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWSMPLCNT 0x00250CC4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS 0x00250CC8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0 0x00250CCC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1 0x00250CD0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW2 0x00250CD4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0 0x00250CD8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1 0x00250CDC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_STARTEXPERIMENT 0x00250CE0 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0 0x00250CE4 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1 0x00250CE8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG 0x00250CEC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DEBUG 0x00250CF8 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DAISY_DISABLE 0x00250CFC /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB 0x00250D08 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC 0x00250D10 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLD 0x00250D20 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_PERFMONID 0x00250D28 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW2 0x00250D14 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW3 0x00250D18 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW4 0x00250D1C /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TOTAL_TRIG_RCV 0x00250D24 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER 0x00250D30 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLAMP_CYA_CONTROL 0x00250D00 /* RW-4R */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPGS_LTCS_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS 0x0027FFFF:0x0027C000 /* RW--D */ #define NV_PERF_PMMFBP_FBPSROUTER 0x00251BFF:0x00251A00 /* RW--D */ #define NV_PERF_PMMFBP_FBPSROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL(i) (0x0027C000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL(i) (0x0027C004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL(i) (0x0027C008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL(i) (0x0027C00C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL(i) (0x0027C010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL(i) (0x0027C014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC(i) (0x0027C020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC(i) (0x0027C024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC(i) (0x0027C028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC(i) (0x0027C02C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC(i) (0x0027C030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC(i) (0x0027C034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_TRIG0_SEL(i) (0x0027C040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_TRIG0_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP(i) (0x0027C044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG1_SEL(i) (0x0027C048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_TRIG1_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP(i) (0x0027C04C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_EVENT_SEL(i) (0x0027C050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_EVENT_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP(i) (0x0027C054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL(i) (0x0027C058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP(i) (0x0027C05C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP(i) (0x0027C060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP(i) (0x0027C064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SELECTMUX(i) (0x0027C068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMFBP_FBPS_SELECTMUX__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_ENGINE_SEL(i) (0x0027C06C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_ENGINE_SEL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_ELAPSED(i) (0x0027C070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_ELAPSED__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_MODEC5CNT(i) (0x0027C074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_MODEC5CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CYCLECNT(i) (0x0027C078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CYCLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_MODEC6CNT(i) (0x0027C07C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_MODEC6CNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_EVENTCNT(i) (0x0027C080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_EVENTCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER(i) (0x0027C084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_THRESHCNT(i) (0x0027C088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_THRESHCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_TRIGGERCNT(i) (0x0027C08C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_TRIGGERCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_SAMPLECNT(i) (0x0027C090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_SAMPLECNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_THRESHOLD(i) (0x0027C098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_THRESHOLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMFBP_FBPS_CONTROL(i) (0x0027C09C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_RELEASE(i) (0x0027C0A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RELEASE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBPS_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT0(i) (0x0027C0A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWCNT0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT1(i) (0x0027C0A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWCNT1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT2(i) (0x0027C0AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWCNT2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT3(i) (0x0027C0B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWCNT3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT4(i) (0x0027C0B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWCNT4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT5(i) (0x0027C0B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWCNT5__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT6(i) (0x0027C0BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWCNT6__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWCNT7(i) (0x0027C0C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWCNT7__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_RAWSMPLCNT(i) (0x0027C0C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_RAWSMPLCNT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS(i) (0x0027C0C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0(i) (0x0027C0CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1(i) (0x0027C0D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW2(i) (0x0027C0D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_WBSKEW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0(i) (0x0027C0D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1(i) (0x0027C0DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_STARTEXPERIMENT(i) (0x0027C0E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_STARTEXPERIMENT__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPS_CTXSW0(i) (0x0027C0E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CTXSW0__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1(i) (0x0027C0E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CTXSW1__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG(i) (0x0027C0EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBPS_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPS_DEBUG(i) (0x0027C0F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_DEBUG__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMFBP_FBPS_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMFBP_FBPS_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMFBP_FBPS_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMFBP_FBPS_DAISY_DISABLE(i) (0x0027C0FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_DAISY_DISABLE__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB(i) (0x0027C108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CONTROLB__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC(i) (0x0027C110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CONTROLC__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLD(i) (0x0027C120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CONTROLD__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_PERFMONID(i) (0x0027C128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_PERFMONID__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CTXSW2(i) (0x0027C114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CTXSW2__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW3(i) (0x0027C118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CTXSW3__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CTXSW4(i) (0x0027C11C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CTXSW4__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_TOTAL_TRIG_RCV(i) (0x0027C124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_TOTAL_TRIG_RCV__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER(i) (0x0027C130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMFBP_FBPS_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL 0x00251A00 /* RW-4R */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_GRANT 0x00251A04 /* -W-4R */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_PMMTRIGGERCNT 0x00251A08 /* RW-4R */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CTXSW0 0x00251A0C /* R-E4R */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBPSROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS 0x00251A10 /* RW-4R */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_PERFMONSTATUS 0x00251A14 /* R--4R */ #define NV_PERF_PMMFBP_FBPSROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2 0x00251A18 /* RW-4R */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMFBP_FBPSROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG 0x00251A1C /* RW-4R */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPSROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_RECORD_DEBUG 0x00251B54 /* RW-4R */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG 0x00251B50 /* RW-4R */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMFBP_FBPSROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL(i) (0x0027C100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL__SIZE_1 12 /* */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL11 0x0027D700 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL11_LTC1_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL10 0x0027D500 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL10_LTC1_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL9 0x0027D300 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL9_LTC1_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL8 0x0027D100 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL8_LTC1_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL7 0x0027CF00 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL7_LTC0_LTS3 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL6 0x0027CD00 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL6_LTC0_LTS2 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL5 0x0027CB00 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL5_LTC0_LTS1 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL4 0x0027C900 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL4_LTC0_LTS0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL3 0x0027C700 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL3_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL2 0x0027C500 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL2_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL1 0x0027C300 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL1_FB_PA0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0 0x0027C100 /* RW-4R */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0_LTC0 0:0 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0_LTC1 1:1 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0_PMMFBP_ROUTER 2:2 /* RWXUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMFBP_FBPS_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_PERDOMAIN_OFFSET 0x00000200 /* */ #define NV_PERF_PMMGPC 0x00183FFF:0x00180000 /* RW--D */ #define NV_PERF_PMMGPCROUTER 0x002441FF:0x00244000 /* RW--D */ #define NV_PERF_PMMGPCROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_FT0_INPUTSEL(i) (0x00180000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_FT1_INPUTSEL(i) (0x00180004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_FT2_INPUTSEL(i) (0x00180008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_FT3_INPUTSEL(i) (0x0018000C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_FT4_INPUTSEL(i) (0x00180010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_FT5_INPUTSEL(i) (0x00180014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR0_INC(i) (0x00180020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC(i) (0x00180024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC(i) (0x00180028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC(i) (0x0018002C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC(i) (0x00180030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC(i) (0x00180034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_TRIG0_SEL(i) (0x00180040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_TRIG0_OP(i) (0x00180044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG1_SEL(i) (0x00180048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_TRIG1_OP(i) (0x0018004C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_EVENT_SEL(i) (0x00180050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_EVENT_OP(i) (0x00180054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SAMPLE_SEL(i) (0x00180058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_SAMPLE_OP(i) (0x0018005C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SETFLAG_OP(i) (0x00180060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CLRFLAG_OP(i) (0x00180064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SELECTMUX(i) (0x00180068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_ENGINE_SEL(i) (0x0018006C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_ELAPSED(i) (0x00180070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_MODEC5CNT(i) (0x00180074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CYCLECNT(i) (0x00180078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_MODEC6CNT(i) (0x0018007C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_EVENTCNT(i) (0x00180080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_DFD_CNT_UPPER(i) (0x00180084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_THRESHCNT(i) (0x00180088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_TRIGGERCNT(i) (0x0018008C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_SAMPLECNT(i) (0x00180090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_THRESHOLD(i) (0x00180098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_CONTROL(i) (0x0018009C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_RELEASE(i) (0x001800A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT0(i) (0x001800A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT1(i) (0x001800A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT2(i) (0x001800AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT3(i) (0x001800B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT4(i) (0x001800B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT5(i) (0x001800B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT6(i) (0x001800BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWCNT7(i) (0x001800C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_RAWSMPLCNT(i) (0x001800C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_ENGINESTATUS(i) (0x001800C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_WBSKEW0(i) (0x001800CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW1(i) (0x001800D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW2(i) (0x001800D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0(i) (0x001800D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1(i) (0x001800DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_STARTEXPERIMENT(i) (0x001800E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_CTXSW0(i) (0x001800E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1(i) (0x001800E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG(i) (0x001800EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_DEBUG(i) (0x001800F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_DAISY_DISABLE(i) (0x001800FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_CONTROLB(i) (0x00180108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLC(i) (0x00180110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLD(i) (0x00180120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_PERFMONID(i) (0x00180128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CTXSW2(i) (0x00180114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW3(i) (0x00180118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_CTXSW4(i) (0x0018011C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_TOTAL_TRIG_RCV(i) (0x00180124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_FLAG_BIT_TIMER(i) (0x00180130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL 0x00244000 /* RW-4R */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPCROUTER_RECORD_GRANT 0x00244004 /* -W-4R */ #define NV_PERF_PMMGPCROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPCROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPCROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_PMMTRIGGERCNT 0x00244008 /* RW-4R */ #define NV_PERF_PMMGPCROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CTXSW0 0x0024400C /* R-E4R */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPCROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS 0x00244010 /* RW-4R */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPCROUTER_PERFMONSTATUS 0x00244014 /* R--4R */ #define NV_PERF_PMMGPCROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPCROUTER_CG2 0x00244018 /* RW-4R */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPCROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPCROUTER_RECORD_DEBUG 0x0024401C /* RW-4R */ #define NV_PERF_PMMGPCROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPCROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPCROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPCROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPCROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPCROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPCROUTER_HS_RECORD_DEBUG 0x00244154 /* RW-4R */ #define NV_PERF_PMMGPCROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPCROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPCROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPCROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPCROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPCROUTER_HS_CONFIG 0x00244150 /* RW-4R */ #define NV_PERF_PMMGPCROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPCROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPCROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPCROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPCROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPCROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL(i) (0x00180100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21 0x00182B00 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20 0x00182900 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19 0x00182700 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18 0x00182500 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17 0x00182300 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16 0x00182100 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15 0x00181F00 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14 0x00181D00 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13 0x00181B00 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12 0x00181900 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11 0x00181700 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10 0x00181500 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9 0x00181300 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8 0x00181100 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7 0x00180F00 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6 0x00180D00 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5 0x00180B00 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4 0x00180900 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3 0x00180700 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2 0x00180500 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1 0x00180300 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0 0x00180100 /* RW-4R */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0 0x00183FFF:0x00180000 /* RW--D */ #define NV_PERF_PMMGPC_GPC0ROUTER 0x002441FF:0x00244000 /* RW--D */ #define NV_PERF_PMMGPC_GPC0ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL(i) (0x00180000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL(i) (0x00180004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL(i) (0x00180008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL(i) (0x0018000C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL(i) (0x00180010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL(i) (0x00180014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC(i) (0x00180020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC(i) (0x00180024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC(i) (0x00180028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC(i) (0x0018002C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC(i) (0x00180030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC(i) (0x00180034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_TRIG0_SEL(i) (0x00180040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP(i) (0x00180044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG1_SEL(i) (0x00180048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP(i) (0x0018004C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_EVENT_SEL(i) (0x00180050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP(i) (0x00180054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL(i) (0x00180058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP(i) (0x0018005C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP(i) (0x00180060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP(i) (0x00180064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SELECTMUX(i) (0x00180068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_GPC0_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_ENGINE_SEL(i) (0x0018006C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_ELAPSED(i) (0x00180070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_MODEC5CNT(i) (0x00180074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CYCLECNT(i) (0x00180078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_MODEC6CNT(i) (0x0018007C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_EVENTCNT(i) (0x00180080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER(i) (0x00180084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_THRESHCNT(i) (0x00180088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_TRIGGERCNT(i) (0x0018008C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_SAMPLECNT(i) (0x00180090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_THRESHOLD(i) (0x00180098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPC0_CONTROL(i) (0x0018009C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_RELEASE(i) (0x001800A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC0_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT0(i) (0x001800A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT1(i) (0x001800A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT2(i) (0x001800AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT3(i) (0x001800B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT4(i) (0x001800B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT5(i) (0x001800B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT6(i) (0x001800BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWCNT7(i) (0x001800C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_RAWSMPLCNT(i) (0x001800C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS(i) (0x001800C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0(i) (0x001800CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1(i) (0x001800D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW2(i) (0x001800D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0(i) (0x001800D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1(i) (0x001800DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_STARTEXPERIMENT(i) (0x001800E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC0_CTXSW0(i) (0x001800E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1(i) (0x001800E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG(i) (0x001800EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC0_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC0_DEBUG(i) (0x001800F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPC0_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPC0_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPC0_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPC0_DAISY_DISABLE(i) (0x001800FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB(i) (0x00180108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC(i) (0x00180110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLD(i) (0x00180120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_PERFMONID(i) (0x00180128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CTXSW2(i) (0x00180114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW3(i) (0x00180118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CTXSW4(i) (0x0018011C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_TOTAL_TRIG_RCV(i) (0x00180124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER(i) (0x00180130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL 0x00244000 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_GRANT 0x00244004 /* -W-4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_PMMTRIGGERCNT 0x00244008 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CTXSW0 0x0024400C /* R-E4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS 0x00244010 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_PERFMONSTATUS 0x00244014 /* R--4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2 0x00244018 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPC_GPC0ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG 0x0024401C /* RW-4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_RECORD_DEBUG 0x00244154 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG 0x00244150 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC0ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL(i) (0x00180100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21 0x00182B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20 0x00182900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19 0x00182700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18 0x00182500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17 0x00182300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16 0x00182100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15 0x00181F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14 0x00181D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13 0x00181B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12 0x00181900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11 0x00181700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10 0x00181500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9 0x00181300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8 0x00181100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7 0x00180F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6 0x00180D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5 0x00180B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4 0x00180900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3 0x00180700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2 0x00180500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1 0x00180300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0 0x00180100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC0_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1 0x00187FFF:0x00184000 /* RW--D */ #define NV_PERF_PMMGPC_GPC1ROUTER 0x002443FF:0x00244200 /* RW--D */ #define NV_PERF_PMMGPC_GPC1ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL(i) (0x00184000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL(i) (0x00184004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL(i) (0x00184008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL(i) (0x0018400C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL(i) (0x00184010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL(i) (0x00184014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC(i) (0x00184020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC(i) (0x00184024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC(i) (0x00184028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC(i) (0x0018402C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC(i) (0x00184030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC(i) (0x00184034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_TRIG0_SEL(i) (0x00184040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP(i) (0x00184044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG1_SEL(i) (0x00184048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP(i) (0x0018404C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_EVENT_SEL(i) (0x00184050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP(i) (0x00184054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL(i) (0x00184058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP(i) (0x0018405C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP(i) (0x00184060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP(i) (0x00184064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SELECTMUX(i) (0x00184068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_GPC1_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_ENGINE_SEL(i) (0x0018406C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_ELAPSED(i) (0x00184070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_MODEC5CNT(i) (0x00184074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CYCLECNT(i) (0x00184078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_MODEC6CNT(i) (0x0018407C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_EVENTCNT(i) (0x00184080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER(i) (0x00184084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_THRESHCNT(i) (0x00184088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_TRIGGERCNT(i) (0x0018408C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_SAMPLECNT(i) (0x00184090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_THRESHOLD(i) (0x00184098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPC1_CONTROL(i) (0x0018409C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_RELEASE(i) (0x001840A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC1_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT0(i) (0x001840A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT1(i) (0x001840A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT2(i) (0x001840AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT3(i) (0x001840B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT4(i) (0x001840B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT5(i) (0x001840B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT6(i) (0x001840BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWCNT7(i) (0x001840C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_RAWSMPLCNT(i) (0x001840C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS(i) (0x001840C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0(i) (0x001840CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1(i) (0x001840D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW2(i) (0x001840D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0(i) (0x001840D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1(i) (0x001840DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_STARTEXPERIMENT(i) (0x001840E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC1_CTXSW0(i) (0x001840E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1(i) (0x001840E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG(i) (0x001840EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC1_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC1_DEBUG(i) (0x001840F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPC1_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPC1_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPC1_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPC1_DAISY_DISABLE(i) (0x001840FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB(i) (0x00184108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC(i) (0x00184110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLD(i) (0x00184120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_PERFMONID(i) (0x00184128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CTXSW2(i) (0x00184114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW3(i) (0x00184118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CTXSW4(i) (0x0018411C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_TOTAL_TRIG_RCV(i) (0x00184124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER(i) (0x00184130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL 0x00244200 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_GRANT 0x00244204 /* -W-4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_PMMTRIGGERCNT 0x00244208 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CTXSW0 0x0024420C /* R-E4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS 0x00244210 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_PERFMONSTATUS 0x00244214 /* R--4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2 0x00244218 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPC_GPC1ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG 0x0024421C /* RW-4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_RECORD_DEBUG 0x00244354 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG 0x00244350 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC1ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL(i) (0x00184100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21 0x00186B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20 0x00186900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19 0x00186700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18 0x00186500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17 0x00186300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16 0x00186100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15 0x00185F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14 0x00185D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13 0x00185B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12 0x00185900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11 0x00185700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10 0x00185500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9 0x00185300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8 0x00185100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7 0x00184F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6 0x00184D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5 0x00184B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4 0x00184900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3 0x00184700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2 0x00184500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1 0x00184300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0 0x00184100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC1_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2 0x0018BFFF:0x00188000 /* RW--D */ #define NV_PERF_PMMGPC_GPC2ROUTER 0x002445FF:0x00244400 /* RW--D */ #define NV_PERF_PMMGPC_GPC2ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL(i) (0x00188000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL(i) (0x00188004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL(i) (0x00188008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL(i) (0x0018800C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL(i) (0x00188010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL(i) (0x00188014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC(i) (0x00188020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC(i) (0x00188024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC(i) (0x00188028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC(i) (0x0018802C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC(i) (0x00188030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC(i) (0x00188034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_TRIG0_SEL(i) (0x00188040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP(i) (0x00188044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG1_SEL(i) (0x00188048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP(i) (0x0018804C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_EVENT_SEL(i) (0x00188050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP(i) (0x00188054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL(i) (0x00188058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP(i) (0x0018805C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP(i) (0x00188060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP(i) (0x00188064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SELECTMUX(i) (0x00188068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_GPC2_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_ENGINE_SEL(i) (0x0018806C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_ELAPSED(i) (0x00188070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_MODEC5CNT(i) (0x00188074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CYCLECNT(i) (0x00188078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_MODEC6CNT(i) (0x0018807C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_EVENTCNT(i) (0x00188080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER(i) (0x00188084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_THRESHCNT(i) (0x00188088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_TRIGGERCNT(i) (0x0018808C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_SAMPLECNT(i) (0x00188090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_THRESHOLD(i) (0x00188098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPC2_CONTROL(i) (0x0018809C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_RELEASE(i) (0x001880A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC2_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT0(i) (0x001880A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT1(i) (0x001880A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT2(i) (0x001880AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT3(i) (0x001880B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT4(i) (0x001880B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT5(i) (0x001880B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT6(i) (0x001880BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWCNT7(i) (0x001880C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_RAWSMPLCNT(i) (0x001880C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS(i) (0x001880C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0(i) (0x001880CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1(i) (0x001880D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW2(i) (0x001880D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0(i) (0x001880D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1(i) (0x001880DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_STARTEXPERIMENT(i) (0x001880E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC2_CTXSW0(i) (0x001880E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1(i) (0x001880E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG(i) (0x001880EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC2_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC2_DEBUG(i) (0x001880F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPC2_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPC2_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPC2_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPC2_DAISY_DISABLE(i) (0x001880FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB(i) (0x00188108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC(i) (0x00188110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLD(i) (0x00188120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_PERFMONID(i) (0x00188128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CTXSW2(i) (0x00188114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW3(i) (0x00188118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CTXSW4(i) (0x0018811C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_TOTAL_TRIG_RCV(i) (0x00188124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER(i) (0x00188130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL 0x00244400 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_GRANT 0x00244404 /* -W-4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_PMMTRIGGERCNT 0x00244408 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CTXSW0 0x0024440C /* R-E4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS 0x00244410 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_PERFMONSTATUS 0x00244414 /* R--4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2 0x00244418 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPC_GPC2ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG 0x0024441C /* RW-4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_RECORD_DEBUG 0x00244554 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG 0x00244550 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC2ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL(i) (0x00188100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21 0x0018AB00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20 0x0018A900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19 0x0018A700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18 0x0018A500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17 0x0018A300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16 0x0018A100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15 0x00189F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14 0x00189D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13 0x00189B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12 0x00189900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11 0x00189700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10 0x00189500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9 0x00189300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8 0x00189100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7 0x00188F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6 0x00188D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5 0x00188B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4 0x00188900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3 0x00188700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2 0x00188500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1 0x00188300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0 0x00188100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC2_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3 0x0018FFFF:0x0018C000 /* RW--D */ #define NV_PERF_PMMGPC_GPC3ROUTER 0x002447FF:0x00244600 /* RW--D */ #define NV_PERF_PMMGPC_GPC3ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL(i) (0x0018C000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL(i) (0x0018C004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL(i) (0x0018C008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL(i) (0x0018C00C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL(i) (0x0018C010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL(i) (0x0018C014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC(i) (0x0018C020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC(i) (0x0018C024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC(i) (0x0018C028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC(i) (0x0018C02C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC(i) (0x0018C030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC(i) (0x0018C034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_TRIG0_SEL(i) (0x0018C040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP(i) (0x0018C044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG1_SEL(i) (0x0018C048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP(i) (0x0018C04C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_EVENT_SEL(i) (0x0018C050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP(i) (0x0018C054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL(i) (0x0018C058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP(i) (0x0018C05C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP(i) (0x0018C060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP(i) (0x0018C064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SELECTMUX(i) (0x0018C068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_GPC3_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_ENGINE_SEL(i) (0x0018C06C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_ELAPSED(i) (0x0018C070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_MODEC5CNT(i) (0x0018C074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CYCLECNT(i) (0x0018C078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_MODEC6CNT(i) (0x0018C07C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_EVENTCNT(i) (0x0018C080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER(i) (0x0018C084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_THRESHCNT(i) (0x0018C088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_TRIGGERCNT(i) (0x0018C08C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_SAMPLECNT(i) (0x0018C090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_THRESHOLD(i) (0x0018C098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPC3_CONTROL(i) (0x0018C09C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_RELEASE(i) (0x0018C0A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC3_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT0(i) (0x0018C0A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT1(i) (0x0018C0A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT2(i) (0x0018C0AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT3(i) (0x0018C0B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT4(i) (0x0018C0B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT5(i) (0x0018C0B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT6(i) (0x0018C0BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWCNT7(i) (0x0018C0C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_RAWSMPLCNT(i) (0x0018C0C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS(i) (0x0018C0C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0(i) (0x0018C0CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1(i) (0x0018C0D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW2(i) (0x0018C0D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0(i) (0x0018C0D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1(i) (0x0018C0DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_STARTEXPERIMENT(i) (0x0018C0E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC3_CTXSW0(i) (0x0018C0E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1(i) (0x0018C0E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG(i) (0x0018C0EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC3_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC3_DEBUG(i) (0x0018C0F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPC3_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPC3_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPC3_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPC3_DAISY_DISABLE(i) (0x0018C0FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB(i) (0x0018C108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC(i) (0x0018C110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLD(i) (0x0018C120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_PERFMONID(i) (0x0018C128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CTXSW2(i) (0x0018C114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW3(i) (0x0018C118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CTXSW4(i) (0x0018C11C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_TOTAL_TRIG_RCV(i) (0x0018C124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER(i) (0x0018C130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL 0x00244600 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_GRANT 0x00244604 /* -W-4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_PMMTRIGGERCNT 0x00244608 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CTXSW0 0x0024460C /* R-E4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS 0x00244610 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_PERFMONSTATUS 0x00244614 /* R--4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2 0x00244618 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPC_GPC3ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG 0x0024461C /* RW-4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_RECORD_DEBUG 0x00244754 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG 0x00244750 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC3ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL(i) (0x0018C100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21 0x0018EB00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20 0x0018E900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19 0x0018E700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18 0x0018E500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17 0x0018E300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16 0x0018E100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15 0x0018DF00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14 0x0018DD00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13 0x0018DB00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12 0x0018D900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11 0x0018D700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10 0x0018D500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9 0x0018D300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8 0x0018D100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7 0x0018CF00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6 0x0018CD00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5 0x0018CB00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4 0x0018C900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3 0x0018C700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2 0x0018C500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1 0x0018C300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0 0x0018C100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC3_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4 0x00193FFF:0x00190000 /* RW--D */ #define NV_PERF_PMMGPC_GPC4ROUTER 0x002449FF:0x00244800 /* RW--D */ #define NV_PERF_PMMGPC_GPC4ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL(i) (0x00190000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL(i) (0x00190004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL(i) (0x00190008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL(i) (0x0019000C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL(i) (0x00190010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL(i) (0x00190014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC(i) (0x00190020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC(i) (0x00190024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC(i) (0x00190028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC(i) (0x0019002C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC(i) (0x00190030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC(i) (0x00190034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_TRIG0_SEL(i) (0x00190040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP(i) (0x00190044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG1_SEL(i) (0x00190048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP(i) (0x0019004C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_EVENT_SEL(i) (0x00190050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP(i) (0x00190054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL(i) (0x00190058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP(i) (0x0019005C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP(i) (0x00190060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP(i) (0x00190064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SELECTMUX(i) (0x00190068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_GPC4_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_ENGINE_SEL(i) (0x0019006C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_ELAPSED(i) (0x00190070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_MODEC5CNT(i) (0x00190074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CYCLECNT(i) (0x00190078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_MODEC6CNT(i) (0x0019007C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_EVENTCNT(i) (0x00190080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER(i) (0x00190084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_THRESHCNT(i) (0x00190088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_TRIGGERCNT(i) (0x0019008C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_SAMPLECNT(i) (0x00190090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_THRESHOLD(i) (0x00190098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPC4_CONTROL(i) (0x0019009C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_RELEASE(i) (0x001900A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC4_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT0(i) (0x001900A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT1(i) (0x001900A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT2(i) (0x001900AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT3(i) (0x001900B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT4(i) (0x001900B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT5(i) (0x001900B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT6(i) (0x001900BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWCNT7(i) (0x001900C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_RAWSMPLCNT(i) (0x001900C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS(i) (0x001900C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0(i) (0x001900CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1(i) (0x001900D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW2(i) (0x001900D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0(i) (0x001900D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1(i) (0x001900DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_STARTEXPERIMENT(i) (0x001900E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC4_CTXSW0(i) (0x001900E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1(i) (0x001900E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG(i) (0x001900EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC4_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC4_DEBUG(i) (0x001900F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPC4_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPC4_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPC4_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPC4_DAISY_DISABLE(i) (0x001900FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB(i) (0x00190108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC(i) (0x00190110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLD(i) (0x00190120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_PERFMONID(i) (0x00190128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CTXSW2(i) (0x00190114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW3(i) (0x00190118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CTXSW4(i) (0x0019011C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_TOTAL_TRIG_RCV(i) (0x00190124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER(i) (0x00190130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL 0x00244800 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_GRANT 0x00244804 /* -W-4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_PMMTRIGGERCNT 0x00244808 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CTXSW0 0x0024480C /* R-E4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS 0x00244810 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_PERFMONSTATUS 0x00244814 /* R--4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2 0x00244818 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPC_GPC4ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG 0x0024481C /* RW-4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_RECORD_DEBUG 0x00244954 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG 0x00244950 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC4ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL(i) (0x00190100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21 0x00192B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20 0x00192900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19 0x00192700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18 0x00192500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17 0x00192300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16 0x00192100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15 0x00191F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14 0x00191D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13 0x00191B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12 0x00191900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11 0x00191700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10 0x00191500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9 0x00191300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8 0x00191100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7 0x00190F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6 0x00190D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5 0x00190B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4 0x00190900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3 0x00190700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2 0x00190500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1 0x00190300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0 0x00190100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC4_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5 0x00197FFF:0x00194000 /* RW--D */ #define NV_PERF_PMMGPC_GPC5ROUTER 0x00244BFF:0x00244A00 /* RW--D */ #define NV_PERF_PMMGPC_GPC5ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL(i) (0x00194000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL(i) (0x00194004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL(i) (0x00194008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL(i) (0x0019400C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL(i) (0x00194010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL(i) (0x00194014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC(i) (0x00194020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC(i) (0x00194024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC(i) (0x00194028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC(i) (0x0019402C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC(i) (0x00194030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC(i) (0x00194034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_TRIG0_SEL(i) (0x00194040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP(i) (0x00194044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG1_SEL(i) (0x00194048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP(i) (0x0019404C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_EVENT_SEL(i) (0x00194050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP(i) (0x00194054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL(i) (0x00194058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP(i) (0x0019405C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP(i) (0x00194060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP(i) (0x00194064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SELECTMUX(i) (0x00194068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_GPC5_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_ENGINE_SEL(i) (0x0019406C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_ELAPSED(i) (0x00194070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_MODEC5CNT(i) (0x00194074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CYCLECNT(i) (0x00194078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_MODEC6CNT(i) (0x0019407C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_EVENTCNT(i) (0x00194080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER(i) (0x00194084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_THRESHCNT(i) (0x00194088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_TRIGGERCNT(i) (0x0019408C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_SAMPLECNT(i) (0x00194090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_THRESHOLD(i) (0x00194098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPC5_CONTROL(i) (0x0019409C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_RELEASE(i) (0x001940A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC5_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT0(i) (0x001940A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT1(i) (0x001940A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT2(i) (0x001940AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT3(i) (0x001940B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT4(i) (0x001940B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT5(i) (0x001940B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT6(i) (0x001940BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWCNT7(i) (0x001940C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_RAWSMPLCNT(i) (0x001940C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS(i) (0x001940C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0(i) (0x001940CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1(i) (0x001940D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW2(i) (0x001940D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0(i) (0x001940D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1(i) (0x001940DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_STARTEXPERIMENT(i) (0x001940E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC5_CTXSW0(i) (0x001940E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1(i) (0x001940E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG(i) (0x001940EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC5_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC5_DEBUG(i) (0x001940F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPC5_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPC5_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPC5_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPC5_DAISY_DISABLE(i) (0x001940FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB(i) (0x00194108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC(i) (0x00194110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLD(i) (0x00194120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_PERFMONID(i) (0x00194128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CTXSW2(i) (0x00194114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW3(i) (0x00194118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CTXSW4(i) (0x0019411C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_TOTAL_TRIG_RCV(i) (0x00194124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER(i) (0x00194130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL 0x00244A00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_GRANT 0x00244A04 /* -W-4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_PMMTRIGGERCNT 0x00244A08 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CTXSW0 0x00244A0C /* R-E4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS 0x00244A10 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_PERFMONSTATUS 0x00244A14 /* R--4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2 0x00244A18 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPC_GPC5ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG 0x00244A1C /* RW-4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_RECORD_DEBUG 0x00244B54 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG 0x00244B50 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC5ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL(i) (0x00194100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21 0x00196B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20 0x00196900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19 0x00196700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18 0x00196500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17 0x00196300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16 0x00196100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15 0x00195F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14 0x00195D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13 0x00195B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12 0x00195900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11 0x00195700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10 0x00195500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9 0x00195300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8 0x00195100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7 0x00194F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6 0x00194D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5 0x00194B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4 0x00194900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3 0x00194700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2 0x00194500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1 0x00194300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0 0x00194100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC5_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6 0x0019BFFF:0x00198000 /* RW--D */ #define NV_PERF_PMMGPC_GPC6ROUTER 0x00244DFF:0x00244C00 /* RW--D */ #define NV_PERF_PMMGPC_GPC6ROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL(i) (0x00198000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL(i) (0x00198004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL(i) (0x00198008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL(i) (0x0019800C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL(i) (0x00198010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL(i) (0x00198014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC(i) (0x00198020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC(i) (0x00198024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC(i) (0x00198028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC(i) (0x0019802C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC(i) (0x00198030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC(i) (0x00198034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_TRIG0_SEL(i) (0x00198040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP(i) (0x00198044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG1_SEL(i) (0x00198048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP(i) (0x0019804C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_EVENT_SEL(i) (0x00198050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP(i) (0x00198054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL(i) (0x00198058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP(i) (0x0019805C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP(i) (0x00198060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP(i) (0x00198064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SELECTMUX(i) (0x00198068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_GPC6_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_ENGINE_SEL(i) (0x0019806C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_ELAPSED(i) (0x00198070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_MODEC5CNT(i) (0x00198074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CYCLECNT(i) (0x00198078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_MODEC6CNT(i) (0x0019807C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_EVENTCNT(i) (0x00198080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER(i) (0x00198084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_THRESHCNT(i) (0x00198088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_TRIGGERCNT(i) (0x0019808C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_SAMPLECNT(i) (0x00198090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_THRESHOLD(i) (0x00198098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPC6_CONTROL(i) (0x0019809C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_RELEASE(i) (0x001980A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC6_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT0(i) (0x001980A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT1(i) (0x001980A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT2(i) (0x001980AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT3(i) (0x001980B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT4(i) (0x001980B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT5(i) (0x001980B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT6(i) (0x001980BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWCNT7(i) (0x001980C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_RAWSMPLCNT(i) (0x001980C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS(i) (0x001980C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0(i) (0x001980CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1(i) (0x001980D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW2(i) (0x001980D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0(i) (0x001980D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1(i) (0x001980DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_STARTEXPERIMENT(i) (0x001980E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC6_CTXSW0(i) (0x001980E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1(i) (0x001980E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG(i) (0x001980EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC6_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC6_DEBUG(i) (0x001980F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPC6_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPC6_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPC6_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPC6_DAISY_DISABLE(i) (0x001980FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB(i) (0x00198108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC(i) (0x00198110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLD(i) (0x00198120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_PERFMONID(i) (0x00198128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CTXSW2(i) (0x00198114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW3(i) (0x00198118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CTXSW4(i) (0x0019811C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_TOTAL_TRIG_RCV(i) (0x00198124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER(i) (0x00198130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL 0x00244C00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_GRANT 0x00244C04 /* -W-4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_PMMTRIGGERCNT 0x00244C08 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CTXSW0 0x00244C0C /* R-E4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS 0x00244C10 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_PERFMONSTATUS 0x00244C14 /* R--4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2 0x00244C18 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPC_GPC6ROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG 0x00244C1C /* RW-4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_RECORD_DEBUG 0x00244D54 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG 0x00244D50 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPC6ROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL(i) (0x00198100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21 0x0019AB00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20 0x0019A900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19 0x0019A700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18 0x0019A500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17 0x0019A300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16 0x0019A100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15 0x00199F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14 0x00199D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13 0x00199B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12 0x00199900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11 0x00199700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10 0x00199500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9 0x00199300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8 0x00199100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7 0x00198F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6 0x00198D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5 0x00198B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4 0x00198900 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3 0x00198700 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2 0x00198500 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1 0x00198300 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0 0x00198100 /* RW-4R */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPC6_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA 0x002501FF:0x00250000 /* RW--D */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT0_INPUTSEL 0x00250000 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT1_INPUTSEL 0x00250004 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT2_INPUTSEL 0x00250008 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT3_INPUTSEL 0x0025000C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT4_INPUTSEL 0x00250010 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT5_INPUTSEL 0x00250014 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC 0x00250020 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC 0x00250024 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC 0x00250028 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC 0x0025002C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC 0x00250030 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC 0x00250034 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_SEL 0x00250040 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP 0x00250044 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_SEL 0x00250048 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP 0x0025004C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_SEL 0x00250050 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP 0x00250054 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_SEL 0x00250058 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP 0x0025005C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP 0x00250060 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP 0x00250064 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX 0x00250068 /* R--4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINE_SEL 0x0025006C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ELAPSED 0x00250070 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC5CNT 0x00250074 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CYCLECNT 0x00250078 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC6CNT 0x0025007C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENTCNT 0x00250080 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DFD_CNT_UPPER 0x00250084 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHCNT 0x00250088 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIGGERCNT 0x0025008C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLECNT 0x00250090 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHOLD 0x00250098 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL 0x0025009C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RELEASE 0x002500A0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT0 0x002500A4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT1 0x002500A8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT2 0x002500AC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT3 0x002500B0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT4 0x002500B4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT5 0x002500B8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT6 0x002500BC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT7 0x002500C0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWSMPLCNT 0x002500C4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS 0x002500C8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0 0x002500CC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1 0x002500D0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW2 0x002500D4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0 0x002500D8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1 0x002500DC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_STARTEXPERIMENT 0x002500E0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0 0x002500E4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1 0x002500E8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG 0x002500EC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DEBUG 0x002500F8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DAISY_DISABLE 0x002500FC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB 0x00250108 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC 0x00250110 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLD 0x00250120 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_PERFMONID 0x00250128 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW2 0x00250114 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW3 0x00250118 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW4 0x0025011C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TOTAL_TRIG_RCV 0x00250124 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER 0x00250130 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLAMP_CYA_CONTROL 0x00250100 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCA_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB 0x002503FF:0x00250200 /* RW--D */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT0_INPUTSEL 0x00250200 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT1_INPUTSEL 0x00250204 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT2_INPUTSEL 0x00250208 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT3_INPUTSEL 0x0025020C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT4_INPUTSEL 0x00250210 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT5_INPUTSEL 0x00250214 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC 0x00250220 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC 0x00250224 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC 0x00250228 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC 0x0025022C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC 0x00250230 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC 0x00250234 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_SEL 0x00250240 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP 0x00250244 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_SEL 0x00250248 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP 0x0025024C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_SEL 0x00250250 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP 0x00250254 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_SEL 0x00250258 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP 0x0025025C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP 0x00250260 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP 0x00250264 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX 0x00250268 /* R--4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINE_SEL 0x0025026C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ELAPSED 0x00250270 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC5CNT 0x00250274 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CYCLECNT 0x00250278 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC6CNT 0x0025027C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENTCNT 0x00250280 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DFD_CNT_UPPER 0x00250284 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHCNT 0x00250288 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIGGERCNT 0x0025028C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLECNT 0x00250290 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHOLD 0x00250298 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL 0x0025029C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RELEASE 0x002502A0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT0 0x002502A4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT1 0x002502A8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT2 0x002502AC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT3 0x002502B0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT4 0x002502B4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT5 0x002502B8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT6 0x002502BC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT7 0x002502C0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWSMPLCNT 0x002502C4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS 0x002502C8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0 0x002502CC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1 0x002502D0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW2 0x002502D4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0 0x002502D8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1 0x002502DC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_STARTEXPERIMENT 0x002502E0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0 0x002502E4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1 0x002502E8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG 0x002502EC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DEBUG 0x002502F8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DAISY_DISABLE 0x002502FC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB 0x00250308 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC 0x00250310 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLD 0x00250320 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_PERFMONID 0x00250328 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW2 0x00250314 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW3 0x00250318 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW4 0x0025031C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TOTAL_TRIG_RCV 0x00250324 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER 0x00250330 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLAMP_CYA_CONTROL 0x00250300 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCB_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC 0x002505FF:0x00250400 /* RW--D */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT0_INPUTSEL 0x00250400 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT1_INPUTSEL 0x00250404 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT2_INPUTSEL 0x00250408 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT3_INPUTSEL 0x0025040C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT4_INPUTSEL 0x00250410 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT5_INPUTSEL 0x00250414 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC 0x00250420 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC 0x00250424 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC 0x00250428 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC 0x0025042C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC 0x00250430 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC 0x00250434 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_SEL 0x00250440 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP 0x00250444 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_SEL 0x00250448 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP 0x0025044C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_SEL 0x00250450 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP 0x00250454 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_SEL 0x00250458 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP 0x0025045C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP 0x00250460 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP 0x00250464 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX 0x00250468 /* R--4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINE_SEL 0x0025046C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ELAPSED 0x00250470 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC5CNT 0x00250474 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CYCLECNT 0x00250478 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC6CNT 0x0025047C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENTCNT 0x00250480 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DFD_CNT_UPPER 0x00250484 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHCNT 0x00250488 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIGGERCNT 0x0025048C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLECNT 0x00250490 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHOLD 0x00250498 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL 0x0025049C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RELEASE 0x002504A0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT0 0x002504A4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT1 0x002504A8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT2 0x002504AC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT3 0x002504B0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT4 0x002504B4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT5 0x002504B8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT6 0x002504BC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT7 0x002504C0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWSMPLCNT 0x002504C4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS 0x002504C8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0 0x002504CC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1 0x002504D0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW2 0x002504D4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0 0x002504D8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1 0x002504DC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_STARTEXPERIMENT 0x002504E0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0 0x002504E4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1 0x002504E8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG 0x002504EC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DEBUG 0x002504F8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DAISY_DISABLE 0x002504FC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB 0x00250508 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC 0x00250510 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLD 0x00250520 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_PERFMONID 0x00250528 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW2 0x00250514 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW3 0x00250518 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW4 0x0025051C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TOTAL_TRIG_RCV 0x00250524 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER 0x00250530 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLAMP_CYA_CONTROL 0x00250500 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_GPCTPCC_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCGS_ROP 0x002507FF:0x00250600 /* RW--D */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT0_INPUTSEL 0x00250600 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT1_INPUTSEL 0x00250604 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT2_INPUTSEL 0x00250608 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT3_INPUTSEL 0x0025060C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT4_INPUTSEL 0x00250610 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT5_INPUTSEL 0x00250614 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC 0x00250620 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC 0x00250624 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC 0x00250628 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC 0x0025062C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC 0x00250630 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC 0x00250634 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_SEL 0x00250640 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP 0x00250644 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_SEL 0x00250648 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP 0x0025064C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_SEL 0x00250650 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP 0x00250654 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_SEL 0x00250658 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP 0x0025065C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP 0x00250660 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP 0x00250664 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX 0x00250668 /* R--4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINE_SEL 0x0025066C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ELAPSED 0x00250670 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_MODEC5CNT 0x00250674 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CYCLECNT 0x00250678 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_MODEC6CNT 0x0025067C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENTCNT 0x00250680 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_DFD_CNT_UPPER 0x00250684 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_THRESHCNT 0x00250688 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIGGERCNT 0x0025068C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLECNT 0x00250690 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_THRESHOLD 0x00250698 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL 0x0025069C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RELEASE 0x002506A0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPCGS_ROP_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT0 0x002506A4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT1 0x002506A8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT2 0x002506AC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT3 0x002506B0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT4 0x002506B4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT5 0x002506B8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT6 0x002506BC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT7 0x002506C0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWSMPLCNT 0x002506C4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS 0x002506C8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0 0x002506CC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1 0x002506D0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW2 0x002506D4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0 0x002506D8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1 0x002506DC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_STARTEXPERIMENT 0x002506E0 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0 0x002506E4 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1 0x002506E8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG 0x002506EC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_DEBUG 0x002506F8 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_ROP_DAISY_DISABLE 0x002506FC /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB 0x00250708 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC 0x00250710 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLD 0x00250720 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_PERFMONID 0x00250728 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW2 0x00250714 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW3 0x00250718 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW4 0x0025071C /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TOTAL_TRIG_RCV 0x00250724 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER 0x00250730 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCGS_ROP_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLAMP_CYA_CONTROL 0x00250700 /* RW-4R */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCGS_ROP_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS 0x0027BFFF:0x00278000 /* RW--D */ #define NV_PERF_PMMGPC_GPCSROUTER 0x002519FF:0x00251800 /* RW--D */ #define NV_PERF_PMMGPC_GPCSROUTER_PERTRIGGER_SLICE_OFFSET 0x0000000F /* */ #define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL(i) (0x00278000+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT0_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL(i) (0x00278004+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT1_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL(i) (0x00278008+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT2_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL(i) (0x0027800C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT3_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL(i) (0x00278010+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT4_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL(i) (0x00278014+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL_BIT0 5:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL_BIT1 13:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL_BIT2 21:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_FT5_INPUTSEL_BIT3 29:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC(i) (0x00278020+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR0_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC(i) (0x00278024+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR1_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC(i) (0x00278028+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR2_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC(i) (0x0027802C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR3_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC(i) (0x00278030+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR4_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC(i) (0x00278034+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_INCMASK 11:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_INCMASKRSVD 18:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_INCBASE 24:19 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_FUNCSEL 28:25 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_FUNCSEL_0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_FUNCSEL_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_FUNCSEL_2 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_FUNCSEL_3 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_FUNCSEL_4 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_FUNCSEL_5 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_FUNCSEL_TRUE 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_INCFN 31:29 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_INCFN_NOP 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CNTR5_INC_INCFN_POPCOUNT 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_TRIG0_SEL(i) (0x00278040+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_TRIG0_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_TRIG0_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP(i) (0x00278044+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG0_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG1_SEL(i) (0x00278048+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_TRIG1_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_TRIG1_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP(i) (0x0027804C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIG1_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_EVENT_SEL(i) (0x00278050+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_EVENT_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_EVENT_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP(i) (0x00278054+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_EVENT_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL(i) (0x00278058+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL_SEL0 7:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL_SEL1 15:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL_SEL2 23:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_SEL_SEL3 31:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP(i) (0x0027805C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_SSEL3 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_SSEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLE_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP(i) (0x00278060+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SETFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP(i) (0x00278064+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_FUNC 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_FUNC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_DSEL0 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_DSEL0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_DSEL1 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_DSEL1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_DSEL0_TO_SEL2 19:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_DSEL0_TO_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_DSEL1_TO_SEL3 20:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CLRFLAG_OP_DSEL1_TO_SEL3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SELECTMUX(i) (0x00278068+(i)*0x00000200) /* R--4A */ #define NV_PERF_PMMGPC_GPCS_SELECTMUX__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_SELECTMUX_TRIG0_SEL 3:0 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_SELECTMUX_TRIG1_SEL 7:4 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_SELECTMUX_EVENT_SEL 11:8 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_SELECTMUX_SAMPLE_SEL 15:12 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_SELECTMUX_CLRFLAG_SEL 19:16 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_SELECTMUX_SETFLAG_SEL 23:20 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_ENGINE_SEL(i) (0x0027806C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_ENGINE_SEL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_ENGINE_SEL_START 7:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_ENGINE_SEL_START_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_ELAPSED(i) (0x00278070+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_ELAPSED__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_ELAPSED_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_ELAPSED_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_MODEC5CNT(i) (0x00278074+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_MODEC5CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_MODEC5CNT_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_MODEC5CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CYCLECNT(i) (0x00278078+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CYCLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CYCLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CYCLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_MODEC6CNT(i) (0x0027807C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_MODEC6CNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_MODEC6CNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_MODEC6CNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_EVENTCNT(i) (0x00278080+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_EVENTCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_EVENTCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_EVENTCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER(i) (0x00278084+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER_SAMPLECNT 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER_SAMPLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER_CYCLECNT 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_DFD_CNT_UPPER_CYCLECNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_THRESHCNT(i) (0x00278088+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_THRESHCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_THRESHCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_THRESHCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_TRIGGERCNT(i) (0x0027808C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_TRIGGERCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_TRIGGERCNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TRIGGERCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_SAMPLECNT(i) (0x00278090+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_SAMPLECNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_SAMPLECNT_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_SAMPLECNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_THRESHOLD(i) (0x00278098+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_THRESHOLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_THRESHOLD_VAL 31:0 /* RW-UF */ #define NV_PERF_PMMGPC_GPCS_CONTROL(i) (0x0027809C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODE 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODE_A 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODE_B 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODE_C 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODE_E 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODE_NULL 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR 5:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR_INCR 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR_EVENT4 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR_EVENT6 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR_TRIG4 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR_TRIG6 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR_VIVEK 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR_4444 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_ADDTOCTR_2X4B4I 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CLEAR_EVENT_ONCE 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_EVENT_SYNC_MODE 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_EVENT_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_EVENT_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_FLAG_SYNC_MODE 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_FLAG_SYNC_MODE_LEVEL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_FLAG_SYNC_MODE_PULSE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODEC_4X16_4X32 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODEC_4X16_4X32_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_MODEC_4X16_4X32_RECONFIGURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CTXSW_MODE 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CTXSW_MODE_ENABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CTXSW_MODE_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES 23:21 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES_1K 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES_2K 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES_4K 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES_8K 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES_16K 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES_32K 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_TIMEBASE_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_SHADOW_STATE 25:24 /* R-XUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_SHADOW_STATE_INVALID 0x00000000 /* R---V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_SHADOW_STATE_VALID 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_SHADOW_STATE_OVERFLOW 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_DRIVE_DEBUG_PORT 26:26 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_DRIVE_DEBUG_PORT_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_DRIVE_DEBUG_PORT_OBSERVE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CTXSW_TIMER 27:27 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CTXSW_TIMER_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_CTXSW_TIMER_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_STATE 29:28 /* R-EUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_STATE_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_STATE_CAPTURE 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_WBMASK 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_WBMASK_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_WBMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_DRIVE_DFD_TRIGGER 31:31 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROL_DRIVE_DFD_TRIGGER_NORMAL 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROL_DRIVE_DFD_TRIGGER_DEBUG 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_RELEASE(i) (0x002780A0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RELEASE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RELEASE_SHADOWS 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RELEASE_SHADOWS_DOIT 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPCS_RELEASE_SHADOWS_HOLD 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT0(i) (0x002780A4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWCNT0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWCNT0_CNT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT0_CNT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT0_CNT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT0_CNT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT1(i) (0x002780A8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWCNT1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWCNT1_CNT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT1_CNT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT1_CNT3_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT1_CNT3_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT2(i) (0x002780AC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWCNT2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWCNT2_CNT4_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT2_CNT4_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT2_CNT5_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT2_CNT5_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT3(i) (0x002780B0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWCNT3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWCNT3_CNT6_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT3_CNT6_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT3_CNT7_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT3_CNT7_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT4(i) (0x002780B4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWCNT4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWCNT4_CNT8_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT4_CNT8_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT4_CNT9_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT4_CNT9_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT5(i) (0x002780B8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWCNT5__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWCNT5_CNT10_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT5_CNT10_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT5_CNT11_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT5_CNT11_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT6(i) (0x002780BC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWCNT6__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWCNT6_CNTT0_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT6_CNTT0_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT6_CNTT1_VAL 31:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT6_CNTT1_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWCNT7(i) (0x002780C0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWCNT7__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWCNT7_CNTT2_VAL 15:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWCNT7_CNTT2_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_RAWSMPLCNT(i) (0x002780C4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_RAWSMPLCNT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_RAWSMPLCNT_VAL 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_RAWSMPLCNT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS(i) (0x002780C8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0(i) (0x002780CC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_0_VALUE 0x3 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG0_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG1_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG1_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG1_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG1_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG1_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG1_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG1_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW0_TRIG1_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1(i) (0x002780D0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_EVENT_0 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_EVENT_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_EVENT_1 6:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_EVENT_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_EVENT_2 10:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_EVENT_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_EVENT_3 14:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_EVENT_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_SAMPLE_0 18:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_SAMPLE_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_SAMPLE_1 22:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_SAMPLE_1_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_SAMPLE_2 26:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_SAMPLE_2_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_SAMPLE_3 30:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW1_SAMPLE_3_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW2(i) (0x002780D4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_WBSKEW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_WBSKEW2_ENGINESELECT 2:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW2_ENGINESELECT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW2_CHAINENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW2_CHAINENABLE_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0(i) (0x002780D8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG0_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG0_0_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG0_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG0_1_INIT 0x1 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG0_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG0_2_INIT 0x2 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG0_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG0_3_INIT 0x3 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG1_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG1_0_INIT 0x4 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG1_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG1_1_INIT 0x5 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG1_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG1_2_INIT 0x6 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG1_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN0_TRIG1_3_INIT 0x7 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1(i) (0x002780DC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_EVENT_0 3:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_EVENT_0_INIT 0x8 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_EVENT_1 7:4 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_EVENT_1_INIT 0x9 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_EVENT_2 11:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_EVENT_2_INIT 0xA /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_EVENT_3 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_EVENT_3_INIT 0xB /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_SAMPLE_0 19:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_SAMPLE_0_INIT 0xC /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_SAMPLE_1 23:20 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_SAMPLE_1_INIT 0xD /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_SAMPLE_2 27:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_SAMPLE_2_INIT 0xE /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_SAMPLE_3 31:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_WBSKEW_CHAIN1_SAMPLE_3_INIT 0xF /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_STARTEXPERIMENT(i) (0x002780E0+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_STARTEXPERIMENT__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_STARTEXPERIMENT_START 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_STARTEXPERIMENT_START_DOIT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_STARTEXPERIMENT_START_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCS_CTXSW0(i) (0x002780E4+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CTXSW0__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_PMSTATE 1:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_PMSHADOWSTATE 3:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_FLAGBIT 4:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_FLAGBITP 5:5 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_FLAGBITTGL 6:6 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_EVENTSTROBETGL 7:7 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_EVENTSIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_ENGINESELECT 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_SMPLSIGP 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_CLRFLGSIGP 21:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_SETFLGSIGP 23:22 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_EVENTSTROBEP 24:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_TRIG0STBP 25:25 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_TRIG1STBP 26:26 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_SMPLSTBP 27:27 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_1STCLKCAP 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_SAMPENP 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_INCTHRSHCNTP 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW0_PMTRIGGERDLY 31:31 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1(i) (0x002780E8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CTXSW1__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_CAPTURELAST 0:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_IDLELAST 1:1 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_DFDTRIGGER 2:2 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_XFERCNT 7:4 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_TRIG0SIGP 11:8 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_TRIG1SIGP 15:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_TRIG0SIGNALS 19:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_TRIG1SIGNALS 23:20 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_EVENTSIGNALS 27:24 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW1_SAMPLESIGNALS 31:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG(i) (0x002780EC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI 3:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL0 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL1 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL2 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE1_SIGNAL3 0x00000008 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL0 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL1 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL2 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_CONTROLBYPRI_DRIVE0_SIGNAL3 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_SELFCLEAR 7:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCS_WATCHBUSDEBUG_SELFCLEAR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCS_DEBUG(i) (0x002780F8+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_DEBUG__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_DEBUG_TOTAL_RECORDS_SENT 6:0 /* R-XVF */ #define NV_PERF_PMMGPC_GPCS_DEBUG_TOTAL_RECORDS_RESET 7:7 /* -WEVF */ #define NV_PERF_PMMGPC_GPCS_DEBUG_TOTAL_RECORDS_RESET_INIT 0x0 /* R-E-V */ #define NV_PERF_PMMGPC_GPCS_DEBUG_TOTAL_RECORDS_RESET_DOIT 0x1 /* -W--T */ #define NV_PERF_PMMGPC_GPCS_DAISY_DISABLE(i) (0x002780FC+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_DAISY_DISABLE__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_DAISY_DISABLE_VAL 31:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB(i) (0x00278108+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CONTROLB__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_POWERCLAMP 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_POWERCLAMP_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_POWERCLAMP_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMM2ALLCTXSWFREEZE 2:2 /* R--UF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_FLUSH_RECORD 4:4 /* -WEVF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_FLUSH_RECORD_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_FLUSH_RECORD_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_MODEE_USERDATA 5:5 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_MODEE_USERDATA_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_MODEE_USERDATA_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PTIMER 6:6 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PTIMER_DISABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PTIMER_ENABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIGA_EN 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIGA_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIGA_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIGB_EN 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIGB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIGB_EN_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIG_TPULSE 10:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIG_TPULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PMLOCALTRIG_TPULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFDTRIGMODE 12:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFDTRIGMODE_NORMAL 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFDTRIGMODE_BACKPRESSURE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFDMANUALTRIG 13:13 /* -WEVF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFDMANUALTRIG_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFDMANUALTRIG_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMING 16:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMING_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMING_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGMODE 17:17 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGMODE_LATENCY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGMODE_ACCUMULATOR 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLATENCYINC 18:18 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLATENCYINC_N 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLATENCYINC_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE 21:19 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_OFF 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_1 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_4 0x00000002 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_8 0x00000003 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_16 0x00000004 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_32 0x00000005 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_64 0x00000006 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_HISTOGRAMMINGLINEARSIZE_128 0x00000007 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PULSE_ENGINE_SEL 24:24 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PULSE_ENGINE_SEL_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_PULSE_ENGINE_SEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_TRIGRCV_IN_MODEC 25:25 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_TRIGRCV_IN_MODEC_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_TRIGRCV_IN_MODEC_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_COUNTING_MODE 27:26 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_COUNTING_MODE_LEGACY 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_COUNTING_MODE_GENERAL 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DROP_OVERFLOW_RECORDS 28:28 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DROP_OVERFLOW_RECORDS_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DROP_OVERFLOW_RECORDS_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH 29:29 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_DISABLED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DRIVE_DFD_TRIGGER_EVENT_LESS_THAN_THRESH_ENABLED 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFD_FLAG_BIT_ENABLE 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFD_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_DFD_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_EXT_FLAG_BIT_ENABLE 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_EXT_FLAG_BIT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLB_EXT_FLAG_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC(i) (0x00278110+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CONTROLC__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTERMAP_EVENT 1:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_EVENT 3:3 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_EVENT_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_EVENT_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTERMAP_SAMPLE 5:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_SAMPLE 7:7 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_SAMPLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_SAMPLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTERMAP_TRIG0 9:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_TRIG0 11:11 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_TRIG0_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_TRIG0_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTERMAP_TRIG1 13:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_TRIG1 15:15 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_TRIG1_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_FILTER_TRIG1_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET 26:16 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLC_HISTOGRAMMINGBUCKETOFFSET_VALX8 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLD(i) (0x00278120+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CONTROLD__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CONTROLD_TRIG_SKIP_COUNT 9:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLD_TRIG_SKIP_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CONTROLD_TRIG_INCR_COUNT 19:10 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_CONTROLD_TRIG_INCR_COUNT_ZERO 0x00000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_PERFMONID(i) (0x00278128+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_PERFMONID__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_PERFMONID_VAL 10:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_PERFMONID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CTXSW2(i) (0x00278114+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CTXSW2__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CTXSW2_HISTOGRAM_COUNTER 14:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW2_HISTOGRAM_SENTCNT 27:16 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW2_HISTOGRAM_LATENCYSTATE 28:28 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW2_HISTOGRAM_LATENCYERROR 29:29 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW2_HISTOGRAM_LATENCYDMAX 30:30 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW3(i) (0x00278118+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CTXSW3__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CTXSW3_HISTOGRAM_SENTSAVE 11:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW3_HISTOGRAM_RECEIVEDCNT 23:12 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CTXSW4(i) (0x0027811C+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CTXSW4__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CTXSW4_HISTOGRAM_OFFSET 13:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_TOTAL_TRIG_RCV(i) (0x00278124+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_TOTAL_TRIG_RCV__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_TOTAL_TRIG_RCV_VAL 31:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_TOTAL_TRIG_RCV_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER(i) (0x00278130+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_HOLD 25:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_HOLD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_DEASSERTION 30:30 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_DEASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_ASSERTION 31:31 /* RWEUF */ #define NV_PERF_PMMGPC_GPCS_FLAG_BIT_TIMER_ASSERTION_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL 0x00251800 /* RW-4R */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_MODEC 0:0 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_MODEC_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_MODEC_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS 1:1 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_ALL_COUNTERS_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE 2:2 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ENABLE_FE2ALL_FREEZE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE 3:3 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_PMM_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES 4:4 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HOLD_TIMEBASES_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME 5:5 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ONE_AT_A_TIME_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE 8:8 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_HS_STREAM_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_START_OF_TEST 14:14 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_START_OF_TEST_RESET 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_START_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_END_OF_TEST 15:15 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_END_OF_TEST_RESET 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_END_OF_TEST_SET 0x00000001 /* -W--T */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT 26:16 /* R-XVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_DATA_IN_FLIGHT_RESERVE_FUTURE 28:27 /* R-XVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ACK_WRITES 29:29 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ACK_WRITES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_ACK_WRITES_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_WRITE_NACK 30:30 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_WRITE_NACK_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_WRITE_NACK_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_UNEXP_GRANT 31:31 /* RWEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_UNEXP_GRANT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CNTRL_UNEXP_GRANT_RESET 0x00000001 /* RW--T */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_GRANT 0x00251804 /* -W-4R */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_GRANT_CREDIT 31:31 /* -WEUF */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_GRANT_CREDIT_NOCREDIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_GRANT_CREDIT_INC 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_PMMTRIGGERCNT 0x00251808 /* RW-4R */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_PMMTRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_PMMTRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CTXSW0 0x0025180C /* R-E4R */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CTXSW0_VAL 31:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPCSROUTER_GLOBAL_CTXSW0_VAL_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS 0x00251810 /* RW-4R */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_ENABLE 8:8 /* RWEUF */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_ENABLE_MASKED 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_ENGINESTATUS_ENABLE_OUT 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_PERFMONSTATUS 0x00251814 /* R--4R */ #define NV_PERF_PMMGPC_GPCSROUTER_PERFMONSTATUS_MERGED 2:0 /* R--UF */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2 0x00251818 /* RW-4R */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_PERFMON 0:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_PERFMON_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_PERFMON_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_PERFMON__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_ROUTER 1:1 /* RWEUF */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_ROUTER_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_ROUTER_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_ROUTER__PROD 0x00000000 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG 1:0 /* */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG_DISABLED 0x00000003 /* ----V */ #define NV_PERF_PMMGPC_GPCSROUTER_CG2_SLCG__PROD 0x00000000 /* ----V */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG 0x0025181C /* RW-4R */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG_NUM_RIF 4:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG_TOTAL_REQUESTS 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCSROUTER_RECORD_DEBUG_TOTAL_GRANTS 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_RECORD_DEBUG 0x00251954 /* RW-4R */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_RECORD_DEBUG_TOTAL_RESET 15:15 /* -WEVF */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_RECORD_DEBUG_TOTAL_RESET_INIT 0x0 /* -WE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_RECORD_DEBUG_TOTAL_RESET_DOIT 0x1 /* -W--V */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_RECORD_DEBUG_TOTAL_CREDITS_RECEIVED 22:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_RECORD_DEBUG_TOTAL_RECORDS_SENT 30:24 /* RWXUF */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG 0x00251950 /* RW-4R */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_CREDITS 8:0 /* RWEUF */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_CREDITS_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_USE_PROG_ID 9:9 /* RWEUF */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_USE_PROG_ID_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_USE_PROG_ID_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_PROG_ID 15:12 /* RWEUF */ #define NV_PERF_PMMGPC_GPCSROUTER_HS_CONFIG_PROG_ID_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL(i) (0x00278100+(i)*0x00000200) /* RW-4A */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL__SIZE_1 22 /* */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL_VAL 30:0 /* RWXVF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL_ENABLECYA 31:31 /* RWIVF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21 0x0027AB00 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21_CROP1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21_RRH1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21_ZROP1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL21_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20 0x0027A900 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20_CROP0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20_RRH0 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20_ZROP0 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL20_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19 0x0027A700 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19_TPC5_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19_TPC5_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19_TPC5_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL19_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18 0x0027A500 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18_TPC4_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18_TPC4_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18_TPC4_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL18_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17 0x0027A300 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17_TPC3_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17_TPC3_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17_TPC3_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL17_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16 0x0027A100 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16_TPC2_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16_TPC2_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16_TPC2_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL16_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15 0x00279F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15_TPC1_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15_TPC1_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15_TPC1_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL15_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14 0x00279D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14_TPC0_MPC_SM1 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14_TPC0_PEL 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14_TPC0_SMV_TTU 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL14_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13 0x00279B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_TPC5_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_TPC5_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_TPC5_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_TPC5_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL13_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12 0x00279900 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_TPC4_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_TPC4_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_TPC4_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_TPC4_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL12_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11 0x00279700 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_TPC3_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_TPC3_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_TPC3_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_TPC3_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL11_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10 0x00279500 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_TPC2_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_TPC2_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_TPC2_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_TPC2_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL10_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9 0x00279300 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_TPC1_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_TPC1_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_TPC1_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_TPC1_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL9_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8 0x00279100 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL10 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL11 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL12 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_TPC0_SMV_SCTL13 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_TPC0_SMV_CORE1 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_TPC0_SMV_MIO1 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_TPC0_SMV_TEX1 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL8_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7 0x00278F00 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_TPC5_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_TPC5_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_TPC5_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_TPC5_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_TPC5_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL7_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6 0x00278D00 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_TPC4_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_TPC4_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_TPC4_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_TPC4_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_TPC4_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL6_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5 0x00278B00 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_TPC3_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_TPC3_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_TPC3_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_TPC3_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_TPC3_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL5_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4 0x00278900 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_TPC2_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_TPC2_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_TPC2_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_TPC2_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_TPC2_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL4_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3 0x00278700 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_TPC1_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_TPC1_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_TPC1_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_TPC1_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_TPC1_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL3_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2 0x00278500 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_TPC0_MPC_SM0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL00 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL01 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL02 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_TPC0_SMV_SCTL03 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_TPC0_SMV_CORE0 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_TPC0_SMV_MIO0 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_TPC0_SMV_TEX0 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL2_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1 0x00278300 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_GCC 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_GPC_PRI_HUB 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_GPCCS_FALCON 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_GPCCS 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_GPCMMU_MUX0 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_GPMREPORT 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_GPMPD 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_GPMSD 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC0_CBMGR 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC0_PES 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC0_WWDX 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC1_CBMGR 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC1_PES 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC1_WWDX 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC2_CBMGR 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC2_PES 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_PPC2_WWDX 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_WDXPS 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL1_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0 0x00278100 /* RW-4R */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_GNIC_MUX0 0:0 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_GNIC_MUX1 1:1 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_GPCMMU_MUX1 2:2 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_PMMGPC_ROUTER 3:3 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_PROP 4:4 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_CRSTR 5:5 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_FRSTR 6:6 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_RASTERARB 7:7 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_SETUP 8:8 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_TC 9:9 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_WIDCLIP 10:10 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_ZCULL 11:11 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_SWDX 12:12 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_TPC0_CAU0 13:13 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_TPC1_CAU0 14:14 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_TPC2_CAU0 15:15 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_TPC3_CAU0 16:16 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_TPC4_CAU0 17:17 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_TPC5_CAU0 18:18 /* RWXUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_ENABLECYA 31:31 /* RWIUF */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_ENABLECYA_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMMGPC_GPCS_CLAMP_CYA_CONTROL0_ENABLECYA_ENABLE 0x1 /* RWI-V */ #define NV_PERF_PMASYS 0x0024BFFF:0x0024A000 /* RW--D */ #define NV_PERF_PMASYS_NUM_CHANNELS 1 /* */ #define NV_PERF_PMASYS_NUM_SMC_TRIGGER_SLICES 0 /* */ #define NV_PERF_PMASYS_NUM_DEVICE_TRIGGER_SLICES 1 /* */ #define NV_PERF_PMASYS_STRIDE_PER_CHANNEL 0x180 /* */ #define NV_PERF_PMASYS_CONTROL 0x0024A000 /* RWE4R */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT 14:9 /* RWEUF */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_CE0 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_CE1 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_CE2 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_CE3 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_CE4 0x00000004 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_CE5 0x00000005 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_CESHIM 0x00000006 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_GR 0x00000007 /* RWE-V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_GSP 0x00000008 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_NVDEC0 0x00000009 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_NVDEC1 0x0000000A /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_NVENC0 0x0000000B /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_OFA 0x0000000C /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_PMA 0x0000000D /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_PWR 0x0000000E /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_TRIGGER_SELECT_SEC 0x0000000F /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_ENABLE 16:16 /* RWEUF */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_SOURCE 18:17 /* RWEUF */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_SOURCE_INTERNAL 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_SOURCE_RES_1 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_SOURCE_RES_2 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_SOURCE_RES_3 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_WINDOW 19:19 /* RWEUF */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_WINDOW_INSIDE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CONTROL_PMA_PULSE_WINDOW_FREERUN 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_PMA_PULSE_CNTR 21:20 /* RWEUF */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_PMA_PULSE_CNTR_ONE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_PMA_PULSE_CNTR_EIGHT 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_PMA_PULSE_CNTR_SIXTEEN 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_CONTROL_PMA_RECORD_PMA_PULSE_CNTR_THIRTYTWO 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_PULSE_TIMEBASESET 0x0024A698 /* RW-4R */ #define NV_PERF_PMASYS_PULSE_TIMEBASESET_VALUE 31:0 /* RW-UF */ #define NV_PERF_PMASYS_PULSE_TIMEBASECNT 0x0024A69C /* RW-4R */ #define NV_PERF_PMASYS_PULSE_TIMEBASECNT_VALUE 31:0 /* RW-UF */ #define NV_PERF_PMASYS_DEBUG 0x0024A614 /* RW-4R */ #define NV_PERF_PMASYS_DEBUG_WR_MISS 0:0 /* R-EUF */ #define NV_PERF_PMASYS_DEBUG_WR_MISS_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_DEBUG_WR_MISS_CLR 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_DEBUG_CNTR_CLR 1:1 /* -WEUF */ #define NV_PERF_PMASYS_DEBUG_CNTR_CLR_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_DEBUG_CNTR_CLR_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_DEBUG_REQUEST_CNTR 8:2 /* RWEUF */ #define NV_PERF_PMASYS_DEBUG_REQUEST_CNTR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_DEBUG_GRANT_CNTR 15:9 /* RWEUF */ #define NV_PERF_PMASYS_DEBUG_GRANT_CNTR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_DEBUG_WR_MISS_READBACK 16:16 /* R-EUF */ #define NV_PERF_PMASYS_DEBUG_WR_MISS_READBACK_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL 0x0024A008 /* RW-4R */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_MANUAL_START 4:4 /* -WEVF */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_MANUAL_START_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_MANUAL_START_PULSE 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_MANUAL_STOP 5:5 /* -WEVF */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_MANUAL_STOP_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_MANUAL_STOP_PULSE 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_GPC 8:8 /* RWEVF */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_GPC_INIT 0x0 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_GPC_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_FBP 9:9 /* RWEVF */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_FBP_INIT 0x0 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_FBP_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_SYS 10:10 /* RWEVF */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_SYS_INIT 0x0 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_GLOBAL_TESLA_TRIGGER_MODE_SYS_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_HS_INFO 0x0024A00C /* R--4R */ #define NV_PERF_PMASYS_HS_INFO_TOTAL_FIFO_CREDITS 8:0 /* R--UF */ #define NV_PERF_PMASYS_HS_INFO_TOTAL_FIFO_CREDITS_INIT 0x0 /* R---V */ #define NV_PERF_PMASYS_HS_INFO_RECORDS_IN_FIFO 19:11 /* R--UF */ #define NV_PERF_PMASYS_HS_INFO_RECORDS_IN_FIFO_INIT 0x0 /* R---V */ #define NV_PERF_PMASYS_HS_INFO_FIFO_ERROR 24:24 /* R-EUF */ #define NV_PERF_PMASYS_HS_INFO_FIFO_ERROR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_HS_DEBUG 0x0024A618 /* RW-4R */ #define NV_PERF_PMASYS_HS_DEBUG_CNTR_CLR 0:0 /* -WEUF */ #define NV_PERF_PMASYS_HS_DEBUG_CNTR_CLR_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_HS_DEBUG_CNTR_CLR_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_HS_DEBUG_CREDIT_CNTR 10:4 /* RWEUF */ #define NV_PERF_PMASYS_HS_DEBUG_CREDIT_CNTR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_HS_DEBUG_RECORD_CNTR 22:16 /* RWEUF */ #define NV_PERF_PMASYS_HS_DEBUG_RECORD_CNTR_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START 0x0024A6D0 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STARTB 0x24A6D4 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_STARTB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STARTB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START 0x0024A6D8 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STARTB 0x24A6DC /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_STARTB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STARTB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START 0x0024A6E0 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STARTB 0x24A6E4 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_STARTB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STARTB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK 0x0024A65C /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASK_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASKB 0x24A660 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASKB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_START_MASKB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK 0x0024A664 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASK_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASKB 0x24A668 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASKB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_START_MASKB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK 0x0024A66C /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASKB 0x24A670 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASKB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_START_MASKB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP 0x0024A6E8 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOPB 0x24A6EC /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOPB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOPB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP 0x0024A6F0 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOPB 0x24A6F4 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOPB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOPB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP 0x0024A6F8 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOPB 0x24A6FC /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOPB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOPB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK 0x0024A674 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASK_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASKB 0x24A678 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASKB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STOP_MASKB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK 0x0024A67C /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASK_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASKB 0x24A680 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASKB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STOP_MASKB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK 0x0024A684 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASKB 0x24A688 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASKB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASKB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS 0x0024A700 /* RW-4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_CE0 0:0 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_CE1 1:1 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_CE2 2:2 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_CE3 3:3 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_CE4 4:4 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_CE5 5:5 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_CESHIM 6:6 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_GR 7:7 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_GSP 8:8 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_NVDEC0 9:9 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_NVDEC1 10:10 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_NVENC0 11:11 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_OFA 12:12 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_PWR 13:13 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUS_ENGINE_SEC 14:14 /* RW-VF */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUSB 0x24A704 /* RW-4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_STATUSB_ENGINE_PMA 31:31 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS 0x0024A708 /* RW-4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_CE0 0:0 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_CE1 1:1 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_CE2 2:2 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_CE3 3:3 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_CE4 4:4 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_CE5 5:5 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_CESHIM 6:6 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_GR 7:7 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_GSP 8:8 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_NVDEC0 9:9 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_NVDEC1 10:10 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_NVENC0 11:11 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_OFA 12:12 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_PWR 13:13 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUS_ENGINE_SEC 14:14 /* RW-VF */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUSB 0x24A70C /* RW-4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_STATUSB_ENGINE_PMA 31:31 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS 0x0024A710 /* RW-4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_CE0 0:0 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_CE1 1:1 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_CE2 2:2 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_CE3 3:3 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_CE4 4:4 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_CE5 5:5 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_CESHIM 6:6 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_GR 7:7 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_GSP 8:8 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_NVDEC0 9:9 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_NVDEC1 10:10 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_NVENC0 11:11 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_OFA 12:12 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_PWR 13:13 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUS_ENGINE_SEC 14:14 /* RW-VF */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUSB 0x24A714 /* RW-4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_STATUSB_ENGINE_PMA 31:31 /* RW-VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START 0x0024A600 /* R--4R */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_CE0 0:0 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_CE1 1:1 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_CE2 2:2 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_CE3 3:3 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_CE4 4:4 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_CE5 5:5 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_CESHIM 6:6 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_GR 7:7 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_GSP 8:8 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_NVDEC0 9:9 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_NVDEC1 10:10 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_NVENC0 11:11 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_OFA 12:12 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_PWR 13:13 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_START_ENGINE_SEC 14:14 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STARTB 0x24A604 /* R--4R */ #define NV_PERF_PMASYS_ENGINE_STATUS_STARTB_ENGINE_PMA 31:31 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP 0x0024A608 /* R--4R */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_CE0 0:0 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_CE1 1:1 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_CE2 2:2 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_CE3 3:3 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_CE4 4:4 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_CE5 5:5 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_CESHIM 6:6 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_GR 7:7 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_GSP 8:8 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_NVDEC0 9:9 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_NVDEC1 10:10 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_NVENC0 11:11 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_OFA 12:12 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_PWR 13:13 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOP_ENGINE_SEC 14:14 /* R--VF */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOPB 0x24A60C /* R--4R */ #define NV_PERF_PMASYS_ENGINE_STATUS_STOPB_ENGINE_PMA 31:31 /* R--VF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0 0x0024A68C /* RWE4R */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_0 5:0 /* RWEVF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_0_INIT 0x00 /* RWE-V */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_1 13:8 /* RWEVF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_1_INIT 0x00 /* RWE-V */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_2 21:16 /* RWEVF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_2_INIT 0x00 /* RWE-V */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_3 29:24 /* RWEVF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT0_3_INIT 0x00 /* RWE-V */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1 0x0024A690 /* RWE4R */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_4 5:0 /* RWEVF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_4_INIT 0x00 /* RWE-V */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_5 13:8 /* RWEVF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_5_INIT 0x00 /* RWE-V */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_6 21:16 /* RWEVF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_6_INIT 0x00 /* RWE-V */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_7 29:24 /* RWEVF */ #define NV_PERF_PMASYS_ROUTER_TRIGGER_SELECT1_7_INIT 0x00 /* RWE-V */ #define NV_PERF_PMASYS_CONTROLB 0x0024A070 /* RW-4R */ #define NV_PERF_PMASYS_CONTROLB_MBU_CYA_SMB 0:0 /* RWEVF */ #define NV_PERF_PMASYS_CONTROLB_MBU_CYA_SMB_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMASYS_CONTROLB_MBU_CYA_SMB_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_MBU_CYA_SS 1:1 /* RWEVF */ #define NV_PERF_PMASYS_CONTROLB_MBU_CYA_SS_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMASYS_CONTROLB_MBU_CYA_SS_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_KEEP_LATEST 2:2 /* RWEVF */ #define NV_PERF_PMASYS_CONTROLB_KEEP_LATEST_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMASYS_CONTROLB_KEEP_LATEST_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_FAULT_NACK_CYA 3:3 /* RWEVF */ #define NV_PERF_PMASYS_CONTROLB_FAULT_NACK_CYA_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMASYS_CONTROLB_FAULT_NACK_CYA_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES 6:4 /* RWEUF */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES__PROD 0x00000004 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_0 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_32 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_64 0x00000002 /* RWE-V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_256 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_1K 0x00000004 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_4K 0x00000005 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_16K 0x00000006 /* RW--V */ #define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0 0x0024A010 /* RWE4R */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE0 0:0 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE0_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE1 1:1 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE1_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE2 2:2 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE2_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE3 3:3 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE3_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE4 4:4 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE4_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE5 5:5 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CE5_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CESHIM 6:6 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_CESHIM_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_GR 7:7 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_GR_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_GSP 8:8 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_GSP_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_NVDEC0 9:9 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_NVDEC0_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_NVDEC1 10:10 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_NVDEC1_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_NVENC0 11:11 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_NVENC0_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_OFA 12:12 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_OFA_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_PWR 13:13 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_PWR_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_SEC 14:14 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE0_ENGINE_SEC_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE1 0x24A014 /* RWE4R */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE1_ENGINE_PMA 31:31 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_MASK_SECURE1_ENGINE_PMA_INIT 1 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL(i) (0x0024A730+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_CONTROL__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_STREAM 0:0 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_STREAM_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_STREAM_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMACTXSW_MODE 1:1 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMACTXSW_MODE_ENABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMACTXSW_MODE_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_STOPVPMCAPTURE 2:2 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_STOPVPMCAPTURE_INIT 0x00000000 /* --E-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_STOPVPMCAPTURE_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_UPDATE_BYTES 3:3 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_UPDATE_BYTES_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_UPDATE_BYTES_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_MEMBUF_STATUS 4:4 /* R-EVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_MEMBUF_STATUS_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_MEMBUF_STATUS_OVERFLOWED 0x00000001 /* R---V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_MEMBUF_CLEAR_STATUS 5:5 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_MEMBUF_CLEAR_STATUS_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_MEMBUF_CLEAR_STATUS_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_FLUSH_COALESCE_FIFO 6:6 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_FLUSH_COALESCE_FIFO_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_FLUSH_COALESCE_FIFO_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMA_RECORD_STREAM 8:8 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMA_RECORD_STREAM_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMA_RECORD_STREAM_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_FE2ALL_CTXSW_FREEZE_ENABLE 22:22 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_FE2ALL_CTXSW_FREEZE_ENABLE_TRUE 0x00000001 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_FE2ALL_CTXSW_FREEZE_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMA_CTXSW_FREEZE 23:23 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMA_CTXSW_FREEZE_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_PMA_CTXSW_FREEZE_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_SEND_BIND 24:24 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_SEND_BIND_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_SEND_BIND_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK(i) (0x0024A638+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_PTR 29:0 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_PTR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_BASE 27:0 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_BASE_DEFAULT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET 29:28 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET_LFB 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET_SYS_COH 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET_SYS_NCOH 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID 31:31 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID_TRUE 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_OUTBASE(i) (0x0024A644+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_OUTBASE__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_OUTBASE_PTR 31:5 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_OUTBASE_PTR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER(i) (0x0024A648+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_PTR 7:0 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_PTR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_OUTSIZE(i) (0x0024A64C+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_OUTSIZE__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_OUTSIZE_NUMBYTES 31:5 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_OUTSIZE_NUMBYTES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_MEM_HEAD(i) (0x0024A650+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_MEM_HEAD__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_MEM_HEAD_PTR 31:4 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_MEM_HEAD_PTR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BYTES(i) (0x0024A654+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_MEM_BYTES__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_NUMBYTES 31:4 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_NUMBYTES_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BUMP(i) (0x0024A624+(i)*4) /* -W-4A */ #define NV_PERF_PMASYS_CHANNEL_MEM_BUMP__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_MEM_BUMP_NUMBYTES 31:4 /* -WEUF */ #define NV_PERF_PMASYS_CHANNEL_MEM_BUMP_NUMBYTES_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR(i) (0x0024A658+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_PTR 31:2 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_PTR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CTXSW(i) (0x0024A734+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_CTXSW__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_CTXSW_GPC_TRIGGER 0:0 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CTXSW_GPC_TRIGGER_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CTXSW_FBP_TRIGGER 1:1 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CTXSW_FBP_TRIGGER_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CTXSW_SYS_TRIGGER 2:2 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CTXSW_SYS_TRIGGER_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CTXSW_FAULT_NACK_HAPPENED 8:8 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CTXSW_FAULT_NACK_HAPPENED_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_GFID(i) (0x0024A634+(i)*4) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_GFID__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_GFID_PTR 5:0 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_GFID_PTR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGERCNT 0x0024A718 /* RW-4R */ #define NV_PERF_PMASYS_GPC_TRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMASYS_GPC_TRIGGERCNT_COUNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGERCNT 0x0024A71C /* RW-4R */ #define NV_PERF_PMASYS_FBP_TRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMASYS_FBP_TRIGGERCNT_COUNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGERCNT 0x0024A720 /* RW-4R */ #define NV_PERF_PMASYS_SYS_TRIGGERCNT_COUNT 5:0 /* RWEUF */ #define NV_PERF_PMASYS_SYS_TRIGGERCNT_COUNT_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_ENGINESTATUS 0x0024A75C /* R--4R */ #define NV_PERF_PMASYS_ENGINESTATUS_STATUS 2:0 /* R-EUF */ #define NV_PERF_PMASYS_ENGINESTATUS_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_ENGINESTATUS_STATUS_ACTIVE 0x00000001 /* R---V */ #define NV_PERF_PMASYS_ENGINESTATUS_STATUS_PAUSED 0x00000002 /* R---V */ #define NV_PERF_PMASYS_ENGINESTATUS_STATUS_QUIESCENT 0x00000003 /* R---V */ #define NV_PERF_PMASYS_ENGINESTATUS_STATUS_STALLED 0x00000005 /* R---V */ #define NV_PERF_PMASYS_ENGINESTATUS_STATUS_FAULTED 0x00000006 /* R---V */ #define NV_PERF_PMASYS_ENGINESTATUS_STATUS_HALTED 0x00000007 /* R---V */ #define NV_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY 4:4 /* R-EUF */ #define NV_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_EMPTY 0x00000001 /* R-E-V */ #define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS 6:5 /* R-EUF */ #define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS_IDLE 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS_BUSY 0x00000001 /* R---V */ #define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS_PENDING 0x00000002 /* R---V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE 0x0024A6A0 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODE_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODEB 0x24A6A4 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODEB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_TESLA_MODEB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE 0x0024A6B8 /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODE_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODEB 0x24A6BC /* RWE4R */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODEB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_GPC_TRIGGER_CONFIG_MIXED_MODEB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE 0x0024A6A8 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODE_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODEB 0x24A6AC /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODEB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_TESLA_MODEB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE 0x0024A6C0 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODE_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODEB 0x24A6C4 /* RWE4R */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODEB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_FBP_TRIGGER_CONFIG_MIXED_MODEB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE 0x0024A6B0 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODE_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODEB 0x24A6B4 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODEB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_TESLA_MODEB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE 0x0024A6C8 /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE0 0:0 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE1 1:1 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE2 2:2 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE3 3:3 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE3_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE4 4:4 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE4_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE5 5:5 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CE5_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CESHIM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_CESHIM_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GR 7:7 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GSP 8:8 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC0 9:9 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC1 10:10 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVDEC1_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVENC0 11:11 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_OFA 12:12 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_PWR 13:13 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_PWR_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_SEC 14:14 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODE_ENGINE_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODEB 0x24A6CC /* RWE4R */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODEB_ENGINE_PMA 31:31 /* RWEVF */ #define NV_PERF_PMASYS_SYS_TRIGGER_CONFIG_MIXED_MODEB_ENGINE_PMA_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL 0x0024A040 /* RW-4R */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_EN_CMD 0:0 /* RWEVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_EN_CMD_UNARMED 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_EN_CMD_ARMED 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_EN_CMD_INIT 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_EN_STATUS 1:1 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_EN_STATUS_BUSY 0x00000000 /* R---V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_EN_STATUS_ACKED 0x00000001 /* R---V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_EN_STATUS_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_INTR_STAT 2:2 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_INTR_STAT_NOT_ASSERTED 0x00000000 /* R---V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_INTR_STAT_ASSERTED 0x00000001 /* R---V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_BLOCK_INTR_STAT_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_INTR_OVERRIDE_VAL 3:3 /* RWEVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_INTR_OVERRIDE_VAL_FALSE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_INTR_OVERRIDE_VAL_TRUE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_OUTSTANDING_REQ 31:16 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_CTRL_OUTSTANDING_REQ_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0 0x0024A020 /* R--4R */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0_OP 4:0 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0_OP_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0_RD 5:5 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0_RD_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0_ADR_LO 31:6 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG0_ADR_LO_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1 0x0024A024 /* R--4R */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_ADR_HI 13:0 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_ADR_HI_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_SUBID 21:14 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_SUBID_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_WID 24:22 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_WID_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_SZ 29:25 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_SZ_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_L2_CLASS 31:30 /* R-EVF */ #define NV_PERF_PMASYS_SYS_FB_BLOCKER_DEBUG1_L2_CLASS_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_CG2 0x0024A044 /* RW-4R */ #define NV_PERF_PMASYS_CG2_SLCG 0:0 /* RWEVF */ #define NV_PERF_PMASYS_CG2_SLCG_ENABLED 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CG2_SLCG_DISABLED 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK 0x0024A038 /* RWE4R */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_PRIV_LEVEL_MASK_SOURCE_ENABLE_SEC2_IFF_PMA_ENABLED 0x00000244 /* RWE-V */ #define NV_PERF_PMASYS_CONTROLREG 0x0024A03C /* RWE4R */ #define NV_PERF_PMASYS_CONTROLREG_LEGACY_MODE 0:0 /* RWEUF */ #define NV_PERF_PMASYS_CONTROLREG_LEGACY_MODE_ENABLE 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_CONTROLREG_LEGACY_MODE_DISABLE 0x00000001 /* RWE-V */ #define NV_PERF_PMASYS_PMCONTROL 0x0024A08C /* RW-4R */ #define NV_PERF_PMASYS_PMCONTROL_GRP 3:0 /* RWEVF */ #define NV_PERF_PMASYS_PMCONTROL_GRP_DEBUGA 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_DEBUGB 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_COALESCEA 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_COALESCEB 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_HIGHSPEED 0x00000004 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_MBU 0x00000005 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_XACTIONS 0x00000006 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_HISTOGRAM 0x00000007 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_HIGHSPEED_INA 0x00000008 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_HIGHSPEED_INB 0x00000009 /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_HIGHSPEED_INC 0x0000000A /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_RFIFO_HISTOGRAM 0x0000000B /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_STATUS 0x0000000C /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_STATIC_PATTERN_111_10_GROUP 0x0000000E /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_GRP_STATIC_PATTERN_2EE_10_GROUP 0x0000000F /* RW--V */ #define NV_PERF_PMASYS_PMCONTROL_ENABLE 31:31 /* RWEVF */ #define NV_PERF_PMASYS_PMCONTROL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_PMCONTROL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_RECORD_REQUEST_GPC(i) (0x0024A200+(i)*4) /* -W-4A */ #define NV_PERF_PMASYS_RECORD_REQUEST_GPC__SIZE_1 16 /* */ #define NV_PERF_PMASYS_RECORD_REQUEST_GPC_REQ_XACTION 31:31 /* -WXUF */ #define NV_PERF_PMASYS_RECORD_REQUEST_GPC_REQ_XACTION_NOREQ 0x00000000 /* -W--V */ #define NV_PERF_PMASYS_RECORD_REQUEST_GPC_REQ_XACTION_REQ 0x00000001 /* -W--V */ #define NV_PERF_PMASYS_RECORD_REQUEST_FBP(i) (0x0024A280+(i)*4) /* -W-4A */ #define NV_PERF_PMASYS_RECORD_REQUEST_FBP__SIZE_1 16 /* */ #define NV_PERF_PMASYS_RECORD_REQUEST_FBP_REQ_XACTION 31:31 /* -WXUF */ #define NV_PERF_PMASYS_RECORD_REQUEST_FBP_REQ_XACTION_NOREQ 0x00000000 /* -W--V */ #define NV_PERF_PMASYS_RECORD_REQUEST_FBP_REQ_XACTION_REQ 0x00000001 /* -W--V */ #define NV_PERF_PMASYS_RECORD_REQUEST_SYS(i) (0x0024A300+(i)*4) /* -W-4A */ #define NV_PERF_PMASYS_RECORD_REQUEST_SYS__SIZE_1 16 /* */ #define NV_PERF_PMASYS_RECORD_REQUEST_SYS_REQ_XACTION 31:31 /* -WXUF */ #define NV_PERF_PMASYS_RECORD_REQUEST_SYS_REQ_XACTION_NOREQ 0x00000000 /* -W--V */ #define NV_PERF_PMASYS_RECORD_REQUEST_SYS_REQ_XACTION_REQ 0x00000001 /* -W--V */ #define NV_PERF_PMASYS_RECORD_DATA_GPC(i) (0x0024A400+(i)*4) /* -W-4A */ #define NV_PERF_PMASYS_RECORD_DATA_GPC__SIZE_1 16 /* */ #define NV_PERF_PMASYS_RECORD_DATA_GPC__PRIV_LEVEL_MASK 0x0024A038 /* */ #define NV_PERF_PMASYS_RECORD_DATA_GPC_DATA 31:0 /* -WXVF */ #define NV_PERF_PMASYS_RECORD_DATA_FBP(i) (0x0024A480+(i)*4) /* -W-4A */ #define NV_PERF_PMASYS_RECORD_DATA_FBP__SIZE_1 16 /* */ #define NV_PERF_PMASYS_RECORD_DATA_FBP__PRIV_LEVEL_MASK 0x0024A038 /* */ #define NV_PERF_PMASYS_RECORD_DATA_FBP_DATA 31:0 /* -WXVF */ #define NV_PERF_PMASYS_RECORD_DATA_SYS(i) (0x0024A500+(i)*4) /* -W-4A */ #define NV_PERF_PMASYS_RECORD_DATA_SYS__SIZE_1 16 /* */ #define NV_PERF_PMASYS_RECORD_DATA_SYS__PRIV_LEVEL_MASK 0x0024A038 /* */ #define NV_PERF_PMASYS_RECORD_DATA_SYS_DATA 31:0 /* -WXVF */ #define NV_PERF_PMASYS_RECORD_START_TRIGGERCNT 0x0024A724 /* RW-4R */ #define NV_PERF_PMASYS_RECORD_START_TRIGGERCNT_COUNT 31:0 /* RWEUF */ #define NV_PERF_PMASYS_RECORD_START_TRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMASYS_RECORD_STOP_TRIGGERCNT 0x0024A728 /* RW-4R */ #define NV_PERF_PMASYS_RECORD_STOP_TRIGGERCNT_COUNT 31:0 /* RWEUF */ #define NV_PERF_PMASYS_RECORD_STOP_TRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMASYS_RECORD_TOTAL_TRIGGERCNT 0x0024A72C /* RW-4R */ #define NV_PERF_PMASYS_RECORD_TOTAL_TRIGGERCNT_COUNT 31:0 /* RWEUF */ #define NV_PERF_PMASYS_RECORD_TOTAL_TRIGGERCNT_COUNT_INIT 0x0 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE(i) (0x0024A610+(i)*0x180) /* R-E4A */ #define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS 0:0 /* R-EVF */ #define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS_INIT 0x00000000 /* R-E-V */ #define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS_OVERFLOWED 0x00000001 /* R---V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_SECURE(i) (0x0024A61C+(i)*0x180) /* -WE4A */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_SECURE__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_SECURE_STOPVPMCAPTURE 31:31 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_SECURE_STOPVPMCAPTURE_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_SECURE_STOPVPMCAPTURE_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER(i) (0x0024A640+(i)*0x180) /* RW-4A */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES 6:4 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES__PROD 0x00000004 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_0 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_32 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_64 0x00000002 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_256 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_1K 0x00000004 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_4K 0x00000005 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_16K 0x00000006 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_64K 0x00000007 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_KEEP_LATEST 2:2 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_KEEP_LATEST_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_KEEP_LATEST_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER(i) (0x0024A620+(i)*0x180) /* RWE4A */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM 0:0 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_MEMBUF_CLEAR_STATUS 1:1 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_MEMBUF_CLEAR_STATUS_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_MEMBUF_CLEAR_STATUS_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_FLUSH_COALESCE_FIFO 2:2 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_FLUSH_COALESCE_FIFO_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_FLUSH_COALESCE_FIFO_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_SEND_BIND 3:3 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_SEND_BIND_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_SEND_BIND_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_RESET_DATA_FIFO 25:25 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_RESET_DATA_FIFO_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_RESET_DATA_FIFO_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES 31:31 /* -WEVF */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES_INIT 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES_DOIT 0x00000001 /* -W--T */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE(i) (0x0024A628+(i)*0x180) /* RWE4A */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP 3:0 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_DEBUGA 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_DEBUGB 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_COALESCEA 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_COALESCEB 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_HIGHSPEED 0x00000004 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_MBU 0x00000005 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_XACTIONS 0x00000006 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_HISTOGRAM 0x00000007 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_HIGHSPEED_INA 0x00000008 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_HIGHSPEED_INB 0x00000009 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_HIGHSPEED_INC 0x0000000A /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_RFIFO_HISTOGRAM 0x0000000B /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_STATUS 0x0000000C /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_STATIC_PATTERN_111_10_GROUP 0x0000000E /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_GRP_STATIC_PATTERN_2EE_10_GROUP 0x0000000F /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_ENABLE 31:31 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_PERFMUX_CONFIG_SECURE_PMCONTROL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER(i) (0x0024A694+(i)*0x180) /* RWE4A */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER__SIZE_1 1 /* */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE 0:0 /* RWEVF */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_WINDOW 1:1 /* RWEVF */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_WINDOW_INSIDE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_WINDOW_FREERUN 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_SOURCE 3:2 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_SOURCE_INTERNAL 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_SOURCE_REFCLK 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_SOURCE_RES_2 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_SOURCE_RES_3 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_CNTR 5:4 /* RWEUF */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_CNTR_ONE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_CNTR_EIGHT 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_CNTR_SIXTEEN 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_CNTR_THIRTYTWO 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM 6:6 /* RWEVF */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM_DISABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM_ENABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE(i) (0x0024A62C+(i)*0x180) /* RWE4A */ #define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_PMACTXSW_MODE 20:20 /* RWEVF */ #define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_PMACTXSW_MODE_ENABLE 0x00000000 /* RWE-V */ #define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_PMACTXSW_MODE_DISABLE 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_FE2ALL_CTXSW_FREEZE 21:21 /* RWEVF */ #define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_FE2ALL_CTXSW_FREEZE_DISABLE 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_CTXSW_CONFIG_SECURE_FE2ALL_CTXSW_FREEZE_ENABLE 0x00000001 /* RWE-V */ #define NV_PERF_PMASYS_CTXSW_CONTROL_FIRMWARE(i) (0x0024A630+(i)*0x180) /* -WE4A */ #define NV_PERF_PMASYS_CTXSW_CONTROL_FIRMWARE__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CTXSW_CONTROL_FIRMWARE_PMA_CTXSW_FREEZE 0:0 /* -WEVF */ #define NV_PERF_PMASYS_CTXSW_CONTROL_FIRMWARE_PMA_CTXSW_FREEZE_DISABLE 0x00000000 /* -WE-V */ #define NV_PERF_PMASYS_CTXSW_CONTROL_FIRMWARE_PMA_CTXSW_FREEZE_ENABLE 0x00000001 /* -W--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE(i) (0x0024A63C+(i)*0x180) /* RWE4A */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE__SIZE_1 1 /* */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_MBU_CYA_SS 1:1 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_MBU_CYA_SS_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_MBU_CYA_SS_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_MBU_CYA_SMB 2:2 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_MBU_CYA_SMB_DISABLE 0x0 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_MBU_CYA_SMB_ENABLE 0x1 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_FAULT_NACK_CYA 3:3 /* RWEVF */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_FAULT_NACK_CYA_DISABLE 0x0 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_FAULT_NACK_CYA_ENABLE 0x1 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT 13:8 /* RWEUF */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_CE0 0x00000000 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_CE1 0x00000001 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_CE2 0x00000002 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_CE3 0x00000003 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_CE4 0x00000004 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_CE5 0x00000005 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_CESHIM 0x00000006 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_GR 0x00000007 /* RWE-V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_GSP 0x00000008 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_NVDEC0 0x00000009 /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_NVDEC1 0x0000000A /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_NVENC0 0x0000000B /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_OFA 0x0000000C /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_PMA 0x0000000D /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_PWR 0x0000000E /* RW--V */ #define NV_PERF_PMASYS_CHANNEL_CONFIG_SECURE_PMA_RECORD_TRIGGER_SELECT_SEC 0x0000000F /* RW--V */ #endif // __ga102_dev_perf_h__