/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_nvdec_pri_h__ #define __ga102_dev_nvdec_pri_h__ /* This file is autogenerated. Do not edit */ #define NV_PNVDEC(dev) 0x0084bfff+(dev)*16384:0x00848000+(dev)*16384 /* RW--D */ #define NV_PNVDEC__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEM_PDUK_IDX 0 #define NV_PNVDEC_FALCON_KMEM_PMUK_IDX 1 #define NV_PNVDEC_FALCON_KMEM_KEK_IDX 2 #define NV_PNVDEC_FALCON_KMEM_EK_LOW_IDX 3 #define NV_PNVDEC_FALCON_KMEM_EK_HIGH_IDX 4 #define NV_PNVDEC_FALCON_KMEM_MPK_LOW_IDX 6 #define NV_PNVDEC_FALCON_KMEM_MPK_HIGH_IDX 7 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_READ 0:0 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_READ_ENABLE 0x00000001 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_READ_DISABLE 0x00000000 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE 1:1 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE_ENABLE 0x00000001 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE_DISABLE 0x00000000 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_READ 2:2 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_READ_ENABLE 0x00000001 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_READ_DISABLE 0x00000000 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE 3:3 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE_ENABLE 0x00000001 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE_DISABLE 0x00000000 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_READ 4:4 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_READ_ENABLE 0x00000001 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_READ_DISABLE 0x00000000 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE 5:5 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE_ENABLE 0x00000001 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE_DISABLE 0x00000000 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_READ 6:6 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_READ_ENABLE 0x00000001 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_READ_DISABLE 0x00000000 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE 7:7 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE_ENABLE 0x00000001 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE_DISABLE 0x00000000 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_ACL_K0 8:8 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_ACL_K3 9:9 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_RECYCLABLE 10:10 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_PRIV_EN 11:11 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_NS_63LOADABLE 12:12 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_LS_63LOADABLE 13:13 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_HS_63LOADABLE 14:14 #define NV_PNVDEC_FALCON_KMEM_PROTECTINFO_UCODEIDMASK 31:15 #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK(dev) (0x00848280+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK(dev) (0x00848284+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK(dev) (0x00848288+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK(dev) (0x00848290+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK(dev) (0x008480e8+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK(dev) (0x008480ec+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse2" /* */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK(dev) (0x00848298+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK(dev) (0x0084829c+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK(dev) (0x008483d0+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK(dev) (0x008483f0+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK(dev) (0x008483f4+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK(dev) (0x008483f8+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK(dev) (0x008483fc+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x8 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(dev,i) (0x008483d8+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_2 2 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(dev,i) (0x0084818c+(dev)*16384+(i)*16) /* RW-4A */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_2 1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev,i) (0x008482b0+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK(dev) (0x00848194+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK(dev) (0x00848198+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK(dev) (0x0084819c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK(dev) (0x008481a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK(dev) (0x008481a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK(dev) (0x008481a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK(dev) (0x008481bc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK(dev) (0x008481e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK(dev) (0x008481e4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK(dev) (0x008481e8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK(dev) (0x008481ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK(dev) (0x008481f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK(dev) (0x008481f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK(dev) (0x008481f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK(dev) (0x008481fc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK(dev) (0x00848220+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK(dev) (0x00848224+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK(dev) (0x0084822c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSSET(dev) (0x00848000+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_IRQSSET__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_GPTMR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_WDTMR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_MTHD_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_CTXSW_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_HALT_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_EXTERR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_SWGEN0_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_SWGEN1_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ1_SET 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ2_SET 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ3_SET 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ4_SET 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ5_SET 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ6_SET 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ7_SET 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */ #define NV_PNVDEC_FALCON_IRQSSET_EXT_EXTIRQ8_SET 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_DMA_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSSET_SHA 17:17 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSSET_SHA_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR(dev) (0x00848004+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_IRQSCLR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_GPTMR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_WDTMR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_MTHD_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_CTXSW_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_HALT_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXTERR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_SWGEN0_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_SWGEN1_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_DMA_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQSCLR_SHA_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQSTAT(dev) (0x00848008+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_IRQSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_GPTMR_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_GPTMR_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_WDTMR_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_WDTMR_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_MTHD_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_MTHD_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_CTXSW_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_CTXSW_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_HALT_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_HALT_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXTERR_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXTERR_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_SWGEN0_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_SWGEN0_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_SWGEN1_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_SWGEN1_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_DMA_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_DMA_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQSTAT_SHA_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQSTAT_SHA_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMODE(dev) (0x0084800c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IRQMODE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQMODE__PRIV_LEVEL_MASK(dev) (0x00848290+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IRQMODE__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_MTHD_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_MTHD_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_MTHD_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_HALT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_HALT_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_HALT_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXTERR_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_INIT 0xfc /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_DMA_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_DMA_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_DMA_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SHA 17:17 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SHA_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SHA_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQMODE_LVL_SHA_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK(dev) (0x008480e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IRQSCMASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK__PRIV_LEVEL_MASK(dev) (0x008481a4+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IRQSCMASK__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_GPTMR_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_GPTMR_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_WDTMR_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_WDTMR_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_MTHD_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_MTHD_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_CTXSW_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_CTXSW_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_HALT_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_HALT_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXTERR_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXTERR_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_ENABLE 0xff /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_DISABLE 0x00 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_DMA_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_DMA_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQSCMASK_SHA 17:17 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQSCMASK_SHA_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQSCMASK_SHA_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL(dev,i) (0x008483e0+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_INTR_CTRL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL__SIZE_2 2 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_INTR_CTRL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_INTR_CTRL_VECTOR 11:0 /* RW-VF */ #define NV_PNVDEC_FALCON_INTR_CTRL_GFID 25:20 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_GFID_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_GSP 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_GSP_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_GSP_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_CTRL_CPU 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_INTR_CTRL_CPU_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_INTR_CTRL_CPU_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_INTR_RETRIGGER(dev,i) (0x008483e8+(dev)*16384+(i)*4) /* -W-4A */ #define NV_PNVDEC_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_INTR_RETRIGGER__SIZE_2 2 /* */ #define NV_PNVDEC_FALCON_INTR_RETRIGGER__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_INTR_RETRIGGER__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */ #define NV_PNVDEC_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET(dev) (0x00848010+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_IRQMSET__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQMSET__PRIV_LEVEL_MASK(dev) (0x00848290+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IRQMSET__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_GPTMR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_WDTMR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_MTHD_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_CTXSW_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_HALT_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXTERR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_SWGEN0_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_SWGEN1_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_DMA_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMSET_SHA 17:17 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMSET_SHA_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR(dev) (0x00848014+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_IRQMCLR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQMCLR__PRIV_LEVEL_MASK(dev) (0x00848290+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IRQMCLR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_GPTMR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_WDTMR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_MTHD_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_CTXSW_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_HALT_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXTERR_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_SWGEN0_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_SWGEN1_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_DMA_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMCLR_SHA 17:17 /* -WXVF */ #define NV_PNVDEC_FALCON_IRQMCLR_SHA_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_IRQMASK(dev) (0x00848018+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_IRQMASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_GPTMR_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_GPTMR_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_WDTMR_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_WDTMR_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_MTHD_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_MTHD_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_CTXSW_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_CTXSW_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_HALT_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_HALT_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXTERR_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_EXTERR_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_SWGEN0_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_SWGEN0_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_SWGEN1_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_SWGEN1_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_DMA_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_DMA_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQMASK_SHA 17:17 /* R-IVF */ #define NV_PNVDEC_FALCON_IRQMASK_SHA_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IRQMASK_SHA_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IRQDEST(dev) (0x0084801c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IRQDEST__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQDEST__PRIV_LEVEL_MASK(dev) (0x00848290+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IRQDEST__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_GPTMR_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_WDTMR_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_MTHD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_MTHD_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_MTHD_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_CTXSW_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_HALT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_HALT_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_HALT_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXTERR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXTERR_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_MTHD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_HALT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2(dev) (0x0084803c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IRQDEST2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQDEST2__PRIV_LEVEL_MASK(dev) (0x00848290+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IRQDEST2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST2_HOST_DMA_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST2_HOST_DMA_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_HOST_DMA_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_HOST_SHA 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST2_HOST_SHA_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST2_HOST_SHA_FALCON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_HOST_SHA_HOST 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_DMA_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_SHA 17:17 /* RWIVF */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_SHA_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ0 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_SHA_HOST_NORMAL 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IRQDEST2_TARGET_SHA_HOST_NONSTALL 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_GPTMRINT(dev) (0x00848020+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_GPTMRINT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_GPTMRINT__PRIV_LEVEL_MASK(dev) (0x008481a0+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_GPTMRINT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_GPTMRVAL(dev) (0x00848024+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_GPTMRVAL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_GPTMRVAL__PRIV_LEVEL_MASK(dev) (0x008481a0+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_GPTMRVAL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_GPTMRCTL(dev) (0x00848028+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_GPTMRCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_GPTMRCTL__PRIV_LEVEL_MASK(dev) (0x008481a0+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_GPTMRCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_GPTMRCTL_GPTMREN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_PTIMER0(dev) (0x0084802c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_PTIMER0__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PTIMER0__PRIV_LEVEL_MASK(dev) (0x008481bc+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_PTIMER0__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_PTIMER1(dev) (0x00848030+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_PTIMER1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PTIMER1__PRIV_LEVEL_MASK(dev) (0x008481bc+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_PTIMER1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_WDTMRVAL(dev) (0x00848034+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_WDTMRVAL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_WDTMRVAL__PRIV_LEVEL_MASK(dev) (0x0084829c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_WDTMRVAL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMRCTL(dev) (0x00848038+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_WDTMRCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_WDTMRCTL__PRIV_LEVEL_MASK(dev) (0x0084829c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_WDTMRCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMRCTL_WDTMREN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDDATA(dev) (0x00848064+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_MTHDDATA__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDDATA__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_MTHDDATA__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_PNVDEC_FALCON_MTHDID(dev) (0x00848068+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_MTHDID__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDID__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_MTHDID__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_PNVDEC_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_PNVDEC_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_PNVDEC_FALCON_MTHDID_PRIV_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDID_PRIV_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_PNVDEC_FALCON_MTHDID_WPEND_DONE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_MTHDID_WPEND_PENDING 0x1 /* R---V */ #define NV_PNVDEC_FALCON_MTHDWDAT(dev) (0x0084806c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_MTHDWDAT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDWDAT__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_MTHDWDAT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_MTHDCOUNT(dev) (0x00848070+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_MTHDCOUNT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_PNVDEC_FALCON_MTHDCOUNT_COUNT_INIT 0x0000 /* R-I-V */ #define NV_PNVDEC_FALCON_MTHDPOP(dev) (0x00848074+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_MTHDPOP__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDPOP__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_MTHDPOP__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_PNVDEC_FALCON_MTHDPOP_POP_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_MTHDPOP_POP_FALSE 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_MTHDRAMSZ(dev) (0x00848078+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_MTHDRAMSZ__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_PNVDEC_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_FALCON_CURCTX(dev) (0x00848050+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_CURCTX__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CURCTX__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_CURCTX__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_CURCTX_CTXVLD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_CURCTX_CTXVLD_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CURCTX_CTXVLD_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PNVDEC_FALCON_CURCTX_CTXTGT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PNVDEC_FALCON_CURCTX_CTXPTR_INIT 0x0000000 /* RWI-V */ #define NV_PNVDEC_FALCON_NXTCTX(dev) (0x00848054+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_NXTCTX__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_NXTCTX__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_NXTCTX__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_NXTCTX_CTXVLD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_NXTCTX_CTXVLD_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_NXTCTX_CTXVLD_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PNVDEC_FALCON_NXTCTX_CTXTGT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PNVDEC_FALCON_NXTCTX_CTXPTR_INIT 0x0000000 /* RWI-V */ #define NV_PNVDEC_FALCON_CTXACK(dev) (0x00848058+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_CTXACK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CTXACK__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_CTXACK__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_PNVDEC_FALCON_CTXACK_SAVE_ACK_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_CTXACK_SAVE_ACK_CLEAR 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_PNVDEC_FALCON_CTXACK_REST_ACK_SET 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_CTXACK_REST_ACK_CLEAR 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_CURCTX2(dev) (0x008483c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_CURCTX2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CURCTX2__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_CURCTX2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CURCTX2_CTXGFID 5:0 /* RWIVF */ #define NV_PNVDEC_FALCON_CURCTX2_CTXGFID_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_NXTCTX2(dev) (0x008483cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_NXTCTX2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_NXTCTX2__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_NXTCTX2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_NXTCTX2_CTXGFID 5:0 /* RWIVF */ #define NV_PNVDEC_FALCON_NXTCTX2_CTXGFID_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_MAILBOX0(dev) (0x00848040+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_MAILBOX0__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_MAILBOX1(dev) (0x00848044+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_MAILBOX1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_ITFEN(dev) (0x00848048+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_ITFEN__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ITFEN__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_ITFEN__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_ITFEN_CTXEN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_ITFEN_CTXEN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_CTXEN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_ITFEN_MTHDEN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_ITFEN_MTHDEN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_MTHDEN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_PNVDEC_FALCON_ITFEN_PRIV_POSTWR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_ITFEN_CTXSW_NACK_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ITFEN_CTXSW_NACK_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_PNVDEC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IDLESTATE(dev) (0x0084804c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IDLESTATE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IDLESTATE__PRIV_LEVEL_MASK(dev) (0x008481e0+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IDLESTATE__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_PNVDEC_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_PNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_PNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_IDLESTATE_INT_BUSY_SHA 24:24 /* R-IVF */ #define NV_PNVDEC_FALCON_IDLESTATE_INT_BUSY_SHA_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IDLESTATE_INT_BUSY_SHA_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_FHSTATE(dev) (0x0084805c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_FHSTATE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_FHSTATE__PRIV_LEVEL_MASK(dev) (0x008481e4+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_FHSTATE__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_PNVDEC_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_PNVDEC_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_PNVDEC_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_PNVDEC_FALCON_FHSTATE_STALL_REQ_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_FHSTATE_STALL_REQ_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_PRIVSTATE(dev) (0x00848060+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_PRIVSTATE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE__PRIV_LEVEL_MASK(dev) (0x008483d0+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_PRIVSTATE__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_PRIV_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_VPR_FORCE_STICKY 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SFTRESET(dev) (0x0084807c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SFTRESET__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SFTRESET__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SFTRESET__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_PNVDEC_FALCON_SFTRESET_EXT_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SFTRESET_EXT_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL(dev) (0x008480a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_ENGCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_PNVDEC_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_PNVDEC_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_PNVDEC_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_PNVDEC_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_PNVDEC_FALCON_ENGCTL_STALLREQ_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_ENGCTL_STALLREQ_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_PNVDEC_FALCON_ENGCTL_STALLACK_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_ENGCTL_STALLACK_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_ADDR(dev) (0x008480ac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ADDR__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_ADDR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ADDR_LSB 5:0 /* RWIVF */ #define NV_PNVDEC_FALCON_ADDR_LSB_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_PNVDEC_FALCON_ADDR_MSB_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_ADDR_EXT 11:0 /* */ #define NV_PNVDEC_FALCON_DMACTL(dev) (0x0084810c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMACTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMACTL__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMACTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMACTL_REQUIRE_CTX_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_PNVDEC_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_PNVDEC_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */ #define NV_PNVDEC_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_PNVDEC_FALCON_DMATRFBASE(dev) (0x00848110+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMATRFBASE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFBASE__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMATRFBASE__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_DMATRFMOFFS(dev) (0x00848114+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMATRFMOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMATRFMOFFS_OFFS_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_FALCON_DMATRFCMD(dev) (0x00848118+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMATRFCMD__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFCMD__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMATRFCMD__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_FULL_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMATRFCMD_FULL_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_IDLE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMATRFCMD_IDLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_IMEM_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_IMEM_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_WRITE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_WRITE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_NOTIFY_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_NOTIFY_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_SIZE_4B 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SIZE_8B 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SIZE_16B 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SIZE_32B 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SIZE_64B 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SIZE_128B 0x5 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SIZE_256B 0x6 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_ERROR_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMATRFCMD_ERROR_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_PNVDEC_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMATRFFBOFFS(dev) (0x0084811c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMATRFFBOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB(dev) (0x00848120+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMAPOLL_FB__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP(dev) (0x00848124+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMAPOLL_CP__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMATRFBASE1(dev) (0x00848128+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMATRFBASE1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMATRFBASE1_BASE_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_LOW(dev) (0x008482c0+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_LOW__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH(dev) (0x008482c4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_LOW(dev) (0x008482c8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_LOW__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH(dev) (0x008482cc+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_LOW(dev) (0x008482d0+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_LOW__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH(dev) (0x008482d4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_LOW(dev) (0x008482d8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_LOW__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH(dev) (0x008482dc+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CTL(dev) (0x008482e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMAINFO_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_HIGH(dev) (0x008482e4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_HIGH__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_LOW(dev) (0x008482e8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_LOW__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK(dev) (0x00848190+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_IMEMC(dev,i) (0x00848180+(dev)*16384+(i)*16) /* RW-4A */ #define NV_PNVDEC_FALCON_IMEMC__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEMC__SIZE_2 1 /* */ #define NV_PNVDEC_FALCON_IMEMC__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_IMEMC__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEMC_OFFS_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEMC_BLK_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEMC_AINCW_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IMEMC_AINCW_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEMC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IMEMC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_PNVDEC_FALCON_IMEMC_SECURE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_PNVDEC_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_PNVDEC_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_PNVDEC_FALCON_IMEMC_SEC_LOCK_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_IMEMC_SEC_LOCK_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_IMEMD(dev,i) (0x00848184+(dev)*16384+(i)*16) /* RW-4A */ #define NV_PNVDEC_FALCON_IMEMD__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEMD__SIZE_2 1 /* */ #define NV_PNVDEC_FALCON_IMEMD__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_IMEMD__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_IMEMT(dev,i) (0x00848188+(dev)*16384+(i)*16) /* RW-4A */ #define NV_PNVDEC_FALCON_IMEMT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEMT__SIZE_2 1 /* */ #define NV_PNVDEC_FALCON_IMEMT__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_IMEMT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_PNVDEC_FALCON_DMEMC(dev,i) (0x008481c0+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_FALCON_DMEMC__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEMC__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_DMEMC__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_DMEMC__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEMC_ADDRESS_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_PNVDEC_FALCON_DMEMC_OFFS_INIT 0x00 /* */ #define NV_PNVDEC_FALCON_DMEMC_BLK 23:8 /* */ #define NV_PNVDEC_FALCON_DMEMC_BLK_INIT 0x0000 /* */ #define NV_PNVDEC_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEMC_AINCW_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_AINCW_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEMC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEMC_SETTAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEMC_SETTAG_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_SETTAG_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEMC_SETLVL_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEMC_SETLVL_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_SETLVL_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_PNVDEC_FALCON_DMEMC_VA_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMEMC_VA_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_VA_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_PNVDEC_FALCON_DMEMC_MISS_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMEMC_MISS_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_PNVDEC_FALCON_DMEMC_MULTIHIT_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMEMC_MULTIHIT_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_PNVDEC_FALCON_DMEMC_LVLERR_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_DMEMC_LVLERR_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_DMEMD(dev,i) (0x008481c4+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_FALCON_DMEMD__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEMD__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_DMEMD__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_DMEMD__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_DMEMT(dev,i) (0x00848210+(dev)*16384+(i)*4) /* -W-4A */ #define NV_PNVDEC_FALCON_DMEMT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEMT__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_DMEMT__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_DMEMT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_PNVDEC_FALCON_DMEML(dev,i) (0x008482a0+(dev)*16384+(i)*4) /* -W-4A */ #define NV_PNVDEC_FALCON_DMEML__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEML__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_DMEML__PRIV_LEVEL_MASK(dev) NV_PNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev) /* */ #define NV_PNVDEC_FALCON_DMEML__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_PNVDEC_FALCON_DMEM_DUMMY(dev) (0x00848258+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DMEM_DUMMY__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK(dev) (0x00848284+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PNVDEC_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PNVDEC_FALCON_IMEM_DUMMY(dev) (0x008481b4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_IMEM_DUMMY__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK(dev) (0x00848280+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PNVDEC_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PNVDEC_FALCON_DIO_RESET_DELAY(dev) (0x00848274+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DIO_RESET_DELAY__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIO_RESET_DELAY__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DIO_RESET_DELAY__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIO_RESET_DELAY_VALUE 15:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DIO_RESET_DELAY_VALUE_INIT 0x0100 /* RWI-V */ #define NV_PNVDEC_FALCON_DOC_CTRL(dev) (0x00848340+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DOC_CTRL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DOC_CTRL__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DOC_CTRL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DOC_CTRL_COUNT 7:0 /* R--VF */ #define NV_PNVDEC_FALCON_DOC_CTRL_RESET 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_DOC_CTRL_RESET_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DOC_CTRL_STOP 17:17 /* RWIVF */ #define NV_PNVDEC_FALCON_DOC_CTRL_STOP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DOC_CTRL_EMPTY 18:18 /* R-IVF */ #define NV_PNVDEC_FALCON_DOC_CTRL_EMPTY_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_DOC_CTRL_WR_FINISHED 19:19 /* R-IVF */ #define NV_PNVDEC_FALCON_DOC_CTRL_WR_FINISHED_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_DOC_CTRL_RD_FINISHED 20:20 /* R-IVF */ #define NV_PNVDEC_FALCON_DOC_CTRL_RD_FINISHED_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_DOC_CTRL_WR_ERROR 21:21 /* RWIVF */ #define NV_PNVDEC_FALCON_DOC_CTRL_WR_ERROR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DOC_CTRL_RD_ERROR 22:22 /* RWIVF */ #define NV_PNVDEC_FALCON_DOC_CTRL_RD_ERROR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DOC_CTRL_PROTOCOL_ERROR 23:23 /* RWIVF */ #define NV_PNVDEC_FALCON_DOC_CTRL_PROTOCOL_ERROR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DOC_D0(dev) (0x00848344+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DOC_D0__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DOC_D0__PRIV_LEVEL_MASK(dev) (0x008480ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DOC_D0__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DOC_D0_DATA 31:0 /* RW-VF */ #define NV_PNVDEC_FALCON_DOC_D1(dev) (0x00848348+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DOC_D1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DOC_D1__PRIV_LEVEL_MASK(dev) (0x008480ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DOC_D1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DOC_D1_DATA 31:0 /* RW-VF */ #define NV_PNVDEC_FALCON_DOC_D2(dev) (0x0084834c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DOC_D2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DOC_D2__PRIV_LEVEL_MASK(dev) (0x008480ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DOC_D2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DOC_D2_DATA 15:0 /* RW-VF */ #define NV_PNVDEC_FALCON_DIC_CTRL(dev) (0x00848350+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DIC_CTRL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIC_CTRL__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DIC_CTRL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIC_CTRL_COUNT 7:0 /* R--VF */ #define NV_PNVDEC_FALCON_DIC_CTRL_RESET 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_DIC_CTRL_RESET_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DIC_CTRL_VALID 19:19 /* R-IVF */ #define NV_PNVDEC_FALCON_DIC_CTRL_VALID_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_DIC_CTRL_POP 20:20 /* -W-VF */ #define NV_PNVDEC_FALCON_DIC_D0(dev) (0x00848354+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DIC_D0__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIC_D0__PRIV_LEVEL_MASK(dev) (0x008480ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DIC_D0__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIC_D0_DATA 31:0 /* RW-VF */ #define NV_PNVDEC_FALCON_DIC_D1(dev) (0x00848358+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DIC_D1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIC_D1__PRIV_LEVEL_MASK(dev) (0x008480ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DIC_D1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIC_D1_DATA 31:0 /* RW-VF */ #define NV_PNVDEC_FALCON_DIC_D2(dev) (0x0084835c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DIC_D2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIC_D2__PRIV_LEVEL_MASK(dev) (0x008480ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DIC_D2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIC_D2_DATA 15:0 /* RW-VF */ #define NV_PNVDEC_FALCON_DIO_ERR(dev) (0x00848360+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_DIO_ERR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIO_ERR__PRIV_LEVEL_MASK(dev) (0x008480ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DIO_ERR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DIO_ERR_INFO 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0(dev,i) (0x00848300+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK(dev) (0x008483f0+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1(dev,i) (0x00848310+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK(dev) (0x008483f4+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2(dev,i) (0x00848320+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK(dev) (0x008483f8+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3(dev,i) (0x00848330+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK(dev) (0x008483fc+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_PRGNVER(dev) (0x008483d4+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_PRGNVER__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_PNVDEC_FALCON_PRGNVER_MAJOR_DEFT 0x2 /* R-I-V */ #define NV_PNVDEC_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_PNVDEC_FALCON_PRGNVER_MINOR_DEFT 0x0000 /* R-I-V */ #define NV_PNVDEC_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_PNVDEC_FALCON_PRGNVER_BUGFIX_DEFT 0x0000 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG(dev) (0x00848108+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_HWCFG__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_PNVDEC_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_PNVDEC_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG1(dev) (0x0084812c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_HWCFG1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_INIT 0x6 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_1_0 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_2_0 0x2 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_3_0 0x3 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_4_0 0x4 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_5_0 0x5 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_6_0 0x6 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_7_0 0x7 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x3 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x2 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x3 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x2 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x3 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_IMEM_PORTS_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_DMEM_PORTS_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_TAG_WIDTH_INIT 0x10 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x10 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_PNVDEC_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2(dev) (0x008480f4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_HWCFG2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_SHA_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_SHA_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_BMEM_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_BMEM_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_PKCBOOT_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_PKCBOOT_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_DBGMODE_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_DBGMODE_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_KMEM_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_KMEM_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_VHR_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_VHR_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_HS_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_HS_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_SECUREBUS_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_SECUREBUS_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_HWCFG3(dev) (0x00848278+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_HWCFG3__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_PNVDEC_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_PNVDEC_FALCON_CGCTL(dev) (0x008480a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_CGCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_CGCTL_CG_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2(dev) (0x00848134+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_CG2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CG2__PRIV_LEVEL_MASK(dev) (0x008481e8+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_CG2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CG2_SLCG 17:1 /* */ #define NV_PNVDEC_FALCON_CG2_SLCG_ENABLED 0x00000 /* */ #define NV_PNVDEC_FALCON_CG2_SLCG_DISABLED 0x1ffff /* */ #define NV_PNVDEC_FALCON_CG2_SLCG__PROD 0x000a0 /* */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FBIF_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FBIF_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_SHA 18:18 /* RWIVF */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_SHA__PROD 0x1 /* */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_SHA_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CG2_SLCG_FALCON_SHA_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_ENGID(dev) (0x0084813c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_ENGID__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ENGID_INSTID 7:0 /* R-IVF */ #define NV_PNVDEC_FALCON_ENGID_INSTID_INIT 0x00 /* R-I-V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID 15:8 /* R--VF */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_SEC 0x01 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_DPU 0x02 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_NVDEC 0x03 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_PWR_PMU 0x04 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_FBFACLON 0x05 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_NVENC 0x06 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_GPCCS 0x07 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_FECS 0x08 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_MINION 0x09 /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_XUSB 0x0a /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_GSP 0x0b /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_NVJPG 0x0c /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_OFA 0x0d /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_PSC 0x0e /* R---V */ #define NV_PNVDEC_FALCON_ENGID_FAMILYID_SOE 0x0f /* R---V */ #define NV_PNVDEC_FALCON_SCTL(dev) (0x00848240+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SCTL__PRIV_LEVEL_MASK(dev) (0x00848298+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_LSMODE_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_LSMODE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_PNVDEC_FALCON_SCTL_HSMODE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_SCTL_HSMODE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_LSMODE_LEVEL_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_PNVDEC_FALCON_SCTL_UCODE_LEVEL_INIT 0x0 /* */ #define NV_PNVDEC_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL_AUTH_EN_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SCTL_AUTH_EN_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL1(dev) (0x00848250+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SCTL1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SCTL1__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SCTL1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL1_CSBLVL_MASK_INIT 0x3 /* RWI-V */ #define NV_PNVDEC_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_PNVDEC_FALCON_SCTL1_EXTLVL_MASK_INIT 0x3 /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL(dev) (0x008480e4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_HSCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_HSCTL__PRIV_LEVEL_MASK(dev) (0x008480e8+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_HSCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_TRACEPC_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_TRACEPC_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_HSCTL_SP_MIN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_HSCTL_SP_MIN_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_OS(dev) (0x00848080+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_OS__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_RM(dev) (0x00848084+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_RM__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_SOFT_PM(dev) (0x00848088+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SOFT_PM__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SOFT_PM__PRIV_LEVEL_MASK(dev) (0x008481ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SOFT_PM__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_PNVDEC_FALCON_SOFT_PM_TRIGGER_START_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_SOFT_PM_TRIGGER_END_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SOFT_PM_PROBE_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_SOFT_MODE(dev) (0x0084808c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SOFT_MODE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SOFT_MODE__PRIV_LEVEL_MASK(dev) (0x008481ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SOFT_MODE__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SOFT_MODE_PROBE_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_PMM(dev) (0x008480a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_PMM__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PMM__PRIV_LEVEL_MASK(dev) (0x008481ec+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_PMM__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_CODE 0x01 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x02 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x03 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x04 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x05 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_IPND 0x06 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x07 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_SB 0x08 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x09 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0a /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0b /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0c /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0d /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0e /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0f /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x10 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x11 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_PNVDEC_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x5 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x5 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x6 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x7 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x9 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0xa /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0xb /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_PNVDEC_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL 19:16 /* RWIVF */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_FB_BSY 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_RDAT_WAIT 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ32BYTE 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ64BYTE 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ128BYTE 0x5 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x6 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_FB_BSY_SC 0x7 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_RDAT_WAIT_SC 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ32BYTE_SC 0x9 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ64BYTE_SC 0xa /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ128BYTE_SC 0xb /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_WREQ 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x5 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RREQ 0x6 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x7 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_WREQ_SC 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x9 /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0xa /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0xb /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0xc /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0xd /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RREQ_SC 0xe /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0xf /* RW--V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_PNVDEC_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DEBUG1(dev) (0x00848090+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DEBUG1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DEBUG1__PRIV_LEVEL_MASK(dev) (0x00848294+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DEBUG1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x0040 /* RWI-V */ #define NV_PNVDEC_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_DEBUG1_CTXSW_MODE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_PNVDEC_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_PNVDEC_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DEBUGINFO(dev) (0x00848094+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DEBUGINFO__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_SP_MIN(dev) (0x00848270+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SP_MIN__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SP_MIN__PRIV_LEVEL_MASK(dev) (0x008481f0+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SP_MIN__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SP_MIN_VALUE_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_FALCON_EXCI(dev) (0x008480d0+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_EXCI__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_EXCI__PRIV_LEVEL_MASK(dev) (0x008481f4+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_EXCI__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_TRAP0 0x00 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_TRAP1 0x01 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_TRAP2 0x02 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_TRAP3 0x03 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_ILL_INS 0x08 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_INV_INS 0x09 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_MISS_INS 0x0a /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0b /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0d /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0f /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x10 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x11 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x12 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x13 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_BROM_CALL_INS 0x15 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_KMEM_VIOLATION_INS 0x16 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXCAUSE_BMEM_PERMISSION_INS 0x17 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_PNVDEC_FALCON_EXCI2(dev) (0x008480bc+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_EXCI2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_EXCI2__PRIV_LEVEL_MASK(dev) (0x008481f4+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_EXCI2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_PNVDEC_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_PNVDEC_FALCON_SVEC_SPR(dev) (0x008480d4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SVEC_SPR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR__PRIV_LEVEL_MASK(dev) (0x008481f8+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SVEC_SPR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_PNVDEC_FALCON_SVEC_SPR_SIGPASS_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SVEC_SPR_SIGPASS_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_CPUCTL(dev) (0x00848100+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_CPUCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CPUCTL__PRIV_LEVEL_MASK(dev) (0x00848288+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_CPUCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_PNVDEC_FALCON_CPUCTL_IINVAL_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_IINVAL_FALSE 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_PNVDEC_FALCON_CPUCTL_STARTCPU_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_STARTCPU_FALSE 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_PNVDEC_FALCON_CPUCTL_SRESET_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_SRESET_FALSE 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_PNVDEC_FALCON_CPUCTL_HRESET_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_HRESET_FALSE 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_PNVDEC_FALCON_CPUCTL_HALTED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_CPUCTL_HALTED_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_PNVDEC_FALCON_CPUCTL_STOPPED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_CPUCTL_STOPPED_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS_EN_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS_EN_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS(dev) (0x00848130+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x1 /* -W--V */ #define NV_PNVDEC_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x0 /* -W--V */ #define NV_PNVDEC_FALCON_STACKCFG(dev) (0x00848138+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_STACKCFG__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_STACKCFG__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_STACKCFG__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_PNVDEC_FALCON_STACKCFG_BOTTOM_INIT 0x000000 /* RW--V */ #define NV_PNVDEC_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_STACKCFG_SPEXC_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_STACKCFG_SPEXC_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_STACKCFG_SPEXC_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_BOOTVEC(dev) (0x00848104+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_BOOTVEC__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BOOTVEC__PRIV_LEVEL_MASK(dev) (0x00848194+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_BOOTVEC__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL(dev) (0x00848254+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DBGCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DBGCTL__PRIV_LEVEL_MASK(dev) (0x008481a8+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DBGCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_PNVDEC_FALCON_DBGCTL_VAL_INIT 0x000 /* */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_TRACE_MODE_FULL 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_TRACE_MODE_STACK 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_PNVDEC_FALCON_DBGCTL_CYA_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_FALCON_DBGCTL_CYA_ENABLE 0x8afe /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT1(dev) (0x00848098+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IBRKPT1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT1__PRIV_LEVEL_MASK(dev) (0x008481fc+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IBRKPT1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT1_PC_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT1_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT1_SKIP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT1_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT1_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT1_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT1_EN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT1_EN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT2(dev) (0x0084809c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IBRKPT2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT2__PRIV_LEVEL_MASK(dev) (0x008481fc+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IBRKPT2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT2_PC_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT2_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT2_SKIP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT2_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT2_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT2_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT2_EN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT2_EN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT3(dev) (0x008480b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IBRKPT3__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT3__PRIV_LEVEL_MASK(dev) (0x008481fc+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IBRKPT3__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT3_PC_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT3_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT3_SKIP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT3_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT3_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT3_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT3_EN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT3_EN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT4(dev) (0x008480b4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IBRKPT4__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT4__PRIV_LEVEL_MASK(dev) (0x008481fc+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IBRKPT4__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT4_PC_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT4_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT4_SKIP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT4_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT4_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT4_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT4_EN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT4_EN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT5(dev) (0x008480b8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IBRKPT5__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT5__PRIV_LEVEL_MASK(dev) (0x008481fc+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IBRKPT5__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT5_PC_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT5_SUPPRESS_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT5_SKIP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT5_SKIP_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT5_SKIP_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_IBRKPT5_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_IBRKPT5_EN_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IBRKPT5_EN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD(dev) (0x00848200+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_ICD_CMD__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_CMD__PRIV_LEVEL_MASK(dev) (0x00848220+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_ICD_CMD__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_STOP 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_RUN 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_JRUN 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_RUNB 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_JRUNB 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_STEP 0x5 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_JSTEP 0x6 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_EMASK 0x7 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_RREG 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_WREG 0x9 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_RDM 0xa /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_WDM 0xb /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_RCM 0xc /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_WCM 0xd /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_RSTAT 0xe /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_OPC_SBU 0xf /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_SZ_B 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_SZ_HW 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_SZ_W 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG0 0x00 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG1 0x01 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG2 0x02 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG3 0x03 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG4 0x04 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG5 0x05 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG6 0x06 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG7 0x07 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG8 0x08 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG9 0x09 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG10 0x0a /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG11 0x0b /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG12 0x0c /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG13 0x0d /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG14 0x0e /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_REG15 0x0f /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_IV0 0x10 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_IV1 0x11 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_EV 0x13 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_SP 0x14 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_PC 0x15 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_IMB 0x16 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_DMB 0x17 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_CSW 0x18 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_CCR 0x19 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_SEC 0x1a /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_CTX 0x1b /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_EXCI 0x1c /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_SEC1 0x1e /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_IMB1 0x1e /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_DMB1 0x1f /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_RSTAT0 0x00 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_RSTAT1 0x01 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_RSTAT2 0x02 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_RSTAT3 0x03 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_RSTAT4 0x04 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_RSTAT5 0x05 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_WB0 0x00 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_WB1 0x01 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_WB2 0x02 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_IDX_WB3 0x03 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_PNVDEC_FALCON_ICD_CMD_ERROR_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_ICD_CMD_ERROR_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_PNVDEC_FALCON_ICD_CMD_RDVLD_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_ICD_CMD_RDVLD_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_ADDR(dev) (0x00848204+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_ICD_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_ADDR__PRIV_LEVEL_MASK(dev) (0x00848220+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_ICD_ADDR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_WDATA(dev) (0x00848208+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_ICD_WDATA__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_WDATA__PRIV_LEVEL_MASK(dev) (0x00848220+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_ICD_WDATA__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_ICD_RDATA(dev) (0x0084820c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_ICD_RDATA__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA__PRIV_LEVEL_MASK(dev) (0x00848220+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_ICD_RDATA__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 0x2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 0x2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 0x2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 0x2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 0x2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 0x3 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 0x4 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 0x5 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 0x6 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 0x7 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 0x2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 0x3 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 0x2 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 0x1 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0x0 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_PNVDEC_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_PNVDEC_FALCON_RSTAT0(dev) (0x008480d8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_RSTAT0__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_RSTAT0__PRIV_LEVEL_MASK(dev) (0x00848224+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_RSTAT0__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3(dev) (0x008480dc+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_RSTAT3__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_PNVDEC_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_PNVDEC_FALCON_TRACEIDX(dev) (0x00848148+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_TRACEIDX__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_TRACEIDX__PRIV_LEVEL_MASK(dev) (0x0084819c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_TRACEIDX__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_PNVDEC_FALCON_TRACEIDX_CNT_INIT 0x00 /* R-I-V */ #define NV_PNVDEC_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_PNVDEC_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_PNVDEC_FALCON_TRACEIDX_IDX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_TRACEPC(dev) (0x0084814c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_TRACEPC__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_TRACEPC__PRIV_LEVEL_MASK(dev) (0x0084819c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_TRACEPC__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_PNVDEC_FALCON_TRACEINFO(dev) (0x0084817c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_TRACEINFO__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_TRACEINFO__PRIV_LEVEL_MASK(dev) (0x0084819c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_TRACEINFO__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_PNVDEC_FALCON_IMCTL(dev) (0x00848140+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IMCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMCTL__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IMCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PNVDEC_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_PNVDEC_FALCON_IMCTL_CMD_NOP 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMCTL_CMD_IMINV 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_IMCTL_CMD_IMBLK 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_IMCTL_CMD_IMTAG 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_IMCTL_DEBUG(dev) (0x0084815c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IMCTL_DEBUG__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_PNVDEC_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_PNVDEC_FALCON_IMCTL_DEBUG_CMD_NOP 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_IMSTAT(dev) (0x00848144+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IMSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMSTAT__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IMSTAT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_IMFILLRNG0(dev) (0x00848150+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IMFILLRNG0__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IMFILLRNG0_TAG_LO_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_PNVDEC_FALCON_IMFILLRNG0_TAG_HI_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_FALCON_IMFILLRNG1(dev) (0x00848154+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IMFILLRNG1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IMFILLRNG1_TAG_LO_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_PNVDEC_FALCON_IMFILLRNG1_TAG_HI_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_FALCON_IMFILLCTL(dev) (0x00848158+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_IMFILLCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMFILLCTL__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_IMFILLCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_PNVDEC_FALCON_IMFILLCTL_NBLOCKS_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_FALCON_DMCTL(dev) (0x00848260+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMCTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMCTL__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMCTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PNVDEC_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_PNVDEC_FALCON_DMCTL_CMD_NOP 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMCTL_CMD_DMINV 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMCTL_CMD_DMBLK 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_DMCTL_CMD_DMTAG 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_DMCTL_CMD_DMCLEAN 0x5 /* RW--V */ #define NV_PNVDEC_FALCON_DMCTL_CMD_DMLVL 0x6 /* RW--V */ #define NV_PNVDEC_FALCON_DMSTAT(dev) (0x00848264+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMSTAT__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMSTAT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_DMVACTL(dev) (0x00848268+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMVACTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMVACTL__PRIV_LEVEL_MASK(dev) (0x00848198+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMVACTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMVACTL_BOUND_INIT 0x000000a0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMCYA(dev) (0x0084826c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_DMCYA__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMCYA__PRIV_LEVEL_MASK(dev) (0x0084828c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_DMCYA__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_DMCYA_LDSTVA_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_DMCYA_LDSTVA_DIS_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_DMCYA_LDSTVA_DIS_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_DMCYA_ROB_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_DMCYA_ROB_DIS_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMCYA_ROB_DIS_TRUE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMCYA_ROBWB_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_FALCON_DMCYA_ROBWB_DIS_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMCYA_ROBWB_DIS_TRUE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_DMCYA_ROBSPR_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_FALCON_DMCYA_ROBSPR_DIS_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_DMCYA_ROBSPR_DIS_TRUE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERRSTAT(dev) (0x00848244+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_CSBERRSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK(dev) (0x0084822c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_PNVDEC_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERRSTAT_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERRSTAT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERRSTAT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_PNVDEC_FALCON_CSBERRSTAT_VALID_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_CSBERRSTAT_VALID_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERRSTAT_VALID_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_CSBERR_ADDR(dev) (0x0084824c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_CSBERR_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK(dev) (0x0084822c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_CSBERR_INFO(dev) (0x00848248+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_CSBERR_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK(dev) (0x0084822c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK(dev) (0x00849e50+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK(dev) (0x00849e5c+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK(dev) (0x00849e54+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK__SETLVL_SIGNAL "setlvlm" /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK__CLRLVL_SIGNAL "clrlvlm" /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x4 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG(dev) (0x00849c04+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_CONFIG__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_CONFIG__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_CONFIG__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_MODE 31:24 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA1 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA224 0x04 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA256 0x05 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA384 0x06 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA512 0x07 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA512_224 0x07 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA512_256 0x07 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_ALG 15:12 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_ALG_SHA 0x3 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_ENC_ALG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_DST 4:2 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_CONFIG_DST_HASH_REG 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CONFIG_DST_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_TASK_CONFIG(dev) (0x00849c08+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SHA_TASK_CONFIG__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_TASK_CONFIG__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_TASK_CONFIG__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR(dev) (0x00849c0c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR_VAL 31:0 /* RWXVF */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR_HI(dev) (0x00849c10+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR_HI__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR_HI__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR_HI__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR_HI_MSB 31:24 /* RWXVF */ #define NV_PNVDEC_FALCON_SHA_IN_ADDR_HI_SZ 23:0 /* RWXVF */ #define NV_PNVDEC_FALCON_SHA_MSG_LENGTH(dev,i) (0x00849c1c+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_MSG_LENGTH__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MSG_LENGTH__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_SHA_MSG_LENGTH__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_MSG_LENGTH__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MSG_LENGTH_VAL 31:0 /* RW-VF */ #define NV_PNVDEC_FALCON_SHA_MSG_LEFT(dev,i) (0x00849c2c+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_MSG_LEFT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MSG_LEFT__SIZE_2 4 /* */ #define NV_PNVDEC_FALCON_SHA_MSG_LEFT__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_MSG_LEFT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MSG_LEFT_VAL 31:0 /* RW-VF */ #define NV_PNVDEC_FALCON_SHA_HASH_RESULT(dev,i) (0x00849c3c+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_HASH_RESULT__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_HASH_RESULT__SIZE_2 16 /* */ #define NV_PNVDEC_FALCON_SHA_HASH_RESULT__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_HASH_RESULT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_HASH_RESULT_VAL 31:0 /* RW-VF */ #define NV_PNVDEC_FALCON_SHA_OPERATION(dev) (0x00849c7c+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SHA_OPERATION__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_OPERATION__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_OPERATION__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_OPERATION_LAST_BUF 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_OPERATION_LAST_BUF_TRUE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_OPERATION_LAST_BUF_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_OPERATION_SOFTRESET 6:6 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_OPERATION_SOFTRESET_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_OPERATION_SOFTRESET_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_OPERATION_HALT 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_OPERATION_HALT_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_OPERATION_HALT_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_OPERATION_OP 2:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_OPERATION_OP_NOP 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_OPERATION_OP_START 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_OPERATION_OP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_STATUS(dev) (0x00849c80+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_SHA_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_STATUS__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_STATUS__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_STATUS_STATE 2:0 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_STATUS_STATE_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_STATUS_STATE_IDLE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_SHA_STATUS_STATE_BUSY 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_STATUS_STATE_HALTED 0x7 /* R---V */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR(dev) (0x00849c84+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI(dev) (0x00849c88+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN(dev) (0x00849c8c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_SET 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_UNSET 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_SET 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_UNSET 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR(dev) (0x00849c90+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI(dev) (0x00849c94+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS(dev) (0x00849d30+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_LEVEL_ERR 12:12 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_LEVEL_ERR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_LEVEL_ERR_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_LEVEL_ERR_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_MULTI_HIT 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_MULTI_HIT_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_MULTI_HIT_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_MULTI_HIT_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_MISS 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_MISS_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_MISS_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_MISS_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_PA_FAULT 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_PA_FAULT_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_PA_FAULT_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_PA_FAULT_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_FBIF_ERR 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_FBIF_ERR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_FBIF_ERR_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_FBIF_ERR_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_NS_ACCESS 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_NS_ACCESS_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_NS_ACCESS_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_ERR_STATUS_NS_ACCESS_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR(dev) (0x00849d20+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR_VAL 31:0 /* R-XVF */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR_HI(dev) (0x00849d24+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR_HI__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR_HI__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR_HI__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_ERR_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS(dev) (0x00849d34+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS_ERR_STATUS 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS_ERR_STATUS_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS_ERR_STATUS_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS_ERR_STATUS_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS_OP_DONE 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS_OP_DONE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS_OP_DONE_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_INT_STATUS_OP_DONE_CLEAR 0x1 /* */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE(dev) (0x00849d38+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE_ERR_STATUS 16:16 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE_ERR_STATUS_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE_ERR_STATUS_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE_OP_DONE 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE_OP_DONE_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_INT_ENABLE_OP_DONE_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_MUTEX(dev) (0x00849d00+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_SHA_MUTEX__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX_VAL 7:0 /* -W-VF */ #define NV_PNVDEC_FALCON_SHA_MUTEX_RELEASE(dev) (0x00849d04+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_FALCON_SHA_MUTEX_RELEASE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX_RELEASE__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX_RELEASE__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX_RELEASE_VAL 7:0 /* -W-VF */ #define NV_PNVDEC_FALCON_SHA_MUTEX_STATUS(dev) (0x00849d08+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_SHA_MUTEX_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX_STATUS__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX_STATUS__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_MUTEX_STATUS_LOCKED 7:0 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_MUTEX_STATUS_LOCKED_INIT 0x00 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG(dev) (0x00849d10+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_FB_BASE 24:16 /* RWXVF */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION 7:7 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_CTXDMA 6:4 /* RWXVF */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_SRC 1:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_SRC_DMEM 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_SRC_IMEM 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_SRC_CONFIG_SRC_FB 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_REQ_CTRL(dev) (0x00849d14+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_SHA_REQ_CTRL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_REQ_CTRL__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_REQ_CTRL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_REQ_CTRL_WINDOW 31:16 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_REQ_CTRL_WINDOW_INIT 0x1000 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_REQ_CTRL_LIMIT 15:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_REQ_CTRL_LIMIT_INIT 0x0800 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_CTRL(dev) (0x00849c98+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SHA_CTRL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_CTRL__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_CTRL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_CTRL_FB_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_CTRL_FB_DIS_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_CTRL_FB_DIS_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CYA(dev) (0x00849d18+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_SHA_CYA__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_CYA__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_CYA__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_CYA_BW_THROTTLE_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_SHA_CYA_BW_THROTTLE_DIS_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_SHA_CYA_BW_THROTTLE_DIS_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO(dev) (0x00849d1c+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_PW_HALTED 13:13 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_PW_HALTED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_PW_HALTED_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_IDMA_HALTED 12:12 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_IDMA_HALTED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_IDMA_HALTED_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_ALU_HALTED 11:11 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_ALU_HALTED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_ALU_HALTED_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_PW_IDLE 10:10 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_PW_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_PW_IDLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_IDMA_IDLE 9:9 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_IDMA_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_IDMA_IDLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_ALU_IDLE 8:8 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_ALU_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_ALU_IDLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_CORE_STATUS 6:4 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_CORE_STATUS_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_CORE_STATUS_BUSY 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_SECURE_LEVEL 1:0 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_INFO_SECURE_LEVEL_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_0(dev) (0x00849d40+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_0__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_0__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_0__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_0_SHA_SHA_PREPROC_STATE 11:10 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_0_SHA_WD_NUMBER 9:6 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_0_SHA_SHA_HASH_STATE 5:3 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_0_SHA_BYTE_COUNTER 2:0 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1(dev) (0x00849d44+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN 18:18 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN 17:17 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS 14:14 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_2(dev) (0x00849d48+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_2__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_2__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_SIZE 23:0 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_ADDR 31:24 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_3(dev) (0x00849d4c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_3__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_3__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_3__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_3_SHA_IDMA_RESP_DMA_ADDR 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_4(dev) (0x00849d50+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_4__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_4__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_4__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_4_SHA_IDMA_RESP_DMA_ADDR 8:0 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_4_SHA_IDMA_CORRECTED_RESP_DMA_SIZE 31:11 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_5(dev) (0x00849d54+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_5__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_5__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_5__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_5_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 31:0 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6(dev) (0x00849d58+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 12:0 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_FREE_COUNT 21:16 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH 24:24 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE 25:25 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE 26:26 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA 27:27 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_LASTBUF 28:28 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0 29:29 /* R-IVF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7(dev) (0x00849d5c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7__PRIV_LEVEL_MASK(dev) (0x00849d28+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_PVLD 25:25 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_READ 24:24 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PRDY 23:23 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PVLD 22:22 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PRDY 21:21 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PVLD 20:20 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_VALID 15:15 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_STALL 14:14 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_PVLD 9:9 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_STALL 8:8 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PVLD 7:7 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PRDY 6:6 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PVLD 5:5 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PRDY 4:4 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_REQ 1:1 /* R--VF */ #define NV_PNVDEC_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_BUSY 0:0 /* R--VF */ #define NV_PNVDEC_FALCON_VER(dev) (0x00849d88+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_VER__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_VER_MAJOR 3:0 /* R-IVF */ #define NV_PNVDEC_FALCON_VER_MAJOR_DEFT 0x2 /* R-I-V */ #define NV_PNVDEC_FALCON_VER_MINOR 17:4 /* R-IVF */ #define NV_PNVDEC_FALCON_VER_MINOR_DEFT 0x0000 /* R-I-V */ #define NV_PNVDEC_FALCON_VER_BUGFIX 31:18 /* R-IVF */ #define NV_PNVDEC_FALCON_VER_BUGFIX_DEFT 0x0000 /* R-I-V */ #define NV_PNVDEC_FALCON_MOD_SEL(dev) (0x00849d80+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_MOD_SEL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MOD_SEL_ALGO 7:0 /* RWIVF */ #define NV_PNVDEC_FALCON_MOD_SEL_ALGO_AES 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_MOD_SEL_ALGO_RSA3K 0x01 /* RW--V */ #define NV_PNVDEC_FALCON_MOD_EN(dev) (0x00849d84+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_MOD_EN__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_MOD_EN_AES 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_MOD_EN_AES_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_MOD_EN_AES_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_MOD_EN_RSA3K 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_MOD_EN_RSA3K_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_MOD_EN_RSA3K_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_PKCBROM_VER(dev) (0x00849d8c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FALCON_PKCBROM_VER__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PKCBROM_VER_DEV 11:0 /* R--VF */ #define NV_PNVDEC_FALCON_PKCBROM_VER_ECO 15:12 /* R--VF */ #define NV_PNVDEC_FALCON_PKCBROM_VER_MINOR 23:16 /* R--VF */ #define NV_PNVDEC_FALCON_PKCBROM_VER_MAJOR 31:24 /* R--VF */ #define NV_PNVDEC_FALCON_VHRCFG_BASE(dev) (0x00849d90+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_VHRCFG_BASE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_VHRCFG_BASE_VAL 31:0 /* R-IVF */ #define NV_PNVDEC_FALCON_VHRCFG_BASE_VAL_SEC 0x00008200 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_BASE_VAL_PWR_PMU 0x000083f0 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_BASE_VAL_NVDEC 0x00008490 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_BASE_VAL_GSP 0x000087a0 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_BASE_VAL_SOE 0x00008200 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_BASE_VAL_PSC 0x00000000 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_BASE_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM(dev) (0x00849de8+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM_VAL 31:0 /* R-IVF */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM_VAL_SEC 0x0000000a /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM_VAL_PWR_PMU 0x00000003 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM_VAL_NVDEC 0x00000010 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM_VAL_GSP 0x00000003 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM_VAL_SOE 0x0000000a /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM_VAL_PSC 0x00000000 /* R---V */ #define NV_PNVDEC_FALCON_VHRCFG_ENTNUM_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_PNVDEC_FALCON_BMEMBASE(dev) (0x00849d94+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_BMEMBASE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BMEMBASE_VAL 31:0 /* R-IVF */ #define NV_PNVDEC_FALCON_BMEMBASE_VAL_DEFT 0x02100000 /* R-I-V */ #define NV_PNVDEC_FALCON_BROM_CURR_UCODE_ID(dev) (0x00849d98+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_BROM_CURR_UCODE_ID__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BROM_CURR_UCODE_ID__PRIV_LEVEL_MASK(dev) (0x00849e50+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_BROM_CURR_UCODE_ID__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BROM_CURR_UCODE_ID_VAL 7:0 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_CURR_UCODE_ID_VAL_DEFT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_CURR_UCODE_ID_VAL_MAX 0x10 /* RW--V */ #define NV_PNVDEC_FALCON_UCODE_VERSION(dev,i) (0x00849da8+(dev)*16384+(i)*4) /* R-I4A */ #define NV_PNVDEC_FALCON_UCODE_VERSION__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_UCODE_VERSION__SIZE_2 16 /* */ #define NV_PNVDEC_FALCON_UCODE_VERSION_VER 7:0 /* R-IVF */ #define NV_PNVDEC_FALCON_UCODE_VERSION_VER_DEF 0x00 /* R-I-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK(dev) (0x00849d9c+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK__PRIV_LEVEL_MASK(dev) (0x00849e50+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_SEC 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_SEC_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_SEC_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_DPU 1:1 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_DPU_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_DPU_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVDEC 2:2 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVDEC_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVDEC_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_PMU 3:3 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_PMU_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_PMU_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_FBFALCON 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_FBFALCON_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_FBFALCON_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVENC 5:5 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVENC_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVENC_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_GPCCS 6:6 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_GPCCS_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_GPCCS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_FECS 7:7 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_FECS_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_FECS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_MINION 8:8 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_MINION_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_MINION_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_XUSB 9:9 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_XUSB_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_XUSB_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_GSP 10:10 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_GSP_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_GSP_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVJPG 11:11 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVJPG_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_NVJPG_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_OFA 12:12 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_OFA_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_OFA_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_PSC 13:13 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_PSC_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_PSC_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_SOE 14:14 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_SOE_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_ENGIDMASK_SOE_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL(dev) (0x00849dec+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL__PRIV_LEVEL_MASK(dev) (0x00849e5c+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_VALID 0:0 /* R-IVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY 1:1 /* R-IVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD 4:4 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_VALID 8:8 /* R-IVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY 9:9 /* R-IVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD 12:12 /* RWIVF */ #define NV_PNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FALCON_PR_CTKID(dev) (0x00849df0+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_PR_CTKID__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_PR_CTKID_VAL 7:0 /* R-IVF */ #define NV_PNVDEC_FALCON_PR_CTKID_VAL_DEF 0x00 /* R-I-V */ #define NV_PNVDEC_FALCON_BROM_FUNID(dev) (0x00849da0+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_BROM_FUNID__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID 7:0 /* R-IVF */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID_DEFT 0x00 /* R-I-V */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID_DECFUSEKEY 0x01 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID_GENTK 0x02 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID_DECMPK 0x03 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID_SIGBYMPK 0x04 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID_CLRMPK 0x05 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID_ECDSASIGN 0x06 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_ID_ECDSAVERIF 0x07 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_CALLER_LVL 9:8 /* R-IVF */ #define NV_PNVDEC_FALCON_BROM_FUNID_CALLER_LVL_0 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_BROM_FUNID_CALLER_LVL_1 0x1 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_CALLER_LVL_2 0x2 /* R---V */ #define NV_PNVDEC_FALCON_BROM_FUNID_CALLER_LVL_3 0x3 /* R---V */ #define NV_PNVDEC_FALCON_BROM_PARAADDR(dev,i) (0x00849e10+(dev)*16384+(i)*4) /* RWI4A */ #define NV_PNVDEC_FALCON_BROM_PARAADDR__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BROM_PARAADDR__SIZE_2 1 /* */ #define NV_PNVDEC_FALCON_BROM_PARAADDR__PRIV_LEVEL_MASK(dev) (0x00849e50+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_BROM_PARAADDR__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BROM_PARAADDR_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_PARAADDR_VAL_DEFT 0x00000000 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_RETCODE(dev) (0x00849da4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FALCON_BROM_RETCODE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR 7:0 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_SUCCESS 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLFUNID 0x01 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_PA_FAULT 0x02 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NOT_IN_DMEM 0x03 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NO_ENOUGH_SPACE 0x04 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_VA_NOT_VALID 0x05 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_4BYTES 0x06 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_16BYTES 0x07 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_32BYTES 0x08 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_OUTPUT_NOT_ALLOWED 0x09 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_TK_PTR_IS_NS_READABLE 0x0a /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_NOT_CALLED_BY_HS 0x0b /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_CALL_FROM_LVL0 0x0c /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLUCODEID 0x0d /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_DISPOSE_MPK_FAIL 0x0e /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_CTKID_INVALID 0x0f /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLTKID 0x10 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_INVLDPMUK 0x11 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_INVLDPDUK 0x12 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_INVLDMPK 0x13 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_SIGFAIL 0x14 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_PDI_INVALID 0x15 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_LOAD_KMEM2SCP_FAIL 0x16 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_WRONG_PROTECTINFO 0x17 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_KSLT_K3_IS_0 0x18 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF16B 0x19 /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF32B 0x1a /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_RSVD_ZEROS 0x1b /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_MPK_IS_VALID 0x1c /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_SCP_ERR 0x1d /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_256BYTES 0x1e /* RW--V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERRID 19:8 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERRID_DEFT 0x000 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_FUNID 23:20 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_RETCODE_FUNID_DEFT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERRINFO 31:24 /* RWIVF */ #define NV_PNVDEC_FALCON_BROM_RETCODE_ERRINFO_DEFT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEMBASE(dev) (0x00849df4+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_KMEMBASE__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEMBASE_VAL 31:0 /* R-IVF */ #define NV_PNVDEC_FALCON_KMEMBASE_VAL_DEF 0x02000000 /* R-I-V */ #define NV_PNVDEC_FALCON_KMEMC(dev,i) (0x00849df8+(dev)*16384+(i)*4) /* RWI4A */ #define NV_PNVDEC_FALCON_KMEMC__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEMC__SIZE_2 2 /* */ #define NV_PNVDEC_FALCON_KMEMC__PRIV_LEVEL_MASK(dev) (0x00849e54+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_KMEMC__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEMC_OFFS 15:2 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEMC_OFFS_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEMC_OFFS_PROTINFO 0x0400 /* RW--V */ #define NV_PNVDEC_FALCON_KMEMC_OFFS_MAX 0x05ff /* RW--V */ #define NV_PNVDEC_FALCON_KMEMC_AINCW 24:24 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEMC_AINCW_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_KMEMC_AINCW_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEMC_AINCR 25:25 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEMC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_KMEMC_AINCR_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEMC_ERR 28:26 /* R-IVF */ #define NV_PNVDEC_FALCON_KMEMC_ERR_SUCCESS 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_KMEMC_ERR_1 0x1 /* R---V */ #define NV_PNVDEC_FALCON_KMEMC_ERR_2 0x2 /* R---V */ #define NV_PNVDEC_FALCON_KMEMC_ERR_3 0x3 /* R---V */ #define NV_PNVDEC_FALCON_KMEMC_ERR_4 0x4 /* R---V */ #define NV_PNVDEC_FALCON_KMEMC_ERR_5 0x5 /* R---V */ #define NV_PNVDEC_FALCON_KMEMC_ERR_6 0x6 /* R---V */ #define NV_PNVDEC_FALCON_KMEMD(dev,i) (0x00849e00+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FALCON_KMEMD__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEMD__SIZE_2 2 /* */ #define NV_PNVDEC_FALCON_KMEMD__PRIV_LEVEL_MASK(dev) (0x00849e54+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_KMEMD__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEMD_DATA 31:0 /* RW-VF */ #define NV_PNVDEC_FALCON_KMEM_CTL(dev) (0x00849e08+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_KMEM_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEM_CTL__PRIV_LEVEL_MASK(dev) (0x00849e54+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_KMEM_CTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEM_CTL_IDX 7:0 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_CTL_IDX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_CTL_CMD 19:16 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_CTL_CMD_NOP 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_CTL_CMD_DISPOSE 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_CTL_CMD_LOADTO63 0x2 /* RW--V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT 23:20 /* R-IVF */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_NOP 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_DISPOSE_DONE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_RECYCLABLE_IS_0 0x2 /* R---V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_PRIVDISABLED 0x3 /* R---V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_NOTWRITEABLE 0x4 /* R---V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_LOADTO63_DONE 0x5 /* R---V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_LOADABLE_IS_0 0x6 /* R---V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_PRIVDISABLED 0x7 /* R---V */ #define NV_PNVDEC_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_UCODIDMASK_IS_0 0x8 /* R---V */ #define NV_PNVDEC_FALCON_KMEMCFG(dev) (0x00849e0c+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_KMEMCFG__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEMCFG_NUMOFKSLT 15:0 /* R-IVF */ #define NV_PNVDEC_FALCON_KMEMCFG_NUMOFKSLT_DEFT 0x0100 /* R-I-V */ #define NV_PNVDEC_FALCON_KMEMCFG_KSLT_LENGTH 21:16 /* R-IVF */ #define NV_PNVDEC_FALCON_KMEMCFG_KSLT_LENGTH_DEFT 0x10 /* R-I-V */ #define NV_PNVDEC_FALCON_KMEMCFG_PROTECTINFO_LENGTH 25:22 /* R-IVF */ #define NV_PNVDEC_FALCON_KMEMCFG_PROTECTINFO_LENGTH_DEFT 0x8 /* R-I-V */ #define NV_PNVDEC_FALCON_KMEMCFG_BROM_USED_SLOTS 31:26 /* R-IVF */ #define NV_PNVDEC_FALCON_KMEMCFG_BROM_USED_SLOTS_DEFT 0x10 /* R-I-V */ #define NV_PNVDEC_FALCON_KMEM_VALID(dev,i) (0x00849e18+(dev)*16384+(i)*4) /* R-I4A */ #define NV_PNVDEC_FALCON_KMEM_VALID__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEM_VALID__SIZE_2 8 /* */ #define NV_PNVDEC_FALCON_KMEM_VALID__PRIV_LEVEL_MASK(dev) (0x00849e54+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_KMEM_VALID__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEM_VALID_VAL 31:0 /* R-IVF */ #define NV_PNVDEC_FALCON_KMEM_VALID_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_PNVDEC_FALCON_KMEM_VIOLATION_CTL(dev) (0x00849e38+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FALCON_KMEM_VIOLATION_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEM_VIOLATION_CTL__PRIV_LEVEL_MASK(dev) (0x00849e54+(dev)*16384) /* */ #define NV_PNVDEC_FALCON_KMEM_VIOLATION_CTL__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_KMEM_VIOLATION_CTL_ACT 0:0 /* RWIVF */ #define NV_PNVDEC_FALCON_KMEM_VIOLATION_CTL_ACT_HALT 0x0 /* RWI-V */ #define NV_PNVDEC_FALCON_KMEM_VIOLATION_CTL_ACT_EXC 0x1 /* RW--V */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF(dev) (0x00849e3c+(dev)*16384) /* R-I4A */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF__SIZE_1 2 /* */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP 0:0 /* R-IVF */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_READ 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_WRITE 0x1 /* R---V */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL 5:4 /* R-IVF */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID 15:8 /* R-IVF */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID_INIT 0x00 /* R-I-V */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX 23:16 /* R-IVF */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX_INIT 0x00 /* R-I-V */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET 24:24 /* R-IVF */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_KSLT 0x0 /* R-I-V */ #define NV_PNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_PROTINFO 0x1 /* R---V */ #define NV_PNVDEC_DBFCTL(dev) (0x008486c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFCTL__SIZE_1 2 /* */ #define NV_PNVDEC_DBFCTL_CODEC 2:0 /* RWIUF */ #define NV_PNVDEC_DBFCTL_CODEC_MPEG1 0x0 /* RWI-V */ #define NV_PNVDEC_DBFCTL_CODEC_MPEG2 0x1 /* RW--V */ #define NV_PNVDEC_DBFCTL_CODEC_VC1 0x2 /* RW--V */ #define NV_PNVDEC_DBFCTL_CODEC_H264 0x3 /* RW--V */ #define NV_PNVDEC_DBFCTL_CODEC_MPEG4 0x4 /* RW--V */ #define NV_PNVDEC_DBFCTL_CODEC_VP8 0x5 /* RW--V */ #define NV_PNVDEC_DBFCTL_PQUANT 7:3 /* RWIUF */ #define NV_PNVDEC_DBFCTL_PQUANT_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_DBFCTL_INTERLACED 8:8 /* RWIUF */ #define NV_PNVDEC_DBFCTL_INTERLACED_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_DBFCTL_MBAFF_FRAME 9:9 /* RWIUF */ #define NV_PNVDEC_DBFCTL_MBAFF_FRAME_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_DBFCTL_MBAFF_FRAME_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_DBFCTL_APPLE_OOLD_REF 10:10 /* RWIUF */ #define NV_PNVDEC_DBFCTL_APPLE_OOLD_REF_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_DBFCTL_APPLE_OOLD_REF_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_DBFCTL_MODE 12:11 /* RWIUF */ #define NV_PNVDEC_DBFCTL_MODE_NORMAL 0x0 /* RWI-V */ #define NV_PNVDEC_DBFCTL_MODE_SIMPLE 0x1 /* RW--V */ #define NV_PNVDEC_DBFCTL_MODE_DISABLE 0x2 /* RW--V */ #define NV_PNVDEC_DBFCTL_SVC 11:11 /* RWIUF */ #define NV_PNVDEC_DBFCTL_SVC_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_DBFCTL_SVC_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_DBFINTRPTEN(dev) (0x008486c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFINTRPTEN__SIZE_1 2 /* */ #define NV_PNVDEC_DBFINTRPTEN_CFGERR 0:0 /* RWIUF */ #define NV_PNVDEC_DBFINTRPTEN_CFGERR_ON 0x1 /* RW--V */ #define NV_PNVDEC_DBFINTRPTEN_CFGERR_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_DBFINTRPTEN_DMAERR 4:4 /* RWIUF */ #define NV_PNVDEC_DBFINTRPTEN_DMAERR_ON 0x1 /* RW--V */ #define NV_PNVDEC_DBFINTRPTEN_DMAERR_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_DBFINTRPTEN_MVERR 8:8 /* RWIUF */ #define NV_PNVDEC_DBFINTRPTEN_MVERR_ON 0x1 /* RW--V */ #define NV_PNVDEC_DBFINTRPTEN_MVERR_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_DBFINTRPTSTAT(dev) (0x008486c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFINTRPTSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_DBFINTRPTSTAT_CFGERR 0:0 /* RWIUF */ #define NV_PNVDEC_DBFINTRPTSTAT_CFGERR_ON 0x1 /* RW--V */ #define NV_PNVDEC_DBFINTRPTSTAT_CFGERR_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_DBFINTRPTSTAT_DMAERR 4:4 /* RWIUF */ #define NV_PNVDEC_DBFINTRPTSTAT_DMAERR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_DBFINTRPTSTAT_DMAERR_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_DBFINTRPTSTAT_MVERR 8:8 /* RWIUF */ #define NV_PNVDEC_DBFINTRPTSTAT_MVERR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_DBFINTRPTSTAT_MVERR_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDBG1(dev) (0x008486cc+(dev)*16384) /* R--4A */ #define NV_PNVDEC_DBFDBG1__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDBG1_CUR_LUMA_ST 2:0 /* R-XUF */ #define NV_PNVDEC_DBFDBG1_CUR_CHRO_ST 5:3 /* R-XUF */ #define NV_PNVDEC_DBFDBG1_CUR_INPUT_ST 8:6 /* R-XUF */ #define NV_PNVDEC_DBFDBG1_PR_FCNT 16:9 /* R-XUF */ #define NV_PNVDEC_DBFDBG1_PR_FDONE 17:17 /* R-XUF */ #define NV_PNVDEC_DBFDBG1_INPUT_DONE 18:18 /* R-XUF */ #define NV_PNVDEC_DBFDBG1_OUTPUT_DONE 19:19 /* R-XUF */ #define NV_PNVDEC_MCLUMSCALE(dev,i) (0x00848680+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_MCLUMSCALE__SIZE_1 2 /* */ #define NV_PNVDEC_MCLUMSCALE__SIZE_2 3 /* */ #define NV_PNVDEC_MCLUMSCALE_SCALE1 5:0 /* RWXVF */ #define NV_PNVDEC_MCLUMSCALE_SCALE2 13:8 /* RWXVF */ #define NV_PNVDEC_MCLUMSHIFT(dev,i) (0x00848690+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_MCLUMSHIFT__SIZE_1 2 /* */ #define NV_PNVDEC_MCLUMSHIFT__SIZE_2 3 /* */ #define NV_PNVDEC_MCLUMSHIFT_SHIFT1 5:0 /* RWXVF */ #define NV_PNVDEC_MCLUMSHIFT_SHIFT2 13:8 /* RWXVF */ #define NV_PNVDEC_MCCTL(dev) (0x008486a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCCTL__SIZE_1 2 /* */ #define NV_PNVDEC_MCCTL_RANGEADJUST 1:0 /* RWXVF */ #define NV_PNVDEC_MCCTL_RANGERND 2:2 /* RWXVF */ #define NV_PNVDEC_MCCTL_REGCFG 4:4 /* RWXVF */ #define NV_PNVDEC_MCCTL_REGCFG_WAIT 0x0 /* RWX-V */ #define NV_PNVDEC_MCCTL_REGCFG_DONE 0x1 /* RWX-V */ #define NV_PNVDEC_MCCTL_CODEC 7:5 /* RWIVF */ #define NV_PNVDEC_MCCTL_CODEC_MPEG1 0x0 /* RWI-V */ #define NV_PNVDEC_MCCTL_CODEC_MPEG2 0x1 /* RW--V */ #define NV_PNVDEC_MCCTL_CODEC_VC1 0x2 /* RW--V */ #define NV_PNVDEC_MCCTL_CODEC_H264 0x3 /* RW--V */ #define NV_PNVDEC_MCCTL_CODEC_MPEG4 0x4 /* RW--V */ #define NV_PNVDEC_MCCTL_CODEC_VP8 0x5 /* RW--V */ #define NV_PNVDEC_MCINTRPTEN(dev) (0x008486a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCINTRPTEN__SIZE_1 2 /* */ #define NV_PNVDEC_MCINTRPTEN_CONFIGERR 0:0 /* RWXUF */ #define NV_PNVDEC_MCINTRPTEN_CONFIGERR_OFF 0x0 /* RWX-V */ #define NV_PNVDEC_MCINTRPTEN_CONFIGERR_ON 0x1 /* RWX-V */ #define NV_PNVDEC_MCINTRPTSTAT(dev) (0x008486a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCINTRPTSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_MCINTRPTSTAT_CONFIGERR 0:0 /* RWXUF */ #define NV_PNVDEC_MCINTRPTSTAT_CONFIGERR_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_MCINTRPTSTAT_CONFIGERR_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_MCDBG1(dev) (0x008486ac+(dev)*16384) /* R--4A */ #define NV_PNVDEC_MCDBG1__SIZE_1 2 /* */ #define NV_PNVDEC_MCDBG1_CSB_IF_FSM 1:0 /* R-IUF */ #define NV_PNVDEC_MCDBG1_CSB_IF_FSM_INIT 0x2 /* R-I-V */ #define NV_PNVDEC_MCDBG1_RD_OUTBUF_FSM 4:2 /* R-XUF */ #define NV_PNVDEC_MCDBG1_BLK_VALID_STATUS 10:5 /* R-XUF */ #define NV_PNVDEC_MCDBG1_RD_BLK_VALID_STATUS 16:11 /* R-XUF */ #define NV_PNVDEC_MCDBG1_REF_BUF_FULL_STATUS 17:17 /* R-XUF */ #define NV_PNVDEC_MCDBG1_CMD4WP_BUF_RD_STATUS 18:18 /* R-IUF */ #define NV_PNVDEC_MCDBG1_CMD4WP_BUF_RD_STATUS_INIT 0x1 /* R-I-V */ #define NV_PNVDEC_MCDBG1_RD_OUTBUF_SEL 19:19 /* R-XUF */ #define NV_PNVDEC_MCDBG1_REF_BUF_EMPTY 20:20 /* R-IUF */ #define NV_PNVDEC_MCDBG1_REF_BUF_EMPTY_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_MCDBG1_CMD4FLT_BUF_EMPTY 21:21 /* R-IUF */ #define NV_PNVDEC_MCDBG1_CMD4FLT_BUF_EMPTY_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_MCDBG1_CMD4FLT_REG_EMPTY 22:22 /* R-IUF */ #define NV_PNVDEC_MCDBG1_CMD4FLT_REG_EMPTY_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_MCDBG1_DATA_PATH_IDLE 23:23 /* R-IUF */ #define NV_PNVDEC_MCDBG1_DATA_PATH_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_MCDBG1_WP_DATA_VALID_STG0 24:24 /* R-XUF */ #define NV_PNVDEC_MCDBG1_WP_DATA_VALID_STG1 25:25 /* R-XUF */ #define NV_PNVDEC_MCDBG1_WP_DATA_VALID_STG2 26:26 /* R-XUF */ #define NV_PNVDEC_MCDBG1_WP_DATA_VALID_STG3 27:27 /* R-XUF */ #define NV_PNVDEC_MCDBG1_WP_DATA_VALID_STG4 28:28 /* R-XUF */ #define NV_PNVDEC_MCDBG1_OUTBUF0_EMPTY 29:29 /* R-IUF */ #define NV_PNVDEC_MCDBG1_OUTBUF0_EMPTY_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_MCDBG1_OUTBUF1_EMPTY 30:30 /* R-IUF */ #define NV_PNVDEC_MCDBG1_OUTBUF1_EMPTY_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_MCDBG1_CMD4WP_BUF_EMPTY_REG 31:31 /* R-IUF */ #define NV_PNVDEC_MCDBG1_CMD4WP_BUF_EMPTY_REG_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_VERSION(dev) (0x0084931c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VERSION__SIZE_1 2 /* */ #define NV_PNVDEC_VERSION_DEV 7:0 /* RWIVF */ #define NV_PNVDEC_VERSION_DEV_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_VERSION_ECO 15:8 /* RWIVF */ #define NV_PNVDEC_VERSION_ECO_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_VERSION_MINOR 23:16 /* RWIVF */ #define NV_PNVDEC_VERSION_MINOR_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_VERSION_MAJOR 31:24 /* RWIVF */ #define NV_PNVDEC_VERSION_MAJOR_INIT 0x05 /* RWI-V */ #define NV_PNVDEC_CAP_REG0(dev) (0x00849304+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CAP_REG0__SIZE_1 2 /* */ #define NV_PNVDEC_CAP_REG0_SECURE_RB 1:1 /* RWIVF */ #define NV_PNVDEC_CAP_REG0_SECURE_RB_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CAP_REG0_SECURE_RB_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CAP_REG0_VP8 2:2 /* RWIVF */ #define NV_PNVDEC_CAP_REG0_VP8_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_CAP_REG0_VP8_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CAP_REG0_VP9_HBD 4:4 /* RWIVF */ #define NV_PNVDEC_CAP_REG0_VP9_HBD_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_CAP_REG0_VP9_HBD_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CAP_REG0_HS_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CAP_REG0_HS_DIS_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_CAP_REG0_HS_DIS_ON 0x1 /* RW--V */ #define NV_PNVDEC_CAP_REG0_RESERVED 31:6 /* RWIVF */ #define NV_PNVDEC_CAP_REG0_RESERVED_INIT 0x0000000 /* RWI-V */ #define NV_PNVDEC_CAP_REG1(dev) (0x00849308+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CAP_REG1__SIZE_1 2 /* */ #define NV_PNVDEC_CAP_REG1_RESERVED 31:0 /* RWIVF */ #define NV_PNVDEC_CAP_REG1_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_CAP_REG2(dev) (0x0084930c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CAP_REG2__SIZE_1 2 /* */ #define NV_PNVDEC_CAP_REG2_RESERVED 31:0 /* RWIVF */ #define NV_PNVDEC_CAP_REG2_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_CAP_REG3(dev) (0x00849310+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CAP_REG3__SIZE_1 2 /* */ #define NV_PNVDEC_CAP_REG3_RESERVED 31:0 /* RWIVF */ #define NV_PNVDEC_CAP_REG3_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_PERF_DECODE_FRAME(dev) (0x00849334+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_PERF_DECODE_FRAME__SIZE_1 2 /* */ #define NV_PNVDEC_PERF_DECODE_FRAME_V 31:0 /* RWIVF */ #define NV_PNVDEC_OTF_MODE(dev) (0x00849338+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_OTF_MODE__SIZE_1 2 /* */ #define NV_PNVDEC_OTF_MODE_EN 0:0 /* RWIVF */ #define NV_PNVDEC_PERF_DECODE_BW_LIMIT(dev) (0x0084933c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_PERF_DECODE_BW_LIMIT__SIZE_1 2 /* */ #define NV_PNVDEC_PERF_DECODE_BW_LIMIT_V 31:0 /* RWIVF */ #define NV_PNVDEC_CG(dev) (0x00849320+(dev)*16384) /* RWE4A */ #define NV_PNVDEC_CG__SIZE_1 2 /* */ #define NV_PNVDEC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PNVDEC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PNVDEC_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PNVDEC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PNVDEC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PNVDEC_CG_IDLE_CG_EN__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG_STATE_CG_EN 7:7 /* */ #define NV_PNVDEC_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PNVDEC_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PNVDEC_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PNVDEC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PNVDEC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PNVDEC_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */ #define NV_PNVDEC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PNVDEC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PNVDEC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PNVDEC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PNVDEC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PNVDEC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PNVDEC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PNVDEC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PNVDEC_CG_WAKEUP_DLY_CNT__PROD 0x4 /* RW--V */ #define NV_PNVDEC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PNVDEC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PNVDEC_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PNVDEC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PNVDEC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PNVDEC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PNVDEC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PNVDEC_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PNVDEC_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PNVDEC_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PNVDEC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PNVDEC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PNVDEC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PNVDEC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PNVDEC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PNVDEC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PNVDEC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PNVDEC_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PNVDEC_CG_HALT_CG_EN 31:31 /* */ #define NV_PNVDEC_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PNVDEC_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PNVDEC_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PNVDEC_CG1(dev) (0x00849324+(dev)*16384) /* RWE4A */ #define NV_PNVDEC_CG1__SIZE_1 2 /* */ #define NV_PNVDEC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PNVDEC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PNVDEC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG1_SLCG 1:1 /* RWEVF */ #define NV_PNVDEC_CG1_SLCG_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG1_SLCG_DISABLED 0x1 /* RWE-V */ #define NV_PNVDEC_CG1_SLCG__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2(dev) (0x00849328+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG2__SIZE_1 2 /* */ #define NV_PNVDEC_CG2_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG2_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_EDOB_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_EDOB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_EDOB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_EDOB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_SCP_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_SCP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_SCP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_SCP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_MEMACC_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_MEMACC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_MEMACC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_MEMACC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_FFCTL_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_FFCTL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_FFCTL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_FFCTL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_CBC_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_CBC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_CBC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_CBC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_CBCODATA_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_CBCODATA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_CBCODATA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_CBCODATA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_CVC_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_CVC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_CVC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_CVC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_MBPRED_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_MBPRED_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_MBPRED_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_MBPRED_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_MPG_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_MPG_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_MPG_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_MPG_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_SUBMBPRED_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_SUBMBPRED_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_SUBMBPRED_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_SUBMBPRED_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_VC1_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_VC1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_VC1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_VC1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_CVCNB_DIS 11:11 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_CVCNB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_CVCNB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_CVCNB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_RSDCTL_DIS 12:12 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_RSDCTL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_RSDCTL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_RSDCTL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_HIST_DIS 13:13 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_VLD_HIST_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_VLD_HIST_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_VLD_HIST_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_H264_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_H264_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_H264_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_H264_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MDXVA_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MDXVA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MDXVA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MDXVA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MPEG4_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MPEG4_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MPEG4_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MPEG4_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MPEG2_DIS 17:17 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MPEG2_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MPEG2_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_MPEG2_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VC1_DIS 18:18 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VC1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VC1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VC1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VDXVA_DIS 19:19 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VDXVA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VDXVA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VDXVA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VP8_DIS 20:20 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VP8_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VP8_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_SEQ_VP8_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_NMB_DIS 21:21 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_NMB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_NMB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_NMB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_CMB_DIS 22:22 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_CMB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_CMB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_CMB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_PMB_DIS 23:23 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_PMB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_PMB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_PMB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_MMB_DIS 24:24 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_MMB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_MMB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_MMB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_LMWT_DIS 25:25 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_LMWT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_LMWT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_LMWT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_CPA_DIS 26:26 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_CPA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_CPA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_CPA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_RCOL_DIS 27:27 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_RCOL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_RCOL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_RCOL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_WCOL_DIS 28:28 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_WCOL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_WCOL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_WCOL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_CPD_DIS 29:29 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_CPD_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_CPD_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_CPD_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_OSP_DBL_DIS 30:30 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_OSP_DBL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_OSP_DBL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_OSP_DBL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_OSP_RDS_DIS 31:31 /* RWIVF */ #define NV_PNVDEC_CG2_SLCG_MV_OSP_RDS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG2_SLCG_MV_OSP_RDS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG2_SLCG_MV_OSP_RDS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3(dev) (0x0084932c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG3__SIZE_1 2 /* */ #define NV_PNVDEC_CG3_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG3_SLCG__PROD 0x00800000 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_REC_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_REC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_REC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_REC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_MCS_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_MCS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_MCS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_MCS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_IS_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_MV_IS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_IS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_MV_IS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_ILPMB_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_MV_ILPMB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_ILPMB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_MV_ILPMB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_ILP_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_ILP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_ILP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_MV_OSP_ILP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_IQT_IQ_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_IQT_IQ_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_IQT_IQ_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_IQT_IQ_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_IQT_IT_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_IQT_IT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_IQT_IT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_IQT_IT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MCF_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_MCF_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MCF_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_MCF_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MCC_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_MCC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MCC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_MCC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MC_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_MC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_MC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_MC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_H264_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_H264_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_H264_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_H264_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_MPG_DIS 11:11 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_MPG_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_MPG_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_MPG_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_VC1_DIS 12:12 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_VC1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_VC1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_VC1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_HB_DIS 13:13 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_HB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_HB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_HB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_HIST_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_HIST_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_HIST_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_HIST_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_MV2REC_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_MV2REC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_MV2REC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_MV2REC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_REC2DBF_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_REC2DBF_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_REC2DBF_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_REC2DBF_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_RECIP_DIS 17:17 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_RECIP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_RECIP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_RECIP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_ILP_DIS 18:18 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_REC_ILP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_REC_ILP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_REC_ILP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_DBF_DIS 19:19 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_DBF_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_DBF_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_DBF_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_HIST_DIS 20:20 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_HIST_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_HIST_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_HIST_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_ILP_DIS 21:21 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_ILP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_ILP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_ILP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_DBFDMA_DIS 22:22 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_DBFDMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_DBFDMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_DBFDMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_CFG_DIS 23:23 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_CFG_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_CFG_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_CFG_DIS__PROD 0x1 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_ECDMA_DIS 24:24 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_ECDMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_ECDMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_ECDMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_LEGACY_DMA_MUX_DIS 25:25 /* RWIVF */ #define NV_PNVDEC_CG3_SLCG_LEGACY_DMA_MUX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG3_SLCG_LEGACY_DMA_MUX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG3_SLCG_LEGACY_DMA_MUX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_PMM(dev) (0x00848b5c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_PMM__SIZE_1 2 /* */ #define NV_PNVDEC_PMM_SEL0 9:0 /* RWIUF */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_REQ_ISSUED 0x000 /* RWI-V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_REQ_ISSUED_SC 0x001 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_PRED_WAITING 0x002 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_PRED_WAITING_SC 0x003 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_PRED_STARTING 0x004 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_PRED_STARTING_SC 0x005 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_P2STALL_ALLOC 0x006 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_P2STALL_ALLOC_SC 0x007 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_P2STALL_FETCH 0x008 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_P2STALL_FETCH_SC 0x009 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_P2STALL_ADMWR 0x00a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_P2STALL_ADMWR_SC 0x00b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_LINE_STORED 0x00c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_LINE_STORED_SC 0x00d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_LINE_DISCARDED 0x00e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_LINE_DISCARDED_SC 0x00f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_REQ_MRQFULL 0x010 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_REQ_MRQFULL_SC 0x011 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_REQ_REQLIMIT 0x012 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_REQ_REQLIMIT_SC 0x013 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_START 0x014 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_START_SC 0x015 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_DONE 0x016 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_DONE_SC 0x017 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_MBDONE 0x018 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_MBDONE_SC 0x019 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_QSTALL 0x01a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_QSTALL_SC 0x01b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_IDLE 0x01c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_FB_MCF_RET_IDLE_SC 0x01d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_IDLE 0x01e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_IDLE_SC 0x01f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_READ_MV_STARVED 0x020 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_READ_MV_STARVED_SC 0x021 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_READ_DBF_STARVED 0x022 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_READ_DBF_STARVED_SC 0x023 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_READ_IQT_STARVED 0x024 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_READ_IQT_STARVED_SC 0x025 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_READ_REC_STARVED 0x026 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_READ_REC_STARVED_SC 0x027 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_WRITE_MV_FULL 0x028 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_WRITE_MV_FULL_SC 0x029 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_WRITE_DBF_FULL 0x02a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_WRITE_DBF_FULL_SC 0x02b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_WRITE_IQT_FULL 0x02c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_WRITE_IQT_FULL_SC 0x02d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_WRITE_REC_FULL 0x02e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_HIST_WRITE_REC_FULL_SC 0x02f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_IDLE 0x030 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_IDLE_SC 0x031 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_HALTED 0x032 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_HALTED_SC 0x033 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_WD_EXPIRED 0x034 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_WD_EXPIRED_SC 0x035 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_SOFT_PM1 0x036 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_SOFT_PM1_SC 0x037 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_SOFT_PM0 0x038 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_SOFT_PM0_SC 0x039 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_CONSUMED_WORD 0x03a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_CONSUMED_WORD_SC 0x03b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_COPY_NXT2CUR 0x03c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_COPY_NXT2CUR_SC 0x03d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_STALLED_ON_IS 0x03e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_STALLED_ON_IS_SC 0x03f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_COLOC_RD 0x040 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_COLOC_RD_SC 0x041 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_COLOC_WR 0x042 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_COLOC_WR_SC 0x043 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_RDS 0x044 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_RDS_SC 0x045 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_DBL 0x046 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_DBL_SC 0x047 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_MCS 0x048 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_MCS_SC 0x049 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_REC 0x04a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_REC_SC 0x04b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_HIST_RD 0x04c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_HIST_RD_SC 0x04d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_HIST_WR 0x04e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_HIST_WR_SC 0x04f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_READ_MV 0x050 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_READ_MV_SC 0x051 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_READ_HIST 0x052 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_READ_HIST_SC 0x053 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_WRITE_REC 0x054 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_WRITE_REC_SC 0x055 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_WRITE_HIST 0x056 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_WRITE_HIST_SC 0x057 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_IDLE 0x058 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_IDLE_SC 0x059 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_MACROBLOCK_START 0x05a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_MACROBLOCK_START_SC 0x05b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_MV 0x05c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_MV_SC 0x05d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_IQT 0x05e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_IQT_SC 0x05f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_MC 0x060 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_MC_SC 0x061 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_HIST 0x062 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_HIST_SC 0x063 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_HIST 0x064 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_HIST_SC 0x065 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_DBF 0x066 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_DBF_SC 0x067 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_IDLE 0x068 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_IDLE_SC 0x069 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_MACROBLOCK_END 0x06a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_MACROBLOCK_END_SC 0x06b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_STALLED_READ 0x06c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_STALLED_READ_SC 0x06d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_STALLED_WRITE 0x06e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_STALLED_WRITE_SC 0x06f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_MACROBLOCK_START 0x070 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_MACROBLOCK_START_SC 0x071 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_MACROBLOCK_END 0x072 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_MACROBLOCK_END_SC 0x073 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_IDLE 0x074 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_IDLE_SC 0x075 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_DATAPATH_VALID 0x076 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MC_DATAPATH_VALID_SC 0x077 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_STALLED_DBFDMA_READ 0x078 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_STALLED_DBFDMA_READ_SC 0x079 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_STALLED_REC_READ 0x07a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_STALLED_REC_READ_SC 0x07b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_STALLED_WRITE 0x07c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_STALLED_WRITE_SC 0x07d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_IDLE 0x07e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_IDLE_SC 0x07f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_MACROBLOCK_START 0x080 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_MACROBLOCK_START_SC 0x081 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_MACROBLOCK_BUSY 0x082 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_MACROBLOCK_BUSY_SC 0x083 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_PICTURE_START 0x084 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_PICTURE_START_SC 0x085 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_PICTURE_END 0x086 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBF_PICTURE_END_SC 0x087 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_STALLED_READ 0x088 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_STALLED_READ_SC 0x089 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_STALLED_WRITE 0x08a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_STALLED_WRITE_SC 0x08b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_IDLE 0x08c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_IDLE_SC 0x08d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_PICTURE_START 0x08e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_PICTURE_START_SC 0x08f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_PICTURE_END 0x090 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_PICTURE_END_SC 0x091 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_WRITE_FBIF 0x092 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_WRITE_FBIF_SC 0x093 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_READ_FBIF 0x094 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_IQT_STALLED_READ_FBIF_SC 0x095 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_STALLED_WRITE_ILP 0x096 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_DBFDMA_STALLED_WRITE_ILP_SC 0x097 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_CTRL_IDLE 0x098 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_CTRL_IDLE_SC 0x099 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_DMA_IDLE 0x09a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_DMA_IDLE_SC 0x09b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_FILTER_IDLE 0x09c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_FILTER_IDLE_SC 0x09d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_OUTBUF_IDLE 0x09e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_OUTBUF_IDLE_SC 0x09f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_WRDMA_IDLE 0x0a0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_WRDMA_IDLE_SC 0x0a1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_IDLE 0x0a2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_IDLE_SC 0x0a3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_DBFDMA2ILPDMA_MB_ONGOING 0x0a4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_DBFDMA2ILPDMA_MB_ONGOING_SC 0x0a5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_REC2ILPDMA_MB_ONGOING 0x0a6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_REC2ILPDMA_MB_ONGOING_SC 0x0a7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_ILPDMA2FB_ONGOING 0x0a8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_ILPDMA2FB_ONGOING_SC 0x0a9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_DMA_MB_START 0x0aa /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_DMA_MB_START_SC 0x0ab /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_DMA_MB_END 0x0ac /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_DMA_MB_END_SC 0x0ad /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_REGFIELD_MB_START 0x0ae /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_REGFIELD_MB_START_SC 0x0af /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_REGFIELD_MB_END 0x0b0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_REGFIELD_MB_END_SC 0x0b1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_SURFACE_NOTAVAIL 0x0b2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_SURFACE_NOTAVAIL_SC 0x0b3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_STALLED_ON_MV 0x0b4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_STALLED_ON_MV_SC 0x0b5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_STALLED_ON_REC 0x0b6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_STALLED_ON_REC_SC 0x0b7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_WAIT_FBIF 0x0b8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_ILP_WAIT_FBIF_SC 0x0b9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_ILPMB_RD 0x0ba /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_ILPMB_RD_SC 0x0bb /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_ILPMB_WR 0x0bc /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MV_ME_WAIT_ILPMB_WR_SC 0x0bd /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_ILP 0x0be /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_ILP_SC 0x0bf /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_ILP 0x0c0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_ILP_SC 0x0c1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_STALLED_READ 0x0c2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_STALLED_EDOB 0x0c3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_EDOB_STALLED_WRITE 0x0c4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_EDOB_STALLED_LIMIT 0x0c5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_AND_EDOB_STALLED 0x0c6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_SLICEPARSER_BUSY 0x0c7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_IDLE 0x0c8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_SLICE_START 0x0c9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_SLICE_END 0x0ca /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_MACROBLOCK_START 0x0cb /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_MACROBLOCK_END 0x0cc /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_4BYTES_USED 0x0cd /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_STALLED_READ_SC 0x0ce /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_STALLED_EDOB_SC 0x0cf /* RW--V */ #define NV_PNVDEC_PMM_SEL0_EDOB_STALLED_WRITE_SC 0x0d0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_EDOB_STALLED_LIMIT_SC 0x0d1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_AND_EDOB_STALLED_SC 0x0d2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_SLICEPARSER_BUSY_SC 0x0d3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_IDLE_SC 0x0d4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_SLICE_START_SC 0x0d5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_SLICE_END_SC 0x0d6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_MACROBLOCK_START_SC 0x0d7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_MACROBLOCK_END_SC 0x0d8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_VLD_4BYTES_USED_SC 0x0d9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_FRAME_START 0x0da /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_FRAME_END 0x0db /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_IQT_STALL_EMD 0x0dc /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_IQT_WAIT_EMD 0x0dd /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PRED_STALL_IQT 0x0de /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PRED_WAIT_IQT 0x0df /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_MVD_STALL_EMD 0x0e0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_MVD_WAIT_EMD 0x0e1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PREFETCH_STALL_MVD 0x0e2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PREFETCH_WAIT_MVD 0x0e3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PRED_WAIT_MCF 0x0e4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PRED_INTRA_STALL_INTER 0x0e5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_FILTER_STALL_PRED 0x0e6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_FILTER_WAIT_PRED 0x0e7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_SAO_STALL_FILTER 0x0e8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_FRAME_START_SC 0x0e9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_FRAME_END_SC 0x0ea /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_IQT_STALL_EMD_SC 0x0eb /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_IQT_WAIT_EMD_SC 0x0ec /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PRED_STALL_IQT_SC 0x0ed /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PRED_WAIT_IQT_SC 0x0ee /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_MVD_STALL_EMD_SC 0x0ef /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_MVD_WAIT_EMD_SC 0x0f0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PREFETCH_STALL_MVD_SC 0x0f1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PREFETCH_WAIT_MVD_SC 0x0f2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PRED_WAIT_MCF_SC 0x0f3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_PRED_INTRA_STALL_INTER_SC 0x0f4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_FILTER_STALL_PRED_SC 0x0f5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_FILTER_WAIT_PRED_SC 0x0f6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_GIP_SAO_STALL_FILTER_SC 0x0f7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x0f8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x0f9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_STATIC_PATTERN_1_1_GROUP_SC 0x0fa /* RW--V */ #define NV_PNVDEC_PMM_SEL0_STATIC_PATTERN_0_1_GROUP_SC 0x0fb /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLMVDATA_DMA2MVD_AV1_STALLING 0x100 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLMVDATA_DMA2MVD_AV1_STALLING_SC 0x101 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLMVDATA_DMA2MVD_AV1_STARVING 0x102 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLMVDATA_DMA2MVD_AV1_STARVING_SC 0x103 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLMVDATA_MVD2DMA_AV1_STALLING 0x104 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLMVDATA_MVD2DMA_AV1_STALLING_SC 0x105 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLMVDATA_MVD2DMA_AV1_STARVING 0x106 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLMVDATA_MVD2DMA_AV1_STARVING_SC 0x107 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLOC_CTRL_OUT_STALLING 0x108 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLOC_CTRL_OUT_STALLING_SC 0x109 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLOC_CTRL_OUT_STARVING 0x10a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLOC_CTRL_OUT_STARVING_SC 0x10b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLOC_MV_REF_PIC_BASE_STALLING 0x10c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLOC_MV_REF_PIC_BASE_STALLING_SC 0x10d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLOC_MV_REF_PIC_BASE_STARVING 0x10e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_COLOC_MV_REF_PIC_BASE_STARVING_SC 0x10f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2STREAMIF_DATA_STALLING 0x110 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2STREAMIF_DATA_STALLING_SC 0x111 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2STREAMIF_DATA_STARVING 0x112 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2STREAMIF_DATA_STARVING_SC 0x113 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2FILTER_CTB_CTRL_STALLING 0x114 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2FILTER_CTB_CTRL_STALLING_SC 0x115 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2FILTER_CTB_CTRL_STARVING 0x116 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2FILTER_CTB_CTRL_STARVING_SC 0x117 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2INTRA_PALETTE_DATA_STALLING 0x118 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2INTRA_PALETTE_DATA_STALLING_SC 0x119 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2INTRA_PALETTE_DATA_STARVING 0x11a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2INTRA_PALETTE_DATA_STARVING_SC 0x11b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2IQT_COEFF_STALLING 0x11c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2IQT_COEFF_STALLING_SC 0x11d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2IQT_COEFF_STARVING 0x11e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2IQT_COEFF_STARVING_SC 0x11f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2IQT_TU_CTRL_STALLING 0x120 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2IQT_TU_CTRL_STALLING_SC 0x121 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2IQT_TU_CTRL_STARVING 0x122 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP2IQT_TU_CTRL_STARVING_SC 0x123 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_RD_STALLING 0x124 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_RD_STALLING_SC 0x125 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_RD_STARVING 0x126 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_RD_STARVING_SC 0x127 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_WR_STALLING 0x128 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_WR_STALLING_SC 0x129 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_WR_STARVING 0x12a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_WR_STARVING_SC 0x12b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_CUCTRL_STALLING 0x12c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_CUCTRL_STALLING_SC 0x12d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_CUCTRL_STARVING 0x12e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_CUCTRL_STARVING_SC 0x12f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_MVCTRL_STALLING 0x130 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_MVCTRL_STALLING_SC 0x131 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_MVCTRL_STARVING 0x132 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_MVCTRL_STARVING_SC 0x133 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_STREAM_FIFO_STALLING 0x134 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_STREAM_FIFO_STALLING_SC 0x135 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_STREAM_FIFO_STARVING 0x136 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_STREAM_FIFO_STARVING_SC 0x137 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_STREAMIF2SA_DATA_STALLING 0x138 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_STREAMIF2SA_DATA_STALLING_SC 0x139 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_STREAMIF2SA_DATA_STARVING 0x13a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_STREAMIF2SA_DATA_STARVING_SC 0x13b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_SEGMENT_OUT_STALLING 0x13c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_SEGMENT_OUT_STALLING_SC 0x13d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_SEGMENT_OUT_STARVING 0x13e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_SEGMENT_OUT_STARVING_SC 0x13f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CU_CONTROL_INTER_STALLING 0x140 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CU_CONTROL_INTER_STALLING_SC 0x141 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CU_CONTROL_INTER_STARVING 0x142 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CU_CONTROL_INTER_STARVING_SC 0x143 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2IQT_DATA_STALLING 0x144 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2IQT_DATA_STALLING_SC 0x145 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2IQT_DATA_STARVING 0x146 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2IQT_DATA_STARVING_SC 0x147 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FETCH_CONTROL_OUT_STALLING 0x148 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FETCH_CONTROL_OUT_STALLING_SC 0x149 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FETCH_CONTROL_OUT_STARVING 0x14a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FETCH_CONTROL_OUT_STARVING_SC 0x14b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2DMA_DATA_STALLING 0x14c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2DMA_DATA_STALLING_SC 0x14d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2DMA_DATA_STARVING 0x14e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2DMA_DATA_STARVING_SC 0x14f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2INTRA_RESIDUAL_STALLING 0x150 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2INTRA_RESIDUAL_STALLING_SC 0x151 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2INTRA_RESIDUAL_STARVING 0x152 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2INTRA_RESIDUAL_STARVING_SC 0x153 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2INTRA_TU_CTRL_STALLING 0x154 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2INTRA_TU_CTRL_STALLING_SC 0x155 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2INTRA_TU_CTRL_STARVING 0x156 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQT2INTRA_TU_CTRL_STARVING_SC 0x157 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQTDMA2FBIF_RD_REQ_STALLING 0x158 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQTDMA2FBIF_RD_REQ_STALLING_SC 0x159 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQTDMA2FBIF_RD_REQ_STARVING 0x15a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_IQTDMA2FBIF_RD_REQ_STARVING_SC 0x15b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MV_CONTROL_INTER_STALLING 0x15c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MV_CONTROL_INTER_STALLING_SC 0x15d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MV_CONTROL_INTER_STARVING 0x15e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MV_CONTROL_INTER_STARVING_SC 0x15f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PART_CONTROL_INTER_STALLING 0x160 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PART_CONTROL_INTER_STALLING_SC 0x161 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PART_CONTROL_INTER_STARVING 0x162 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PART_CONTROL_INTER_STARVING_SC 0x163 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PREFETCH2INTRA_CU_CTRL_STALLING 0x164 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PREFETCH2INTRA_CU_CTRL_STALLING_SC 0x165 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PREFETCH2INTRA_CU_CTRL_STARVING 0x166 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PREFETCH2INTRA_CU_CTRL_STARVING_SC 0x167 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TU_CONTROL_INTER_STALLING 0x168 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TU_CONTROL_INTER_STALLING_SC 0x169 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TU_CONTROL_INTER_STARVING 0x16a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TU_CONTROL_INTER_STARVING_SC 0x16b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CU_CONTROL_FILTER_OUT_STALLING 0x16c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CU_CONTROL_FILTER_OUT_STALLING_SC 0x16d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CU_CONTROL_FILTER_OUT_STARVING 0x16e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CU_CONTROL_FILTER_OUT_STARVING_SC 0x16f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2INTRA_DATA_STALLING 0x170 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2INTRA_DATA_STALLING_SC 0x171 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2INTRA_DATA_STARVING 0x172 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2INTRA_DATA_STARVING_SC 0x173 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRA2DMA_DATA_STALLING 0x174 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRA2DMA_DATA_STALLING_SC 0x175 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRA2DMA_DATA_STARVING 0x176 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRA2DMA_DATA_STARVING_SC 0x177 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRA2FILTER_TILE_INFO_STALLING 0x178 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRA2FILTER_TILE_INFO_STALLING_SC 0x179 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRA2FILTER_TILE_INFO_STARVING 0x17a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRA2FILTER_TILE_INFO_STARVING_SC 0x17b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_RD_REQ_STALLING 0x17c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_RD_REQ_STALLING_SC 0x17d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_RD_REQ_STARVING 0x17e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_RD_REQ_STARVING_SC 0x17f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_WR_STALLING 0x180 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_WR_STALLING_SC 0x181 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_WR_STARVING 0x182 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_WR_STARVING_SC 0x183 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MV_CONTROL_FILTER_OUT_STALLING 0x184 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MV_CONTROL_FILTER_OUT_STALLING_SC 0x185 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MV_CONTROL_FILTER_OUT_STARVING 0x186 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_MV_CONTROL_FILTER_OUT_STARVING_SC 0x187 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_RECON2FILTER_DATA_STALLING 0x188 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_RECON2FILTER_DATA_STALLING_SC 0x189 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_RECON2FILTER_DATA_STARVING 0x18a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_RECON2FILTER_DATA_STARVING_SC 0x18b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TILEINFO_STALLING 0x18c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TILEINFO_STALLING_SC 0x18d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TILEINFO_STARVING 0x18e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TILEINFO_STARVING_SC 0x18f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TU_CONTROL_FILTER_OUT_STALLING 0x190 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TU_CONTROL_FILTER_OUT_STALLING_SC 0x191 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TU_CONTROL_FILTER_OUT_STARVING 0x192 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_TU_CONTROL_FILTER_OUT_STARVING_SC 0x193 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CDEF_LEFT_NB_OUT_STALLING 0x194 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CDEF_LEFT_NB_OUT_STALLING_SC 0x195 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CDEF_LEFT_NB_OUT_STARVING 0x196 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_CDEF_LEFT_NB_OUT_STARVING_SC 0x197 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK2DMA_TILE_INFO_STALLING 0x198 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK2DMA_TILE_INFO_STALLING_SC 0x199 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK2DMA_TILE_INFO_STARVING 0x19a /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK2DMA_TILE_INFO_STARVING_SC 0x19b /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK_LEFT_NB_OUT_STALLING 0x19c /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK_LEFT_NB_OUT_STALLING_SC 0x19d /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK_LEFT_NB_OUT_STARVING 0x19e /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK_LEFT_NB_OUT_STARVING_SC 0x19f /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK_TOP_NB_OUT_STALLING 0x1a0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK_TOP_NB_OUT_STALLING_SC 0x1a1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK_TOP_NB_OUT_STARVING 0x1a2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DBLK_TOP_NB_OUT_STARVING_SC 0x1a3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2FGS_LU_STALLING 0x1a4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2FGS_LU_STALLING_SC 0x1a5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2FGS_LU_STARVING 0x1a6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2FGS_LU_STARVING_SC 0x1a7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2FGS_NOISE_DATA_STALLING 0x1a8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2FGS_NOISE_DATA_STALLING_SC 0x1a9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2FGS_NOISE_DATA_STARVING 0x1aa /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_DMA2FGS_NOISE_DATA_STARVING_SC 0x1ab /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FBIF_RD_REQ_STALLING 0x1ac /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FBIF_RD_REQ_STALLING_SC 0x1ad /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FBIF_RD_REQ_STARVING 0x1ae /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FBIF_RD_REQ_STARVING_SC 0x1af /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FBIF_WR_REQ_STALLING 0x1b0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FBIF_WR_REQ_STALLING_SC 0x1b1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FBIF_WR_REQ_STARVING 0x1b2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FBIF_WR_REQ_STARVING_SC 0x1b3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS2DMA_LU_STALLING 0x1b4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS2DMA_LU_STALLING_SC 0x1b5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS2DMA_LU_STARVING 0x1b6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS2DMA_LU_STARVING_SC 0x1b7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS_PP2TF_CTRL_STALLING 0x1b8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS_PP2TF_CTRL_STALLING_SC 0x1b9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS_PP2TF_CTRL_STARVING 0x1ba /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS_PP2TF_CTRL_STARVING_SC 0x1bb /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS_PP2TF_DATA_STALLING 0x1bc /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS_PP2TF_DATA_STALLING_SC 0x1bd /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS_PP2TF_DATA_STARVING 0x1be /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_FGS_PP2TF_DATA_STARVING_SC 0x1bf /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_HUS_LEFT_NB_OUT_STALLING 0x1c0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_HUS_LEFT_NB_OUT_STALLING_SC 0x1c1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_HUS_LEFT_NB_OUT_STARVING 0x1c2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_HUS_LEFT_NB_OUT_STARVING_SC 0x1c3 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_LR_LEFT_NB_OUT_STALLING 0x1c4 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_LR_LEFT_NB_OUT_STALLING_SC 0x1c5 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_LR_LEFT_NB_OUT_STARVING 0x1c6 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_LR_LEFT_NB_OUT_STARVING_SC 0x1c7 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PP2HIST_DMA_STALLING 0x1c8 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PP2HIST_DMA_STALLING_SC 0x1c9 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PP2HIST_DMA_STARVING 0x1ca /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PP2HIST_DMA_STARVING_SC 0x1cb /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PP2TF_CTRL_STALLING 0x1cc /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PP2TF_CTRL_STALLING_SC 0x1cd /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PP2TF_CTRL_STARVING 0x1ce /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_PP2TF_CTRL_STARVING_SC 0x1cf /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_SAO_LEFT_NB_OUT_STALLING 0x1d0 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_SAO_LEFT_NB_OUT_STALLING_SC 0x1d1 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_SAO_LEFT_NB_OUT_STARVING 0x1d2 /* RW--V */ #define NV_PNVDEC_PMM_SEL0_AVD_SAO_LEFT_NB_OUT_STARVING_SC 0x1d3 /* RW--V */ #define NV_PNVDEC_PMM_SEL1 19:10 /* RWIUF */ #define NV_PNVDEC_PMM_SEL1_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM_SEL2 29:20 /* RWIUF */ #define NV_PNVDEC_PMM_SEL2_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM_BUSEN 31:31 /* RWIUF */ #define NV_PNVDEC_PMM_BUSEN_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_PMM_BUSEN_ON 0x1 /* RW--V */ #define NV_PNVDEC_PMM1(dev) (0x00848b58+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_PMM1__SIZE_1 2 /* */ #define NV_PNVDEC_PMM1_SEL0 9:0 /* RWIUF */ #define NV_PNVDEC_PMM1_SEL0_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM1_SEL1 19:10 /* RWIUF */ #define NV_PNVDEC_PMM1_SEL1_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM1_SEL2 29:20 /* RWIUF */ #define NV_PNVDEC_PMM1_SEL2_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM2(dev) (0x00848b54+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_PMM2__SIZE_1 2 /* */ #define NV_PNVDEC_PMM2_SEL0 9:0 /* RWIUF */ #define NV_PNVDEC_PMM2_SEL0_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM2_SEL1 19:10 /* RWIUF */ #define NV_PNVDEC_PMM2_SEL1_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM2_SEL2 29:20 /* RWIUF */ #define NV_PNVDEC_PMM2_SEL2_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM3(dev) (0x00848b50+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_PMM3__SIZE_1 2 /* */ #define NV_PNVDEC_PMM3_SEL0 9:0 /* RWIUF */ #define NV_PNVDEC_PMM3_SEL0_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM3_SEL1 19:10 /* RWIUF */ #define NV_PNVDEC_PMM3_SEL1_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM3_SEL2 29:20 /* RWIUF */ #define NV_PNVDEC_PMM3_SEL2_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_PMM_LTA(dev) (0x00848b4c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_PMM_LTA__SIZE_1 2 /* */ #define NV_PNVDEC_PMM_LTA_LOCAL_TRIGGERA 31:31 /* RWIUF */ #define NV_PNVDEC_PMM_LTA_LOCAL_TRIGGERA_INIT_VAL 0x0 /* RWI-V */ #define NV_PNVDEC_PMM_LTA_LOCAL_BKMKA 15:0 /* RWIUF */ #define NV_PNVDEC_PMM_LTA_LOCAL_BKMKA_INIT_VAL 0x0000 /* RWI-V */ #define NV_PNVDEC_PMM_LTB(dev) (0x00848b48+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_PMM_LTB__SIZE_1 2 /* */ #define NV_PNVDEC_PMM_LTB_LOCAL_TRIGGERB 31:31 /* RWIUF */ #define NV_PNVDEC_PMM_LTB_LOCAL_TRIGGERB_INIT_VAL 0x0 /* RWI-V */ #define NV_PNVDEC_PMM_LTB_LOCAL_BKMKB 15:0 /* RWIUF */ #define NV_PNVDEC_PMM_LTB_LOCAL_BKMKB_INIT_VAL 0x0000 /* RWI-V */ #define NV_PNVDEC_RECCTL(dev) (0x00848b00+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_RECCTL__SIZE_1 2 /* */ #define NV_PNVDEC_RECCTL_CODEC 2:0 /* RWIVF */ #define NV_PNVDEC_RECCTL_CODEC_MPEG1 0x0 /* RWI-V */ #define NV_PNVDEC_RECCTL_CODEC_MPEG2 0x1 /* RW--V */ #define NV_PNVDEC_RECCTL_CODEC_VC1 0x2 /* RW--V */ #define NV_PNVDEC_RECCTL_CODEC_H264 0x3 /* RW--V */ #define NV_PNVDEC_RECCTL_CODEC_MPEG4 0x4 /* RW--V */ #define NV_PNVDEC_RECCTL_CODEC_VP8 0x5 /* RW--V */ #define NV_PNVDEC_RECCTL_REGCFG 3:3 /* RWIVF */ #define NV_PNVDEC_RECCTL_REGCFG_WAIT 0x0 /* RWI-V */ #define NV_PNVDEC_RECCTL_REGCFG_DONE 0x1 /* RW--V */ #define NV_PNVDEC_RECCTL_OVRHORZ 4:4 /* RWIVF */ #define NV_PNVDEC_RECCTL_OVRHORZ_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_RECCTL_MBAFF 5:5 /* RWIVF */ #define NV_PNVDEC_RECCTL_MBAFF_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_RECCTL_LOSSLESS_I8X8_PREFILT 6:6 /* RWIVF */ #define NV_PNVDEC_RECCTL_LOSSLESS_I8X8_PREFILT_ENABLE 0x1 /* RWI-V */ #define NV_PNVDEC_RECCTL_LOSSLESS_I8X8_PREFILT_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_RECCTL_INTRA_ALLOW_RES_PRED 7:7 /* RWIVF */ #define NV_PNVDEC_RECCTL_INTRA_ALLOW_RES_PRED_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_RECCTL_INTRA_ALLOW_RES_PRED_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_RECCTL_ILP_ENABLE 8:8 /* RWIVF */ #define NV_PNVDEC_RECCTL_ILP_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_RECCTL_DBF_DISABLE 9:9 /* RWIVF */ #define NV_PNVDEC_RECCTL_DBF_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_RECCTL_MCS_DISABLE 10:10 /* RWIVF */ #define NV_PNVDEC_RECCTL_MCS_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_RECINTEN(dev) (0x00848b04+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_RECINTEN__SIZE_1 2 /* */ #define NV_PNVDEC_RECINTEN_IRQ_CFGWR 0:0 /* RWIVF */ #define NV_PNVDEC_RECINTEN_IRQ_CFGWR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_RECINTCSW(dev) (0x00848b08+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_RECINTCSW__SIZE_1 2 /* */ #define NV_PNVDEC_RECINTCSW_IRQ_CFGWR 0:0 /* RW-VF */ #define NV_PNVDEC_RECDBG1(dev) (0x00848b0c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_RECDBG1__SIZE_1 2 /* */ #define NV_PNVDEC_RECDBG1_H264_CUR_ST 2:0 /* R-XUF */ #define NV_PNVDEC_RECDBG1_INIT_CUR_ST 4:3 /* R-XUF */ #define NV_PNVDEC_RECDBG1_DP_CUR_ST 6:5 /* R-XUF */ #define NV_PNVDEC_RECDBG1_DI_CUR_ST 8:7 /* R-XUF */ #define NV_PNVDEC_RECDBG1_MPEG_CUR_ST 9:9 /* R-XUF */ #define NV_PNVDEC_RECDBG1_HIST2REC_RD_CUR_ST 11:10 /* R-XUF */ #define NV_PNVDEC_RECDBG1_MV2REC_RD_CUR_ST 12:12 /* R-XUF */ #define NV_PNVDEC_RECDBG1_REC2DBF_RD_CUR_ST 15:13 /* R-IUF */ #define NV_PNVDEC_RECDBG1_REC2DBF_RD_CUR_ST_IDLE 0x1 /* R-I-V */ #define NV_PNVDEC_RECDBG1_REC2HIST_RD_CUR_ST 18:16 /* R-XUF */ #define NV_PNVDEC_RECDBG1_IQT_CUR_ST 19:19 /* R-XUF */ #define NV_PNVDEC_RECDBG1_VC1_CUR_ST 22:20 /* R-XUF */ #define NV_PNVDEC_RECDBG1_LES_CUR_ST 24:23 /* R-XUF */ #define NV_PNVDEC_RECDBG1_TES_CUR_ST 26:25 /* R-XUF */ #define NV_PNVDEC_RECDBG1_RSI_CUR_ST 28:27 /* R-XUF */ #define NV_PNVDEC_RECDBG1_RCTL_CUR_ST 30:29 /* R-XUF */ #define NV_PNVDEC_RECDBG2(dev) (0x00848b10+(dev)*16384) /* R--4A */ #define NV_PNVDEC_RECDBG2__SIZE_1 2 /* */ #define NV_PNVDEC_RECDBG2_CFG_CUR_ST 1:0 /* R-IUF */ #define NV_PNVDEC_RECDBG2_CFG_CUR_ST_RD 0x2 /* R-I-V */ #define NV_PNVDEC_RECDBG2_INTER_CUR_ST 3:2 /* R-XUF */ #define NV_PNVDEC_RECDBG2_REC_IDLE 4:4 /* R-IUF */ #define NV_PNVDEC_RECDBG2_REC_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_RECDBG2_RECIP_IDLE 5:5 /* R-IUF */ #define NV_PNVDEC_RECDBG2_RECIP_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_RECDBG2_MV2REC_IDLE 6:6 /* R-IUF */ #define NV_PNVDEC_RECDBG2_MV2REC_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_RECDBG2_REC2DBF_IDLE 7:7 /* R-IUF */ #define NV_PNVDEC_RECDBG2_REC2DBF_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_RECDBG2_REC2HIST_IDLE 8:8 /* R-IUF */ #define NV_PNVDEC_RECDBG2_REC2HIST_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_RECDBG2_ILP2REC_RD_CUR_ST 9:9 /* R-IUF */ #define NV_PNVDEC_RECDBG2_ILP2REC_RD_CUR_ST_PK0 0x0 /* R-I-V */ #define NV_PNVDEC_RECDBG2_ILP2REC_RD_CUR_ST_PK1 0x1 /* R---V */ #define NV_PNVDEC_RECDBG2_REC2ILP_RD_CUR_ST 11:10 /* R-IUF */ #define NV_PNVDEC_RECDBG2_REC2ILP_RD_CUR_ST_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_RECDBG2_REC2ILP_RD_CUR_ST_CTRL 0x1 /* R---V */ #define NV_PNVDEC_RECDBG2_REC2ILP_RD_CUR_ST_DATA 0x2 /* R---V */ #define NV_PNVDEC_RECDBG2_REC2ILP_RD_CUR_ST_EMPT 0x3 /* R---V */ #define NV_PNVDEC_RECDBG2_REC2ILP_IDLE 12:12 /* R-IUF */ #define NV_PNVDEC_RECDBG2_REC2ILP_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON(dev) (0x00848400+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_WIDTH_IN_MBS 7:0 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_FRAME_HEIGHT_IN_MBS 15:8 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_TYPE 17:16 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_TYPE_FRAME 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_TYPE_TOP_FIELD 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_TYPE_BOTTOM_FIELD 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING 19:18 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG_D 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG_I 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG_P 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG_B 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1_SKIPPED 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1_I_OR_BI 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1_P 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1_B 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG4_SKIPPED 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG4_I 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG4_P 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG4_B 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VP8_I 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VP8_P 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE 22:20 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_MPEG1 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_MPEG2 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_VC1 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_H264 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_MPEG4 0x4 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_VP8 0x5 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PROFILE 25:24 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PROFILE_VC1_SIMPLE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PROFILE_VC1_MAIN 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PROFILE_VC1_ADVANCED 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_PROFILE_MPEG4_SHORT_HEADER 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_SSM_EN 26:26 /* RWIVF */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_SSM_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_SSM_EN_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA 27:27 /* RWIVF */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA_ON 0x1 /* RW--V */ #define NV_PNVDEC_VLD_PIC_INFO_H264(dev) (0x00848404+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PIC_INFO_H264__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PIC_INFO_H264_CABAC 0:0 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_H264_CABAC_CAVLC 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_H264_CABAC_CABAC 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_H264_MBAFF_FRAME_FLAG 9:9 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_H264_NALUNIT_TYPE 16:12 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_H264_CONSTRAINED_INTRA_PRED_FLAG 17:17 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_H264_CABAC_INIT_IDC 19:18 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_H264_CHROMA_FORMAT_IDC 21:20 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_H264_DIRECT_8X8_INFERENCE_FLAG 22:22 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_H264_TRANSFORM_8X8_MODE_FLAG 23:23 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2(dev) (0x00848408+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2_INTRA_DC_PRECISION 1:0 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2_FRAME_PRED_FRAME_DCT 2:2 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2_INTRA_VLC_FORMAT 3:3 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2_CONCEALMENT_MOTION_VEC 4:4 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2_F_CODE00 19:16 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2_F_CODE01 23:20 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2_F_CODE10 27:24 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_MPEG2_F_CODE11 31:28 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB(dev) (0x0084840c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_SLICE_ADDR 6:0 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_NUM_REF 7:7 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_NUM_REF_ONE_REF_PIC 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_NUM_REF_TWO_REF_PIC 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_FCM 9:8 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_FCM_PROGRESSIVE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_FCM_FRAME_INTERLACE 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_FCM_FIELD_INTERLACE 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_FCM_MPEG4_INTERLACE 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_REF_DIST 11:10 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_REF_FIELD 12:12 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_REF_FIELD_TEMP_CLOSEST 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_REF_FIELD_SECOND_MOST_TEMP_CLOSEST 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_FIELD_TX 16:16 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_FIELD_TX_RAW 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_FIELD_TX_BITPLANE 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1GB_SLICE_ADDRX 31:24 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T(dev) (0x00848410+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_CBP_TAB 2:0 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_MV_TAB 6:4 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TWO_MV_BP_TAB 9:8 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_FOUR_MV_BP_TAB 11:10 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_MB_MODE_TAB 14:12 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_DC_TAB 16:16 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_DC_TAB_LOW_MOTION 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_DC_TAB_HIGH_MOTION 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_ESC_LVL_SZ_TAB 17:17 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_ESC_LVL_SZ_TAB_TABLE59 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_ESC_LVL_SZ_TAB_TABLE60 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1 21:20 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1_HIGH_RATE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1_LOW_MOTION 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1_HIGH_MOTION 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1_MID_RATE 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2 23:22 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2_HIGH_RATE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2_LOW_MOTION 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2_HIGH_MOTION 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2_MID_RATE 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q(dev) (0x00848414+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_FRAME 0:0 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_BINARY_LEVEL 1:1 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE 3:2 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_4_EDGE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_2_EDGE 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_1_EDGE 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_ALL_MB 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_SDB_EDGE 5:4 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_PICTURE_QUANTIZER_STEP 20:16 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1Q_ALT_PICTURE_QUANTIZER_STEP 28:24 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P(dev) (0x00848418+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE 1:0 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE_NORM_HORZ_NORM_VERT 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE_EXT_HORZ_NORM_VERT 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE_NORM_HORZ_EXT_VERT 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE_EXT_HORZ_EXT_VERT 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_MV_RANGE 3:2 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_MV_MODE 5:4 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_MV_MODE_MIXED_MV 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_MV_MODE_1_MV 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_MV_MODE_1_MV_HALF_PEL 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_MV_MODE_1_MV_HALF_PEL_BILINEAR 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE 7:6 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_8X8 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_8X4 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_4X8 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_4X4 0x3 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_TRANSFORM_TYPE_FLAG 8:8 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_FOUR_MV_SWITCH 9:9 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_COND_OVER_MB 10:10 /* RWXUF */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_COND_OVER_MB_PICTURE_LEVEL 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_COND_OVER_MB_MB_LEVEL 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_PIC_INFO_VC1P_SYNCMARKER 11:11 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO(dev) (0x0084841c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_SLICE_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_SLICE_INFO_SLICE_TYPE 1:0 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SLICE_TYPE_P 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SLICE_TYPE_B 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SLICE_TYPE_I 0x2 /* RWX-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SLICE_NUM 14:2 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_NUM_REF_IDXL0_ACTIVE_MINUS1 19:15 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_NUM_REF_IDXL1_ACTIVE_MINUS1 24:20 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SLICE_QPY 30:25 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_ROWXPICWIDTH_MBS 14:2 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SLICE_ROW 22:15 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_QUANT_SCALE_CODE 29:25 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_EXT(dev) (0x00848420+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_SLICE_INFO_EXT__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_SLICE_INFO_EXT_SLICE_NUM 2:0 /* RWXUF */ #define NV_PNVDEC_VLD_EDOB_MB_INFO(dev) (0x00848424+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_EDOB_MB_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_EDOB_MB_INFO_MB_ADDR 15:0 /* RWXUF */ #define NV_PNVDEC_VLD_EDOB_MB_INFO_SLICE_FIRST_MB_FLAG 16:16 /* RWXUF */ #define NV_PNVDEC_VLD_EDOB_MB_INFO_MB_RSTN 17:17 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC(dev) (0x00848428+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_BASE_MODE 1:0 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_BASE_MODE_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_BASE_MODE_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_BASE_MODE_ADAPTIVE 0x2 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_RES_PRED 3:2 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_RES_PRED_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_RES_PRED_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_RES_PRED_ADAPTIVE 0x2 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_MOTION_PRED 5:4 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_MOTION_PRED_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_MOTION_PRED_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_MOTION_PRED_ADAPTIVE 0x2 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CBP_PRED 6:6 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CBP_PRED_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CBP_PRED_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_ACSCANSTARTADJ 7:7 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_ACSCANSTARTADJ_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_ACSCANSTARTADJ_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_SCAN_START 11:8 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_SCAN_START_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_SCAN_END 15:12 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_SCAN_END_INIT 0xf /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_SKIP_MAX 28:16 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_SKIP 29:29 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_SKIP_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_SKIP_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP(dev) (0x0084842c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP_XMIN 7:0 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP_XMIN_INIT 0x01 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP_XMAX 15:8 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP_XMAX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP_YMIN 23:16 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP_YMIN_INIT 0x01 /* RWI-V */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP_YMAX 31:24 /* RWIUF */ #define NV_PNVDEC_VLD_SLICE_INFO_SVC_CROP_YMAX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD_EDOB_MB_POS(dev) (0x00848430+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_EDOB_MB_POS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_EDOB_MB_POS_MB_X 7:0 /* RWXUF */ #define NV_PNVDEC_VLD_EDOB_MB_POS_MB_Y 15:8 /* RWXUF */ #define NV_PNVDEC_VLD_MB_INFO(dev) (0x00848434+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_MB_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_MB_INFO_MB_ADDR 15:0 /* RWXUF */ #define NV_PNVDEC_VLD_MB_INFO_SLICE_FIRST_MB_FLAG 16:16 /* RWXUF */ #define NV_PNVDEC_VLD_MB_POS(dev) (0x00848438+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_MB_POS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_MB_POS_MB_X 7:0 /* RWXUF */ #define NV_PNVDEC_VLD_MB_POS_MB_Y 15:8 /* RWXUF */ #define NV_PNVDEC_VLD_PARSE_CMD(dev) (0x0084843c+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_VLD_PARSE_CMD__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD 4:0 /* -WXUF */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_UE 0x00 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_SE 0x01 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_U 0x02 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_NAL_HEAD 0x03 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_VP8_PIC_HEAD 0x03 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_BYTE_ALIGNED 0x04 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_MORE_RBSP_DATA 0x05 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_MB_SKIP_FLAG_AE 0x06 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_END_OF_SLICE_FLAG_AE 0x07 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_START_CABAC_INIT 0x08 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_SKIP_MB 0x09 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_NON_SKIP_MB 0x0a /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_PARSE_PRED_WEIGHT_TABLE 0x0b /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_H264_PARSE_SLICE_DATA 0x0c /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_VC1_PARSE_MACROBLOCKS 0x0c /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_MPEG2_PARSE_SLICEDATA 0x0c /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_VP8_PARSE_PICDATA 0x0c /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_MPEG2_RESERVED 0x0d /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_MPEG2_NEXT_BITS 0x0e /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_MPEG2_PARSE_PICTURE_DATA 0x0f /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_VC1_PARSE_PICTURE_HEADER 0x10 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_VC1_PARSE_BITPLANE 0x11 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_SEND_EOS 0x12 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_INSERT_ERROR_MB 0x13 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_CMD_NOP 0x14 /* -WX-V */ #define NV_PNVDEC_VLD_PARSE_CMD_PARAM 10:5 /* -WXUF */ #define NV_PNVDEC_VLD_PARSE_CMD_PARAM_READ_MB_FIELD_DECODE_FLAG 5:5 /* -WXUF */ #define NV_PNVDEC_VLD_PARSE_CMD_PARAM_VC1_TARGET_PLANE 6:5 /* -WXUF */ #define NV_PNVDEC_VLD_STATUS(dev) (0x00848440+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_STATUS_BUSY 0:0 /* R-XUF */ #define NV_PNVDEC_VLD_STATUS_SLICE_BUSY 1:1 /* R-XUF */ #define NV_PNVDEC_VLD_STATUS_EDOB_BUSY 2:2 /* R-XUF */ #define NV_PNVDEC_VLD_STATUS_VC1_PIC_BUSY 3:3 /* R-XUF */ #define NV_PNVDEC_VLD_STATUS_EDOB_NON_EMPTY 4:4 /* R-XUF */ #define NV_PNVDEC_VLD_STATUS_MEMACC_BUSY 5:5 /* R-XUF */ #define NV_PNVDEC_VLD_STATUS_FIFOCTRL_BUSY 6:6 /* R-XUF */ #define NV_PNVDEC_VLD_STATUS_HIST_BUSY 7:7 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT(dev) (0x00848444+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD_RESULT__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_RESULT_RESULT_DATA 31:0 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_NAL_UNIT_TYPE 4:0 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_NAL_REF_IDC 6:5 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_FORBIDDEN_ZERO_BIT 7:7 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_COLOR_SPACE 0:0 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_CLAMPING_TYPE 1:1 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_SEGMENTATION_ENABLED 2:2 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_SEGMENT_FEATURE_MODE 3:3 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_FILTER_TYPE 4:4 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_LOOP_FILTER_LEVEL 10:5 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_SHARPNESS_LEVEL 13:11 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_LOG2_NBR_OF_DCT_PARTITIONS 15:14 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_REFRESH_GOLDEN_FRAME 16:16 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_REFRESH_ALTERNATE_FRAME 17:17 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_COPY_BUFFER_TO_GOLDEN 19:18 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_COPY_BUFFER_TO_ALTERNATE 21:20 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_SIGN_BIAS_GOLDEN 22:22 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_SIGN_BIAS_ALTERNATE 23:23 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_REFRESH_ENTROPY_PROB 24:24 /* R-XUF */ #define NV_PNVDEC_VLD_RESULT_REFRESH_LAST 25:25 /* R-XUF */ #define NV_PNVDEC_VLD_INTRPT_EN(dev) (0x00848448+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_INTRPT_EN__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_INTRPT_EN_WATCHDOG_TIMER_EN 0:0 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_EN_BUFF_EMPTY_EN 1:1 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_EN_BIT_ERROR_EN 2:2 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_EN_LIMIT_EN 3:3 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_EN_SLICE_DONE_EN 4:4 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_STATUS(dev) (0x0084844c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_INTRPT_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_INTRPT_STATUS_WATCHDOG_TIMER 0:0 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_STATUS_BUFF_EMPTY 1:1 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_STATUS_BIT_ERROR 2:2 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_STATUS_LIMIT 3:3 /* RWXUF */ #define NV_PNVDEC_VLD_INTRPT_STATUS_SLICE_DONE 4:4 /* RWXUF */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE(dev) (0x00848450+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE 31:0 /* RWXUF */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_NONE 0x00000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_SYNCMARKER 0x00000001 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_CBPCY 0x00000002 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTRA_DCCOEF 0x00000004 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ACCOEF1 0x00000008 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_RLL 0x00000010 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ACCOEF2 0x00000020 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_D_LEVEL 0x00000040 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_D_RUN 0x00000080 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ESCLVLSZ 0x00000100 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTRA_INVALID_IDX 0x00000200 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_TTBLK 0x00000400 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_SUBBLKPAT 0x00000800 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_SUBBLKPAT_8X4_4X8 0x00001000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_MVDATA 0x00002000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_INVALID_IDX 0x00004000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_INSUF_BP_BUF 0x00008000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_SLICE_END_MBADDR 0x00010000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_TTMB 0x00020000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_INV_INTRAFLAG_BMV2 0x00040000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_MBMODE 0x00080000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_TWOMVBP 0x00100000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_FOURMVBP 0x00200000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_MVDATA_PF1R 0x00400000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_MVDATA_PF2R 0x00800000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_MIXEDMV 0x01000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_ONEMV 0x02000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_BP_IMODE6_TABLE81 0x04000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MP4_MB_VIDEOPACKETHEADER 0x08000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MP4_MB_MCBPC 0x00020000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MP4_MB_MODBMBTYPE 0x00040000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MP4_MB_MCBPY 0x00080000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_SLICE_END 0x00000001 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_ADDR_INC 0x00000002 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MB_TYPE 0x00000004 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MT_TYPE 0x00000008 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MVX_GET 0x00000010 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MVY_GET 0x00000020 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_CBP_GET 0x00000040 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_QFS_GET 0x00000080 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MARKER_BIT 0x00000100 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_NB_PARAM 0x00000200 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_SKIP_MBS 0x00000400 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_SLICE_END_AT_SMALLER_MB_ADDR 0x00000001 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_SKIP_RUN 0x00000002 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_I_SLICE 0x00000004 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_P_SLICE 0x00000008 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_B_SLICE 0x00000010 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_SI_SLICE 0x00000020 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_SP_SLICE 0x00000040 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_QP_DELTA_OUT_OF_RANGE 0x00000080 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_RESIDUAL_COEFF_COUNT 0x00000100 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_TYPE 0x00000200 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_MB_REF_IDX_L0 0x00000400 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_MB_REF_IDX_L1 0x00000800 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_REF_IDX_L0 0x00001000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_REF_IDX_L1 0x00002000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN0 0x00004000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN1 0x00008000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN2 0x00010000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN3 0x00020000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOTAL_ZEROS 0x00040000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_RUN_BEFORE 0x00080000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_FIXED_PTRN_BIT_STRING 0x00100000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_CODED_BLOCK_PATTERN 0x00200000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_LARGE_LUMA_LOG_WD 0x00400000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_LARGE_CHR_LOG_WD 0x00800000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_LUMA_WEIGHT 0x01000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_LUMA_OFFSET 0x02000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_CHROMA_WEIGHT 0x04000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_CHROMA_OFFSET 0x08000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_EXCEED_SLICE_OFFSET_LIMIT 0x10000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_MB_DATA_EXCEED_EDOB_FIFO_LIMIT 0x20000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_UNCLASSIFIED 0x40000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_CODE_SW_ERROR 0x80000000 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_VP8 31:0 /* RWXUF */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_VP8_BUFF2GOLD 0x00000001 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_VP8_BUFF2ALT 0x00000002 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_VP8_INVALID_TOKEN 0x00000004 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_VP8_EXCEED_TOKEN_LIMIT 0x00000008 /* RWX-V */ #define NV_PNVDEC_VLD_BIT_ERROR_CODE_VP8_ZERO_NO_EOB 0x00000010 /* RWX-V */ #define NV_PNVDEC_VLD_SCP_CFG(dev) (0x00848454+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_SCP_CFG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_SCP_CFG_PARSE_CMD_MODE 16:16 /* R-IUF */ #define NV_PNVDEC_VLD_SCP_CFG_PARSE_CMD_MODE_INSECURE 0x0 /* R-I-V */ #define NV_PNVDEC_VLD_SCP_CFG_PARSE_CMD_MODE_SECURE 0x1 /* R---V */ #define NV_PNVDEC_VLD_TIMEOUT_VALUE(dev) (0x00848458+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_TIMEOUT_VALUE__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_TIMEOUT_VALUE_MB_DECODE_TIMEOUT 31:0 /* RWXUF */ #define NV_PNVDEC_VLD_RESET_CTL(dev) (0x0084845c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_RESET_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_RESET_CTL_SOFT_RESET 0:0 /* -WXUF */ #define NV_PNVDEC_VLD_RESET_CTL_HARD_RESET 1:1 /* -WXUF */ #define NV_PNVDEC_VLD_RESET_CTL_SLICE_RESET 2:2 /* -WXUF */ #define NV_PNVDEC_VLD_IDMA_BUFF_A(dev,i) (0x00848460+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_VLD_IDMA_BUFF_A__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_IDMA_BUFF_A__SIZE_2 4 /* */ #define NV_PNVDEC_VLD_IDMA_BUFF_A_COUNT 23:0 /* RWXUF */ #define NV_PNVDEC_VLD_IDMA_BUFF_A_ADDR_HIGH 31:24 /* RWXUF */ #define NV_PNVDEC_VLD_IDMA_BUFF_B(dev,i) (0x00848464+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_VLD_IDMA_BUFF_B__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_IDMA_BUFF_B__SIZE_2 4 /* */ #define NV_PNVDEC_VLD_IDMA_BUFF_B_VALID 0:0 /* RWXUF */ #define NV_PNVDEC_VLD_IDMA_BUFF_B_ENCRYPT 1:1 /* RWXUF */ #define NV_PNVDEC_VLD_IDMA_BUFF_B_ADDR_LOW 31:2 /* RWXUF */ #define NV_PNVDEC_VLD_CURR_IDMA_INFO(dev) (0x008484a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_CURR_IDMA_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_CURR_IDMA_INFO_CURR_IDMA_BIT_INDEX 2:0 /* RWXUF */ #define NV_PNVDEC_VLD_CURR_IDMA_INFO_CURR_IDMA_BUFF_OFFSET 26:3 /* RWXUF */ #define NV_PNVDEC_VLD_CURR_IDMA_INFO_CURR_IDMA_BUFF_INDEX 28:27 /* RWXUF */ #define NV_PNVDEC_VLD_CLEAR_INPUT_BUFFERS(dev) (0x008484a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_CLEAR_INPUT_BUFFERS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS 0:0 /* RWXUF */ #define NV_PNVDEC_VLD_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS_DONE 0x0 /* RW--V */ #define NV_PNVDEC_VLD_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS_FLUSH 0x1 /* RW--V */ #define NV_PNVDEC_VLD_CLEAR_INPUT_BUFFERS_BUFF_ID 2:1 /* RWIUF */ #define NV_PNVDEC_VLD_CLEAR_INPUT_BUFFERS_BUFF_ID_DEFAULT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD_HIST_START_ADDR(dev) (0x008484c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_HIST_START_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_HIST_START_ADDR_START_ADDR_HIGH 31:0 /* RWXUF */ #define NV_PNVDEC_VLD_HIST_SIZE(dev) (0x008484cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_HIST_SIZE__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_HIST_SIZE_SIZE 11:0 /* RWXUF */ #define NV_PNVDEC_VLD_HIST_CTL(dev) (0x008484d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_HIST_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_HIST_CTL_ENABLE 0:0 /* RWXUF */ #define NV_PNVDEC_VLD_HIST_CTL_ENABLE_DIS 0x0 /* RW--V */ #define NV_PNVDEC_VLD_HIST_CTL_ENABLE_EN 0x1 /* RW--V */ #define NV_PNVDEC_VLD_HIST_CTL_LINEBUF_ENABLE 1:1 /* RWXUF */ #define NV_PNVDEC_VLD_HIST_CTL_LINEBUF_ENABLE_DIS 0x0 /* RW--V */ #define NV_PNVDEC_VLD_HIST_CTL_LINEBUF_ENABLE_EN 0x1 /* RW--V */ #define NV_PNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP(dev) (0x008484d4+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_OFFSET 11:0 /* -WXUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_RW 12:12 /* -WXUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA(dev) (0x008484d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_RESULT_DATA 31:0 /* RWXUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG(dev) (0x008484dc+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_MEMACC_ST 2:0 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_FIFOCTRL_ST 5:3 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_MEMACC_REQ0_OUTSTANDING 6:6 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_MEMACC_REQ1_OUTSTANDING 7:7 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_MEMACC_SCP_PKTS_PEND 12:8 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_MB_STATE 17:13 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_RES_BLK_TYPE 20:18 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_CBC_VRAM_PS 24:21 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_DEBUG_CAVLD_STATE 28:25 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0(dev) (0x008484e0+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MB_STATE 7:0 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_CBPCY_STATE 9:8 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MVD_STATE 13:12 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MVDPF1R_STATE 17:16 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MVDPF2R_STATE 21:20 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MVP_STATE 27:24 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_ACP_STATE 29:28 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1(dev) (0x008484e4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_INTRA_STATE 2:0 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_INTER_STATE 6:4 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_VLCAC_STATE 11:8 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_OUTIF_STATE 15:12 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_BP_STATE 18:16 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_BP_RD_STATE 21:20 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPG_DEBUG(dev) (0x008484e8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPG_DEBUG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPG_DEBUG_MB_STATE 3:0 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPG_DEBUG_MBI_STATE 5:4 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPG_DEBUG_QFS_STATE 8:6 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPG_DEBUG_OUTIF_STATE 12:9 /* R-XUF */ #define NV_PNVDEC_VLD_BIT_ERROR_MASK(dev) (0x008484ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_BIT_ERROR_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_BIT_ERROR_MASK_MASKFIELD 31:0 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_LIMIT(dev) (0x008484f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_SLICE_LIMIT__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_SLICE_LIMIT_SLICE_BYTE_COUNT 31:0 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_ERROR_CTL(dev) (0x008484f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_SLICE_ERROR_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_SLICE_ERROR_CTL_NEXT_SLICE_MB_ADDR 16:0 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_ERROR_CTL_SET_SW_ERROR 31:31 /* RWXUF */ #define NV_PNVDEC_VLD_SLICE_ERROR_CTL_SET_SW_ERROR_CLR 0x0 /* RWX-V */ #define NV_PNVDEC_VLD_SLICE_ERROR_CTL_SET_SW_ERROR_SET 0x1 /* RWX-V */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG(dev) (0x008484f8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG_MP4_STATE 3:0 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG_MP4IP_STATE 7:4 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG_BP_ILLEGAL_READ 8:8 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG_BP_ILLEGAL_WRITE 9:9 /* R-XUF */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY(dev,i,j) (0x008484fc+(dev)*16384+(i)*4+(j)*0) /* RW-4A */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_2 4 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_3 64 /* */ #define NV_PNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_VLD_PROBBUF_WRITE_REG(dev) (0x00848510+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PROBBUF_WRITE_REG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PROBBUF_WRITE_REG_DATA 31:0 /* -W-UF */ #define NV_PNVDEC_VLD_PROBBUF_READ_REG(dev) (0x00848514+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PROBBUF_READ_REG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PROBBUF_READ_REG_DATA 31:0 /* R--UF */ #define NV_PNVDEC_VLD_PROBBUF_RW_OFFSET(dev) (0x00848518+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_PROBBUF_RW_OFFSET__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_PROBBUF_RW_OFFSET_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_VLD_IDMA1_BUFF_A(dev,i) (0x00848520+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_VLD_IDMA1_BUFF_A__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_IDMA1_BUFF_A__SIZE_2 8 /* */ #define NV_PNVDEC_VLD_IDMA1_BUFF_A_COUNT 23:0 /* RWXUF */ #define NV_PNVDEC_VLD_IDMA1_BUFF_A_ADDR_HIGH 31:24 /* RWXUF */ #define NV_PNVDEC_VLD_IDMA1_BUFF_B(dev,i) (0x00848524+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_VLD_IDMA1_BUFF_B__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_IDMA1_BUFF_B__SIZE_2 8 /* */ #define NV_PNVDEC_VLD_IDMA1_BUFF_B_VALID 0:0 /* RWXUF */ #define NV_PNVDEC_VLD_IDMA1_BUFF_B_ENCRYPT 1:1 /* RWXUF */ #define NV_PNVDEC_VLD_IDMA1_BUFF_B_ADDR_LOW 31:2 /* RWXUF */ #define NV_PNVDEC_VLD_CURR_IDMA1_INFO(dev) (0x00848560+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_CURR_IDMA1_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_CURR_IDMA1_INFO_CURR_IDMA_BIT_INDEX 2:0 /* RWXUF */ #define NV_PNVDEC_VLD_CURR_IDMA1_INFO_CURR_IDMA_BUFF_OFFSET 26:3 /* RWXUF */ #define NV_PNVDEC_VLD_CURR_IDMA1_INFO_CURR_IDMA_BUFF_INDEX 29:27 /* RWXUF */ #define NV_PNVDEC_VLD_SEGMENT_ID_START_ADDR(dev) (0x00848564+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_SEGMENT_ID_START_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_SEGMENT_ID_START_ADDR_START_ADDR_HIGH 31:0 /* RWXUF */ #define NV_PNVDEC_VLD_STREAM_LEN(dev) (0x00848568+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD_STREAM_LEN__SIZE_1 2 /* */ #define NV_PNVDEC_VLD_STREAM_LEN_VALUE 31:0 /* RWXUF */ #define NV_PNVDEC_DBFDMA_SFC_WIDTH(dev) (0x00848784+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_SFC_WIDTH__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_SFC_WIDTH_LUMA 11:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_SFC_WIDTH_CHROMA 27:16 /* RW-VF */ #define NV_PNVDEC_DBFDMA_TOP_SFC_LUMA(dev) (0x00848790+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TOP_SFC_LUMA__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TOP_SFC_LUMA_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_TOP_SFC_CHROMA(dev) (0x00848794+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TOP_SFC_CHROMA__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TOP_SFC_CHROMA_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_BOT_SFC_LUMA(dev) (0x00848798+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_BOT_SFC_LUMA__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_BOT_SFC_LUMA_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_BOT_SFC_CHROMA(dev) (0x0084879c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_BOT_SFC_CHROMA__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_BOT_SFC_CHROMA_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_RW_CTL(dev) (0x008487a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_RW_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_RW_CTL_RD_OFFS_L 1:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_RW_CTL_RD_OFFS_C 5:4 /* RW-VF */ #define NV_PNVDEC_DBFDMA_RW_CTL_WR_OFFS_L 9:8 /* RW-VF */ #define NV_PNVDEC_DBFDMA_RW_CTL_WR_OFFS_C 13:12 /* RW-VF */ #define NV_PNVDEC_DBFDMA_RW_CTL_WR_HEIGHT_L 18:16 /* RW-VF */ #define NV_PNVDEC_DBFDMA_RW_CTL_WR_HEIGHT_C 22:20 /* RW-VF */ #define NV_PNVDEC_DBFDMA_RW_CTL_TILE_FORMAT 24:23 /* RWIVF */ #define NV_PNVDEC_DBFDMA_RW_CTL_TILE_FORMAT_TBL 0x0 /* RW--V */ #define NV_PNVDEC_DBFDMA_RW_CTL_TILE_FORMAT_KBL 0x1 /* RWI-V */ #define NV_PNVDEC_DBFDMA_RW_CTL_TILE_FORMAT_16X16 0x2 /* RW--V */ #define NV_PNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT 27:25 /* RWIVF */ #define NV_PNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_2 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_4 0x1 /* RW--V */ #define NV_PNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_8 0x2 /* RW--V */ #define NV_PNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_16 0x3 /* RW--V */ #define NV_PNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_32 0x4 /* RW--V */ #define NV_PNVDEC_DBFDMA_CTL(dev) (0x008487a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_CTL_FRM_WIDTH 7:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_CTL_TYPE 9:8 /* RWXVF */ #define NV_PNVDEC_DBFDMA_CTL_TYPE_FRAME 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_TYPE_FIELD_TOP 0x2 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_TYPE_FIELD_BOT 0x3 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_FRM_WRITE 10:10 /* RWXVF */ #define NV_PNVDEC_DBFDMA_CTL_FRM_WRITE_DISABLE 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_FRM_WRITE_ENABLE 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_DBL_ROWS 11:11 /* RWXVF */ #define NV_PNVDEC_DBFDMA_CTL_DBL_ROWS_DISABLE 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_DBL_ROWS_ENABLE 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_APPLE_OOLD 12:12 /* RWXVF */ #define NV_PNVDEC_DBFDMA_CTL_APPLE_OOLD_DISABLE 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_APPLE_OOLD_ENABLE 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_FLAG 13:13 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_FLAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_FLAG_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_FLAG_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPY 16:14 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_FLAG 17:17 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_FLAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_FLAG_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_FLAG_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV 20:18 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_USE_INTERNAL_BUFF 21:21 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_USE_INTERNAL_BUFF_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_TFOUTPUT 22:22 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_TFOUTPUT_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_DITHER_Y 23:23 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_DITHER_Y_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_DITHER_U 24:24 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_DITHER_U_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_DITHER_V 25:25 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_DITHER_V_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_HISTOGRAM 26:26 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_HISTOGRAM_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_4LINE 27:27 /* RWIUF */ #define NV_PNVDEC_DBFDMA_CTL_ENABLE_4LINE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_FETCH(dev) (0x008487a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_FETCH__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_FETCH_COUNTER 16:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_INTRPTEN(dev) (0x008487ac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_INTRPTEN__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_INTRPTEN_OFFSETERR 0:0 /* RWXUF */ #define NV_PNVDEC_DBFDMA_INTRPTEN_OFFSETERR_ON 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTEN_OFFSETERR_OFF 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTEN_CFGWRERR 4:4 /* RWXUF */ #define NV_PNVDEC_DBFDMA_INTRPTEN_CFGWRERR_ON 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTEN_CFGWRERR_OFF 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTEN_ROWEND 8:8 /* RWXUF */ #define NV_PNVDEC_DBFDMA_INTRPTEN_ROWEND_ON 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTEN_ROWEND_OFF 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT(dev) (0x008487b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_OFFSETERR 0:0 /* RWXUF */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_OFFSETERR_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_OFFSETERR_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_CFGWRERR 4:4 /* RWXUF */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_CFGWRERR_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_CFGWRERR_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_ROWEND 8:8 /* RWXUF */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_ROWEND_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_DBFDMA_INTRPTSTAT_ROWEND_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_DBFDMA_DBG1(dev) (0x008487b4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_DBFDMA_DBG1__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_DBG1_DBFDMA_READ_CS 1:0 /* R-XUF */ #define NV_PNVDEC_DBFDMA_DBG1_DBFDMA_WRITE_CS 5:2 /* R-XUF */ #define NV_PNVDEC_DBFDMA_DBG1_RBUF_READ_CS 8:6 /* R-XUF */ #define NV_PNVDEC_DBFDMA_DBG1_WR_IDLE_N 9:9 /* R-IUF */ #define NV_PNVDEC_DBFDMA_DBG1_WR_IDLE_N_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_DBFDMA_DBG1_RD_IDLE_N 10:10 /* R-IUF */ #define NV_PNVDEC_DBFDMA_DBG1_RD_IDLE_N_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_DBFDMA_DBG1_RD_FIFO_EMPTY 11:11 /* R-IUF */ #define NV_PNVDEC_DBFDMA_DBG1_RD_FIFO_EMPTY_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_DBFDMA_DBG1_CFG_FETCH_RD_IS_0 12:12 /* R-IUF */ #define NV_PNVDEC_DBFDMA_DBG1_CFG_FETCH_RD_IS_0_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_DBFDMA_DBG1_CFG_FETCH_RFW_IS_0 13:13 /* R-IUF */ #define NV_PNVDEC_DBFDMA_DBG1_CFG_FETCH_RFW_IS_0_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_DBFDMA_DBG1_CFG_FETCH_WR_IS_0 14:14 /* R-IUF */ #define NV_PNVDEC_DBFDMA_DBG1_CFG_FETCH_WR_IS_0_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_DBFDMA_ROW_COUNTER(dev) (0x008487b8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_DBFDMA_ROW_COUNTER__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_ROW_COUNTER_REG 11:0 /* R-XUF */ #define NV_PNVDEC_DBFDMA_MB_COUNTER(dev) (0x008487bc+(dev)*16384) /* R--4A */ #define NV_PNVDEC_DBFDMA_MB_COUNTER__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_MB_COUNTER_REG 16:0 /* R-XUF */ #define NV_PNVDEC_DBFDMA_SFC_WIDTH_FIELD_UNFILTERED(dev) (0x008487c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_SFC_WIDTH_FIELD_UNFILTERED__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_SFC_WIDTH_FIELD_UNFILTERED_LUMA 11:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_SFC_WIDTH_FIELD_UNFILTERED_CHROMA 27:16 /* RW-VF */ #define NV_PNVDEC_DBFDMA_TOP_SFC_LUMA_UNFILTERED(dev) (0x008487c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TOP_SFC_LUMA_UNFILTERED__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TOP_SFC_LUMA_UNFILTERED_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_TOP_SFC_CHROMA_UNFILTERED(dev) (0x008487c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TOP_SFC_CHROMA_UNFILTERED__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TOP_SFC_CHROMA_UNFILTERED_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_BOT_SFC_LUMA_UNFILTERED(dev) (0x008487cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_BOT_SFC_LUMA_UNFILTERED__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_BOT_SFC_LUMA_UNFILTERED_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_BOT_SFC_CHROMA_UNFILTERED(dev) (0x008487d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_BOT_SFC_CHROMA_UNFILTERED__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_BOT_SFC_CHROMA_UNFILTERED_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO(dev) (0x008487d4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_PIC_STRIDE 7:0 /* RWIUF */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_PIC_STRIDE_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE 18:16 /* RWIUF */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_1D 0x0 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_PITCH_LINEAR_2D 0x1 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_16X16 0x2 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_BLOCK_LINEAR_TEXTURE 0x3 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_NAIVE_BLOCK_LINEAR 0x4 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_RESERVED_0 0x5 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_RESERVED_1 0x6 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_RESERVED_2 0x7 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_STRUCTURE 19:19 /* RWIUF */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_STRUCTURE_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_STRUCTURE_FRAME 0x0 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_STRUCTURE_FIELD 0x1 /* RW--V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_PIC_HEIGHT 31:24 /* RWIUF */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_PIC_HEIGHT_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_LUMA_TOP_FIELD(dev) (0x008487d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_LUMA_TOP_FIELD__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_LUMA_TOP_FIELD_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_LUMA_BOTTOM_FIELD(dev) (0x008487dc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_LUMA_BOTTOM_FIELD__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_LUMA_BOTTOM_FIELD_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_CHROMA_TOP_FIELD(dev) (0x008487e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_CHROMA_TOP_FIELD__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_CHROMA_TOP_FIELD_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_CHROMA_BOTTOM_FIELD(dev) (0x008487e4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_CHROMA_BOTTOM_FIELD__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_TF_OUTPUT_CHROMA_BOTTOM_FIELD_BASE 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_START(dev) (0x008487e8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_START__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_START_X 11:0 /* RWIVF */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_START_X_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_START_Y 27:16 /* RWIVF */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_START_Y_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_END(dev) (0x008487ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_END__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_END_X 11:0 /* RWIVF */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_END_X_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_END_Y 27:16 /* RWIVF */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_WINDOW_END_Y_INIT 0x000 /* RWI-V */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_RESULT(dev) (0x008487f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_RESULT__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_RESULT_REG 23:0 /* RWIVF */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_RESULT_REG_INIT 0x000000 /* RWI-V */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_RESULT_OFFSET(dev) (0x008487f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_RESULT_OFFSET__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_RESULT_OFFSET_REG 7:0 /* RWIVF */ #define NV_PNVDEC_DBFDMA_HISTOGRAM_RESULT_OFFSET_REG_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_DBFDMA_DITHER_MATRIX_WRITE_DATA(dev) (0x008487f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_DITHER_MATRIX_WRITE_DATA__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_DITHER_MATRIX_WRITE_DATA_REG 31:0 /* RW-VF */ #define NV_PNVDEC_DBFDMA_DITHER_MATRIX_WRITE_OFFSET(dev) (0x008487fc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBFDMA_DITHER_MATRIX_WRITE_OFFSET__SIZE_1 2 /* */ #define NV_PNVDEC_DBFDMA_DITHER_MATRIX_WRITE_OFFSET_REG 31:0 /* RWIVF */ #define NV_PNVDEC_DBFDMA_DITHER_MATRIX_WRITE_OFFSET_REG_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_HIST_CFG(dev) (0x00848740+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_HIST_CFG__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_CFG_CODEC 2:0 /* RWXVF */ #define NV_PNVDEC_HIST_CFG_CODEC_MPEG1 0x0 /* RWX-V */ #define NV_PNVDEC_HIST_CFG_CODEC_MPEG2 0x1 /* RWX-V */ #define NV_PNVDEC_HIST_CFG_CODEC_VC1 0x2 /* RWX-V */ #define NV_PNVDEC_HIST_CFG_CODEC_H264 0x3 /* RWX-V */ #define NV_PNVDEC_HIST_CFG_CODEC_MPEG4 0x4 /* RWX-V */ #define NV_PNVDEC_HIST_CFG_CODEC_VP8 0x5 /* RWX-V */ #define NV_PNVDEC_HIST_CFG_MBAFF 3:3 /* RW-VF */ #define NV_PNVDEC_HIST_CFG_MVDEL 4:4 /* RW-VF */ #define NV_PNVDEC_HIST_CFG_IQTDEL 5:5 /* RW-VF */ #define NV_PNVDEC_HIST_CFG_RECDEL 6:6 /* RW-VF */ #define NV_PNVDEC_HIST_CFG_DBFDEL 7:7 /* RW-VF */ #define NV_PNVDEC_HIST_CFG_DXVA 8:8 /* RW-VF */ #define NV_PNVDEC_HIST_CFG_PICWIDTHINMBS 23:16 /* RW-VF */ #define NV_PNVDEC_HIST_CFG_PICHEIGHTINMBS 31:24 /* RW-VF */ #define NV_PNVDEC_HIST_CTL(dev) (0x00848744+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_HIST_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_CTL_ENABLE 0:0 /* RWIVF */ #define NV_PNVDEC_HIST_CTL_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_HIST_CTL_RST_HISTW 1:1 /* RWIVF */ #define NV_PNVDEC_HIST_CTL_RST_HISTW_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_HIST_CTL_RST_HISTR 2:2 /* RWIVF */ #define NV_PNVDEC_HIST_CTL_RST_HISTR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_HIST_CTL_DBF_DISABLE 3:3 /* RWIVF */ #define NV_PNVDEC_HIST_CTL_DBF_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_HIST_CTL_LINEBUF_ENABLE 4:4 /* RWXUF */ #define NV_PNVDEC_HIST_CTL_LINEBUF_ENABLE_DIS 0x0 /* RW--V */ #define NV_PNVDEC_HIST_CTL_LINEBUF_ENABLE_EN 0x1 /* RW--V */ #define NV_PNVDEC_HIST_BUF_START(dev) (0x00848748+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_HIST_BUF_START__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_BUF_START_ADDR 31:0 /* RWXVF */ #define NV_PNVDEC_HIST_BUF_SIZE(dev) (0x0084874c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_HIST_BUF_SIZE__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_BUF_SIZE_SIZE 15:0 /* RWXVF */ #define NV_PNVDEC_HIST_DBG0(dev) (0x00848750+(dev)*16384) /* R--4A */ #define NV_PNVDEC_HIST_DBG0__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_DBG0_MV_RD_STATE 3:0 /* R-XVF */ #define NV_PNVDEC_HIST_DBG0_MV_RD_HWVLD 4:4 /* R-XVF */ #define NV_PNVDEC_HIST_DBG0_MV_RD_HOVLD 5:5 /* R-XVF */ #define NV_PNVDEC_HIST_DBG0_MV_RD_RDREQ 6:6 /* R-XVF */ #define NV_PNVDEC_HIST_DBG0_MV_RD_LDREQ 7:7 /* R-XVF */ #define NV_PNVDEC_HIST_DBG0_MV_RD_RECCNT 11:8 /* R-XVF */ #define NV_PNVDEC_HIST_DBG0_MV_RD_REQCNT 15:12 /* R-XVF */ #define NV_PNVDEC_HIST_DBG0_MV_RD_COLCNT 23:16 /* R-XVF */ #define NV_PNVDEC_HIST_DBG0_MV_RD_ROWCNT 31:24 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1(dev) (0x00848754+(dev)*16384) /* R--4A */ #define NV_PNVDEC_HIST_DBG1__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_STATE 3:0 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_HWVLD 4:4 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_HOVLD 5:5 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_RDREQ 6:6 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_LDREQ 7:7 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_RECCNT 11:8 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_REQCNT 15:12 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_COLCNT 23:16 /* R-XVF */ #define NV_PNVDEC_HIST_DBG1_IQT_RD_ROWCNT 31:24 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2(dev) (0x00848758+(dev)*16384) /* R--4A */ #define NV_PNVDEC_HIST_DBG2__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_DBG2_REC_RD_STATE 3:0 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2_REC_RD_HWVLD 4:4 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2_REC_RD_HOVLD 5:5 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2_REC_RD_RDREQ 6:6 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2_REC_RD_LDREQ 7:7 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2_REC_RD_RECCNT 11:8 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2_REC_RD_REQCNT 15:12 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2_REC_RD_COLCNT 23:16 /* R-XVF */ #define NV_PNVDEC_HIST_DBG2_REC_RD_ROWCNT 31:24 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3(dev) (0x0084875c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_HIST_DBG3__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_STATE 3:0 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_HWVLD 4:4 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_HOVLD 5:5 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_RDREQ 6:6 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_LDREQ 7:7 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_DBFCNT 11:8 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_REQCNT 15:12 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_COLCNT 23:16 /* R-XVF */ #define NV_PNVDEC_HIST_DBG3_DBF_RD_ROWCNT 31:24 /* R-XVF */ #define NV_PNVDEC_HIST_DBG4(dev) (0x00848760+(dev)*16384) /* R--4A */ #define NV_PNVDEC_HIST_DBG4__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_DBG4_MV_WR_STATE 3:0 /* R-XVF */ #define NV_PNVDEC_HIST_DBG4_MV_WR_HIVLD 6:6 /* R-XVF */ #define NV_PNVDEC_HIST_DBG4_MV_WR_HOVLD 7:7 /* R-XVF */ #define NV_PNVDEC_HIST_DBG4_MV_WR_RECCNT 11:8 /* R-XVF */ #define NV_PNVDEC_HIST_DBG4_IQT_WR_STATE 19:16 /* R-XVF */ #define NV_PNVDEC_HIST_DBG4_IQT_WR_HIVLD 22:22 /* R-XVF */ #define NV_PNVDEC_HIST_DBG4_IQT_WR_HOVLD 23:23 /* R-XVF */ #define NV_PNVDEC_HIST_DBG4_IQT_WR_RECCNT 27:24 /* R-XVF */ #define NV_PNVDEC_HIST_DBG5(dev) (0x00848764+(dev)*16384) /* R--4A */ #define NV_PNVDEC_HIST_DBG5__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_DBG5_REC_WR_STATE 3:0 /* R-XVF */ #define NV_PNVDEC_HIST_DBG5_REC_WR_HIVLD 6:6 /* R-XVF */ #define NV_PNVDEC_HIST_DBG5_REC_WR_HOVLD 7:7 /* R-XVF */ #define NV_PNVDEC_HIST_DBG5_REC_WR_RECCNT 11:8 /* R-XVF */ #define NV_PNVDEC_HIST_DBG5_DBF_WR_STATE 19:16 /* R-XVF */ #define NV_PNVDEC_HIST_DBG5_DBF_WR_HIVLD 22:22 /* R-XVF */ #define NV_PNVDEC_HIST_DBG5_DBF_WR_HOVLD 23:23 /* R-XVF */ #define NV_PNVDEC_HIST_DBG5_DBF_WR_RECCNT 27:24 /* R-XVF */ #define NV_PNVDEC_HIST_DBG6(dev) (0x00848768+(dev)*16384) /* R--4A */ #define NV_PNVDEC_HIST_DBG6__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_DBG6_RXFER_FBCNT 9:0 /* R-XVF */ #define NV_PNVDEC_HIST_DBG6_RXFER_PICDONE 10:10 /* R-XVF */ #define NV_PNVDEC_HIST_DBG6_RXFER_HISTR_IDLE 11:11 /* R-XVF */ #define NV_PNVDEC_HIST_DBG6_RXFER_STARTREQ 12:12 /* R-XVF */ #define NV_PNVDEC_HIST_DBG6_RXFER_RCOUNT 15:13 /* R-XVF */ #define NV_PNVDEC_HIST_DBG6_RXFER_COLCNT 23:16 /* R-XVF */ #define NV_PNVDEC_HIST_DBG6_RXFER_ROWCNT 31:24 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7(dev) (0x0084876c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_HIST_DBG7__SIZE_1 2 /* */ #define NV_PNVDEC_HIST_DBG7_WXFER_STATE 1:0 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7_WXFER_HISTAV 2:2 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7_WXFER_MEMVLD 3:3 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7_WXFER_OVLD 4:4 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7_WXFER_ACKCNT 7:5 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7_WXFER_HISTW_IDLE 8:8 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7_WXFER_FBREC 11:9 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7_WXFER_MEMOFFS 15:12 /* R-XVF */ #define NV_PNVDEC_HIST_DBG7_WXFER_FBOFFS 31:16 /* R-XVF */ #define NV_PNVDEC_IQTINTRPTEN(dev) (0x00848a80+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTINTRPTEN__SIZE_1 2 /* */ #define NV_PNVDEC_IQTINTRPTEN_IQCOEFERR 0:0 /* RWXUF */ #define NV_PNVDEC_IQTINTRPTEN_IQCOEFERR_OFF 0x0 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTEN_IQCOEFERR_ON 0x1 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTEN_IQIDXERR 4:4 /* RWXUF */ #define NV_PNVDEC_IQTINTRPTEN_IQIDXERR_OFF 0x0 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTEN_IQIDXERR_ON 0x1 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTEN_CFGWRERR 8:8 /* RWXUF */ #define NV_PNVDEC_IQTINTRPTEN_CFGWRERR_OFF 0x0 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTEN_CFGWRERR_ON 0x1 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTSTAT(dev) (0x00848a84+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTINTRPTSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_IQTINTRPTSTAT_IQCOEFERR 0:0 /* RWXUF */ #define NV_PNVDEC_IQTINTRPTSTAT_IQCOEFERR_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTSTAT_IQCOEFERR_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTSTAT_IQIDXERR 4:4 /* RWXUF */ #define NV_PNVDEC_IQTINTRPTSTAT_IQIDXERR_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTSTAT_IQIDXERR_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTSTAT_CFGWRERR 8:8 /* RWXUF */ #define NV_PNVDEC_IQTINTRPTSTAT_CFGWRERR_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_IQTINTRPTSTAT_CFGWRERR_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_IQTDBG1(dev) (0x00848a88+(dev)*16384) /* R--4A */ #define NV_PNVDEC_IQTDBG1__SIZE_1 2 /* */ #define NV_PNVDEC_IQTDBG1_HISTIF_PRED_BUFA_CS 2:0 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_HISTIF_PRED_BUFB_CS 5:3 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_IQUANT_IQUANT_CS 8:6 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_IQT_READ_CS 11:9 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX 14:12 /* R-IUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_0 0x0 /* R---V */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_1 0x1 /* R---V */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_2 0x2 /* R---V */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_3 0x3 /* R---V */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_4 0x4 /* R---V */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_5 0x5 /* R-I-V */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_6 0x6 /* R---V */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_7 0x7 /* R---V */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_INTRA 15:15 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_MODE 18:16 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_BLK_SHAPE 20:19 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_MB_ACPRED 21:21 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_MB_FIELD 22:22 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_MB_LEFTEDGE 23:23 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_MB_TOPEDGE 24:24 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_MB_PCM 25:25 /* R-XUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_MB_QUANTY 31:26 /* R-IUF */ #define NV_PNVDEC_IQTDBG1_READ_MV2IQT_MB_QUANTY_INIT 0x3f /* R-I-V */ #define NV_PNVDEC_IQTDBG2(dev) (0x00848a8c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_IQTDBG2__SIZE_1 2 /* */ #define NV_PNVDEC_IQTDBG2_READ_MV2IQT_MB_QUANTCB 5:0 /* R-IUF */ #define NV_PNVDEC_IQTDBG2_READ_MV2IQT_MB_QUANTCB_INIT 0x3f /* R-I-V */ #define NV_PNVDEC_IQTDBG2_READ_MV2IQT_MB_QUANTCR 11:6 /* R-IUF */ #define NV_PNVDEC_IQTDBG2_READ_MV2IQT_MB_QUANTCR_INIT 0x3f /* R-I-V */ #define NV_PNVDEC_IQTDBG2_IT_SEQ_STATE 15:12 /* R-XUF */ #define NV_PNVDEC_IQTDBG2_IT_ENG_STATE 19:16 /* R-XUF */ #define NV_PNVDEC_IQTDBG2_IT_OUT_STATE 22:20 /* R-XUF */ #define NV_PNVDEC_IQTDBG2_IQ2IT_BLK_SHAPE 24:23 /* R-XUF */ #define NV_PNVDEC_IQTDBG2_IQ2IT_BLK_IDX 27:25 /* R-XUF */ #define NV_PNVDEC_IQTDBG2_IQ2IT_INTRA 28:28 /* R-XUF */ #define NV_PNVDEC_IQTDBG2_ST_HISTIF_A_IDLE 29:29 /* R-IUF */ #define NV_PNVDEC_IQTDBG2_ST_HISTIF_A_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_IQTDBG2_ST_HISTIF_B_IDLE 30:30 /* R-IUF */ #define NV_PNVDEC_IQTDBG2_ST_HISTIF_B_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_IQTDBG3(dev) (0x00848a90+(dev)*16384) /* R--4A */ #define NV_PNVDEC_IQTDBG3__SIZE_1 2 /* */ #define NV_PNVDEC_IQTDBG3_SVC_RD_CS 1:0 /* R-XUF */ #define NV_PNVDEC_IQTDBG3_SVC_DMA_DECOMPRESS_CS 6:2 /* R-XUF */ #define NV_PNVDEC_IQTDBG3_SVC_DMA_WR_HDR_CS 8:7 /* R-XUF */ #define NV_PNVDEC_IQTDBG3_SVC_PKG_OUT_CS 11:9 /* R-XUF */ #define NV_PNVDEC_IQTDBG3_SVC_TOFBIF_CS 14:12 /* R-XUF */ #define NV_PNVDEC_IQTDBG3_SVC_PCM_WR_CS 16:15 /* R-XUF */ #define NV_PNVDEC_IQTDBG3_SVC_RD 17:17 /* R-XUF */ #define NV_PNVDEC_IQTDBG3_SVC_RD_FALSE 0x0 /* R---V */ #define NV_PNVDEC_IQTDBG3_SVC_RD_TRUE 0x1 /* R---V */ #define NV_PNVDEC_IQTDBG3_SVC_WR 18:18 /* R-XUF */ #define NV_PNVDEC_IQTDBG3_SVC_WR_FALSE 0x0 /* R---V */ #define NV_PNVDEC_IQTDBG3_SVC_WR_TRUE 0x1 /* R---V */ #define NV_PNVDEC_IQTTYPE(dev) (0x00848a94+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTTYPE__SIZE_1 2 /* */ #define NV_PNVDEC_IQTTYPE_CODEC 2:0 /* RWIVF */ #define NV_PNVDEC_IQTTYPE_CODEC_MPEG1 0x0 /* RWI-V */ #define NV_PNVDEC_IQTTYPE_CODEC_MPEG2 0x1 /* RW--V */ #define NV_PNVDEC_IQTTYPE_CODEC_VC1 0x2 /* RW--V */ #define NV_PNVDEC_IQTTYPE_CODEC_H264 0x3 /* RW--V */ #define NV_PNVDEC_IQTTYPE_CODEC_MPEG4 0x4 /* RW--V */ #define NV_PNVDEC_IQTTYPE_CODEC_VP8 0x5 /* RW--V */ #define NV_PNVDEC_IQTTYPE_DXVA 5:4 /* RWIVF */ #define NV_PNVDEC_IQTTYPE_DXVA_VLD 0x0 /* RWI-V */ #define NV_PNVDEC_IQTTYPE_DXVA_IDCT 0x1 /* RW--V */ #define NV_PNVDEC_IQTTYPE_DXVA_MOCO 0x2 /* RW--V */ #define NV_PNVDEC_IQTTYPE_DXVA_IDCT_ISC 0x3 /* RW--V */ #define NV_PNVDEC_IQTTYPE_ZCOEFF 8:8 /* RWIVF */ #define NV_PNVDEC_IQTTYPE_ZCOEFF_ENABLE 0x0 /* RWI-V */ #define NV_PNVDEC_IQTTYPE_ZCOEFF_DISABLE 0x1 /* RW--V */ #define NV_PNVDEC_IQTTYPE_LOSSLESS 9:9 /* RWIVF */ #define NV_PNVDEC_IQTTYPE_LOSSLESS_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_IQTTYPE_LOSSLESS_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_IQTTYPE_LOSSLESS_ZERO_CHROMA_CYA 10:10 /* RWIVF */ #define NV_PNVDEC_IQTTYPE_LOSSLESS_ZERO_CHROMA_CYA_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_IQTTYPE_LOSSLESS_ZERO_CHROMA_CYA_ON 0x1 /* RW--V */ #define NV_PNVDEC_IQTTYPE_DIVX 31:31 /* RWIVF */ #define NV_PNVDEC_IQTTYPE_DIVX_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_IQTTYPE_DIVX_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_IQTMP2(dev) (0x00848a98+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTMP2__SIZE_1 2 /* */ #define NV_PNVDEC_IQTMP2_QSCALE_TYPE 0:0 /* RWXUF */ #define NV_PNVDEC_IQTMP2_QSCALE_TYPE_LINEAR 0x0 /* RWX-V */ #define NV_PNVDEC_IQTMP2_QSCALE_TYPE_NON_LINEAR 0x1 /* RWX-V */ #define NV_PNVDEC_IQTMP2_ALTERNATE_SCAN 1:1 /* RWXUF */ #define NV_PNVDEC_IQTMP2_ALTERNATE_SCAN_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_IQTMP2_ALTERNATE_SCAN_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_IQTMP2_INTRA_DC_PRECISION 3:2 /* RWXUF */ #define NV_PNVDEC_IQTMP2_INTRA_DC_PRECISION_0 0x0 /* RWX-V */ #define NV_PNVDEC_IQTMP2_INTRA_DC_PRECISION_1 0x1 /* RWX-V */ #define NV_PNVDEC_IQTMP2_INTRA_DC_PRECISION_2 0x2 /* RWX-V */ #define NV_PNVDEC_IQTMP2_INTRA_DC_PRECISION_3 0x3 /* RWX-V */ #define NV_PNVDEC_IQTVC1(dev) (0x00848a9c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTVC1__SIZE_1 2 /* */ #define NV_PNVDEC_IQTVC1_NON_UNIFORM_Q 0:0 /* RWXUF */ #define NV_PNVDEC_IQTVC1_NON_UNIFORM_Q_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_IQTVC1_NON_UNIFORM_Q_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_IQTVC1_ADVANCED_PROFILE 1:1 /* RWXUF */ #define NV_PNVDEC_IQTVC1_ADVANCED_PROFILE_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_IQTVC1_ADVANCED_PROFILE_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_IQTVC1_FRAME_CODING_MODE 3:2 /* RWXUF */ #define NV_PNVDEC_IQTVC1_FRAME_CODING_MODE_PROG 0x0 /* RWX-V */ #define NV_PNVDEC_IQTVC1_FRAME_CODING_MODE_FRAME_INTL 0x2 /* RWX-V */ #define NV_PNVDEC_IQTVC1_FRAME_CODING_MODE_FIELD_INTL 0x3 /* RWX-V */ #define NV_PNVDEC_IQTVC1_IPICTURE 4:4 /* RWXUF */ #define NV_PNVDEC_IQTVC1_IPICTURE_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_IQTVC1_IPICTURE_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_IQTVC1_BIAS 5:5 /* RWXUF */ #define NV_PNVDEC_IQTVC1_BIAS_FALSE 0x0 /* RWX-V */ #define NV_PNVDEC_IQTVC1_BIAS_TRUE 0x1 /* RWX-V */ #define NV_PNVDEC_IQTVC1_PRED_DC_DEFAULT 27:16 /* RWXUF */ #define NV_PNVDEC_IQTQMEM(dev) (0x00848aa0+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_IQTQMEM__SIZE_1 2 /* */ #define NV_PNVDEC_IQTQMEM_DATA 31:0 /* -WXUF */ #define NV_PNVDEC_IQTQMEMCTRL(dev) (0x00848aa4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTQMEMCTRL__SIZE_1 2 /* */ #define NV_PNVDEC_IQTQMEMCTRL_MSEL 0:0 /* RWIUF */ #define NV_PNVDEC_IQTDCTCTRL(dev) (0x00848aa8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTDCTCTRL__SIZE_1 2 /* */ #define NV_PNVDEC_IQTDCTCTRL_MICROCODE_MSEL 0:0 /* RWIUF */ #define NV_PNVDEC_IQTDCTCTRL_MICROCODE_MSEL_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_IQTDCTCTRL_MICROCODE_MSEL_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_IQTDCTCTRL_REGCFG 4:4 /* RWIUF */ #define NV_PNVDEC_IQTDCTCTRL_REGCFG_WAIT 0x0 /* RWI-V */ #define NV_PNVDEC_IQTDCTCTRL_REGCFG_DONE 0x1 /* RW--V */ #define NV_PNVDEC_IQTDMA(dev) (0x00848aac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTDMA__SIZE_1 2 /* */ #define NV_PNVDEC_IQTDMA_WIDTHM1 7:0 /* RWIUF */ #define NV_PNVDEC_IQTDMA_WIDTHM1_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_IQTDMA_ENABLE 31:31 /* RWIUF */ #define NV_PNVDEC_IQTDMA_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_IQTRDOFFS(dev) (0x00848ab0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTRDOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_IQTRDOFFS_ADDR 31:0 /* RWIUF */ #define NV_PNVDEC_IQTRDOFFS_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_IQTRDCNT(dev) (0x00848ab4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTRDCNT__SIZE_1 2 /* */ #define NV_PNVDEC_IQTRDCNT_DATA 31:0 /* RWIUF */ #define NV_PNVDEC_IQTRDCNT_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_IQTWROFFS(dev) (0x00848ab8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTWROFFS__SIZE_1 2 /* */ #define NV_PNVDEC_IQTWROFFS_ADDR 31:0 /* RWIUF */ #define NV_PNVDEC_IQTWROFFS_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_IQTWRCNT(dev) (0x00848abc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTWRCNT__SIZE_1 2 /* */ #define NV_PNVDEC_IQTWRCNT_DATA 31:0 /* R-IUF */ #define NV_PNVDEC_IQTWRCNT_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PNVDEC_IQTRDCROP(dev) (0x00848ac0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTRDCROP__SIZE_1 2 /* */ #define NV_PNVDEC_IQTRDCROP_LEFT 7:0 /* RWIUF */ #define NV_PNVDEC_IQTRDCROP_LEFT_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_IQTRDCROP_TOP 15:8 /* RWIUF */ #define NV_PNVDEC_IQTRDCROP_TOP_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_IQTRDCROP_RIGHT 23:16 /* RWIUF */ #define NV_PNVDEC_IQTRDCROP_RIGHT_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_IQTRDCROP_BOTTOM 31:24 /* RWIUF */ #define NV_PNVDEC_IQTRDCROP_BOTTOM_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_IQTWRCROP(dev) (0x00848ac4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_IQTWRCROP__SIZE_1 2 /* */ #define NV_PNVDEC_IQTWRCROP_LEFT 7:0 /* RWIUF */ #define NV_PNVDEC_IQTWRCROP_LEFT_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_IQTWRCROP_TOP 15:8 /* RWIUF */ #define NV_PNVDEC_IQTWRCROP_TOP_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_IQTWRCROP_RIGHT 23:16 /* RWIUF */ #define NV_PNVDEC_IQTWRCROP_RIGHT_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_IQTWRCROP_BOTTOM 31:24 /* RWIUF */ #define NV_PNVDEC_IQTWRCROP_BOTTOM_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL(dev) (0x00848700+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCFETCH_MCFCTL__SIZE_1 2 /* */ #define NV_PNVDEC_MCFETCH_MCFCTL_FRAMEREAD 0:0 /* RW-VF */ #define NV_PNVDEC_MCFETCH_MCFCTL_FETCH16X2 4:4 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_FETCH16X2_ON 0x0 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL_FETCH16X2_OFF 0x1 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_TILE_FORMAT 6:5 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_TILE_FORMAT_TBL 0x0 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_TILE_FORMAT_KBL 0x1 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL_TILE_FORMAT_16X16 0x2 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_MCC_INVALID 7:7 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_MCC_INVALID_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_MCC_INVALID_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL_ECO_1249580_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_ECO_1249580_DIS_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_ECO_1249580_DIS_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GIP 9:9 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_GIP_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GIP_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GT_MAIN8 10:10 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_GT_MAIN8_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GT_MAIN8_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT 13:11 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_2 0x0 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_4 0x1 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_8 0x2 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_16 0x3 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_32 0x4 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_CHROMA_FORMAT 15:14 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_CHROMA_FORMAT_420 0x0 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_CHROMA_FORMAT_444 0x1 /* RWI-V */ #define NV_PNVDEC_MCFETCH_MCFCTL_ECDMA 16:16 /* RWIVF */ #define NV_PNVDEC_MCFETCH_MCFCTL_ECDMA_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_MCFETCH_MCFCTL_ECDMA_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_MCFETCH_FRMSFCW(dev) (0x00848704+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCFETCH_FRMSFCW__SIZE_1 2 /* */ #define NV_PNVDEC_MCFETCH_FRMSFCW_LUMA 11:0 /* RW-VF */ #define NV_PNVDEC_MCFETCH_FRMSFCW_CHROMA 27:16 /* RW-VF */ #define NV_PNVDEC_MCFETCH_FLDSFCW(dev) (0x00848708+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCFETCH_FLDSFCW__SIZE_1 2 /* */ #define NV_PNVDEC_MCFETCH_FLDSFCW_LUMA 11:0 /* RW-VF */ #define NV_PNVDEC_MCFETCH_FLDSFCW_CHROMA 27:16 /* RW-VF */ #define NV_PNVDEC_MCFETCH_FRMSIZE(dev) (0x0084870c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCFETCH_FRMSIZE__SIZE_1 2 /* */ #define NV_PNVDEC_MCFETCH_FRMSIZE_WIDTHM1 12:0 /* RW-VF */ #define NV_PNVDEC_MCFETCH_FRMSIZE_HEIGHTM1 28:16 /* RW-VF */ #define NV_PNVDEC_MCFETCH_DBG_STAT(dev,i) (0x00848710+(dev)*16384+(i)*0) /* R--4A */ #define NV_PNVDEC_MCFETCH_DBG_STAT__SIZE_1 2 /* */ #define NV_PNVDEC_MCFETCH_DBG_STAT__SIZE_2 16 /* */ #define NV_PNVDEC_MCFETCH_DBG_STAT_DATA 31:0 /* R--UF */ #define NV_PNVDEC_MCFETCH_CACHE_REQ(dev) (0x00848730+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCFETCH_CACHE_REQ__SIZE_1 2 /* */ #define NV_PNVDEC_MCFETCH_CACHE_REQ_NUM 31:0 /* RW-VF */ #define NV_PNVDEC_MCFETCH_CACHE_HIT(dev) (0x00848734+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MCFETCH_CACHE_HIT__SIZE_1 2 /* */ #define NV_PNVDEC_MCFETCH_CACHE_HIT_NUM 31:0 /* RW-VF */ #define NV_PNVDEC_MVLOCAL_MEMORY(dev,i,j) (0x00848e00+(dev)*16384+(i)*4+(j)*0) /* RW-4A */ #define NV_PNVDEC_MVLOCAL_MEMORY__SIZE_1 2 /* */ #define NV_PNVDEC_MVLOCAL_MEMORY__SIZE_2 12 /* */ #define NV_PNVDEC_MVLOCAL_MEMORY__SIZE_3 64 /* */ #define NV_PNVDEC_MVLOCAL_MEMORY_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MVSEQSTART(dev) (0x00848e40+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVSEQSTART__SIZE_1 2 /* */ #define NV_PNVDEC_MVSEQSTART_SLICE_ENABLE 0:0 /* RWIUF */ #define NV_PNVDEC_MVSEQSTART_SLICE_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVSEQSTART_INIT_ENABLE 4:4 /* RWIUF */ #define NV_PNVDEC_MVSEQSTART_INIT_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVFRMPARAM(dev) (0x00848e44+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVFRMPARAM__SIZE_1 2 /* */ #define NV_PNVDEC_MVFRMPARAM_PICWIDTHINMBS 7:0 /* RWXUF */ #define NV_PNVDEC_MVFRMPARAM_PICWIDTHINMBS_1MB 0x01 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_PICWIDTHINMBS_256MB 0x00 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_PICHEIGHTINMBS 15:8 /* RWXUF */ #define NV_PNVDEC_MVFRMPARAM_PICHEIGHTINMBS_1MB 0x01 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_PICHEIGHTINMBS_256MB 0x00 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PICCODING 18:16 /* RWXUF */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PICCODING_I 0x1 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PICCODING_P 0x2 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PICCODING_B 0x3 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PICCODING_D 0x4 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_PTYPE 22:20 /* RWXUF */ #define NV_PNVDEC_MVFRMPARAM_PTYPE_I 0x0 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_PTYPE_P 0x1 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_PTYPE_B 0x2 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_PTYPE_BI 0x3 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_PTYPE_SKIPPED 0x4 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PTYPE 22:20 /* RWXUF */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PTYPE_RESERVED 0x0 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PTYPE_TOP_FIELD 0x1 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PTYPE_BOTTOM_FIELD 0x2 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_MPEG2_PTYPE_FRAME 0x3 /* RWX-V */ #define NV_PNVDEC_MVFRMPARAM_VC1_MAINPROFILE 24:24 /* RWXUF */ #define NV_PNVDEC_MVWDCOUNTER(dev) (0x00848e48+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVWDCOUNTER__SIZE_1 2 /* */ #define NV_PNVDEC_MVWDCOUNTER_WDCOUNT 15:0 /* RW-UF */ #define NV_PNVDEC_MVWDTIME(dev) (0x00848e4c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVWDTIME__SIZE_1 2 /* */ #define NV_PNVDEC_MVWDTIME_WDTIME 15:0 /* RWIUF */ #define NV_PNVDEC_MVWDTIME_WDTIME_INFINITE 0xffff /* RWI-V */ #define NV_PNVDEC_MVCTRL0(dev) (0x00848e50+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVCTRL0__SIZE_1 2 /* */ #define NV_PNVDEC_MVCTRL0_VC1_DQMODE 1:0 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_VC1_DQMASK 7:4 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_VC1_DPQUANT 13:8 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_VC1_ALT_DPQUANT 21:16 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_VC1_ERRSFCIDX 31:25 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_VC1_ERRSFCIDX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_H264_APPLEOOLD_FLAG 0:0 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_H264_APPLEOOLD_FLAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_H264_REFPIC_FLAG 1:1 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_H264_REFPIC_FLAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_H264_CONSTRAINED_INTRA_PRED 2:2 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_H264_CONSTRAINED_INTRA_PRED_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_H264_CUR_BOTTOM_FIRST 3:3 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_H264_CUR_BOTTOM_FIRST_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_H264_CHROMA_QPIDXOFF 8:4 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_H264_SEC_CHROMA_QPIDXOFF 13:9 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_SVC_NOTLAYERTYPE 15:14 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_NOTLAYERTYPE_TARGETLAYER 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_SVC_NOTLAYERTYPE_REFBASELAYER 0x1 /* RW--V */ #define NV_PNVDEC_MVCTRL0_SVC_NOTLAYERTYPE_BASELAYER_RES 0x2 /* RW--V */ #define NV_PNVDEC_MVCTRL0_SVC_NOTLAYERTYPE_BASELAYER_NORES 0x3 /* RW--V */ #define NV_PNVDEC_MVCTRL0_SVC_NOTBASELAYER 16:16 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_NOTBASELAYER_BASELAYER 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_SVC_NOTBASELAYER_NOTBASELAYER 0x1 /* RW--V */ #define NV_PNVDEC_MVCTRL0_SVC_INPLACEILP 17:17 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_INPLACEILP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_SVC_TCLVLPRED 18:18 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_TCLVLPRED_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_SVC_TCLVLPREDNEXT 19:19 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_TCLVLPREDNEXT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_SVC_TCLVLPREDSLICE 20:20 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_TCLVLPREDSLICE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_SVC_RESCHANGE 21:21 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_RESCHANGE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_SVC_RESTRRESCHANGE 22:22 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_RESTRRESCHANGE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_SVC_INTERLAYERPRED 23:23 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_SVC_INTERLAYERPRED_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_H264_ERRSFCIDX 31:25 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_H264_ERRSFCIDX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_MPEG2_DIVX311 0:0 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_MPEG2_DIVX311_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_MPEG2_TOPFIELD_FIRST 1:1 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_MPEG2_TOPFIELD_FIRST_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_MPEG2_FULL_PEL_FWD_VECTOR 16:16 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_MPEG2_FULL_PEL_BWD_VECTOR 17:17 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_MPEG2_ERRSFCIDX 31:25 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_MPEG2_ERRSFCIDX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_MPEG4_DIVX_FLAG 0:0 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_MPEG4_DIVX_FLAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_MPEG4_TOPFIELD_FIRST 1:1 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_MPEG4_TOPFIELD_FIRST_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_MPEG4_QUARTER_SAMPLE 2:2 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_MPEG4_QUARTER_SAMPLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL0_MPEG4_VOP_FCODE_FWD 6:4 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_MPEG4_VOP_FCODE_BWD 10:8 /* RWXVF */ #define NV_PNVDEC_MVCTRL0_MPEG4_ERRSFCIDX 31:25 /* RWIVF */ #define NV_PNVDEC_MVCTRL0_MPEG4_ERRSFCIDX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_MVCTRL1(dev) (0x00848e54+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVCTRL1__SIZE_1 2 /* */ #define NV_PNVDEC_MVCTRL1_H264_WEIGHTED_PRED_IDC 3:2 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_H264_DIRECT_SPATIAL_MVPRED 4:4 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_H264_SLICE_ALPHAC0_OFFSDIV2 8:5 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_H264_SLICE_BETA_OFFSDIV2 12:9 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_H264_QPY 18:13 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_H264_BOTTOM_IS_CLOSER 19:19 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_H264_BOTTOM_IS_CLOSER_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_H264_REFPIC_IS_BOTTOMFIELD 20:20 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_H264_REFPIC_IS_BOTTOMFIELD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_H264_COLPIC_IS_SHORTTERM 21:21 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_H264_COLPIC_IS_SHORTTERM_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_H264_REFPIC_IS_FIELD 22:22 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_H264_REFPIC_IS_FIELD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_H264_DIS_DEBLOCKING_FLT_IDC 26:24 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_H264_DIS_DEBLOCKING_FLT_IDC_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_VC1_LOOPFILTER 0:0 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_VC1_LOOPFILTER_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_VC1_FASTUVMC 1:1 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_VC1_FASTUVMC_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_VC1_OVERLAP 2:2 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_VC1_OVERLAP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_VC1_CONDOVER 3:3 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_VC1_CONDOVER_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_VC1_MVRANGE 5:4 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_VC1_MVMODE 10:8 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_VC1_MVMODE_MIXEDMV 0x0 /* RWX-V */ #define NV_PNVDEC_MVCTRL1_VC1_MVMODE_1MV 0x1 /* RWX-V */ #define NV_PNVDEC_MVCTRL1_VC1_MVMODE_1MV_HALFPEL 0x2 /* RWX-V */ #define NV_PNVDEC_MVCTRL1_VC1_MVMODE_1MV_HALFPEL_BILINEAR 0x3 /* RWX-V */ #define NV_PNVDEC_MVCTRL1_VC1_MVMODE_INTENSITY_COMPENSATION 0x4 /* RWX-V */ #define NV_PNVDEC_MVCTRL1_VC1_BFRACTION 20:16 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_VC1_REFDIST 28:24 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_VC1_NUMREF 30:30 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_VC1_NUMREF_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_VC1_REFFIELD 31:31 /* RWIVF */ #define NV_PNVDEC_MVCTRL1_VC1_REFFIELD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL1_MPEG4_TRD0 15:0 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_MPEG4_TRD1 31:16 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_MPEG2_FCODE_00 3:0 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_MPEG2_FCODE_01 7:4 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_MPEG2_FCODE_10 11:8 /* RWXVF */ #define NV_PNVDEC_MVCTRL1_MPEG2_FCODE_11 15:12 /* RWXVF */ #define NV_PNVDEC_MVPSINFO(dev) (0x00848e58+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVPSINFO__SIZE_1 2 /* */ #define NV_PNVDEC_MVPSINFO_CODEC 2:0 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_CODEC_MPEG1 0x0 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_CODEC_MPEG2 0x1 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_CODEC_VC1 0x2 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_CODEC_H264 0x3 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_CODEC_MPEG4 0x4 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_CODEC_VP8 0x5 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_DXVA 4:3 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_NOTBASELAYER 6:6 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_BPIC 6:6 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_SECFIELD 7:7 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_MBAFF_TFF 8:8 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_STYPE_FCM 10:9 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_STYPE_FCM_P 0x0 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_STYPE_FCM_B 0x1 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_STYPE_FCM_I 0x2 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_STYPE_FCM_PROG_FRAME 0x0 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_STYPE_FCM_INTL_FRAME 0x2 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_STYPE_FCM_INTL_FIELD 0x3 /* RWX-V */ #define NV_PNVDEC_MVPSINFO_COLOR_BILINEAR 11:11 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_DIR8X8INF_INTLFWD 12:12 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_FIELDPIC_INTLBWD 13:13 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_VERSION 13:11 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_BOTFIELD 14:14 /* RWXVF */ #define NV_PNVDEC_MVPSINFO_FRMSFCEN 15:15 /* RWXVF */ #define NV_PNVDEC_MVCTRL2(dev) (0x00848e5c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVCTRL2__SIZE_1 2 /* */ #define NV_PNVDEC_MVCTRL2_H264_BOTTOMFIRST 15:0 /* RWXVF */ #define NV_PNVDEC_MVCTRL2_INTER_BS_STCOEFF_CHK 16:16 /* RWIVF */ #define NV_PNVDEC_MVCTRL2_INTER_BS_STCOEFF_CHK_REV_032009 0x1 /* RW--V */ #define NV_PNVDEC_MVCTRL2_INTER_BS_STCOEFF_CHK_REV_NEXTREV 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL2_INTER_XF8_NO_NZ_CHK 17:17 /* RWIVF */ #define NV_PNVDEC_MVCTRL2_INTER_XF8_NO_NZ_CHK_REV_032009 0x1 /* RW--V */ #define NV_PNVDEC_MVCTRL2_INTER_XF8_NO_NZ_CHK_REV_NEXTREV 0x0 /* RWI-V */ #define NV_PNVDEC_MVCTRL2_MPEG4_TRB1 31:16 /* RWXVF */ #define NV_PNVDEC_MVCTRL2_MPEG4_TRB0 15:0 /* RWXVF */ #define NV_PNVDEC_MVRPLBASE(dev) (0x00848e60+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVRPLBASE__SIZE_1 2 /* */ #define NV_PNVDEC_MVRPLBASE_ADDR 10:0 /* RWXVF */ #define NV_PNVDEC_MVSPLBASE(dev) (0x00848e64+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVSPLBASE__SIZE_1 2 /* */ #define NV_PNVDEC_MVSPLBASE_ADDR 9:0 /* RWXVF */ #define NV_PNVDEC_MVSTATUS(dev) (0x00848e68+(dev)*16384) /* R--4A */ #define NV_PNVDEC_MVSTATUS__SIZE_1 2 /* */ #define NV_PNVDEC_MVSTATUS_SEQ_BUSY 0:0 /* R--VF */ #define NV_PNVDEC_MVSTATUS_IS_BUSY 1:1 /* R--VF */ #define NV_PNVDEC_MVSTATUS_WCOL_BUSY 2:2 /* R--VF */ #define NV_PNVDEC_MVSTATUS_RCOL_BUSY 3:3 /* R--VF */ #define NV_PNVDEC_MVSTATUS_OSPRDS_BUSY 4:4 /* R--VF */ #define NV_PNVDEC_MVSTATUS_OSPDBL_BUSY 5:5 /* R--VF */ #define NV_PNVDEC_MVSTATUS_OSPREC_BUSY 6:6 /* R--VF */ #define NV_PNVDEC_MVSTATUS_OSPMCS_BUSY 7:7 /* R--VF */ #define NV_PNVDEC_MVSTATUS_H2M_BUSY 8:8 /* R--VF */ #define NV_PNVDEC_MVSTATUS_M2H_BUSY 9:9 /* R--VF */ #define NV_PNVDEC_MVSTATUS_ILPMBRD_BUSY 10:10 /* R--VF */ #define NV_PNVDEC_MVSTATUS_ILPMBWR_BUSY 11:11 /* R--VF */ #define NV_PNVDEC_MVSTATUS_OSPILP_BUSY 12:12 /* R--VF */ #define NV_PNVDEC_MVPSINFO2(dev) (0x00848e6c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVPSINFO2__SIZE_1 2 /* */ #define NV_PNVDEC_MVPSINFO2_DBF_DISABLE 0:0 /* RWIVF */ #define NV_PNVDEC_MVPSINFO2_DBF_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVPSINFO2_MCS_DISABLE 1:1 /* RWIVF */ #define NV_PNVDEC_MVPSINFO2_MCS_DISABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVPSINFO2_ILP_ENABLE 2:2 /* RWIVF */ #define NV_PNVDEC_MVPSINFO2_ILP_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTCSW(dev) (0x00848e70+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVINTCSW__SIZE_1 2 /* */ #define NV_PNVDEC_MVINTCSW_IRQ_WDTMR 0:0 /* RWXVF */ #define NV_PNVDEC_MVINTCSW_IRQ_ISDMA 1:1 /* RWXVF */ #define NV_PNVDEC_MVINTCSW_IRQ_RESERVED 2:2 /* RWXVF */ #define NV_PNVDEC_MVINTCSW_IRQ_EOSP 3:3 /* RWXVF */ #define NV_PNVDEC_MVINTCSW_IRQ_TERR 4:4 /* RWXVF */ #define NV_PNVDEC_MVINTCSW_IRQ_RESERR 5:5 /* RWXVF */ #define NV_PNVDEC_MVINTCSW_IRQ_BERR 6:6 /* RWXVF */ #define NV_PNVDEC_MVINTCSW_IRQ_MC_CFGERR 7:7 /* RWXVF */ #define NV_PNVDEC_MVINTCSW_IRQ_REC_CFGERR 8:8 /* RWXVF */ #define NV_PNVDEC_MVINTEN(dev) (0x00848e74+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVINTEN__SIZE_1 2 /* */ #define NV_PNVDEC_MVINTEN_IRQ_WDTMR 0:0 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_WDTMR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTEN_IRQ_ISDMA 1:1 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_ISDMA_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTEN_IRQ_RESERVED 2:2 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_RESERVED_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTEN_IRQ_EOSP 3:3 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_EOSP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTEN_IRQ_TERR 4:4 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_TERR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTEN_IRQ_RESERR 5:5 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_RESERR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTEN_IRQ_BERR 6:6 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_BERR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTEN_IRQ_MC_CFGERR 7:7 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_MC_CFGERR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVINTEN_IRQ_REC_CFGERR 8:8 /* RWIVF */ #define NV_PNVDEC_MVINTEN_IRQ_REC_CFGERR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVWT_CNTRL(dev) (0x00848e78+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVWT_CNTRL__SIZE_1 2 /* */ #define NV_PNVDEC_MVWT_CNTRL_CHROMA_LOG2_WEIGHT_DENOM 2:0 /* RW-VF */ #define NV_PNVDEC_MVWT_CNTRL_LUMA_LOG2_WEIGHT_DENOM 5:3 /* RW-VF */ #define NV_PNVDEC_MVWT_CNTRL_WEIGHT_DENOM_WR_EN 6:6 /* RW-VF */ #define NV_PNVDEC_MVWT_CNTRL_ADR 14:8 /* RW-VF */ #define NV_PNVDEC_MVWT_CNTRL_ADR_WR_EN 15:15 /* RW-VF */ #define NV_PNVDEC_MVWT_CNTRL_LOADED 16:16 /* RW-VF */ #define NV_PNVDEC_MVWT_DATA(dev) (0x00848e7c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVWT_DATA__SIZE_1 2 /* */ #define NV_PNVDEC_MVWT_DATA_LUMA_OFFSET 7:0 /* RW-VF */ #define NV_PNVDEC_MVWT_DATA_LUMA_WEIGHT 15:8 /* RW-VF */ #define NV_PNVDEC_MVWT_DATA_CHROMA_WEIGHT_FLAG 16:16 /* RW-VF */ #define NV_PNVDEC_MVWT_DATA_LUMA_WEIGHT_FLAG 17:17 /* RW-VF */ #define NV_PNVDEC_MVWT_DATA_CHROMA_V_OFFSET 7:0 /* RW-VF */ #define NV_PNVDEC_MVWT_DATA_CHROMA_V_WEIGHT 15:8 /* RW-VF */ #define NV_PNVDEC_MVWT_DATA_CHROMA_U_OFFSET 23:16 /* RW-VF */ #define NV_PNVDEC_MVWT_DATA_CHROMA_U_WEIGHT 31:24 /* RW-VF */ #define NV_PNVDEC_MVRCOLADDR(dev) (0x00848e80+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVRCOLADDR__SIZE_1 2 /* */ #define NV_PNVDEC_MVRCOLADDR_RCOL_ADDR 31:0 /* RW-UF */ #define NV_PNVDEC_MVRCOLPARAM(dev) (0x00848e84+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVRCOLPARAM__SIZE_1 2 /* */ #define NV_PNVDEC_MVRCOLPARAM_RCOL_LWIDTH 7:0 /* RW-UF */ #define NV_PNVDEC_MVRCOLPARAM_RCOL_NLIN 8:8 /* RW-VF */ #define NV_PNVDEC_MVRCOLLINE(dev) (0x00848e88+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVRCOLLINE__SIZE_1 2 /* */ #define NV_PNVDEC_MVRCOLLINE_RCOL_LREM 7:0 /* RWXUF */ #define NV_PNVDEC_MVRCOLLINE_RCOL_LCNT 16:8 /* RWXUF */ #define NV_PNVDEC_MVRCOLOFFS(dev) (0x00848e8c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVRCOLOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_MVRCOLOFFS_RCOL_OFFS 11:0 /* RW-UF */ #define NV_PNVDEC_MVRCOLOFFS_RCOL_LODD 12:12 /* RW-VF */ #define NV_PNVDEC_MVRCOLOFFS_4K_RCOL_OFFS 15:0 /* RW-UF */ #define NV_PNVDEC_MVRCOLOFFS_4K_RCOL_LODD 16:16 /* RW-VF */ #define NV_PNVDEC_MVRCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_PNVDEC_MVWCOLADDR(dev) (0x00848e90+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVWCOLADDR__SIZE_1 2 /* */ #define NV_PNVDEC_MVWCOLADDR_WCOL_ADDR 31:0 /* RW-UF */ #define NV_PNVDEC_MVWCOLPARAM(dev) (0x00848e94+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVWCOLPARAM__SIZE_1 2 /* */ #define NV_PNVDEC_MVWCOLPARAM_WCOL_LWIDTH 7:0 /* RW-UF */ #define NV_PNVDEC_MVWCOLPARAM_WCOL_MBAFF 8:8 /* RW-VF */ #define NV_PNVDEC_MVWCOLPARAM_WCOL_FIELD 9:9 /* RW-VF */ #define NV_PNVDEC_MVWCOLPARAM_4MV 10:10 /* RWIVF */ #define NV_PNVDEC_MVWCOLPARAM_4MV_DIS 0x0 /* RWI-V */ #define NV_PNVDEC_MVWCOLPARAM_4MV_EN 0x1 /* RW--V */ #define NV_PNVDEC_MVWCOLPARAM_WRITEENABLE 11:11 /* RWIVF */ #define NV_PNVDEC_MVWCOLPARAM_WRITEENABLE_DIS 0x0 /* RWI-V */ #define NV_PNVDEC_MVWCOLPARAM_WRITEENABLE_EN 0x1 /* RW--V */ #define NV_PNVDEC_MVWCOLLINE(dev) (0x00848e98+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVWCOLLINE__SIZE_1 2 /* */ #define NV_PNVDEC_MVWCOLLINE_WCOL_LREM 7:0 /* RW-UF */ #define NV_PNVDEC_MVWCOLLINE_WCOL_LCNT 16:8 /* RW-UF */ #define NV_PNVDEC_MVWCOLOFFS(dev) (0x00848e9c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVWCOLOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_MVWCOLOFFS_WCOL_OFFS 12:0 /* RW-UF */ #define NV_PNVDEC_MVWCOLOFFS_WCOL_LODD 13:13 /* RW-VF */ #define NV_PNVDEC_MVWCOLOFFS_4K_WCOL_OFFS 15:0 /* RW-UF */ #define NV_PNVDEC_MVWCOLOFFS_4K_WCOL_LODD 16:16 /* RW-VF */ #define NV_PNVDEC_MVWCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_PNVDEC_MVISSTART(dev) (0x00848ea0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVISSTART__SIZE_1 2 /* */ #define NV_PNVDEC_MVISSTART_BUF_ADDR 31:0 /* RW-VF */ #define NV_PNVDEC_MVISSIZE(dev) (0x00848ea4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVISSIZE__SIZE_1 2 /* */ #define NV_PNVDEC_MVISSIZE_BUF_SIZE 31:8 /* RW-VF */ #define NV_PNVDEC_MVISOFFS(dev) (0x00848ea8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVISOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_MVISOFFS_BUF_OFFS 31:2 /* RW-VF */ #define NV_PNVDEC_MVISCOUNT(dev) (0x00848eac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVISCOUNT__SIZE_1 2 /* */ #define NV_PNVDEC_MVISCOUNT_BUF_COUNT 31:2 /* RW-VF */ #define NV_PNVDEC_MVISCTL(dev) (0x00848eb0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVISCTL__SIZE_1 2 /* */ #define NV_PNVDEC_MVISCTL_ENABLE 0:0 /* RWIVF */ #define NV_PNVDEC_MVISCTL_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVISCTL_DMASUSPEND 1:1 /* -W-VF */ #define NV_PNVDEC_MVDBG_CTL(dev) (0x00848eb4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVDBG_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_MVDBG_CTL_RDSWAIT 0:0 /* RWIVF */ #define NV_PNVDEC_MVDBG_CTL_RDSWAIT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVDBG_CTL_MCSWAIT 1:1 /* RWIVF */ #define NV_PNVDEC_MVDBG_CTL_MCSWAIT_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVERRORCTL(dev) (0x00848eb8+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_MVERRORCTL__SIZE_1 2 /* */ #define NV_PNVDEC_MVERRORCTL_SET_ERROR_STATUS 0:0 /* -W-VF */ #define NV_PNVDEC_MVERRORCTL_CLR_ERROR_COUNTERS 1:1 /* -W-VF */ #define NV_PNVDEC_MVERRORCTL_CTS_ERROR_CORRECTION 4:4 /* -W-VF */ #define NV_PNVDEC_MVERRORMASK(dev) (0x00848ebc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVERRORMASK__SIZE_1 2 /* */ #define NV_PNVDEC_MVERRORMASK_MVY_RANGE128 0:0 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_MVY_RANGE256 1:1 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_MVY_RANGE512 2:2 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_VLD_MBERROR 3:3 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_H264_INTRA16X16 4:4 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_H264_INTRA8X8 5:5 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_H264_INTRA4X4 6:6 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_H264_BIPRED 7:7 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_H264_NEI_MB 8:8 /* RW-VF */ #define NV_PNVDEC_MVERRORMASK_H264_NEI_PART 9:9 /* RW-VF */ #define NV_PNVDEC_MVERRORSTAT(dev) (0x00848ec0+(dev)*16384) /* R--4A */ #define NV_PNVDEC_MVERRORSTAT__SIZE_1 2 /* */ #define NV_PNVDEC_MVERRORSTAT_MVY_RANGE128 0:0 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_MVY_RANGE256 1:1 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_MVY_RANGE512 2:2 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_VLD_MBERROR 3:3 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_H264_INTRA16X16 4:4 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_H264_INTRA8X8 5:5 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_H264_INTRA4X4 6:6 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_H264_BIPRED 7:7 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_H264_NEI_MB 8:8 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_H264_NEI_PART 9:9 /* R--VF */ #define NV_PNVDEC_MVERRORSTAT_SW_ERR 31:31 /* R--VF */ #define NV_PNVDEC_MV_MB_COUNTER(dev) (0x00848ec4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV_MB_COUNTER__SIZE_1 2 /* */ #define NV_PNVDEC_MV_MB_COUNTER_INTRA 15:0 /* RWIVF */ #define NV_PNVDEC_MV_MB_COUNTER_INTRA_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_MV_MB_COUNTER_SKIP 31:16 /* RWIVF */ #define NV_PNVDEC_MV_MB_COUNTER_SKIP_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_MV_MB_COUNTER1(dev) (0x00848ec8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV_MB_COUNTER1__SIZE_1 2 /* */ #define NV_PNVDEC_MV_MB_COUNTER1_REG 16:0 /* RWIVF */ #define NV_PNVDEC_MV_MB_COUNTER1_REG_INIT 0x00000 /* RWI-V */ #define NV_PNVDEC_MVDBG_STATE(dev,i) (0x00848ecc+(dev)*16384+(i)*0) /* R--4A */ #define NV_PNVDEC_MVDBG_STATE__SIZE_1 2 /* */ #define NV_PNVDEC_MVDBG_STATE__SIZE_2 13 /* */ #define NV_PNVDEC_MVDBG_STATE_DATA 31:0 /* R--UF */ #define NV_PNVDEC_MVILPSCALEMV1X(dev,i) (0x00848ed4+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_MVILPSCALEMV1X__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPSCALEMV1X__SIZE_2 8 /* */ #define NV_PNVDEC_MVILPSCALEMV1X_DATA 23:0 /* RW-UF */ #define NV_PNVDEC_MVILPSCALEMV1Y(dev,i) (0x00848ed4+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_MVILPSCALEMV1Y__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPSCALEMV1Y__SIZE_2 8 /* */ #define NV_PNVDEC_MVILPSCALEMV1Y_DATA 23:0 /* RW-UF */ #define NV_PNVDEC_MVILPSCALEMV2X(dev,i) (0x00848ed4+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_MVILPSCALEMV2X__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPSCALEMV2X__SIZE_2 8 /* */ #define NV_PNVDEC_MVILPSCALEMV2X_DATA 26:0 /* RW-UF */ #define NV_PNVDEC_MVILPSCALEMV2Y(dev,i) (0x00848ed4+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_MVILPSCALEMV2Y__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPSCALEMV2Y__SIZE_2 8 /* */ #define NV_PNVDEC_MVILPSCALEMV2Y_DATA 26:0 /* RW-UF */ #define NV_PNVDEC_MVILPOFFSETMVX(dev,i) (0x00848ed4+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_MVILPOFFSETMVX__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPOFFSETMVX__SIZE_2 8 /* */ #define NV_PNVDEC_MVILPOFFSETMVX_DATA 27:0 /* RW-UF */ #define NV_PNVDEC_MVILPOFFSETMVY(dev,i) (0x00848ed4+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_MVILPOFFSETMVY__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPOFFSETMVY__SIZE_2 8 /* */ #define NV_PNVDEC_MVILPOFFSETMVY_DATA 25:0 /* RW-UF */ #define NV_PNVDEC_MVILPDIM(dev) (0x00848ed8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPDIM__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPDIM_STRIDEM1 7:0 /* RW-UF */ #define NV_PNVDEC_MVILPDIM_WIDTHM1 23:16 /* RW-UF */ #define NV_PNVDEC_MVILPDIM_HEIGHTM1 31:24 /* RW-UF */ #define NV_PNVDEC_MVILPMBCTL_REF(dev) (0x00848edc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPMBCTL_REF__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPMBCTL_REF_OFFS 31:0 /* RW-UF */ #define NV_PNVDEC_MVILPMBCTL_CUR(dev) (0x00848ee0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPMBCTL_CUR__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPMBCTL_CUR_OFFS 31:0 /* RW-UF */ #define NV_PNVDEC_MVILPSLICE_MODE_CUR(dev) (0x00848ee4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPSLICE_MODE_CUR__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPSLICE_MODE_CUR_OFFS 31:0 /* RW-UF */ #define NV_PNVDEC_MVILPLAYER_CTL(dev) (0x00848ee8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPLAYER_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPLAYER_CTL_RD_ENABLE 0:0 /* RW-UF */ #define NV_PNVDEC_MVILPLAYER_CTL_WR_ENABLE 1:1 /* RW-UF */ #define NV_PNVDEC_MVILPLAYER_CTL_CROPCHANGE 2:2 /* RW-UF */ #define NV_PNVDEC_MVILPLAYER_CTL_RESTRRESCHANGE 3:3 /* RW-UF */ #define NV_PNVDEC_MVILPLAYER_CTL_DIR8X8INF 4:4 /* RW-UF */ #define NV_PNVDEC_MVILPLAYER_CTL_REFCLAMP_ENABLE 15:15 /* RW-UF */ #define NV_PNVDEC_MVILPLAYER_CTL_REFWIDTHM1 23:16 /* RW-UF */ #define NV_PNVDEC_MVILPLAYER_CTL_REFHEIGHTM1 31:24 /* RW-UF */ #define NV_PNVDEC_MVILPSLICE_CTL(dev) (0x00848eec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPSLICE_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPSLICE_CTL_SLICETYPE 1:0 /* RWXUF */ #define NV_PNVDEC_MVILPSLICE_CTL_SLICETYPE_INIT 0x0 /* RWX-V */ #define NV_PNVDEC_MVILPSLICE_CTL_SLICETYPE_P 0x0 /* RWX-V */ #define NV_PNVDEC_MVILPSLICE_CTL_SLICETYPE_B 0x1 /* RWX-V */ #define NV_PNVDEC_MVILPSLICE_CTL_SLICETYPE_I 0x2 /* RWX-V */ #define NV_PNVDEC_MVILPSLICE_CTL_NOILP 2:2 /* RWIUF */ #define NV_PNVDEC_MVILPSLICE_CTL_NOILP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MVILPSLICE_CTL_NUMENTRIES 7:4 /* RWIUF */ #define NV_PNVDEC_MVILPSLICE_CTL_NUMENTRIES_INIT 0x8 /* RWI-V */ #define NV_PNVDEC_MVILPCROP(dev) (0x00848ef0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPCROP__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPCROP_LEFT 7:0 /* RW-UF */ #define NV_PNVDEC_MVILPCROP_TOP 15:8 /* RW-UF */ #define NV_PNVDEC_MVILPCROP_RIGHT 23:16 /* RW-UF */ #define NV_PNVDEC_MVILPCROP_BOTTOM 31:24 /* RW-UF */ #define NV_PNVDEC_MVILPOFFSETX_LO(dev) (0x00848ef4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPOFFSETX_LO__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPOFFSETX_LO_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MVILPOFFSETY_LO(dev) (0x00848ef8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPOFFSETY_LO__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPOFFSETY_LO_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MVILPOFFSET_HI(dev) (0x00848efc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPOFFSET_HI__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPOFFSET_HI_X 1:0 /* RW-UF */ #define NV_PNVDEC_MVILPOFFSET_HI_Y 17:16 /* RW-UF */ #define NV_PNVDEC_MVILPSCALEX(dev) (0x00848f00+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPSCALEX__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPSCALEX_DATA 24:0 /* RW-UF */ #define NV_PNVDEC_MVILPSCALEY(dev) (0x00848f04+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPSCALEY__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPSCALEY_DATA 24:0 /* RW-UF */ #define NV_PNVDEC_MVILPREFIDXMAPL0_LO(dev) (0x00848f08+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPREFIDXMAPL0_LO__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPREFIDXMAPL0_LO_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MVILPREFIDXMAPL0_HI(dev) (0x00848f0c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPREFIDXMAPL0_HI__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPREFIDXMAPL0_HI_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MVILPREFIDXMAPL1_LO(dev) (0x00848f10+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPREFIDXMAPL1_LO__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPREFIDXMAPL1_LO_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MVILPREFIDXMAPL1_HI(dev) (0x00848f14+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVILPREFIDXMAPL1_HI__SIZE_1 2 /* */ #define NV_PNVDEC_MVILPREFIDXMAPL1_HI_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MVSFCLAYOUT(dev) (0x00848f18+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MVSFCLAYOUT__SIZE_1 2 /* */ #define NV_PNVDEC_MVSFCLAYOUT_DATA 15:0 /* RWIUF */ #define NV_PNVDEC_MVSFCLAYOUT_DATA_INIT 0xffff /* RWI-V */ #define NV_PNVDEC_SA_CONTROL(dev,i) (0x00848b60+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_SA_CONTROL__SIZE_1 2 /* */ #define NV_PNVDEC_SA_CONTROL__SIZE_2 2 /* */ #define NV_PNVDEC_SA_CONTROL_CMD_CHUNK_SZ 4:0 /* RW-UF */ #define NV_PNVDEC_SA_CONTROL_CIPHER_CNT 9:5 /* RW-UF */ #define NV_PNVDEC_SA_CONTROL_PLAIN_SZ 16:10 /* RW-UF */ #define NV_PNVDEC_SA_CONTROL_INST_CNT 25:20 /* RW-UF */ #define NV_PNVDEC_SA_CONTROL_INST_OFFSET 31:26 /* RW-UF */ #define NV_PNVDEC_SA_START(dev,i) (0x00848b64+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_SA_START__SIZE_1 2 /* */ #define NV_PNVDEC_SA_START__SIZE_2 2 /* */ #define NV_PNVDEC_SA_START_OFFSET 6:0 /* RW-UF */ #define NV_PNVDEC_SA_START_SECTION 8:8 /* RWIUF */ #define NV_PNVDEC_SA_START_SECTION_CIPHER 0x0 /* RWI-V */ #define NV_PNVDEC_SA_START_SECTION_PLAIN 0x1 /* RW--V */ #define NV_PNVDEC_SA_INST_ARRAY(dev,i) (0x00848b68+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_SA_INST_ARRAY__SIZE_1 2 /* */ #define NV_PNVDEC_SA_INST_ARRAY__SIZE_2 4 /* */ #define NV_PNVDEC_SA_INST_ARRAY_OP_0 4:0 /* RW-UF */ #define NV_PNVDEC_SA_INST_ARRAY_RX_0 10:5 /* RW-UF */ #define NV_PNVDEC_SA_INST_ARRAY_RY_0 14:11 /* RW-UF */ #define NV_PNVDEC_SA_INST_ARRAY_OP_1 20:16 /* RW-UF */ #define NV_PNVDEC_SA_INST_ARRAY_RX_1 26:21 /* RW-UF */ #define NV_PNVDEC_SA_INST_ARRAY_RY_1 30:27 /* RW-UF */ #define NV_PNVDEC_SA_STATUS(dev,i) (0x00848b6c+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_SA_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_SA_STATUS__SIZE_2 2 /* */ #define NV_PNVDEC_SA_STATUS_IDLE 0:0 /* R--UF */ #define NV_PNVDEC_SA_STATUS_FLUSH_PENDING 1:1 /* R--UF */ #define NV_PNVDEC_SA_STATUS_PACKETS_OUTSTANDING 2:2 /* R--UF */ #define NV_PNVDEC_SA_STATUS_STOP_UNIT 4:4 /* RWIUF */ #define NV_PNVDEC_SA_STATUS_STOP_UNIT_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SA_STATUS_STOP_UNIT_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_SA_STATUS_UNIT_STATE 9:8 /* R--UF */ #define NV_PNVDEC_SA_STATUS_UNIT_STATE_IDLE 0x0 /* R---V */ #define NV_PNVDEC_SA_STATUS_CIPHER_OFFSET 14:10 /* R--UF */ #define NV_PNVDEC_SA_STATUS_PLAIN_OFFSET 23:15 /* R--UF */ #define NV_PNVDEC_SA_STATUS_CHUNK_OFFSET 30:24 /* R--UF */ #define NV_PNVDEC_SA_PASS2_OTF(dev) (0x00848b70+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_PASS2_OTF__SIZE_1 2 /* */ #define NV_PNVDEC_SA_PASS2_OTF_NON_SLICE_DATA 15:0 /* RW-UF */ #define NV_PNVDEC_SA_PASS2_OTF_SSM_EN 16:16 /* RWIVF */ #define NV_PNVDEC_SA_PASS2_OTF_SSM_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SA_PASS2_OTF_SSM_EN_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SA_PASS2_OTF_DRM_MODE 23:17 /* RW-UF */ #define NV_PNVDEC_SA_PASS2_OTF_IV_REG_IDX 27:24 /* RW-UF */ #define NV_PNVDEC_SA_PASS2_OTF_CTR_IV_OP_OUT_IDX 31:28 /* RW-UF */ #define NV_PNVDEC_SA_SSM_ENTRY(dev) (0x00848b74+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_SSM_ENTRY__SIZE_1 2 /* */ #define NV_PNVDEC_SA_SSM_ENTRY_BASE_ADDRESS 31:0 /* RW-UF */ #define NV_PNVDEC_SA_SSM_IV(dev) (0x00848b78+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_SSM_IV__SIZE_1 2 /* */ #define NV_PNVDEC_SA_SSM_IV_BASE_ADDRESS 31:0 /* RW-UF */ #define NV_PNVDEC_SA_PASS2_OTF2(dev) (0x00848b7c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_PASS2_OTF2__SIZE_1 2 /* */ #define NV_PNVDEC_SA_PASS2_OTF2_LOOP_TRACE_IDX 0:0 /* RWIVF */ #define NV_PNVDEC_SA_PASS2_OTF2_LOOP_TRACE_IDX_0 0x0 /* RWI-V */ #define NV_PNVDEC_SA_PASS2_OTF2_LOOP_TRACE_IDX_1 0x1 /* RW--V */ #define NV_PNVDEC_SA_PASS2_OTF2_CTR_IV_OP_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_SA_PASS2_OTF2_CTR_IV_OP_DIS_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SA_PASS2_OTF2_CTR_IV_OP_DIS_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SA_PASS2_OTF2_CODEC 2:2 /* RWIVF */ #define NV_PNVDEC_SA_PASS2_OTF2_CODEC_IS_LEGACY 0x1 /* RW--V */ #define NV_PNVDEC_SA_PASS2_OTF2_CODEC_IS_HEVC_VP9 0x0 /* RWI-V */ #define NV_PNVDEC_SA_PASS2_OTF2_HALT 3:3 /* RWIVF */ #define NV_PNVDEC_SA_PASS2_OTF2_HALT_REQ 0x1 /* RW--V */ #define NV_PNVDEC_SA_PASS2_OTF2_HALT_DONE 0x0 /* RWI-V */ #define NV_PNVDEC_SA_PASS2_OTF2_CLAMP_SCP_INPUT 4:4 /* RWIVF */ #define NV_PNVDEC_SA_PASS2_OTF2_CLAMP_SCP_INPUT_DIS 0x1 /* RW--V */ #define NV_PNVDEC_SA_PASS2_OTF2_CLAMP_SCP_INPUT_EN 0x0 /* RWI-V */ #define NV_PNVDEC_SA_PASS2_OTF3(dev) (0x00848b80+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_PASS2_OTF3__SIZE_1 2 /* */ #define NV_PNVDEC_SA_PASS2_OTF3_SSM_ENTRY_NUM 15:0 /* RW-UF */ #define NV_PNVDEC_SA_PASS2_OTF3_SSM_IV_NUM 31:16 /* RW-UF */ #define NV_PNVDEC_CTL_STAT(dev) (0x00848d00+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CTL_STAT__SIZE_1 2 /* */ #define NV_PNVDEC_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */ #define NV_PNVDEC_CTL_STAT_DEBUG_MODE_DISABLED 0x0 /* R---V */ #define NV_PNVDEC_CTL_CFG(dev) (0x00848d04+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CTL_CFG__SIZE_1 2 /* */ #define NV_PNVDEC_CTL_CFG_LOCKDOWN 0:0 /* R-IVF */ #define NV_PNVDEC_CTL_CFG_LOCKDOWN_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_CTL_CFG_LOCKDOWN_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_CTL_CFG_LOCKDOWN_SCP 4:4 /* R-IVF */ #define NV_PNVDEC_CTL_CFG_LOCKDOWN_SCP_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_CTL_CFG_LOCKDOWN_SCP_DISABLE 0x0 /* R-I-V */ #define NV_PNVDEC_CTL_SCP(dev) (0x00848d08+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CTL_SCP__SIZE_1 2 /* */ #define NV_PNVDEC_CTL_SCP_TOGGLE_MASTER 0:0 /* RWIVF */ #define NV_PNVDEC_CTL_SCP_TOGGLE_MASTER_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_CTL_SCP_TOGGLE_MASTER_PENDING 0x1 /* RW--V */ #define NV_PNVDEC_CTL_SCP_CURRENT_MASTER 1:1 /* R-IVF */ #define NV_PNVDEC_CTL_SCP_CURRENT_MASTER_FALCON 0x0 /* R-I-V */ #define NV_PNVDEC_CTL_SCP_CURRENT_MASTER_EXT 0x1 /* R---V */ #define NV_PNVDEC_CTL_HDCP0(dev) (0x00848d0c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CTL_HDCP0__SIZE_1 2 /* */ #define NV_PNVDEC_CTL_HDCP0_KEY 31:0 /* RW-VF */ #define NV_PNVDEC_CTL_HDCP1(dev) (0x00848d10+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CTL_HDCP1__SIZE_1 2 /* */ #define NV_PNVDEC_CTL_HDCP1_KEY 23:0 /* RW-VF */ #define NV_PNVDEC_BAR0_CSR(dev) (0x00848c00+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_BAR0_CSR__SIZE_1 2 /* */ #define NV_PNVDEC_BAR0_CSR_CMD 1:0 /* RWIVF */ #define NV_PNVDEC_BAR0_CSR_CMD_READ 0x1 /* RW--V */ #define NV_PNVDEC_BAR0_CSR_CMD_WRITE 0x2 /* RW--V */ #define NV_PNVDEC_BAR0_CSR_CMD_POSTED_WRITE 0x3 /* RW--V */ #define NV_PNVDEC_BAR0_CSR_CMD_UNDEFINED 0x0 /* RWI-V */ #define NV_PNVDEC_BAR0_CSR_BYTE_ENABLE 7:4 /* RWIVF */ #define NV_PNVDEC_BAR0_CSR_BYTE_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_BAR0_CSR_STATUS 14:12 /* R-IVF */ #define NV_PNVDEC_BAR0_CSR_STATUS_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_BAR0_CSR_STATUS_BUSY 0x1 /* R---V */ #define NV_PNVDEC_BAR0_CSR_STATUS_TMOUT 0x2 /* R---V */ #define NV_PNVDEC_BAR0_CSR_STATUS_DIS 0x3 /* R---V */ #define NV_PNVDEC_BAR0_CSR_STATUS_ERR 0x4 /* R---V */ #define NV_PNVDEC_BAR0_CSR_TRIG 31:31 /* RWIVF */ #define NV_PNVDEC_BAR0_CSR_TRIG_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_BAR0_CSR_TRIG_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_BAR0_ADDR(dev) (0x00848c04+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_BAR0_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_BAR0_ADDR_REG_ADDR 31:0 /* RWIVF */ #define NV_PNVDEC_BAR0_ADDR_REG_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_BAR0_DATA(dev) (0x00848c08+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_BAR0_DATA__SIZE_1 2 /* */ #define NV_PNVDEC_BAR0_DATA_RWDATA 31:0 /* RWIVF */ #define NV_PNVDEC_BAR0_DATA_RWDATA_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_BAR0_TMOUT(dev) (0x00848c0c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_BAR0_TMOUT__SIZE_1 2 /* */ #define NV_PNVDEC_BAR0_TMOUT_CYCLES 31:0 /* RWIVF */ #define NV_PNVDEC_BAR0_TMOUT_CYCLES_INIT 0x01f2a737 /* RWI-V */ #define NV_PNVDEC_BAR0_TMOUT_CYCLES__PROD 0x01f2a737 /* RW--V */ #define NV_PNVDEC_SA_KEYSLOT_KEY000(dev) (0x00849000+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY000__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY000_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY001(dev) (0x00849004+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY001__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY001_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY002(dev) (0x00849008+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY002__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY002_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY003(dev) (0x0084900c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY003__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY003_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY010(dev) (0x00849010+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY010__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY010_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY011(dev) (0x00849014+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY011__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY011_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY012(dev) (0x00849018+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY012__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY012_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY013(dev) (0x0084901c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY013__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY013_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY020(dev) (0x00849020+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY020__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY020_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY021(dev) (0x00849024+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY021__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY021_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY022(dev) (0x00849028+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY022__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY022_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY023(dev) (0x0084902c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY023__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY023_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY030(dev) (0x00849030+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY030__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY030_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY031(dev) (0x00849034+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY031__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY031_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY032(dev) (0x00849038+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY032__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY032_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY033(dev) (0x0084903c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY033__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY033_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY040(dev) (0x00849040+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY040__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY040_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY041(dev) (0x00849044+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY041__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY041_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY042(dev) (0x00849048+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY042__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY042_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY043(dev) (0x0084904c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY043__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY043_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY050(dev) (0x00849050+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY050__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY050_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY051(dev) (0x00849054+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY051__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY051_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY052(dev) (0x00849058+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY052__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY052_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY053(dev) (0x0084905c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY053__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY053_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY060(dev) (0x00849060+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY060__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY060_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY061(dev) (0x00849064+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY061__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY061_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY062(dev) (0x00849068+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY062__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY062_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY063(dev) (0x0084906c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY063__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY063_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY070(dev) (0x00849070+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY070__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY070_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY071(dev) (0x00849074+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY071__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY071_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY072(dev) (0x00849078+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY072__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY072_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY073(dev) (0x0084907c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY073__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY073_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY100(dev) (0x00849080+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY100__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY100_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY101(dev) (0x00849084+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY101__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY101_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY102(dev) (0x00849088+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY102__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY102_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY103(dev) (0x0084908c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY103__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY103_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY110(dev) (0x00849090+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY110__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY110_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY111(dev) (0x00849094+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY111__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY111_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY112(dev) (0x00849098+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY112__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY112_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY113(dev) (0x0084909c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY113__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY113_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY120(dev) (0x008490a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY120__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY120_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY121(dev) (0x008490a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY121__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY121_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY122(dev) (0x008490a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY122__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY122_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY123(dev) (0x008490ac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY123__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY123_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY130(dev) (0x008490b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY130__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY130_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY131(dev) (0x008490b4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY131__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY131_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY132(dev) (0x008490b8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY132__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY132_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY133(dev) (0x008490bc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY133__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY133_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY140(dev) (0x008490c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY140__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY140_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY141(dev) (0x008490c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY141__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY141_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY142(dev) (0x008490c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY142__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY142_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY143(dev) (0x008490cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY143__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY143_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY150(dev) (0x008490d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY150__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY150_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY151(dev) (0x008490d4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY151__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY151_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY152(dev) (0x008490d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY152__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY152_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY153(dev) (0x008490dc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY153__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY153_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY160(dev) (0x008490e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY160__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY160_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY161(dev) (0x008490e4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY161__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY161_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY162(dev) (0x008490e8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY162__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY162_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY163(dev) (0x008490ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY163__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY163_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY170(dev) (0x008490f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY170__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY170_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY171(dev) (0x008490f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY171__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY171_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY172(dev) (0x008490f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY172__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY172_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY173(dev) (0x008490fc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY173__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY173_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_FALCON(dev) (0x00849100+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_FALCON__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_FALCON_EN 31:0 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_FALCON_EN_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_SA_KEYSLOT_TZ(dev) (0x00849104+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_TZ__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_TZ_EN 31:0 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_TZ_EN_INIT 0x0000ffff /* RWI-V */ #define NV_PNVDEC_SA_KEYSLOT_FALCON2(dev) (0x00849108+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_FALCON2__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_FALCON2_EN 31:0 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_FALCON2_EN_INIT 0x0000ffff /* RWI-V */ #define NV_PNVDEC_SA_KEYSLOT_OTF(dev) (0x0084910c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_OTF__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_OTF_EN 31:0 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_OTF_EN_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_SA_KEYSLOT_SEL(dev) (0x00849110+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_SEL__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_SEL_V 4:0 /* RWXUF */ #define NV_PNVDEC_SA_KEYSLOT_PUSH(dev) (0x00849114+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_PUSH__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_PUSH_EN 0:0 /* RWXUF */ #define NV_PNVDEC_SA_KEYSLOT_PUSH_MODE 1:1 /* RWXUF */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW(dev) (0x00849118+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW_RD_DIS 15:0 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW_RD_DIS_INIT 0xffff /* RWI-V */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW_WR_DIS 31:16 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW_WR_DIS_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_VPR_ALL_OTF_GOTO_VPR(dev) (0x0084911c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VPR_ALL_OTF_GOTO_VPR__SIZE_1 2 /* */ #define NV_PNVDEC_VPR_ALL_OTF_GOTO_VPR_EN 0:0 /* RWXUF */ #define NV_PNVDEC_VPR_TZ_VPR_WR(dev) (0x00849120+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VPR_TZ_VPR_WR__SIZE_1 2 /* */ #define NV_PNVDEC_VPR_TZ_VPR_WR_EN 0:0 /* RWXUF */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW2(dev) (0x00849124+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW2__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW2_RD_DIS 15:0 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW2_RD_DIS_INIT 0xffff /* RWI-V */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW2_WR_DIS 31:16 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_GLOBAL_RW2_WR_DIS_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_SA_KEYSLOT_LOCK(dev) (0x00849128+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_LOCK__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_LOCK_EN 0:0 /* RWIVF */ #define NV_PNVDEC_SA_KEYSLOT_LOCK_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SA_KEYSLOT_KEY200(dev) (0x00849130+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY200__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY200_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY201(dev) (0x00849134+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY201__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY201_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY202(dev) (0x00849138+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY202__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY202_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY203(dev) (0x0084913c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY203__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY203_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY210(dev) (0x00849140+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY210__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY210_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY211(dev) (0x00849144+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY211__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY211_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY212(dev) (0x00849148+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY212__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY212_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY213(dev) (0x0084914c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY213__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY213_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY220(dev) (0x00849150+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY220__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY220_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY221(dev) (0x00849154+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY221__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY221_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY222(dev) (0x00849158+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY222__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY222_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY223(dev) (0x0084915c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY223__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY223_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY230(dev) (0x00849160+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY230__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY230_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY231(dev) (0x00849164+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY231__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY231_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY232(dev) (0x00849168+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY232__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY232_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY233(dev) (0x0084916c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY233__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY233_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY240(dev) (0x00849170+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY240__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY240_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY241(dev) (0x00849174+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY241__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY241_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY242(dev) (0x00849178+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY242__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY242_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY243(dev) (0x0084917c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY243__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY243_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY250(dev) (0x00849180+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY250__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY250_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY251(dev) (0x00849184+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY251__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY251_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY252(dev) (0x00849188+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY252__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY252_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY253(dev) (0x0084918c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY253__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY253_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY260(dev) (0x00849190+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY260__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY260_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY261(dev) (0x00849194+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY261__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY261_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY262(dev) (0x00849198+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY262__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY262_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY263(dev) (0x0084919c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY263__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY263_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY270(dev) (0x008491a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY270__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY270_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY271(dev) (0x008491a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY271__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY271_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY272(dev) (0x008491a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY272__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY272_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY273(dev) (0x008491ac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY273__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY273_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY300(dev) (0x008491b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY300__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY300_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY301(dev) (0x008491b4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY301__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY301_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY302(dev) (0x008491b8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY302__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY302_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY303(dev) (0x008491bc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY303__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY303_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY310(dev) (0x008491c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY310__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY310_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY311(dev) (0x008491c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY311__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY311_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY312(dev) (0x008491c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY312__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY312_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY313(dev) (0x008491cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY313__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY313_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY320(dev) (0x008491d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY320__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY320_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY321(dev) (0x008491d4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY321__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY321_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY322(dev) (0x008491d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY322__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY322_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY323(dev) (0x008491dc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY323__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY323_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY330(dev) (0x008491e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY330__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY330_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY331(dev) (0x008491e4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY331__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY331_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY332(dev) (0x008491e8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY332__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY332_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY333(dev) (0x008491ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY333__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY333_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY340(dev) (0x008491f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY340__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY340_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY341(dev) (0x008491f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY341__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY341_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY342(dev) (0x008491f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY342__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY342_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY343(dev) (0x008491fc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY343__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY343_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY350(dev) (0x00849200+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY350__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY350_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY351(dev) (0x00849204+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY351__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY351_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY352(dev) (0x00849208+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY352__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY352_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY353(dev) (0x0084920c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY353__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY353_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY360(dev) (0x00849210+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY360__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY360_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY361(dev) (0x00849214+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY361__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY361_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY362(dev) (0x00849218+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY362__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY362_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY363(dev) (0x0084921c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY363__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY363_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY370(dev) (0x00849220+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY370__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY370_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY371(dev) (0x00849224+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY371__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY371_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY372(dev) (0x00849228+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY372__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY372_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_SA_KEYSLOT_KEY373(dev) (0x0084922c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SA_KEYSLOT_KEY373__SIZE_1 2 /* */ #define NV_PNVDEC_SA_KEYSLOT_KEY373_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG(dev,i) (0x00848600+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_FBIF_TRANSCFG__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_TRANSCFG__SIZE_2 8 /* */ #define NV_PNVDEC_FBIF_TRANSCFG__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_TRANSCFG__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_TARGET_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x0 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x1 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x2 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_MEM_TYPE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x0 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x1 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_WR_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x0 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x1 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x2 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_RD_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x0 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x1 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x2 /* R---V */ #define NV_PNVDEC_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_WACHK0_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_WACHK0_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_TRANSCFG_WACHK0_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_WACHK1_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_WACHK1_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_TRANSCFG_WACHK1_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_RACHK0_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_RACHK0_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_TRANSCFG_RACHK0_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_RACHK1_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_RACHK1_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_TRANSCFG_RACHK1_DISABLE 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_TRANSCFG_ENGINE_ID_FLAG 16:16 /* RWIVF */ #define NV_PNVDEC_FBIF_TRANSCFG_ENGINE_ID_FLAG_BAR2_FN0 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_TRANSCFG_ENGINE_ID_FLAG_OWN 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_INSTBLK(dev) (0x00848620+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_INSTBLK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_INSTBLK_PTR 27:0 /* R--VF */ #define NV_PNVDEC_FBIF_INSTBLK_TARGET 29:28 /* R--VF */ #define NV_PNVDEC_FBIF_INSTBLK_TARGET_LOCAL_FB 0x0 /* R---V */ #define NV_PNVDEC_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x1 /* R---V */ #define NV_PNVDEC_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x2 /* R---V */ #define NV_PNVDEC_FBIF_BIND_STATUS(dev) (0x00848628+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_BIND_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_BIND_STATUS_STATUS 1:0 /* R-IVF */ #define NV_PNVDEC_FBIF_BIND_STATUS_STATUS_NOT_BIND 0x0 /* R-I-V */ #define NV_PNVDEC_FBIF_BIND_STATUS_STATUS_BOUND 0x2 /* R---V */ #define NV_PNVDEC_FBIF_BIND_STATUS_GFID 9:4 /* R--VF */ #define NV_PNVDEC_FBIF_BIND_STATUS_GFID_INIT 0x00 /* R---V */ #define NV_PNVDEC_FBIF_BIND_STATUS_ENGINE_ID 23:16 /* R--VF */ #define NV_PNVDEC_FBIF_CTL(dev) (0x00848624+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FBIF_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_CTL_FLUSH 0:0 /* RW-VF */ #define NV_PNVDEC_FBIF_CTL_FLUSH_SET 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_FLUSH_CLEAR 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */ #define NV_PNVDEC_FBIF_CTL_INVAL_CONTEXT_SET 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */ #define NV_PNVDEC_FBIF_CTL_CLR_BWCOUNT_SET 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_ENABLE 4:4 /* RWIVF */ #define NV_PNVDEC_FBIF_CTL_ENABLE_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_CTL_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */ #define NV_PNVDEC_FBIF_CTL_CLR_IDLEWDERR_SET 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_RESET 6:6 /* RW-VF */ #define NV_PNVDEC_FBIF_CTL_RESET_SET 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_RESET_CLEAR 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */ #define NV_PNVDEC_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_IDLE 8:8 /* R--VF */ #define NV_PNVDEC_FBIF_CTL_IDLE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FBIF_CTL_IDLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */ #define NV_PNVDEC_FBIF_CTL_IDLEWDERR_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FBIF_CTL_IDLEWDERR_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_CTL_SRTOUT 10:10 /* R--VF */ #define NV_PNVDEC_FBIF_CTL_SRTOUT_TRUE 0x1 /* R---V */ #define NV_PNVDEC_FBIF_CTL_SRTOUT_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */ #define NV_PNVDEC_FBIF_CTL_CLR_SRTOUT_SET 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_CLR_SRTOUT_CLEAR 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */ #define NV_PNVDEC_FBIF_CTL_SRTOVAL_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_THROTTLE(dev) (0x0084862c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FBIF_THROTTLE__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */ #define NV_PNVDEC_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x064 /* RWI-V */ #define NV_PNVDEC_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */ #define NV_PNVDEC_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x000 /* RWI-V */ #define NV_PNVDEC_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */ #define NV_PNVDEC_FBIF_THROTTLE_LEAK_SIZE_16B 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_THROTTLE_LEAK_SIZE_32B 0x1 /* RW--V */ #define NV_PNVDEC_FBIF_THROTTLE_LEAK_SIZE_64B 0x2 /* RWI-V */ #define NV_PNVDEC_FBIF_THROTTLE_LEAK_SIZE_128B 0x3 /* RW--V */ #define NV_PNVDEC_FBIF_REGIONCFG(dev) (0x0084866c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FBIF_REGIONCFG__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_REGIONCFG__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_REGIONCFG__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_REGIONCFG_T0 3:0 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_T0_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_T1 7:4 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_T1_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_T2 11:8 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_T2_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_T3 15:12 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_T3_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_T4 19:16 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_T4_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_T5 23:20 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_T5_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_T6 27:24 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_T6_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_REGIONCFG_T7 31:28 /* RWIVF */ #define NV_PNVDEC_FBIF_REGIONCFG_T7_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_FBIF_CG1(dev) (0x00848674+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FBIF_CG1__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_CG1_SLCG 3:0 /* */ #define NV_PNVDEC_FBIF_CG1_SLCG_ENABLED 0x0 /* */ #define NV_PNVDEC_FBIF_CG1_SLCG_DISABLED 0xf /* */ #define NV_PNVDEC_FBIF_CG1_SLCG__PROD 0x0 /* */ #define NV_PNVDEC_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */ #define NV_PNVDEC_FBIF_CG1_SLCG_MSD0_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CG1_SLCG_MSD0_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */ #define NV_PNVDEC_FBIF_CG1_SLCG_MSD1_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CG1_SLCG_MSD1_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */ #define NV_PNVDEC_FBIF_CG1_SLCG_FB0_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CG1_SLCG_FB0_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */ #define NV_PNVDEC_FBIF_CG1_SLCG_FB1_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_FBIF_CG1_SLCG_FB1_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_FBIF_ACHK_BLK(dev,i) (0x00848630+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_FBIF_ACHK_BLK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_ACHK_BLK__SIZE_2 2 /* */ #define NV_PNVDEC_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */ #define NV_PNVDEC_FBIF_ACHK_CTL(dev,i) (0x00848634+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_FBIF_ACHK_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_ACHK_CTL__SIZE_2 2 /* */ #define NV_PNVDEC_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */ #define NV_PNVDEC_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */ #define NV_PNVDEC_FBIF_ACHK_CTL_TYPE_INSIDE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x1 /* R---V */ #define NV_PNVDEC_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */ #define NV_PNVDEC_FBIF_ACHK_CTL_STATE_DISABLE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_ACHK_CTL_STATE_ENABLE 0x1 /* R---V */ #define NV_PNVDEC_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */ #define NV_PNVDEC_FBIF_DBG_STAT0(dev) (0x00848640+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_STAT0__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_STAT0__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_STAT0__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE 3:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_IDLE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_CHECK 0x1 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_ALLOC 0x2 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_ISSUE 0x3 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_WDAT 0x4 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_FLT_FLUSH 0x5 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_HALT 0x6 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_INST 0x7 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_INST_ACK 0x8 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_OBJ 0x9 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DSP_STATE_FLUSH 0xa /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_INST_VLD 4:4 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_INST_BOUND 5:5 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_RICF_HAS_DATA 6:6 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_ARQ_HAS_DATA 7:7 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_MRQ_HAS_DATA 8:8 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_FAULT_OR_HALT 9:9 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_ORQ_NOT_FULL 10:10 /* R-IUF */ #define NV_PNVDEC_FBIF_DBG_STAT0_ORQ_NOT_FULL_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_FBIF_DBG_STAT0_ORQ_NOT_FULL_FLASE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_FLUSH_OUTSTANDING 11:11 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_DISPATCH_IDLE 12:12 /* R-IUF */ #define NV_PNVDEC_FBIF_DBG_STAT0_DISPATCH_IDLE_TRUE 0x1 /* R-I-V */ #define NV_PNVDEC_FBIF_DBG_STAT0_DISPATCH_IDLE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_MWF_FSM_STATE 17:16 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_MWF_FSM_STATE_IDLE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_MWF_FSM_STATE_COMMIT 0x1 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_MWF_FSM_STATE_ROLLBACK 0x2 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT0_MWF_HAS_DATA 18:18 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_MWF_COMMIT_COUNT 24:19 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_STALL_RQQ_FULL 25:25 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_STALL_WDF_FULL 26:26 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_STALL_FB_BUSY 27:27 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_STALL_ORQ_FULL 28:28 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_STALL_RDM_ALLOC 29:29 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_STALL_RDM_PORTQ 30:30 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT0_STALL_RDM_CLIENT 31:31 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1(dev) (0x00848644+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_STAT1__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_STAT1__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_STAT1__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_STAT1_FLT_STATE 1:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_FLT_FAULTED 2:2 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_FLT_BUSY 3:3 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_ACKF_HAS_DATA 4:4 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_ORQ_HAS_DATA 5:5 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_ALL_READS_DONE 6:6 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_FBR_IDLE 8:8 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_FBR_FAULTED 9:9 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_FBR_FB_BUSY 10:10 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_FBR_PKT2FB_VLD 11:11 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_FBR_RCV_DATA_VALID 12:12 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_FBR_RCV_DATA_TYPE 15:14 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_WDF_FSM_STATE 17:16 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_WDF_FSM_STATE_IDLE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT1_WDF_FSM_STATE_COMMIT 0x1 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT1_WDF_FSM_STATE_ROLLBACK 0x2 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT1_WDF_HAS_DATA 18:18 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_WDF_COMMIT_COUNT 23:19 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_RDM_STATE 25:24 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_RDM_STATE_IDLE 0x0 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT1_RDM_STATE_WAITBUF 0x1 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT1_RDM_STATE_SAVEBUF 0x2 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT1_RDM_ANY_READY 26:26 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_RDM_DAQ_HAS_DATA 27:27 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_RDM_DEALLOC_COUNT 30:28 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT1_RDATA_WAIT 31:31 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT2(dev) (0x00848648+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_STAT2__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_STAT2__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_STAT2__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_STAT2_FAULTED_PORTID 5:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT2_FAULTED_SUBID 12:6 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT2_FAULTED_SRCQ 13:13 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_STAT2_FAULTED_SRCQ_ARQ 0x1 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT2_FAULTED_SRCQ_MRQ 0x0 /* R---V */ #define NV_PNVDEC_FBIF_DBG_STAT2_FAULTED_VLD 14:14 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_LO(dev) (0x00848650+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_LO__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_LO_DATA 31:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_HI(dev) (0x00848654+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_HI__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_RDCOUNT_HI_DATA 31:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_LO(dev) (0x00848658+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_LO__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_LO_DATA 31:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_HI(dev) (0x0084865c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_HI__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_WRCOUNT_HI_DATA 31:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_R32COUNT(dev) (0x00848660+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_R32COUNT__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_R32COUNT__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_R32COUNT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_R32COUNT_DATA 31:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_R64COUNT(dev) (0x00848664+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_R64COUNT__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_R64COUNT__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_R64COUNT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_R64COUNT_DATA 31:0 /* R--UF */ #define NV_PNVDEC_FBIF_DBG_R128COUNT(dev) (0x00848668+(dev)*16384) /* R--4A */ #define NV_PNVDEC_FBIF_DBG_R128COUNT__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_R128COUNT__PRIV_LEVEL_MASK(dev) (0x00848670+(dev)*16384) /* */ #define NV_PNVDEC_FBIF_DBG_R128COUNT__PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_DBG_R128COUNT_DATA 31:0 /* R--UF */ #define NV_PNVDEC_FBIF_BW_ALLOC(dev) (0x0084864c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_FBIF_BW_ALLOC__SIZE_1 2 /* */ #define NV_PNVDEC_FBIF_BW_ALLOC_VAL 31:0 /* */ #define NV_PNVDEC_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */ #define NV_PNVDEC_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */ #define NV_PNVDEC_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */ #define NV_PNVDEC_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */ #define NV_PNVDEC_SCP_CTL0(dev) (0x00848800+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CTL0__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CTL0_CTL_EN 20:20 /* RWIVF */ #define NV_PNVDEC_SCP_CTL0_CTL_EN_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CTL0_CTL_EN_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CTL0_SEQ_EN 16:16 /* RWIVF */ #define NV_PNVDEC_SCP_CTL0_SEQ_EN_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CTL0_SEQ_EN_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CTL0_SF_CMD_IFACE_EN 14:14 /* RWIVF */ #define NV_PNVDEC_SCP_CTL0_SF_CMD_IFACE_EN_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CTL0_SF_CMD_IFACE_EN_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CTL0_SF_PUSH_IFACE_EN 12:12 /* RWIVF */ #define NV_PNVDEC_SCP_CTL0_SF_PUSH_IFACE_EN_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CTL0_SF_PUSH_IFACE_EN_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CTL0_SF_FETCH_IFACE_EN 10:10 /* RWIVF */ #define NV_PNVDEC_SCP_CTL0_SF_FETCH_IFACE_EN_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CTL0_SF_FETCH_IFACE_EN_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CTL1(dev) (0x00848804+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CTL1__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CTL1_SF_PUSH_BYPASS 24:24 /* RWIVF */ #define NV_PNVDEC_SCP_CTL1_SF_PUSH_BYPASS_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL1_SF_PUSH_BYPASS_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL1_SF_FETCH_BYPASS 20:20 /* RWIVF */ #define NV_PNVDEC_SCP_CTL1_SF_FETCH_BYPASS_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL1_SF_FETCH_BYPASS_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL1_SF_FETCH_AS_ZERO 16:16 /* RWIVF */ #define NV_PNVDEC_SCP_CTL1_SF_FETCH_AS_ZERO_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL1_SF_FETCH_AS_ZERO_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL1_RNG_EN 12:12 /* RWIVF */ #define NV_PNVDEC_SCP_CTL1_RNG_EN_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL1_RNG_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL1_RNG_FAKE_MODE 11:11 /* RWIVF */ #define NV_PNVDEC_SCP_CTL1_RNG_FAKE_MODE_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL1_RNG_FAKE_MODE_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL1_PIPE_RESET 8:8 /* RWIVF */ #define NV_PNVDEC_SCP_CTL1_PIPE_RESET_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL1_PIPE_RESET_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL1_PIPE_RESET_TASK 0x1 /* -W--T */ #define NV_PNVDEC_SCP_CTL1_SEQ_CLEAR 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_CTL1_SEQ_CLEAR_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL1_SEQ_CLEAR_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL1_SEQ_CLEAR_TASK 0x1 /* -W--T */ #define NV_PNVDEC_SCP_CTL_STAT(dev) (0x00848808+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_CTL_STAT__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */ #define NV_PNVDEC_SCP_CTL_STAT_DEBUG_MODE_DISABLED 0x0 /* R---V */ #define NV_PNVDEC_SCP_CTL_STAT_AES_SCC_DIS 2:2 /* R--VF */ #define NV_PNVDEC_SCP_CTL_STAT_AES_SCC_DIS_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_STAT_AES_SCC_DIS_FALSE 0x0 /* R---V */ #define NV_PNVDEC_SCP_CTL_STAT_HSMODE 1:1 /* R--VF */ #define NV_PNVDEC_SCP_CTL_STAT_HSMODE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_STAT_HSMODE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_SCP_CTL_STAT_SBOOT 0:0 /* R--VF */ #define NV_PNVDEC_SCP_CTL_STAT_SBOOT_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_STAT_SBOOT_FALSE 0x0 /* R---V */ #define NV_PNVDEC_SCP_CTL_CFG(dev) (0x0084880c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CTL_CFG__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT 1:1 /* R-IVF */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_PRE 2:2 /* R-IVF */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_PRE_ENABLED 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_PRE_DISABLED 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP 4:4 /* RWIVF */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_PRE 6:6 /* R-IVF */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_ENABLED 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_DISABLED 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CFG0(dev) (0x00848810+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CFG0__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CFG0_STALL_TIMEOUT 31:16 /* RWIVF */ #define NV_PNVDEC_SCP_CFG0_STALL_TIMEOUT_INIT 0xffff /* RWI-V */ #define NV_PNVDEC_SCP_CFG0_CARRY_CHAIN 13:12 /* RWIVF */ #define NV_PNVDEC_SCP_CFG0_CARRY_CHAIN_32 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CFG0_CARRY_CHAIN_64 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CFG0_CARRY_CHAIN_96 0x2 /* RW--V */ #define NV_PNVDEC_SCP_CFG0_CARRY_CHAIN_128 0x3 /* RW--V */ #define NV_PNVDEC_SCP_CFG0_CMD_FLUSH 8:8 /* RWIVF */ #define NV_PNVDEC_SCP_CFG0_CMD_FLUSH_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CFG0_CMD_FLUSH_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CFG0_AES_ENDIAN 4:4 /* RWIVF */ #define NV_PNVDEC_SCP_CFG0_AES_ENDIAN_BIG 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CFG0_AES_ENDIAN_LITTLE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CFG0_PUSH_ENDIAN 3:3 /* RWIVF */ #define NV_PNVDEC_SCP_CFG0_PUSH_ENDIAN_BIG 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CFG0_PUSH_ENDIAN_LITTLE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CFG0_FETCH_ENDIAN 2:2 /* RWIVF */ #define NV_PNVDEC_SCP_CFG0_FETCH_ENDIAN_BIG 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CFG0_FETCH_ENDIAN_LITTLE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CFG0_CMAC_ENDIAN 1:1 /* RWIVF */ #define NV_PNVDEC_SCP_CFG0_CMAC_ENDIAN_BIG 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CFG0_CMAC_ENDIAN_LITTLE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CFG0_ADD_ENDIAN 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_CFG0_ADD_ENDIAN_BIG 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_CFG0_ADD_ENDIAN_LITTLE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_CTL_SCP(dev) (0x00848814+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CTL_SCP__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CTL_SCP_TOGGLE_MASTER 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_CTL_SCP_TOGGLE_MASTER_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL_SCP_TOGGLE_MASTER_PENDING 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL_SCP_CURRENT_MASTER 1:1 /* R-IVF */ #define NV_PNVDEC_SCP_CTL_SCP_CURRENT_MASTER_FALCON 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL_SCP_CURRENT_MASTER_EXT 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_PKEY(dev) (0x00848818+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CTL_PKEY__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CTL_PKEY_REQUEST_RELOAD 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_CTL_PKEY_REQUEST_RELOAD_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL_PKEY_REQUEST_RELOAD_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_PKEY_REQUEST_RELOAD_TASK 0x1 /* -W--T */ #define NV_PNVDEC_SCP_CTL_PKEY_LOADED 1:1 /* R-IVF */ #define NV_PNVDEC_SCP_CTL_PKEY_LOADED_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL_PKEY_LOADED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_DEBUG(dev) (0x0084881c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CTL_DEBUG__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CTL_DEBUG_LOCKDOWN_CYA 4:4 /* RWIVF */ #define NV_PNVDEC_SCP_CTL_DEBUG_LOCKDOWN_CYA_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL_DEBUG_LOCKDOWN_CYA_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA 8:8 /* RWIVF */ #define NV_PNVDEC_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0(dev) (0x00848820+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_DEBUG0__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_DEBUG0_PUSH_SECURE 31:31 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_PUSH_SECURE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_PUSH_SECURE_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_PUSH_VALID 30:30 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_PUSH_VALID_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_PUSH_VALID_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_PUSH_CNT 26:25 /* R-IVF */ #define NV_PNVDEC_SCP_DEBUG0_PUSH_CNT_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_DEBUG0_FETCH_SECURE 24:24 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_FETCH_SECURE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_FETCH_SECURE_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_FETCH_VALID 23:23 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_FETCH_VALID_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_FETCH_VALID_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_FETCH_CNT 22:19 /* R-IVF */ #define NV_PNVDEC_SCP_DEBUG0_FETCH_CNT_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_SECURE 18:18 /* R-IVF */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_SECURE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_SECURE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_VALID 17:17 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_VALID_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_VALID_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_PC 16:13 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_PC_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_DEPTH 12:8 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_SEQ_DEPTH_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_TARGET 6:5 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_TARGET_NONE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_TARGET_PUSH 0x1 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_TARGET_FETCH 0x2 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_TARGET_SEQ 0x3 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_INDEX_AUTOINCREMENT 4:4 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_INDEX_AUTOINCREMENT_TRUE 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG0_INDEX_AUTOINCREMENT_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG0_INDEX 3:0 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG0_INDEX_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG1(dev) (0x00848824+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_DEBUG1__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_DEBUG1_DATA 31:0 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG2(dev) (0x00848828+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_DEBUG2__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_DEBUG2_KU 15:12 /* R-IVF */ #define NV_PNVDEC_SCP_DEBUG2_KU_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_DEBUG2_SEQ_CNT 9:4 /* R-IVF */ #define NV_PNVDEC_SCP_DEBUG2_SEQ_CNT_INIT 0x00 /* R-I-V */ #define NV_PNVDEC_SCP_DEBUG2_SEQ_STATE 1:0 /* R-IVF */ #define NV_PNVDEC_SCP_DEBUG2_SEQ_STATE_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_DEBUG2_SEQ_STATE_IDLE 0x0 /* R---V */ #define NV_PNVDEC_SCP_DEBUG2_SEQ_STATE_LOAD 0x1 /* R---V */ #define NV_PNVDEC_SCP_DEBUG2_SEQ_STATE_LOOP 0x2 /* R---V */ #define NV_PNVDEC_SCP_DEBUG_CMD(dev) (0x00848830+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_DEBUG_CMD__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_DEBUG_CMD_SECURE 31:31 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG_CMD_SECURE_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG_CMD_SECURE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG_CMD_VALID 28:28 /* RWIVF */ #define NV_PNVDEC_SCP_DEBUG_CMD_VALID_FALSE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_DEBUG_CMD_VALID_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_DEBUG_CMD_OP 24:20 /* RWXVF */ #define NV_PNVDEC_SCP_DEBUG_CMD_RX_IMM 13:8 /* RWXVF */ #define NV_PNVDEC_SCP_DEBUG_CMD_RY 3:0 /* RWXVF */ #define NV_PNVDEC_SCP_ACL_FETCH(dev) (0x00848840+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_ACL_FETCH__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_ACL_FETCH_SECURE 23:16 /* R--VF */ #define NV_PNVDEC_SCP_ACL_FETCH_INSECURE 7:0 /* R--VF */ #define NV_PNVDEC_SCP_ACL_KEYABLE(dev) (0x00848844+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_ACL_KEYABLE__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_ACL_KEYABLE_SECURE 23:16 /* R--VF */ #define NV_PNVDEC_SCP_ACL_KEYABLE_INSECURE 7:0 /* R--VF */ #define NV_PNVDEC_SCP_ACL_WRITE(dev) (0x00848848+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_ACL_WRITE__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_ACL_WRITE_INSECURE 7:0 /* R--VF */ #define NV_PNVDEC_SCP_STATUS(dev) (0x00848850+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_STATUS_SCP_ACTIVE 0:0 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_SCP_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_SCP_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_CMD_ACTIVE 2:2 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_CMD_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_CMD_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_PUSH_ACTIVE 4:4 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_PUSH_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_PUSH_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_SEQ_ACTIVE 6:6 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_SEQ_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_SEQ_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_CTL_ACTIVE 8:8 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_CTL_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_CTL_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_FETCH_ACTIVE 10:10 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_FETCH_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_FETCH_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_AES_ACTIVE 14:14 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_AES_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_AES_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_RNG_ACTIVE 16:16 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_RNG_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_RNG_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_PKEY_LOADING_ACTIVE 18:18 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_PKEY_LOADING_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_PKEY_LOADING_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_SFK_LOADING_ACTIVE 20:20 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_SFK_LOADING_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_SFK_LOADING_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_SCC_TRNG_ACTIVE 26:26 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_SCC_TRNG_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_SCC_TRNG_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STATUS_SCC_PRNG_ACTIVE 28:28 /* R-IVF */ #define NV_PNVDEC_SCP_STATUS_SCC_PRNG_ACTIVE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STATUS_SCC_PRNG_ACTIVE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT0(dev) (0x00848854+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_STAT0__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_STAT0_SF_CMD_VLD 14:14 /* R-IVF */ #define NV_PNVDEC_SCP_STAT0_SF_CMD_VLD_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT0_SF_CMD_VLD_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT0_SF_CMD_SECURE 12:12 /* R-XVF */ #define NV_PNVDEC_SCP_STAT0_SF_CMD_SECURE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT0_SF_CMD_SECURE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_SCP_STAT0_SF_PUSH_VLD 10:10 /* R-IVF */ #define NV_PNVDEC_SCP_STAT0_SF_PUSH_VLD_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT0_SF_PUSH_VLD_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT0_SF_PUSH_SECURE 8:8 /* R-XVF */ #define NV_PNVDEC_SCP_STAT0_SF_PUSH_SECURE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT0_SF_PUSH_SECURE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_SCP_STAT0_SF_FETCH_RDY 6:6 /* R-IVF */ #define NV_PNVDEC_SCP_STAT0_SF_FETCH_RDY_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT0_SF_FETCH_RDY_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT0_SF_FETCH_SECURE 4:4 /* R-XVF */ #define NV_PNVDEC_SCP_STAT0_SF_FETCH_SECURE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT0_SF_FETCH_SECURE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_SCP_STAT0_CMP 1:0 /* R-IVF */ #define NV_PNVDEC_SCP_STAT0_CMP_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT0_CMP_PASS 0x3 /* R---V */ #define NV_PNVDEC_SCP_STAT0_CMP_FAIL 0x2 /* R---V */ #define NV_PNVDEC_SCP_STAT1(dev) (0x00848858+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_STAT1__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_STAT1_SEQ_OP 4:0 /* R-XVF */ #define NV_PNVDEC_SCP_STAT1_SF_OP 9:5 /* R-XVF */ #define NV_PNVDEC_SCP_STAT1_DISPATCH_OP 14:10 /* R-XVF */ #define NV_PNVDEC_SCP_STAT1_AES_OP 17:15 /* R-XVF */ #define NV_PNVDEC_SCP_STAT1_AES_OP_ENCRYPT 0x0 /* R---V */ #define NV_PNVDEC_SCP_STAT1_AES_OP_DECRYPT 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT1_AES_OP_RKEY 0x2 /* R---V */ #define NV_PNVDEC_SCP_STAT1_AES_OP_RKEYI 0x3 /* R---V */ #define NV_PNVDEC_SCP_STAT1_HAZARD_STALL 24:24 /* R-IVF */ #define NV_PNVDEC_SCP_STAT1_HAZARD_STALL_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT1_HAZARD_STALL_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT1_PUSH_STALL 25:25 /* R-IVF */ #define NV_PNVDEC_SCP_STAT1_PUSH_STALL_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT1_PUSH_STALL_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT1_FETCH_STALL 26:26 /* R-IVF */ #define NV_PNVDEC_SCP_STAT1_FETCH_STALL_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT1_FETCH_STALL_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT1_RNG_STALL 27:27 /* R-IVF */ #define NV_PNVDEC_SCP_STAT1_RNG_STALL_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT1_RNG_STALL_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT1_WB_STALL 28:28 /* R-IVF */ #define NV_PNVDEC_SCP_STAT1_WB_STALL_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT1_WB_STALL_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT1_AES_STALL 29:29 /* R-IVF */ #define NV_PNVDEC_SCP_STAT1_AES_STALL_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT1_AES_STALL_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_STAT1_SECRET_STALL 30:30 /* R-IVF */ #define NV_PNVDEC_SCP_STAT1_SECRET_STALL_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_STAT1_SECRET_STALL_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_SECRET63_CTL(dev) (0x00848860+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_SECRET63_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_SECRET63_CTL_SEL 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_SECRET63_CTL_SEL_PKEY 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_SECRET63_CTL_SEL_KMEM 0x1 /* RW--V */ #define NV_PNVDEC_SCP_RNG_STAT0(dev) (0x00848870+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNG_STAT0__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNG_STAT0_RAW_RAND_READY 0:0 /* R-IVF */ #define NV_PNVDEC_SCP_RNG_STAT0_RAW_RAND_READY_READY 0x0 /* R---V */ #define NV_PNVDEC_SCP_RNG_STAT0_RAW_RAND_READY_PROCESSING 0x1 /* R---V */ #define NV_PNVDEC_SCP_RNG_STAT0_RAW_RAND_READY_RANDBUF_NOTFULL 0x1 /* R-I-V */ #define NV_PNVDEC_SCP_RNG_STAT0_AUTOCAL_TAP_A 7:4 /* R-IVF */ #define NV_PNVDEC_SCP_RNG_STAT0_AUTOCAL_TAP_A_INIT 0xf /* R-I-V */ #define NV_PNVDEC_SCP_RNG_STAT0_AUTOCAL_TAP_B 11:8 /* R-IVF */ #define NV_PNVDEC_SCP_RNG_STAT0_AUTOCAL_TAP_B_INIT 0xf /* R-I-V */ #define NV_PNVDEC_SCP_RNG_STAT0_LFSR_STAT_A 12:12 /* R-IVF */ #define NV_PNVDEC_SCP_RNG_STAT0_LFSR_STAT_A_LEGAL 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_RNG_STAT0_LFSR_STAT_A_ILLEGAL 0x1 /* R---V */ #define NV_PNVDEC_SCP_RNG_STAT0_LFSR_STAT_B 13:13 /* R-IVF */ #define NV_PNVDEC_SCP_RNG_STAT0_LFSR_STAT_B_LEGAL 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_RNG_STAT0_LFSR_STAT_B_ILLEGAL 0x1 /* R---V */ #define NV_PNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_A 16:16 /* RWIVF */ #define NV_PNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_A_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_A_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_A_CLEAR 0x1 /* -W--T */ #define NV_PNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_B 20:20 /* RWIVF */ #define NV_PNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_B_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_B_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_B_CLEAR 0x1 /* -W--T */ #define NV_PNVDEC_SCP_RNG_STAT1(dev) (0x00848874+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_RNG_STAT1__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A 15:0 /* R-IUF */ #define NV_PNVDEC_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A_INIT 0x0000 /* R-I-V */ #define NV_PNVDEC_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B 31:16 /* R-IUF */ #define NV_PNVDEC_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B_INIT 0x0000 /* R-I-V */ #define NV_PNVDEC_SCP_INTR(dev) (0x00848880+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_INTR__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_INTR_RAND_READY 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_RAND_READY_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_INTR_RAND_READY_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_INTR_RAND_READY_RESET 0x1 /* -W--C */ #define NV_PNVDEC_SCP_INTR_ACL_VIO 8:8 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_ACL_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_INTR_ACL_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_INTR_ACL_VIO_RESET 0x1 /* -W--C */ #define NV_PNVDEC_SCP_INTR_SECURITY_VIO 12:12 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_SECURITY_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_INTR_SECURITY_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_INTR_SECURITY_VIO_RESET 0x1 /* -W--C */ #define NV_PNVDEC_SCP_INTR_CMD_ERROR 16:16 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_CMD_ERROR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_INTR_CMD_ERROR_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_INTR_CMD_ERROR_RESET 0x1 /* -W--C */ #define NV_PNVDEC_SCP_INTR_STEP 20:20 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_STEP_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_INTR_STEP_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_INTR_STEP_RESET 0x1 /* -W--C */ #define NV_PNVDEC_SCP_INTR_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_RNDHOLDOFF_REQUESTED_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_INTR_RNDHOLDOFF_REQUESTED_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_INTR_RNDHOLDOFF_REQUESTED_RESET 0x1 /* -W--C */ #define NV_PNVDEC_SCP_INTR_STALL_TIMEOUT 28:28 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_STALL_TIMEOUT_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_INTR_STALL_TIMEOUT_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_INTR_STALL_TIMEOUT_RESET 0x1 /* -W--C */ #define NV_PNVDEC_SCP_INTR_EN(dev) (0x00848884+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_INTR_EN__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_INTR_EN_RAND_READY 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_EN_RAND_READY_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_INTR_EN_RAND_READY_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_INTR_EN_ACL_VIO 8:8 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_EN_ACL_VIO_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_INTR_EN_ACL_VIO_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_INTR_EN_SECURITY_VIO 12:12 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_EN_SECURITY_VIO_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_INTR_EN_SECURITY_VIO_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_INTR_EN_CMD_ERROR 16:16 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_EN_CMD_ERROR_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_INTR_EN_CMD_ERROR_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_INTR_EN_STEP 20:20 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_EN_STEP_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_INTR_EN_STEP_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_INTR_EN_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_INTR_EN_STALL_TIMEOUT 28:28 /* RWIVF */ #define NV_PNVDEC_SCP_INTR_EN_STALL_TIMEOUT_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_INTR_EN_STALL_TIMEOUT_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_SCP_ACL_VIO(dev) (0x00848890+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_ACL_VIO__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_ACL_VIO_VIOLATION 31:31 /* R-IVF */ #define NV_PNVDEC_SCP_ACL_VIO_VIOLATION_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_ACL_VIO_VIOLATION_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_ACL_VIO_CHMOD_RELAX_VIO 8:8 /* RWIVF */ #define NV_PNVDEC_SCP_ACL_VIO_CHMOD_RELAX_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_ACL_VIO_CHMOD_RELAX_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_ACL_VIO_CHMOD_RELAX_VIO_CLEAR 0x1 /* -W--T */ #define NV_PNVDEC_SCP_ACL_VIO_FETCH_VIO 4:4 /* RWIVF */ #define NV_PNVDEC_SCP_ACL_VIO_FETCH_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_ACL_VIO_FETCH_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_ACL_VIO_FETCH_VIO_CLEAR 0x1 /* -W--T */ #define NV_PNVDEC_SCP_ACL_VIO_WR_VIO 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_ACL_VIO_WR_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_ACL_VIO_WR_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_ACL_VIO_WR_VIO_CLEAR 0x1 /* -W--T */ #define NV_PNVDEC_SCP_SECURITY_VIO(dev) (0x00848894+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_SECURITY_VIO__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_SECURITY_VIO_VIOLATION 31:31 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_VIOLATION_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_VIOLATION_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_VIO_SC 26:25 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_VIO_SC_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_VIO 24:24 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC 22:21 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO 20:20 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_SECURITY_VIO_FETCH_VIO_SC 18:17 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_FETCH_VIO_SC_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_FETCH_VIO 16:16 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_FETCH_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_FETCH_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC 6:5 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO 4:4 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC 2:1 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO 0:0 /* R-IVF */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO_NOT_PENDING 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR(dev) (0x00848898+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CMD_ERROR__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CMD_ERROR_UNDEFINED 0:0 /* RWIVF */ #define NV_PNVDEC_SCP_CMD_ERROR_UNDEFINED_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CMD_ERROR_UNDEFINED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR_UNDEFINED_CLEAR 0x1 /* -W--C */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_EMPTY 4:4 /* RWIVF */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_EMPTY_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_EMPTY_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_EMPTY_CLEAR 0x1 /* -W--C */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_OVERFLOW 8:8 /* RWIVF */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_OVERFLOW_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_OVERFLOW_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_OVERFLOW_CLEAR 0x1 /* -W--C */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING 12:12 /* RWIVF */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_CLEAR 0x1 /* -W--C */ #define NV_PNVDEC_SCP_CMD_ERROR_SIG_INSECURE 16:16 /* RWIVF */ #define NV_PNVDEC_SCP_CMD_ERROR_SIG_INSECURE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CMD_ERROR_SIG_INSECURE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR_SIG_INSECURE_CLEAR 0x1 /* -W--C */ #define NV_PNVDEC_SCP_CMD_ERROR_SIG_INVALID 20:20 /* RWIVF */ #define NV_PNVDEC_SCP_CMD_ERROR_SIG_INVALID_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CMD_ERROR_SIG_INVALID_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR_SIG_INVALID_CLEAR 0x1 /* -W--C */ #define NV_PNVDEC_SCP_CMD_ERROR_CHMOD_INSECURE 24:24 /* RWIVF */ #define NV_PNVDEC_SCP_CMD_ERROR_CHMOD_INSECURE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CMD_ERROR_CHMOD_INSECURE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR_CHMOD_INSECURE_CLEAR 0x1 /* -W--C */ #define NV_PNVDEC_SCP_CMD_ERROR_SECRET_INSECURE 28:28 /* RWIVF */ #define NV_PNVDEC_SCP_CMD_ERROR_SECRET_INSECURE_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CMD_ERROR_SECRET_INSECURE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CMD_ERROR_SECRET_INSECURE_CLEAR 0x1 /* -W--C */ #define NV_PNVDEC_SCP_RNDCTL0(dev) (0x00848900+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNDCTL0__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL0_HOLDOFF_INIT_LOWER 31:0 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL0_HOLDOFF_INIT_LOWER_INIT 0x01c9c380 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL1(dev) (0x00848904+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNDCTL1__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL1_HOLDOFF_INIT_UPPER 15:0 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL1_HOLDOFF_INIT_UPPER_ZERO 0x0000 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL1_HOLDOFF_INTRA_MASK 31:16 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL1_HOLDOFF_INTRA_MASK_INIT 0xffff /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL2(dev) (0x00848908+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNDCTL2__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL2_COMPRESS_CNT 15:0 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL2_COMPRESS_CNT_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL3(dev) (0x0084890c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNDCTL3__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A 12:12 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_TRIGGER 0x1 /* -W--T */ #define NV_PNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B 16:16 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_INIT 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_TRIGGER 0x1 /* -W--T */ #define NV_PNVDEC_SCP_RNDCTL4(dev) (0x00848910+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_SCP_RNDCTL4__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL4_POLYNOMIAL_A 31:0 /* -WIUF */ #define NV_PNVDEC_SCP_RNDCTL4_POLYNOMIAL_A_INIT 0x80200003 /* -WI-V */ #define NV_PNVDEC_SCP_RNDCTL5(dev) (0x00848914+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_SCP_RNDCTL5__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL5_LFSR_INIT_A 31:0 /* -WIUF */ #define NV_PNVDEC_SCP_RNDCTL5_LFSR_INIT_A_INIT 0xdeadbeef /* -WI-V */ #define NV_PNVDEC_SCP_RNDCTL6(dev) (0x00848918+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_SCP_RNDCTL6__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL6_POLYNOMIAL_B 31:0 /* -WIUF */ #define NV_PNVDEC_SCP_RNDCTL6_POLYNOMIAL_B_INIT 0x80200003 /* -WI-V */ #define NV_PNVDEC_SCP_RNDCTL7(dev) (0x0084891c+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_SCP_RNDCTL7__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL7_LFSR_INIT_B 31:0 /* -WIUF */ #define NV_PNVDEC_SCP_RNDCTL7_LFSR_INIT_B_INIT 0xbeefdead /* -WI-V */ #define NV_PNVDEC_SCP_RNDCTL8(dev) (0x00848920+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNDCTL8__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A 15:0 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B 31:16 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL9(dev) (0x00848924+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNDCTL9__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A 15:0 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B 31:16 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL10(dev) (0x00848928+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNDCTL10__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A 15:0 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A_INIT 0x000f /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B 31:16 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B_INIT 0x000f /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11(dev) (0x0084892c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_RNDCTL11__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_ENABLE 0:0 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE 1:1 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_SYNCH_RAND_A 2:2 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_SYNCH_RAND_A_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_SYNCH_RAND_A_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_SYNCH_RAND_A_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_SYNCH_RAND_B 3:3 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_SYNCH_RAND_B_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_SYNCH_RAND_B_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_SYNCH_RAND_B_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A 5:4 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_OSC 0x0 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_AUTOCAL 0x1 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_LFSR 0x2 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_ZERO 0x3 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B 7:6 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_OSC 0x0 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_AUTOCAL 0x1 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_LFSR 0x2 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_ZERO 0x3 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A 11:8 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A_INIT 0xf /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B 15:12 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B_INIT 0xf /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_MIN_AUTO_TAP 19:16 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_MIN_AUTO_TAP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY 23:20 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY_INIT 0x1 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY 30:24 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_SAFE_MODE 31:31 /* RWIUF */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_CTL_P2PRX(dev) (0x00848930+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_CTL_P2PRX__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_FALLBACK_MODE 0:0 /* R--VF */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_FALSE 0x0 /* R---V */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD 2:2 /* RWIVF */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_IDLE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_PENDING 0x1 /* R---V */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_TASK 0x1 /* -W--T */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_LOADED 3:3 /* R-IVF */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_LOADED_FALSE 0x0 /* R-I-V */ #define NV_PNVDEC_SCP_CTL_P2PRX_SFK_LOADED_TRUE 0x1 /* R---V */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG0(dev) (0x00848940+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG0__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT 15:0 /* R-IVF */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT_INIT 0x0020 /* R-I-V */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA 31:16 /* R-IVF */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA_INIT 0x000f /* R-I-V */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG1(dev) (0x00848944+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG1__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX 31:0 /* R-IVF */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX_INIT 0x00000fff /* R-I-V */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG2(dev) (0x00848948+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG2__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD 31:0 /* R-IVF */ #define NV_PNVDEC_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD_INIT 0x7fffffff /* R-I-V */ #define NV_PNVDEC_SCP_SCC_DEBUG_STAT0(dev) (0x0084894c+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_SCC_DEBUG_STAT0__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_SCC_DEBUG_STAT0_RSEED_TMOUT_CNT 31:0 /* R--VF */ #define NV_PNVDEC_SCP_SCC_DEBUG_STAT1(dev) (0x00848950+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_SCC_DEBUG_STAT1__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_SCC_DEBUG_STAT1_RSEED_BIT_CNT 5:0 /* R--VF */ #define NV_PNVDEC_SCP_SCC_DEBUG_STAT1_RSEED_VALID 8:8 /* R--VF */ #define NV_PNVDEC_SCP_SCC_DEBUG_STAT1_RSEED_TMOUT 9:9 /* R--VF */ #define NV_PNVDEC_SCP_PUBKEYC(dev) (0x00848960+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_SCP_PUBKEYC__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_PUBKEYC_RSA1_N_OFFS 0x00000000 /* */ #define NV_PNVDEC_SCP_PUBKEYC_RSA1_N_SIZE 0x00000180 /* */ #define NV_PNVDEC_SCP_PUBKEYC_RSA1_E_OFFS 0x00000180 /* */ #define NV_PNVDEC_SCP_PUBKEYC_RSA1_E_SIZE 0x00000020 /* */ #define NV_PNVDEC_SCP_PUBKEYC_ECC1_X_OFFS 0x000001a0 /* */ #define NV_PNVDEC_SCP_PUBKEYC_ECC1_X_SIZE 0x00000020 /* */ #define NV_PNVDEC_SCP_PUBKEYC_ECC1_Y_OFFS 0x000001c0 /* */ #define NV_PNVDEC_SCP_PUBKEYC_ECC1_Y_SIZE 0x00000020 /* */ #define NV_PNVDEC_SCP_PUBKEYC_OFFS 9:2 /* RWIVF */ #define NV_PNVDEC_SCP_PUBKEYC_OFFS_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_SCP_PUBKEYC_AINCR 31:31 /* RWIVF */ #define NV_PNVDEC_SCP_PUBKEYC_AINCR_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_PUBKEYC_AINCR_TRUE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_PUBKEYC_AINCR_FALSE 0x0 /* RW--V */ #define NV_PNVDEC_SCP_PUBKEYD(dev) (0x00848964+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_PUBKEYD__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_PUBKEYD_DATA 31:0 /* R--VF */ #define NV_PNVDEC_SCP_PK_ADDR(dev) (0x00848970+(dev)*16384) /* RWI4A */ #define NV_PNVDEC_SCP_PK_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_PK_ADDR_OFFSET 11:0 /* RWIVF */ #define NV_PNVDEC_SCP_PK_ADDR_OFFSET_DEFT 0x000 /* RWI-V */ #define NV_PNVDEC_SCP_PK_ADDR_AINCR 31:31 /* RWIVF */ #define NV_PNVDEC_SCP_PK_ADDR_AINCR_ENABLE 0x1 /* RW--V */ #define NV_PNVDEC_SCP_PK_ADDR_AINCR_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_SCP_PK_DATA(dev) (0x00848974+(dev)*16384) /* R--4A */ #define NV_PNVDEC_SCP_PK_DATA__SIZE_1 2 /* */ #define NV_PNVDEC_SCP_PK_DATA_VAL 31:0 /* R--VF */ #define NV_PNVDEC_GIP_SWREG0(dev) (0x00849400+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG0__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG0_RESET 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG0_RESET_TRUE 0x0 /* RW--V */ #define NV_PNVDEC_GIP_SWREG0_RESET_FALSE 0x1 /* RWI-V */ #define NV_PNVDEC_GIP_SWREG1(dev) (0x00849404+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG1__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG1_DEC_SUBSTREAM_DMA_DONE_INT 22:22 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_SUBSTREAM_DMA_RECFG_E 21:21 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_STRM_PREPARSER_INT 20:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_SLICEDONE_INT 19:19 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_TIMEOUT 18:18 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_ERROR_INT 16:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_DMA_DONE_INT 15:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_RDY_INT 12:12 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_STRM_CFG_E 1:1 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG1_DEC_E 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG2(dev) (0x00849408+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG2__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PZ 23:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PZ_V 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PE 19:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PE_V 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PD 15:12 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PD_V 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PC 11:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PC_V 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PB 7:4 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PB_V 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PA 3:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG2_RETIME_LAT_PA_V 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_SWREG3(dev) (0x0084940c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG3__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG3_DEC_MODE 31:27 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG3_DEC_OUT_RS_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG3_DEC_OUT_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG3_FILTERING_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG3_FILTER_BYPASS 13:13 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG3_WRITE_MVS_E 12:12 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG4(dev) (0x00849410+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG4__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG4_PIC_WIDTH_IN_CBS 31:19 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG4_PIC_HEIGHT_IN_CBS 18:6 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG4_REF_FRAMES 4:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG5(dev) (0x00849414+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG5__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG5_STRM_START_BIT 31:25 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG5_SCALING_LIST_E 24:24 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG5_CH_QP_OFFSET 23:19 /* RWISF */ #define NV_PNVDEC_GIP_SWREG5_CH_QP_OFFSET2 18:14 /* RWISF */ #define NV_PNVDEC_GIP_SWREG5_SIGN_DATA_HIDE 12:12 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG5_TEMPOR_MVP_E 11:11 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG5_MAX_CU_QPD_DEPTH 10:5 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG5_CU_QPD_E 4:4 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG6(dev) (0x00849418+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG6__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG6_STREAM_LEN 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7(dev) (0x0084941c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG7__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG7_CABAC_INIT_PRESENT 31:31 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_BLACKWHITE_E 30:30 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_WEIGHT_PRED_E 28:28 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_WEIGHT_BIPR_IDC 27:26 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_FILT_SLICE_BORDER 25:25 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_FILT_TILE_BORDER 24:24 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_ASYM_PRED_E 23:23 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_SAO_E 22:22 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_PCM_FILT_DISABLE 21:21 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_SLICE_CHQP_FLAG 20:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_DEPEND_SLICE_E 19:19 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_FILT_OVERRIDE_E 18:18 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_STRONG_SMOOTH_E 17:17 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_FILT_OFFSET_BETA 16:12 /* RWISF */ #define NV_PNVDEC_GIP_SWREG7_FILT_OFFSET_TC 11:7 /* RWISF */ #define NV_PNVDEC_GIP_SWREG7_SLICE_HDR_EXT_E 6:6 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG7_SLICE_HDR_EBITS 5:3 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG8(dev) (0x00849420+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG8__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG8_CONST_INTRA_E 31:31 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG8_FILT_CTRL_PRES 30:30 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG8_MAX_EIGHTBITS_E 17:17 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG8_IDR_PIC_E 16:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG8_PCM_BITDEPTH_Y 15:12 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG8_PCM_BITDEPTH_C 11:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG8_BITDEPTH_Y 7:4 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG8_BITDEPTH_C 3:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG9(dev) (0x00849424+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG9__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG9_REFIDX1_ACTIVE 23:19 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG9_REFIDX0_ACTIVE 18:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG9_HDR_SKIP_LENGTH 13:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG10(dev) (0x00849428+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG10__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG10_START_CODE_E 31:31 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG10_NUM_TILE_COLS 26:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG10_NUM_TILE_ROWS 19:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG10_INIT_QP 8:2 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG10_TILE_ENABLE 1:1 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG10_ENTR_CODE_SYNCH_E 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG11(dev) (0x0084942c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG11__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG11_TRANSFORM_MODE 29:27 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG11_FILT_SHARPNESS 23:21 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG11_FILT_TYPE 19:19 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG11_MCOMP_FILT_TYPE 10:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG11_HIGH_PREC_MV_E 7:7 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG11_COMP_PRED_MODE 5:4 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG11_GREF_SIGN_BIAS 2:2 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG11_AREF_SIGN_BIAS 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12(dev) (0x00849430+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG12__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG12_REFER_LTERM_E 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12_MIN_CB_SIZE 15:13 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12_MAX_CB_SIZE 12:10 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12_MIN_PCM_SIZE 9:7 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12_MAX_PCM_SIZE 6:4 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12_PCM_E 3:3 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12_TRANSFORM_SKIP_E 2:2 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12_TRANSQ_BYPASS_E 1:1 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG12_REFPICLIST_MOD_E 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13(dev) (0x00849434+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG13__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG13_MIN_TRB_SIZE 15:13 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_MAX_TRB_SIZE 12:10 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_MAX_INTRA_HIERDEPTH 9:7 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_MAX_INTER_HIERDEPTH 6:4 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_PARALLEL_MERGE 3:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_QP_DELTA_Y_DC 28:23 /* RWISF */ #define NV_PNVDEC_GIP_SWREG13_QP_DELTA_CH_DC 22:17 /* RWISF */ #define NV_PNVDEC_GIP_SWREG13_QP_DELTA_CH_AC 16:11 /* RWISF */ #define NV_PNVDEC_GIP_SWREG13_LAST_SIGN_BIAS 10:10 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_LOSSLESS_E 9:9 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_COMP_PRED_VAR_REF1 8:7 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_COMP_PRED_VAR_REF0 6:5 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_COMP_PRED_FIXED_REF 4:3 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_SEGMENT_TEMP_UPD_E 2:2 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_SEGMENT_UPD_E 1:1 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG13_SEGMENT_E 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14(dev) (0x00849438+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG14__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG14_INIT_RLIST_B2 29:25 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_INIT_RLIST_F2 24:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_INIT_RLIST_B1 19:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_INIT_RLIST_F1 14:10 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_INIT_RLIST_B0 9:5 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_INIT_RLIST_F0 4:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_FILT_LEVEL 23:18 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_REFPIC_SEG0 17:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_SKIP_SEG0 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_FILT_LEVEL_SEG0 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG14_QUANT_SEG0 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15(dev) (0x0084943c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG15__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG15_INIT_RLIST_B5 29:25 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_INIT_RLIST_F5 24:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_INIT_RLIST_B4 19:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_INIT_RLIST_F4 14:10 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_INIT_RLIST_B3 9:5 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_INIT_RLIST_F3 4:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_REFPIC_SEG1 17:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_SKIP_SEG1 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_FILT_LEVEL_SEG1 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG15_QUANT_SEG1 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16(dev) (0x00849440+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG16__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG16_INIT_RLIST_B8 29:25 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_INIT_RLIST_F8 24:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_INIT_RLIST_B7 19:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_INIT_RLIST_F7 14:10 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_INIT_RLIST_B6 9:5 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_INIT_RLIST_F6 4:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_REFPIC_SEG2 17:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_SKIP_SEG2 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_FILT_LEVEL_SEG2 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG16_QUANT_SEG2 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17(dev) (0x00849444+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG17__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG17_INIT_RLIST_B11 29:25 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_INIT_RLIST_F11 24:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_INIT_RLIST_B10 19:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_INIT_RLIST_F10 14:10 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_INIT_RLIST_B9 9:5 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_INIT_RLIST_F9 4:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_REFPIC_SEG3 17:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_SKIP_SEG3 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_FILT_LEVEL_SEG3 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG17_QUANT_SEG3 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18(dev) (0x00849448+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG18__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG18_INIT_RLIST_B14 29:25 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_INIT_RLIST_F14 24:20 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_INIT_RLIST_B13 19:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_INIT_RLIST_F13 14:10 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_INIT_RLIST_B12 9:5 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_INIT_RLIST_F12 4:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_REFPIC_SEG4 17:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_SKIP_SEG4 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_FILT_LEVEL_SEG4 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG18_QUANT_SEG4 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG19(dev) (0x0084944c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG19__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG19_INIT_RLIST_B15 9:5 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG19_INIT_RLIST_F15 4:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG19_REFPIC_SEG5 17:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG19_SKIP_SEG5 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG19_FILT_LEVEL_SEG5 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG19_QUANT_SEG5 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG20(dev) (0x00849450+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG20__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG20_PARTIAL_CTB_X 31:31 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG20_PARTIAL_CTB_Y 30:30 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG20_PIC_WIDTH_4X4 27:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG20_PIC_HEIGHT_4X4 11:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG21(dev) (0x00849454+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG21__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG21_EXTERNAL_REF_MEM_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG21_SW_SKIP_START_LENGTH 13:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG29(dev) (0x00849474+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG29__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG29_IS_H264_DUP3 15:15 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_H264_DUP2 14:14 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_H264_DUP1 13:13 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_H264_DUP0 12:12 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_AV1_DUP3 11:11 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_AV1_DUP2 10:10 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_AV1_DUP1 9:9 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_AV1_DUP0 8:8 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_VP9_DUP3 7:7 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_VP9_DUP2 6:6 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_VP9_DUP1 5:5 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_VP9_DUP0 4:4 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_HEVC_DUP3 3:3 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_HEVC_DUP2 2:2 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_HEVC_DUP1 1:1 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG29_IS_HEVC_DUP0 0:0 /* RW-VF */ #define NV_PNVDEC_GIP_SWREG31(dev) (0x0084947c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG31__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG31_REFPIC_SEG6 17:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG31_SKIP_SEG6 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG31_FILT_LEVEL_SEG6 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG31_QUANT_SEG6 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG32(dev) (0x00849480+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG32__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG32_REFPIC_SEG7 17:15 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG32_SKIP_SEG7 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG32_FILT_LEVEL_SEG7 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG32_QUANT_SEG7 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG33(dev) (0x00849484+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG33__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG33_LREF_WIDTH 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG33_LREF_HEIGHT 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG34(dev) (0x00849488+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG34__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG34_GREF_WIDTH 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG34_GREF_HEIGHT 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG35(dev) (0x0084948c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG35__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG35_AREF_WIDTH 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG35_AREF_HEIGHT 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG36(dev) (0x00849490+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG36__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG36_LREF_HOR_SCALE 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG36_LREF_VER_SCALE 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG37(dev) (0x00849494+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG37__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG37_GREF_HOR_SCALE 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG37_GREF_VER_SCALE 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG38(dev) (0x00849498+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG38__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG38_AREF_HOR_SCALE 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG38_AREF_VER_SCALE 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG46(dev) (0x008494b8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG46__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG46_CUR_POC_00 31:24 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG46_CUR_POC_01 23:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG46_CUR_POC_02 15:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG46_CUR_POC_03 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG46_FILT_REF_ADJ_0 30:24 /* RWISF */ #define NV_PNVDEC_GIP_SWREG46_FILT_REF_ADJ_1 22:16 /* RWISF */ #define NV_PNVDEC_GIP_SWREG46_FILT_REF_ADJ_2 14:8 /* RWISF */ #define NV_PNVDEC_GIP_SWREG46_FILT_REF_ADJ_3 6:0 /* RWISF */ #define NV_PNVDEC_GIP_SWREG47(dev) (0x008494bc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG47__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG47_CUR_POC_04 31:24 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG47_CUR_POC_05 23:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG47_CUR_POC_06 15:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG47_CUR_POC_07 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG47_FILT_MB_ADJ_0 30:24 /* RWISF */ #define NV_PNVDEC_GIP_SWREG47_FILT_MB_ADJ_1 22:16 /* RWISF */ #define NV_PNVDEC_GIP_SWREG47_FILT_MB_ADJ_2 14:8 /* RWISF */ #define NV_PNVDEC_GIP_SWREG47_FILT_MB_ADJ_3 6:0 /* RWISF */ #define NV_PNVDEC_GIP_SWREG48(dev) (0x008494c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG48__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG48_CUR_POC_08 31:24 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG48_CUR_POC_09 23:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG48_CUR_POC_10 15:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG48_CUR_POC_11 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG49(dev) (0x008494c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG49__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG49_CUR_POC_12 31:24 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG49_CUR_POC_13 23:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG49_CUR_POC_14 15:8 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG49_CUR_POC_15 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG55(dev) (0x008494dc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG55__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG55_APF_DISABLE 31:31 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG55_APF_SINGLE_PU_MODE 30:30 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG55_APF_THRESHOLD 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_STATUS0(dev) (0x008494f4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_GIP_STATUS0__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STATUS0_OUTPUT_CTB_COUNT 31:0 /* R-IVF */ #define NV_PNVDEC_GIP_STATUS0_OUTPUT_CTB_COUNT_INIT 0x00000000 /* R-I-V */ #define NV_PNVDEC_GIP_SWREG62(dev) (0x008494f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG62__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG62_CU_PIXEL_START_X 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG62_CU_PIXEL_START_Y 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG63(dev) (0x008494fc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG63__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG63_RUNTIME_CYCLES 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG64(dev) (0x00849500+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG64__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG64_DEC_OUT_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG66(dev) (0x00849508+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG66__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG66_REFER0_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG68(dev) (0x00849510+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG68__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG68_REFER1_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG70(dev) (0x00849518+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG70__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG70_REFER2_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG72(dev) (0x00849520+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG72__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG72_REFER3_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG74(dev) (0x00849528+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG74__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG74_REFER4_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG76(dev) (0x00849530+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG76__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG76_REFER5_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG78(dev) (0x00849538+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG78__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG78_REFER6_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG78_SEGMENT_WRITE_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG80(dev) (0x00849540+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG80__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG80_REFER7_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG80_SEGMENT_READ_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG82(dev) (0x00849548+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG82__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG82_REFER8_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG84(dev) (0x00849550+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG84__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG84_REFER9_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG86(dev) (0x00849558+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG86__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG86_REFER10_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG88(dev) (0x00849560+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG88__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG88_REFER11_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG90(dev) (0x00849568+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG90__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG90_REFER12_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG92(dev) (0x00849570+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG92__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG92_REFER13_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG94(dev) (0x00849578+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG94__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG94_REFER14_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG96(dev) (0x00849580+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG96__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG96_REFER15_YBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG98(dev) (0x00849588+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG98__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG98_DEC_OUT_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG100(dev) (0x00849590+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG100__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG100_REFER0_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG102(dev) (0x00849598+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG102__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG102_REFER1_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG104(dev) (0x008495a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG104__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG104_REFER2_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG106(dev) (0x008495a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG106__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG106_REFER3_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG108(dev) (0x008495b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG108__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG108_REFER4_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG110(dev) (0x008495b8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG110__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG110_REFER5_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG112(dev) (0x008495c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG112__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG112_REFER6_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG114(dev) (0x008495c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG114__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG114_REFER7_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG116(dev) (0x008495d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG116__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG116_REFER8_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG118(dev) (0x008495d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG118__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG118_REFER9_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG120(dev) (0x008495e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG120__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG120_REFER10_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG122(dev) (0x008495e8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG122__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG122_REFER11_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG124(dev) (0x008495f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG124__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG124_REFER12_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG126(dev) (0x008495f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG126__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG126_REFER13_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG128(dev) (0x00849600+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG128__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG128_REFER14_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG130(dev) (0x00849608+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG130__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG130_REFER15_CBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG132(dev) (0x00849610+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG132__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG132_DEC_OUT_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG134(dev) (0x00849618+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG134__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG134_REFER0_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG136(dev) (0x00849620+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG136__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG136_REFER1_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG138(dev) (0x00849628+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG138__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG138_REFER2_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG140(dev) (0x00849630+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG140__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG140_REFER3_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG142(dev) (0x00849638+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG142__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG142_REFER4_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG144(dev) (0x00849640+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG144__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG144_REFER5_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG146(dev) (0x00849648+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG146__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG146_REFER6_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG148(dev) (0x00849650+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG148__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG148_REFER7_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG150(dev) (0x00849658+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG150__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG150_REFER8_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG152(dev) (0x00849660+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG152__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG152_REFER9_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG154(dev) (0x00849668+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG154__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG154_REFER10_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG156(dev) (0x00849670+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG156__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG156_REFER11_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG158(dev) (0x00849678+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG158__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG158_REFER12_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG160(dev) (0x00849680+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG160__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG160_REFER13_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG162(dev) (0x00849688+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG162__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG162_REFER14_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG164(dev) (0x00849690+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG164__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG164_REFER15_DBASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG166(dev) (0x00849698+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG166__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG166_TILE_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG168(dev) (0x008496a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG168__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG168_STREAM_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG170(dev) (0x008496a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG170__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG170_SCALE_LIST_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG170_CTX_COUNTER_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG172(dev) (0x008496b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG172__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG172_PROB_TAB_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG178(dev) (0x008496c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG178__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG178_DEC_VERT_FILT_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG180(dev) (0x008496d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG180__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG180_DEC_VERT_SAO_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SWREG182(dev) (0x008496d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SWREG182__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SWREG182_DEC_BSD_CTRL_BASE_MSB 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SURFACE_CTL(dev) (0x008497c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SURFACE_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SURFACE_CTL_BITDEPTH 6:5 /* RWIVF */ #define NV_PNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT 4:2 /* RWIVF */ #define NV_PNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_2 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_4 0x1 /* RW--V */ #define NV_PNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_8 0x2 /* RW--V */ #define NV_PNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_16 0x3 /* RW--V */ #define NV_PNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_32 0x4 /* RW--V */ #define NV_PNVDEC_GIP_SURFACE_CTL_TILE_FORMAT 1:0 /* RWIVF */ #define NV_PNVDEC_GIP_SURFACE_CTL_TILE_FORMAT_TBL 0x0 /* RW--V */ #define NV_PNVDEC_GIP_SURFACE_CTL_TILE_FORMAT_KBL 0x1 /* RWI-V */ #define NV_PNVDEC_GIP_SURFACE_STRIDE(dev) (0x008497c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SURFACE_STRIDE__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_LUMA 12:0 /* RW-VF */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_CHROMA 28:16 /* RW-VF */ #define NV_PNVDEC_GIP_SECURE(dev) (0x008497c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SECURE__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SECURE_OTF_EN 0:0 /* RW-VF */ #define NV_PNVDEC_GIP_SECURE_FLUSH_SA 1:1 /* RW-VF */ #define NV_PNVDEC_GIP_SECURE_CHUNK_SZ_SA 6:2 /* RW-VF */ #define NV_PNVDEC_GIP_SECURE_SSM_EN 7:7 /* RWIVF */ #define NV_PNVDEC_GIP_SECURE_SSM_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_GIP_SECURE_SSM_EN_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_SECURE_OTF_HALT_REQ 8:8 /* RW-VF */ #define NV_PNVDEC_GIP_SECURE_OTF_HALT_DONE 9:9 /* RW-VF */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF0(dev) (0x008497cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF0__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF0_LUMA 11:0 /* RW-VF */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF0_CHROMA 27:16 /* RW-VF */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF1(dev) (0x008497d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF1__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF1_LUMA 11:0 /* RW-VF */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF1_CHROMA 27:16 /* RW-VF */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF2(dev) (0x008497d4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF2__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF2_LUMA 11:0 /* RW-VF */ #define NV_PNVDEC_GIP_SURFACE_STRIDE_REF2_CHROMA 27:16 /* RW-VF */ #define NV_PNVDEC_GIP_CAP_REG0(dev) (0x008497d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_CAP_REG0__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_CAP_REG0_VP9 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_CAP_REG0_VP9_DISABLED 0x0 /* RW--V */ #define NV_PNVDEC_GIP_CAP_REG0_VP9_ENABLED 0x1 /* RWI-V */ #define NV_PNVDEC_GIP_RDY_DELAY(dev) (0x008497dc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_RDY_DELAY__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_RDY_DELAY_V 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_RDY_DELAY_V_RSTVAL 0x0000007f /* RWI-V */ #define NV_PNVDEC_GIP_TIMEOUT_REG(dev) (0x008497e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_TIMEOUT_REG__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_TIMEOUT_REG_V 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_TIMEOUT_REG_V_RSTVAL 0x10000000 /* RWI-V */ #define NV_PNVDEC_GIP_INTR_MASK(dev) (0x008497ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_INTR_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_SUBSTREAM_DMA_DONE_INT 22:22 /* RWIVF */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_SUBSTREAM_DMA_DONE_INT_RSTVAL 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_TIMEOUT 18:18 /* RWIVF */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_TIMEOUT_RSTVAL 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_ERROR_INT 16:16 /* RWIVF */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_ERROR_INT_RSTVAL 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_DMA_DONE_INT 15:15 /* RWIVF */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_DMA_DONE_INT_RSTVAL 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_RDY_INT 12:12 /* RWIVF */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_RDY_INT_RSTVAL 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_E 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_INTR_MASK_DEC_E_RSTVAL 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_P444_SPS_EXT(dev) (0x00849458+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_P444_SPS_EXT__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_P444_SPS_EXT_CHROMA_FORMAT_IDC 1:0 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_SKIP_ROTATION_EN 2:2 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_SKIP_CONTEXT_EN 3:3 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_IBC_EN 4:4 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_IMPL_RDPCM_EN 5:5 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_EXPL_RDPCM_EN 6:6 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_EXT_PRECISION_EN 7:7 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_INTRA_SMOOTH_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_HIGH_PRECISION_OFFSET_EN 9:9 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_FAST_RICE_ADAPT_EN 10:10 /* RWIVF */ #define NV_PNVDEC_GIP_P444_SPS_EXT_CABAC_BYPASS_ALIGN_EN 11:11 /* RWIVF */ #define NV_PNVDEC_GIP_P444_PPS_EXT(dev) (0x0084945c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_P444_PPS_EXT__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_P444_PPS_EXT_MAX_TRANSFORM_SKIP_SIZE 3:0 /* RWIVF */ #define NV_PNVDEC_GIP_P444_PPS_EXT_CROSS_COMPONENT_PRED_EN 4:4 /* RWIVF */ #define NV_PNVDEC_GIP_P444_PPS_EXT_SAO_OFFSET_SCALE_LUMA 7:5 /* RWIVF */ #define NV_PNVDEC_GIP_P444_PPS_EXT_SAO_OFFSET_SCALE_CHROMA 10:8 /* RWIVF */ #define NV_PNVDEC_GIP_P444_PPS_QP_EXT(dev) (0x00849460+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_P444_PPS_QP_EXT__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_P444_PPS_QP_EXT_ADJ_EN 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_P444_PPS_QP_EXT_ADJ_DEPTH 3:1 /* RWIVF */ #define NV_PNVDEC_GIP_P444_PPS_QP_EXT_ADJ_TABLE_SIZE 6:4 /* RWIVF */ #define NV_PNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE(dev) (0x00849464+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_0 4:0 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_1 9:5 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_2 14:10 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_3 19:15 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_4 24:20 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_5 29:25 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE(dev) (0x00849468+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_0 4:0 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_1 9:5 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_2 14:10 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_3 19:15 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_4 24:20 /* RWISF */ #define NV_PNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_5 29:25 /* RWISF */ #define NV_PNVDEC_GIP_FILTER_TOP_BUFFER(dev) (0x0084946c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_FILTER_TOP_BUFFER__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_FILTER_TOP_BUFFER_OFFSET 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_SAO_TOP_BUFFER(dev) (0x00849470+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SAO_TOP_BUFFER__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SAO_TOP_BUFFER_OFFSET 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_HW_CTB_POS(dev) (0x008496f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_HW_CTB_POS__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_HW_CTB_POS_STARTY 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_HW_CTB_POS_STARTX 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_HW_SLICE_POS(dev) (0x008496f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_HW_SLICE_POS__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_HW_SLICE_POS_STARTY 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_HW_SLICE_POS_STARTX 31:16 /* RWIVF */ #define NV_PNVDEC_GIP_ERR_CONCEAL_CTRL(dev) (0x008496f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_ERR_CONCEAL_CTRL__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_ERR_CONCEAL_CTRL_ON 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_ERR_CONCEAL_CTRL_RECOV_START_POS 2:1 /* RWIVF */ #define NV_PNVDEC_GIP_ERR_CONCEAL_CTRL_HEVC_STRM_END_CYA 3:3 /* RWIVF */ #define NV_PNVDEC_GIP_ERR_CONCEAL_CTRL_HEVC_STRM_END_CYA_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_ERR_CONCEAL_CTRL_HEVC_STRM_END_CYA_ON 0x1 /* RW--V */ #define NV_PNVDEC_GIP_ERR_MASK0(dev) (0x008496fc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_ERR_MASK0__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_ERR_MASK0_FIELD 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_ERR_MASK1(dev) (0x00849700+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_ERR_MASK1__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_ERR_MASK1_FIELD 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_ERR_INFO(dev) (0x00849704+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_ERR_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_ERR_INFO_TYPE_FIELD 15:0 /* RWIVF */ #define NV_PNVDEC_GIP_ERR_INFO_HINT 19:16 /* RWIVF */ #define NV_PNVDEC_GIP_REAL_STREAM_LEN(dev) (0x00849708+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_REAL_STREAM_LEN__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_REAL_STREAM_LEN_VALUE 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_INTRA_BLK_CNT(dev) (0x00849720+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_STAT_INTRA_BLK_CNT__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STAT_INTRA_BLK_CNT_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_INTER_BLK_CNT(dev) (0x00849724+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_STAT_INTER_BLK_CNT__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STAT_INTER_BLK_CNT_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_SKIP_BLK_CNT(dev) (0x00849728+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_STAT_SKIP_BLK_CNT__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STAT_SKIP_BLK_CNT_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_FWD_MVX_ABS_SUM(dev) (0x0084972c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_STAT_FWD_MVX_ABS_SUM__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STAT_FWD_MVX_ABS_SUM_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_FWD_MVY_ABS_SUM(dev) (0x00849730+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_STAT_FWD_MVY_ABS_SUM__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STAT_FWD_MVY_ABS_SUM_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_BWD_MVX_ABS_SUM(dev) (0x00849734+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_STAT_BWD_MVX_ABS_SUM__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STAT_BWD_MVX_ABS_SUM_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_BWD_MVY_ABS_SUM(dev) (0x00849738+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_STAT_BWD_MVY_ABS_SUM__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STAT_BWD_MVY_ABS_SUM_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_MV_HEVC_CFG(dev) (0x0084973c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_MV_HEVC_CFG__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_ENABLE 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_ENABLE_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_NUH_LAYER_ID 6:1 /* RWIVF */ #define NV_PNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_DEFAULT_REF_LAYERS_ACTIVE_FLAG 7:7 /* RWIVF */ #define NV_PNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_NUM_DIRECT_REF_LAYERS 13:8 /* RWIVF */ #define NV_PNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_MAX_ONE_ACTIVE_REF_LAYER_FLAG 14:14 /* RWIVF */ #define NV_PNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_NUM_ACTIVE_REF_LAYER_PICS 20:15 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG(dev) (0x0084949c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_DEC_EN 0:0 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_DEC_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_FIRST_SLICE_FLAG 1:1 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_LAST_SLICE_FLAG 2:2 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_EC_EN 3:3 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_EC_EN_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_ERROR_SLICE_FLAG 4:4 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_CTX_SAVE_FLAG 5:5 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_CTX_RESTORE_FLAG 6:6 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_DO_SLICE_EC 7:7 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_DO_SLICE_EC_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_EC_MV_TYPE 9:8 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_EC_SLICE_TYPE 11:10 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_STRM_RECFG_EN 12:12 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_CTB_COUNT(dev) (0x008494a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_HEVC_SLICE_CTB_COUNT__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_HEVC_SLICE_CTB_COUNT_VAL 19:0 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_BS_OFFSET(dev) (0x008494a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_HEVC_SLICE_BS_OFFSET__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_HEVC_SLICE_BS_OFFSET_VAL 31:0 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO1(dev) (0x008494a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO1__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO1_TILEWIDTH 9:0 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO1_TILEHEIGHT 19:10 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO1_TILECOL 24:20 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO1_TILEROW 29:25 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO2(dev) (0x008494ac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO2__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO2_TILE_START_POSX 9:0 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO2_TILE_START_POSY 19:10 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO2_TILE_INDEX 28:20 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO3(dev) (0x008494b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO3__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO3_CTBX_IN_TILE 9:0 /* RWIVF */ #define NV_PNVDEC_GIP_HEVC_SLICE_TILEINFO3_CTBY_IN_TILE 19:10 /* RWIVF */ #define NV_PNVDEC_GIP_SLICE_START_ADDR(dev) (0x008496ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_SLICE_START_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_SLICE_START_ADDR_VAL 19:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_MV_ABS_SUM_EXT(dev) (0x0084971c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_GIP_STAT_MV_ABS_SUM_EXT__SIZE_1 2 /* */ #define NV_PNVDEC_GIP_STAT_MV_ABS_SUM_EXT_FWD_MVX 7:0 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_MV_ABS_SUM_EXT_FWD_MVY 15:8 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_MV_ABS_SUM_EXT_BWD_MVX 23:16 /* RWIVF */ #define NV_PNVDEC_GIP_STAT_MV_ABS_SUM_EXT_BWD_MVY 31:24 /* RWIVF */ #define NV_PNVDEC_AVD_SWREG0(dev) (0x00849800+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG0__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG0_SB_SIZE 0:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ALLOW_FILTER_INTRA 1:1 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ENABLE_INTRA_EDGE_FILTER 2:2 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ALLOW_INTERINTRA 3:3 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ALLOW_MASKED_COMPOUND 4:4 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ENABLE_DUAL_FILTER 5:5 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ENABLE_JNT_COMP 6:6 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ENABLE_CDEF 8:8 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_PIC_TYPE 10:10 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_DISABLE_CDF_UPDATE 11:11 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ALLOW_SCREEN_CONTENT_TOOLS 12:12 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_FORCE_INTEGER_MV 13:13 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_ALLOW_INTRABC 14:14 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_SWITCHABLE_MOTION_MODE 15:15 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_TEMPORAL_MV_E 16:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_DELTA_Q_PRESENT 17:17 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_DELTA_Q_RES_LOG 19:18 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_DELTA_LF_PRESENT 20:20 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_DELTA_LF_MULTI 21:21 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_DELTA_LF_RES_LOG 23:22 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_USE_TEMPORAL0_MVS 24:24 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_USE_TEMPORAL1_MVS 25:25 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_USE_TEMPORAL2_MVS 26:26 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_REF_SCALING_ENABLE 27:27 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_HYBRID_PRED_ENABLE 28:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_COMP_PRED_ONLY 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_SHOW_FRAME 30:30 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG0_SKIP_MODE_FLAG 31:31 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1(dev) (0x00849804+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG1__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG1_SKIP_REF0 3:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_SKIP_REF1 7:4 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_PRESKIP_SEGID 8:8 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_LAST_ACTIVE_SEG 11:9 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_REDUCED_TX_SET_USED 12:12 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_AV1_TILE_ENABLE 13:13 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_DEC_STREAM_ERROR_DETECTION 16:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_DEC_MV_ERROR_DETECTION 17:17 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_DEC_COEFF_ERROR_DETECTION 18:18 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_MONOCHROME 20:20 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_USE_TEMPORAL3_MVS 21:21 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_ALLOW_WARP 23:23 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_ENABLE_HISTOGRAM 26:26 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_RCACHE_DISABLE 27:27 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_SECONDARY_OUTPUT_E 28:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_TILE_TRANSPOSE 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG1_SUBSTREAM_MODE_E 30:30 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG2(dev) (0x00849808+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG2__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG2_TEMPORAL_READ_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG3(dev) (0x0084980c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG3__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG3_TEMPORAL1_READ_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG4(dev) (0x00849810+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG4__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG4_TEMPORAL2_READ_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG5(dev) (0x00849814+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG5__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG5_TEMPORAL3_READ_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG6(dev) (0x00849818+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG6__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG6_TEMPORAL_WRITE_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG7(dev) (0x0084981c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG7__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG7_AV1_SEGMENT_READ_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG8(dev) (0x00849820+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG8__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG8_AV1_SEGMENT_WRITE_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG9(dev) (0x00849824+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG9__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG9_GLOBAL_MODEL_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG10(dev) (0x00849828+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG10__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG10_PROB_TABLE_WRITE_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG11(dev) (0x0084982c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG11__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG11_AV1_PIC_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG11_AV1_PIC_HEIGHT 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG12(dev) (0x00849830+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG12__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG12_SUPERRES_PIC_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG12_SUPERRES_IS_SCALED 16:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG12_SCALE_DENOM_MINUS9 19:17 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG12_AV1_PIC_WIDTH_PAD 22:20 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG12_AV1_PIC_HEIGHT_PAD 25:23 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG13(dev) (0x00849834+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG13__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG13_QUANT_BASE_QINDEX 7:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG13_QUANT_DELTA_Y_DC 14:8 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG13_QUANT_DELTA_UV_DC 21:15 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG13_QUANT_DELTA_UV_AC 28:22 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG14(dev) (0x00849838+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG14__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG14_QUANT_DELTA_V_DC 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG14_QUANT_DELTA_V_AC 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG14_QMLEVEL_Y 17:14 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG14_QMLEVEL_U 21:18 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG14_QMLEVEL_V 25:22 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG15(dev) (0x0084983c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG15__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG15_BASE_LF_LEVEL_0 5:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG15_BASE_LF_LEVEL_1 11:6 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG15_BASE_LF_LEVEL_2 17:12 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG15_BASE_LF_LEVEL_3 23:18 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG16(dev) (0x00849840+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG16__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG16_FILT_REF0_DELTA 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG16_FILT_REF1_DELTA 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG16_FILT_REF2_DELTA 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG16_FILT_REF3_DELTA 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG17(dev) (0x00849844+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG17__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG17_FILT_REF4_DELTA 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG17_FILT_REF5_DELTA 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG17_FILT_REF6_DELTA 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG17_FILT_REF7_DELTA 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG18(dev) (0x00849848+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG18__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG18_FILT_MODE0_DELTA 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG18_FILT_MODE1_DELTA 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG18_SEG_QUANT_SIGN 23:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG19(dev) (0x0084984c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG19__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG19_REF0_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG19_REF0_HEIGHT 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG20(dev) (0x00849850+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG20__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG20_REF1_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG20_REF1_HEIGHT 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG21(dev) (0x00849854+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG21__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG21_REF2_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG21_REF2_HEIGHT 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG22(dev) (0x00849858+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG22__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG22_REF3_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG22_REF3_HEIGHT 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG23(dev) (0x0084985c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG23__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG23_REF4_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG23_REF4_HEIGHT 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG24(dev) (0x00849860+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG24__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG24_REF5_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG24_REF5_HEIGHT 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG25(dev) (0x00849864+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG25__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG25_REF6_WIDTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG25_REF6_HEIGHT 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG26(dev) (0x00849868+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG26__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG26_SURFACE_STRIDE_REF3_LUMA 11:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG26_SURFACE_STRIDE_REF3_CHROMA 27:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG27(dev) (0x0084986c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG27__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG27_SURFACE_STRIDE_REF4_LUMA 11:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG27_SURFACE_STRIDE_REF4_CHROMA 27:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG28(dev) (0x00849870+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG28__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG28_SURFACE_STRIDE_REF5_LUMA 11:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG28_SURFACE_STRIDE_REF5_CHROMA 27:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG29(dev) (0x00849874+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG29__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG29_SURFACE_STRIDE_REF6_LUMA 11:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG29_SURFACE_STRIDE_REF6_CHROMA 27:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG30(dev) (0x00849878+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG30__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG30_AV1_TILE_COLS 7:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG30_AV1_TILE_ROWS 15:8 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG30_CDEF_DAMPING 17:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG30_CDEF_BITS 19:18 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG30_LR_TYPE 25:20 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG30_LR_UNIT_SIZE 31:26 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG31(dev) (0x0084987c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG31__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG31_CDEF_LUMA_PRIMARY_STRENGTH 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG32(dev) (0x00849880+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG32__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG32_CDEF_CHROMA_PRIMARY_STRENGTH 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG33(dev) (0x00849884+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG33__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG33_CDEF_LUMA_SECONDARY_STRENGTH 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG33_CDEF_CHROMA_SECONDARY_STRENGTH 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34(dev) (0x00849888+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG34__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG34_REF0_GM_MODE 1:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF1_GM_MODE 3:2 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF2_GM_MODE 5:4 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF3_GM_MODE 7:6 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF4_GM_MODE 9:8 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF5_GM_MODE 11:10 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF6_GM_MODE 13:12 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF0_SIGN_BIAS 14:14 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF1_SIGN_BIAS 15:15 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF2_SIGN_BIAS 16:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF3_SIGN_BIAS 17:17 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF4_SIGN_BIAS 18:18 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF5_SIGN_BIAS 19:19 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG34_REF6_SIGN_BIAS 20:20 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG35(dev) (0x0084988c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG35__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG35_REF0_HOR_SCALE 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG35_REF0_VER_SCALE 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG36(dev) (0x00849890+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG36__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG36_REF1_HOR_SCALE 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG36_REF1_VER_SCALE 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG37(dev) (0x00849894+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG37__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG37_REF2_HOR_SCALE 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG37_REF2_VER_SCALE 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG38(dev) (0x00849898+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG38__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG38_REF3_HOR_SCALE 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG38_REF3_VER_SCALE 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG39(dev) (0x0084989c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG39__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG39_REF4_HOR_SCALE 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG39_REF4_VER_SCALE 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG40(dev) (0x008498a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG40__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG40_REF5_HOR_SCALE 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG40_REF5_VER_SCALE 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG41(dev) (0x008498a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG41__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG41_REF6_HOR_SCALE 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG41_REF6_VER_SCALE 31:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG42(dev) (0x008498a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG42__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG42_FILT_LEVEL_DELTA0_SEG0 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG42_FILT_LEVEL_DELTA0_SEG1 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG42_FILT_LEVEL_DELTA0_SEG2 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG42_FILT_LEVEL_DELTA0_SEG3 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG42_AV1_REFPIC_SEG0 31:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG43(dev) (0x008498ac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG43__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG43_FILT_LEVEL_DELTA0_SEG4 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG43_FILT_LEVEL_DELTA0_SEG5 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG43_FILT_LEVEL_DELTA0_SEG6 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG43_FILT_LEVEL_DELTA0_SEG7 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG43_AV1_REFPIC_SEG1 31:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG44(dev) (0x008498b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG44__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG44_FILT_LEVEL_DELTA1_SEG0 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG44_FILT_LEVEL_DELTA1_SEG1 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG44_FILT_LEVEL_DELTA1_SEG2 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG44_FILT_LEVEL_DELTA1_SEG3 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG44_AV1_REFPIC_SEG2 31:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG45(dev) (0x008498b4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG45__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG45_FILT_LEVEL_DELTA1_SEG4 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG45_FILT_LEVEL_DELTA1_SEG5 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG45_FILT_LEVEL_DELTA1_SEG6 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG45_FILT_LEVEL_DELTA1_SEG7 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG45_AV1_REFPIC_SEG3 31:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG46(dev) (0x008498b8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG46__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG46_FILT_LEVEL_DELTA2_SEG0 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG46_FILT_LEVEL_DELTA2_SEG1 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG46_FILT_LEVEL_DELTA2_SEG2 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG46_FILT_LEVEL_DELTA2_SEG3 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG46_AV1_REFPIC_SEG4 31:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG47(dev) (0x008498bc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG47__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG47_FILT_LEVEL_DELTA2_SEG4 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG47_FILT_LEVEL_DELTA2_SEG5 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG47_FILT_LEVEL_DELTA2_SEG6 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG47_FILT_LEVEL_DELTA2_SEG7 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG47_AV1_REFPIC_SEG5 31:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG48(dev) (0x008498c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG48__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG48_FILT_LEVEL_DELTA3_SEG0 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG48_FILT_LEVEL_DELTA3_SEG1 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG48_FILT_LEVEL_DELTA3_SEG2 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG48_FILT_LEVEL_DELTA3_SEG3 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG48_GLOBAL_MV_SEG0 28:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG48_GLOBAL_MV_SEG1 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG48_GLOBAL_MV_SEG2 30:30 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG48_GLOBAL_MV_SEG3 31:31 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG49(dev) (0x008498c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG49__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG49_FILT_LEVEL_DELTA3_SEG4 6:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG49_FILT_LEVEL_DELTA3_SEG5 13:7 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG49_FILT_LEVEL_DELTA3_SEG6 20:14 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG49_FILT_LEVEL_DELTA3_SEG7 27:21 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG49_GLOBAL_MV_SEG4 28:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG49_GLOBAL_MV_SEG5 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG49_GLOBAL_MV_SEG6 30:30 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG49_GLOBAL_MV_SEG7 31:31 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG50(dev) (0x008498c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG50__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG50_CUR_LAST_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG50_CUR_LAST2_OFFSET 17:9 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG50_CUR_LAST3_OFFSET 26:18 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG50_AV1_REFPIC_SEG6 30:27 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG51(dev) (0x008498cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG51__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG51_CUR_GOLDEN_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG51_CUR_BWDREF_OFFSET 17:9 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG51_CUR_ALTREF2_OFFSET 26:18 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG51_AV1_REFPIC_SEG7 30:27 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG52(dev) (0x008498d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG52__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG52_CUR_ALTREF_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG52_MF1_LAST_OFFSET 17:9 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG52_MF1_LAST_SIDE 18:18 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG52_MF1_LAST2_OFFSET 27:19 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG52_MF1_LAST2_SIDE 28:28 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG53(dev) (0x008498d4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG53__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG53_MF1_LAST3_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG53_MF1_LAST3_SIDE 9:9 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG53_MF1_GOLDEN_OFFSET 18:10 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG53_MF1_GOLDEN_SIDE 19:19 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG53_MF1_BWDREF_OFFSET 28:20 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG53_MF1_BWDREF_SIDE 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG54(dev) (0x008498d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG54__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG54_MF1_ALTREF2_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG54_MF1_ALTREF2_SIDE 9:9 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG54_MF1_ALTREF_OFFSET 18:10 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG54_MF1_ALTREF_SIDE 19:19 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG54_MF2_LAST_OFFSET 28:20 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG54_MF2_LAST_SIDE 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG55(dev) (0x008498dc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG55__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG55_MF2_LAST2_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG55_MF2_LAST2_SIDE 9:9 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG55_MF2_LAST3_OFFSET 18:10 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG55_MF2_LAST3_SIDE 19:19 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG55_MF2_GOLDEN_OFFSET 28:20 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG55_MF2_GOLDEN_SIDE 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG56(dev) (0x008498e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG56__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG56_MF2_BWDREF_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG56_MF2_BWDREF_SIDE 9:9 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG56_MF2_ALTREF2_OFFSET 18:10 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG56_MF2_ALTREF2_SIDE 19:19 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG56_MF2_ALTREF_OFFSET 28:20 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG56_MF2_ALTREF_SIDE 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG57(dev) (0x008498e4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG57__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG57_MF3_LAST_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG57_MF3_LAST_SIDE 9:9 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG57_MF3_LAST2_OFFSET 18:10 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG57_MF3_LAST2_SIDE 19:19 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG57_MF3_LAST3_OFFSET 28:20 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG57_MF3_LAST3_SIDE 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG58(dev) (0x008498e8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG58__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG58_MF3_GOLDEN_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG58_MF3_GOLDEN_SIDE 9:9 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG58_MF3_BWDREF_OFFSET 18:10 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG58_MF3_BWDREF_SIDE 19:19 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG58_MF3_ALTREF2_OFFSET 28:20 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG58_MF3_ALTREF2_SIDE 29:29 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG59(dev) (0x008498ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG59__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG59_MF3_ALTREF_OFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG59_MF3_ALTREF_SIDE 9:9 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG59_MF1_TYPE 12:10 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG59_MF2_TYPE 15:13 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG59_MF3_TYPE 18:16 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG60(dev) (0x008498f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG60__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG60_RCACHE_DEBUG_STAT_DATA 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG61(dev) (0x008498f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG61__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG61_RCACHE_REQ_NUMBER 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG62(dev) (0x008498f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG62__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG62_RCACHE_HIT_NUMBER 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG63(dev) (0x008498fc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG63__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG63_PRED_INTRA_TOPBUFFER_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG64(dev) (0x00849900+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG64__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG64_DEC_VERT_LR_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG65(dev) (0x00849904+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG65__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG65_DEC_VERT_CDEF_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG66(dev) (0x00849908+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG66__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG66_DEC_VERT_HUS_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG67(dev) (0x0084990c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG67__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG67_SUPERRES_LUMA_STEP 13:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG67_SUPERRES_CHROMA_STEP 27:14 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG68(dev) (0x00849910+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG68__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG68_SUPERRES_INIT_LUMA_SUBPEL_X 13:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG68_SUPERRES_INIT_CHROMA_SUBPEL_X 27:14 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG69(dev) (0x00849914+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG69__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG69_CUR_LAST_ROFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG69_CUR_LAST2_ROFFSET 17:9 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG69_CUR_LAST3_ROFFSET 26:18 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG70(dev) (0x00849918+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG70__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG70_CUR_GOLDEN_ROFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG70_CUR_BWDREF_ROFFSET 17:9 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG70_CUR_ALTREF2_ROFFSET 26:18 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG71(dev) (0x0084991c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG71__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG71_CUR_ALTREF_ROFFSET 8:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG72(dev) (0x00849920+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG72__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG72_CONTEXT_UPDATE_TILE_ID 11:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG73(dev) (0x00849924+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG73__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG73_HISTOGRAM_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74(dev) (0x00849928+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG74__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG74_APPLY_GRAIN 0:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74_OVERLAP_FLAG 1:1 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74_CLIP_TO_RESTRICTED_RANGE 2:2 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74_CHROMA_SCALING_FROM_LUMA 3:3 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74_NUM_Y_POINTS_B 4:4 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74_NUM_CB_POINTS_B 5:5 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74_NUM_CR_POINTS_B 6:6 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74_SCALING_SHIFT 10:7 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG74_CB_OFFSET 19:11 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG74_CR_OFFSET 28:20 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG75(dev) (0x0084992c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG75__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG75_CB_MULT 7:0 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG75_CB_LUMA_MULT 15:8 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG75_CR_MULT 23:16 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG75_CR_LUMA_MULT 31:24 /* RWXSF */ #define NV_PNVDEC_AVD_SWREG76(dev) (0x00849930+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG76__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG76_RANDOM_SEED 15:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG77(dev) (0x00849934+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG77__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG77_FILM_GRAIN_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG78(dev) (0x00849938+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG78__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG78_DISP_BUF_LU_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG79(dev) (0x0084993c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG79__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG79_DISP_BUF_CH_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG80(dev) (0x00849940+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG80__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG80_DEC_VERT_FGS_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG81(dev) (0x00849944+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG81__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG81_DMA_SRC_INFO 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG82(dev) (0x00849948+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG82__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG82_DMA_DST_BASE 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG83(dev) (0x0084994c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG83__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG83_DMA_CMD_SIZE 23:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG83_DMA_CMD_LAST_FLAG 24:24 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG83_DMA_CMD_MODE 26:25 /* RWXVF */ #define NV_PNVDEC_CG4(dev) (0x00849950+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG4__SIZE_1 2 /* */ #define NV_PNVDEC_CG4_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG4_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG4_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_PROC_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_PROC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_PROC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_PROC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_CTRL_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_FETCH2D_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG4_SLCG_RFETCH_FETCH2D_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_FETCH2D_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG4_SLCG_RFETCH_FETCH2D_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RCACHE_CACHE_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG4_SLCG_RCACHE_CACHE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RCACHE_CACHE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG4_SLCG_RCACHE_CACHE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RCACHE_REQ_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG4_SLCG_RCACHE_REQ_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_RCACHE_REQ_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG4_SLCG_RCACHE_REQ_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_ECDMA_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG4_SLCG_ECDMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG4_SLCG_ECDMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG4_SLCG_ECDMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5(dev) (0x00849954+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG5__SIZE_1 2 /* */ #define NV_PNVDEC_CG5_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG5_SLCG__PROD 0x00000040 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_HEVC_HEADER_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EMD_HEVC_HEADER_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_HEVC_HEADER_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EMD_HEVC_HEADER_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_HEVC_SLICE_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EMD_HEVC_SLICE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_HEVC_SLICE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EMD_HEVC_SLICE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_COUNTER_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EMD_COUNTER_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_COUNTER_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EMD_COUNTER_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_VPX_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EMD_VPX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_VPX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EMD_VPX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_GIP_EMD_GLUE_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_GIP_EMD_GLUE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_GIP_EMD_GLUE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_GIP_EMD_GLUE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_GLUE_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EMD_GLUE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_GLUE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EMD_GLUE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_PREPARSER_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EMD_PREPARSER_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EMD_PREPARSER_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EMD_PREPARSER_DIS__PROD 0x1 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_AOM_EMD_RAMS_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_AOM_EMD_RAMS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_AOM_EMD_RAMS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_AOM_EMD_RAMS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_HEVC_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_HEVC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_HEVC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_HEVC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_VP9_CUIN_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_VP9_CUIN_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_VP9_CUIN_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_VP9_CUIN_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_VP9_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_VP9_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_VP9_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_GIP_MVD_VP9_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_CTRL_DIS 11:11 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_DRL_DIS 12:12 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_DRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_DRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_DRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_DEMUX_DIS 13:13 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_DEMUX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_DEMUX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_DEMUX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_PROJ_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_PROJ_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_PROJ_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_PROJ_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_SERVE_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_SERVE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_SERVE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_SERVE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_STRM_CTXS_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MV_STRM_CTXS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_STRM_CTXS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MV_STRM_CTXS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_COL_IN_DIS 17:17 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_COL_IN_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_COL_IN_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_COL_IN_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_COL_OUT_DIS 18:18 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_COL_OUT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_COL_OUT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_COL_OUT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_CU_DIS 19:19 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_CU_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_CU_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_CU_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_MV_DIS 20:20 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_MV_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_MV_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MVD_GLUE_MV_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_TOP_MEM_DIS 21:21 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MVD_TOP_MEM_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MVD_TOP_MEM_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MVD_TOP_MEM_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_WARPED_MODEL_DIS 22:22 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_WARPED_MODEL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_WARPED_MODEL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_WARPED_MODEL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_COL_AV1_DIS 23:23 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_COL_AV1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_COL_AV1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_COL_AV1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_CORE_DIS 24:24 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_CORE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_CORE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_CORE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLOBAL_REQ_DIS 25:25 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLOBAL_REQ_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLOBAL_REQ_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLOBAL_REQ_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLOBAL_DIS 26:26 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLOBAL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLOBAL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLOBAL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLUE_DIS 27:27 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLUE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLUE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_GLUE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_MUX_DIS 28:28 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_MUX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_MUX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_EP_DMA_MUX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_VPC_MAIN_DIS 29:29 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_VPC_MAIN_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_VPC_MAIN_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_VPC_MAIN_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_CTRL_DEMUX_DIS 30:30 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_CTRL_DEMUX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_CTRL_DEMUX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_CTRL_DEMUX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_BUF_DIS 31:31 /* RWIVF */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_BUF_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_BUF_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG5_SLCG_MV_PRED_MF_BUF_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11(dev) (0x0084996c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG11__SIZE_1 2 /* */ #define NV_PNVDEC_CG11_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG11_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_PALETTE_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_PALETTE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_PALETTE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_PALETTE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_DAALA_EC_DEC_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_DAALA_EC_DEC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_DAALA_EC_DEC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_DAALA_EC_DEC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_CTX_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_CTX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_CTX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_CTX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_INTRA_MODE_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_INTRA_MODE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_INTRA_MODE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_INTRA_MODE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_MVD_CTRL_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_MVD_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_MVD_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_MVD_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_SEGMENT_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_SEGMENT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_SEGMENT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_SEGMENT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_TXSIZE_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_TXSIZE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_TXSIZE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_TXSIZE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_CTRL_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_RAM_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_RAM_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_RAM_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_RAM_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_STACK_DIS 11:11 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_STACK_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_STACK_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_STACK_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_DIS 12:12 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_SB_DIS 13:13 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_SB_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_SB_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_SB_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_PALETTE_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_PALETTE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_PALETTE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_DEC_MSYM_PALETTE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_EP_IF_MUX_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_EP_IF_MUX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_EP_IF_MUX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_EP_IF_MUX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_EP_SCD_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_EP_SCD_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_EP_SCD_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_EP_SCD_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_IF_DIS 17:17 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_STREAM_IF_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_STREAM_IF_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_STREAM_IF_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_ERROR_DETECT_DIS 18:18 /* RWIVF */ #define NV_PNVDEC_CG11_SLCG_ERROR_DETECT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG11_SLCG_ERROR_DETECT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG11_SLCG_ERROR_DETECT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6(dev) (0x00849958+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG6__SIZE_1 2 /* */ #define NV_PNVDEC_CG6_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG6_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_PREFETCH_FETCH2D_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_PREFETCH_FETCH2D_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_PREFETCH_FETCH2D_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_PREFETCH_FETCH2D_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_PREFETCH_PROC2D_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_PREFETCH_PROC2D_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_PREFETCH_PROC2D_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_PREFETCH_PROC2D_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_COEFF_SPLIT_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_COEFF_SPLIT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_COEFF_SPLIT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_COEFF_SPLIT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_CTRL2PRED_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_CTRL2PRED_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_CTRL2PRED_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_CTRL2PRED_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_SCAN_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_SCAN_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_SCAN_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_SCAN_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_AV1_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_AV1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_AV1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_AV1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_265_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_265_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_265_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_265_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_OUT_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_OUT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_OUT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_OUT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_CTRL_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RBUF_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RBUF_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RBUF_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RBUF_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RREQ_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RREQ_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RREQ_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RREQ_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_LOSSLESS_DIS 11:11 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_LOSSLESS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_LOSSLESS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_LOSSLESS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_SCAN_DIS 12:12 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_SCAN_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_SCAN_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_SCANQUANT_SCAN_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_LOAD_DATA_DIS 13:13 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_LOAD_DATA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_LOAD_DATA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_LOAD_DATA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T0_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T0_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T0_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T0_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T1_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_265_DIS 17:17 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_265_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_265_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_265_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_AV1_DIS 18:18 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_AV1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_AV1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_AV1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_265_DIS 19:19 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_265_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_265_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_265_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_AV1_DIS 20:20 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_AV1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_AV1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_AV1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_FORMAT_DATA_DIS 21:21 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_FORMAT_DATA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_FORMAT_DATA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_HOR_FORMAT_DATA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_PP_DIS 22:22 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_PP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_PP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_PP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_LOAD_DATA_DIS 23:23 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_LOAD_DATA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_LOAD_DATA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_LOAD_DATA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_265_DIS 24:24 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_265_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_265_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_265_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_AV1_DIS 25:25 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_AV1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_AV1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_AV1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T0_DIS 27:27 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T0_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T0_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T0_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T1_DIS 28:28 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_265_DIS 29:29 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_265_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_265_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_265_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_AV1_DIS 30:30 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_AV1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_AV1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_AV1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_265_DIS 31:31 /* RWIVF */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_265_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_265_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_265_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG12(dev) (0x00849970+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG12__SIZE_1 2 /* */ #define NV_PNVDEC_CG12_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG12_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG12_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_AV1_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG12_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_AV1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_AV1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG12_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_AV1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_265_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_265_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_265_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_265_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_OTH_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_OTH_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_OTH_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_OTH_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_OUT_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_OUT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_OUT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG12_SLCG_TRANS_TO_PRED_OUT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_IQT_DMA_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG12_SLCG_IQT_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_IQT_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG12_SLCG_IQT_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_SCANQUANT_ZERO_RUN_ZERO_VP9_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG12_SLCG_SCANQUANT_ZERO_RUN_ZERO_VP9_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_SCANQUANT_ZERO_RUN_ZERO_VP9_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG12_SLCG_SCANQUANT_ZERO_RUN_ZERO_VP9_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_PREFETCH_PREPROCESS_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG12_SLCG_PREFETCH_PREPROCESS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG12_SLCG_PREFETCH_PREPROCESS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG12_SLCG_PREFETCH_PREPROCESS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7(dev) (0x0084995c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG7__SIZE_1 2 /* */ #define NV_PNVDEC_CG7_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG7_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CALC_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CALC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CALC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CALC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CALHEVC_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CALHEVC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CALHEVC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CALHEVC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CFL_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CFL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CFL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CFL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CTRL_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_FILTER_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_FILTER_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_FILTER_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_FILTER_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_NEIGH_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_NEIGH_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_NEIGH_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_NEIGH_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_PREPROCESS_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_PREPROCESS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_PREPROCESS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_PREPROCESS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_PREHEVC_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_PREHEVC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_PREHEVC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_PREHEVC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_RECONST_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_RECONST_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_RECONST_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_RECONST_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_TU_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_TU_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_TU_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_TU_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLATE_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLATE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLATE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLATE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CONTROL_DIS 11:11 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CONTROL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CONTROL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CONTROL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CALC_DIS 12:12 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CALC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CALC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CALC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_MEM_DIS 13:13 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_MEM_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_MEM_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COLLECT_MEM_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COMBINE_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COMBINE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COMBINE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_COMBINE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FETCH_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FETCH_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FETCH_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FETCH_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FIR_0_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FIR_0_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FIR_0_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FIR_0_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FIR_1_DIS 17:17 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FIR_1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FIR_1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_FIR_1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_MEM_DIS 18:18 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_MEM_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_MEM_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_MEM_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_OBMC_DIS 19:19 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_OBMC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_OBMC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_OBMC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_PAD_DIS 20:20 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_PAD_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_PAD_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_PAD_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_RECIEVE_DIS 21:21 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_RECIEVE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_RECIEVE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_RECIEVE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_SHIFT_DIS 22:22 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_SHIFT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_SHIFT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_SHIFT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_UNIT_DIS 23:23 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_UNIT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_UNIT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTER_UNIT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_DMA_DIS 24:24 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_TILE_INFO_ALLOC_DIS 25:25 /* RWIVF */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_TILE_INFO_ALLOC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_TILE_INFO_ALLOC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG7_SLCG_PRED_INTRA_TILE_INFO_ALLOC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8(dev) (0x00849960+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG8__SIZE_1 2 /* */ #define NV_PNVDEC_CG8_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG8_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_BYPASS_CTRL_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_DBLK_BYPASS_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_BYPASS_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_DBLK_BYPASS_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_CB_R_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_CB_R_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_CB_R_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_CB_R_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_CB_S_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_CB_S_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_CB_S_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_CB_S_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_LB_R_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_LB_R_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_LB_R_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_LB_R_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_LB_S_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_LB_S_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_LB_S_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_DBLK_DMA_LB_S_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_GENPP_CTRL_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_DBLK_GENPP_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_GENPP_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_DBLK_GENPP_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_GENSAO_CTRL_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_DBLK_GENSAO_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_DBLK_GENSAO_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_DBLK_GENSAO_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_COMB_TUS_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_COMB_TUS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_COMB_TUS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_COMB_TUS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_PRE_CTRLS_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_PRE_CTRLS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_PRE_CTRLS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_PRE_CTRLS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_FLAT_SKIP_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_FLAT_SKIP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_FLAT_SKIP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_FLAT_SKIP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_FLAT_TUS_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_FLAT_TUS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_FLAT_TUS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_FLAT_TUS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_CTRL_DIS 11:11 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_DIS 12:12 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_UNPACK_DIS 13:13 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_UNPACK_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_UNPACK_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_HOR_UNPACK_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_CTRLS_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_CTRLS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_CTRLS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_CTRLS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_MVS_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_MVS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_MVS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_MVS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_PIXELS_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_PIXELS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_PIXELS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_PIXELS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_TUS_DIS 17:17 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_TUS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_TUS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_READ_TUS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_VER_CTRL_DIS 18:18 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_VER_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_VER_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_VER_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_VER_DIS 19:19 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILTER_VER_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILTER_VER_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILTER_VER_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILM_GRAIN_DIS 20:20 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_FILM_GRAIN_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_FILM_GRAIN_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_FILM_GRAIN_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_SAO_PREP_DIS 21:21 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_SAO_PREP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_SAO_PREP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_SAO_PREP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_SAO_FILTER_DIS 22:22 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_SAO_FILTER_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_SAO_FILTER_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_SAO_FILTER_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_DIS 23:23 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_HOR_SYNC_DIS 24:24 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_HOR_SYNC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_HOR_SYNC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_HOR_SYNC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_VER_SYNC_DIS 25:25 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_VER_SYNC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_VER_SYNC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_CDEF_CTRL_VER_SYNC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_FINDDIR_DIS 26:26 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_CDEF_FINDDIR_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_FINDDIR_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_CDEF_FINDDIR_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PARAMS_DIS 27:27 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_CDEF_PARAMS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PARAMS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PARAMS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PREP_DIS 28:28 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_CDEF_PREP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PREP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PREP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PROC_DIS 29:29 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_CDEF_PROC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PROC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_CDEF_PROC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_HUS_BLKINFO_DIS 30:30 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_HUS_BLKINFO_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_HUS_BLKINFO_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_HUS_BLKINFO_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_HUS_CTRL_DIS 31:31 /* RWIVF */ #define NV_PNVDEC_CG8_SLCG_HUS_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG8_SLCG_HUS_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG8_SLCG_HUS_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9(dev) (0x00849964+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG9__SIZE_1 2 /* */ #define NV_PNVDEC_CG9_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG9_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_OUTPUT_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_HUS_OUTPUT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_OUTPUT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_HUS_OUTPUT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_PIPE_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_HUS_PIPE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_PIPE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_HUS_PIPE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_PREP_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_HUS_PREP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_PREP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_HUS_PREP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_SBINFO_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_HUS_SBINFO_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_SBINFO_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_HUS_SBINFO_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_SCALE_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_HUS_SCALE_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_SCALE_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_HUS_SCALE_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_SWITCH_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_HUS_SWITCH_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_SWITCH_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_HUS_SWITCH_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_CTRL_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_LR_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_LR_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_OUTPUT_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_LR_OUTPUT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_OUTPUT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_LR_OUTPUT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_PROC_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_LR_PROC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_PROC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_LR_PROC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_SGR_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_LR_SGR_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_SGR_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_LR_SGR_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_WIENER_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_LR_WIENER_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_WIENER_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_LR_WIENER_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_HIST_DIS 11:11 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_PP_HIST_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_HIST_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_PP_HIST_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_OUTPUT_DIS 12:12 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_PP_OUTPUT_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_OUTPUT_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_PP_OUTPUT_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_OUTPUT_FGS_DIS 13:13 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_PP_OUTPUT_FGS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_OUTPUT_FGS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_PP_OUTPUT_FGS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_PROC_DIS 14:14 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_PP_PROC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_PROC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_PP_PROC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_PROC_FGS_DIS 15:15 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_PP_PROC_FGS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_PROC_FGS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_PP_PROC_FGS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_CDEF_LEFTBUF_DMA_DIS 16:16 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_CDEF_LEFTBUF_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_CDEF_LEFTBUF_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_CDEF_LEFTBUF_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_DBLK_LEFTBUF_DMA_DIS 17:17 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_DBLK_LEFTBUF_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_DBLK_LEFTBUF_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_DBLK_LEFTBUF_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_DBLK_TOPBUF_DMA_DIS 18:18 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_DBLK_TOPBUF_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_DBLK_TOPBUF_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_DBLK_TOPBUF_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FGS_LEFTBUF_DMA_DIS 19:19 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_FGS_LEFTBUF_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FGS_LEFTBUF_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_FGS_LEFTBUF_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FGS_NOISE_DMA_DIS 20:20 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_FGS_NOISE_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FGS_NOISE_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_FGS_NOISE_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_DMA_MUX_DIS 21:21 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_FILTER_DMA_MUX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_DMA_MUX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_FILTER_DMA_MUX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_LEFTBUF_DMA_DIS 22:22 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_HUS_LEFTBUF_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_HUS_LEFTBUF_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_HUS_LEFTBUF_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_LEFTBUF_DMA_DIS 23:23 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_LR_LEFTBUF_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_LR_LEFTBUF_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_LR_LEFTBUF_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_HIST_DMA_DIS 24:24 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_PP_HIST_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_PP_HIST_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_PP_HIST_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_SAO_LEFTBUF_DMA_DIS 25:25 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_SAO_LEFTBUF_DMA_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_SAO_LEFTBUF_DMA_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_SAO_LEFTBUF_DMA_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_CALC_CTRLS_DIS 26:26 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_FILTER_CALC_CTRLS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_CALC_CTRLS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_FILTER_CALC_CTRLS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_AV1_DP_DIS 27:27 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_AV1_DP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_AV1_DP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_AV1_DP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_HEVC_DP_DIS 28:28 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_HEVC_DP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_HEVC_DP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_HEVC_DP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_MUX_DIS 29:29 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_MUX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_MUX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_FILTER_VER_MUX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_HOR_MUX_DIS 30:30 /* RWIVF */ #define NV_PNVDEC_CG9_SLCG_FILTER_HOR_MUX_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG9_SLCG_FILTER_HOR_MUX_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG9_SLCG_FILTER_HOR_MUX_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10(dev) (0x00849968+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG10__SIZE_1 2 /* */ #define NV_PNVDEC_CG10_SLCG 31:0 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_PNVDEC_CG10_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_FILTER_HOR_AV1_DP_DIS 0:0 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_FILTER_HOR_AV1_DP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_FILTER_HOR_AV1_DP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_FILTER_HOR_AV1_DP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_FILTER_HOR_HEVC_DP_DIS 1:1 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_FILTER_HOR_HEVC_DP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_FILTER_HOR_HEVC_DP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_FILTER_HOR_HEVC_DP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_HEVC_DIS 2:2 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_HEVC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_HEVC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_HEVC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_AV1_DIS 3:3 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_AV1_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_AV1_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_AV1_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_TILE_INFO_ALLOC_DIS 4:4 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_TILE_INFO_ALLOC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_TILE_INFO_ALLOC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_TILE_INFO_ALLOC_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_SAO_CTRL_DIS 5:5 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_SAO_CTRL_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_SAO_CTRL_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_SAO_CTRL_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_HUS_CTRL_PREP_DIS 6:6 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_HUS_CTRL_PREP_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_HUS_CTRL_PREP_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_HUS_CTRL_PREP_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_HUS_CTRL_MID_DIS 7:7 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_HUS_CTRL_MID_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_HUS_CTRL_MID_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_HUS_CTRL_MID_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_TFC_WR_ACK_DIS 8:8 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_TFC_WR_ACK_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_TFC_WR_ACK_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_TFC_WR_ACK_DIS__PROD 0x1 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_TFC_PROC_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_TFC_PROC_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_TFC_PROC_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_TFC_PROC_DIS__PROD 0x1 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_LR_PARAMS_DIS 10:10 /* RWIVF */ #define NV_PNVDEC_CG10_SLCG_LR_PARAMS_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG10_SLCG_LR_PARAMS_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG10_SLCG_LR_PARAMS_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_CG_SLCG_CTRL(dev) (0x0084997c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_CG_SLCG_CTRL__SIZE_1 2 /* */ #define NV_PNVDEC_CG_SLCG_CTRL_SLCG_IDLE_DLY 8:0 /* RWIVF */ #define NV_PNVDEC_CG_SLCG_CTRL_SLCG_IDLE_DLY_RSTVAL 0x001 /* RWI-V */ #define NV_PNVDEC_CG_SLCG_CTRL_IDLE_SLCG_DIS 9:9 /* RWIVF */ #define NV_PNVDEC_CG_SLCG_CTRL_IDLE_SLCG_DIS_ENABLED 0x0 /* RW--V */ #define NV_PNVDEC_CG_SLCG_CTRL_IDLE_SLCG_DIS_DISABLED 0x1 /* RWI-V */ #define NV_PNVDEC_CG_SLCG_CTRL_IDLE_SLCG_DIS__PROD 0x0 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF(dev) (0x00849980+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL 5:0 /* RWIUF */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_COLMVDATA_DMA2MVD_AV1 0x00 /* RWI-V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_COLMVDATA_DMA2MVD 0x01 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_COLMVDATA_MVD2DMA_AV1 0x02 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_COLMVDATA_MVD2DMA 0x03 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_COLOC_CTRL_OUT 0x04 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_COLOC_MV_REF_PIC_BASE 0x05 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_DMA2STREAMIF_DATA 0x06 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2FILTER_CTB_CTRL 0x07 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2INTRA_PALETTE_DATA 0x08 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2INTRA_TILE_INFO 0x09 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2IQT_COEFF 0x10 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2IQT_TU_CTRL 0x11 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2LR_CB_PARAMS 0x12 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2LR_CR_PARAMS 0x13 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2LR_PARAMS 0x14 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP_DMA2FBIF_RD 0x15 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_EP_DMA2FBIF_WR 0x16 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_GLOBAL_MODEL_DMA2MVD 0x17 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_MVD2PREFETCH_CUCTRL 0x18 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_MVD2PREFETCH_MVCTRL 0x19 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_PROB_TABLE_IN 0x20 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_PROB_TABLE_OUT 0x21 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_SEGMENT_IN 0x22 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_SEGMENT_OUT 0x23 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_STREAM_FIFO 0x24 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_STREAMIF2SA_DATA 0x25 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_TEMPORAL_REQ 0x26 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_TILE_SIZE_FIFO 0x27 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_INTF_SEL_TILE_OFFSET 0x28 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_0(dev) (0x00849984+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_0__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_0_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_1(dev) (0x00849988+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_1__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_1_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_2(dev) (0x0084998c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_2__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_2_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_3(dev) (0x00849990+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_3__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTB_GOLDEN_3_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP(dev) (0x00849994+(dev)*16384) /* R--4A */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C0 0:0 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C0_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C0_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C1 1:1 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C1_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C1_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C2 2:2 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C2_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C2_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C3 3:3 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C3_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTB_COMP_C3_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTB_CONTROL(dev) (0x00849998+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTB_CONTROL__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTB_CONTROL_EN 0:0 /* RWIUF */ #define NV_PNVDEC_DBG_CRC_PARTB_CONTROL_EN_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_DBG_CRC_PARTB_CONTROL_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF(dev) (0x008499a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL 5:0 /* RWIUF */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTER_CU_CTRL_DATA0 0x00 /* RWI-V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTER_CU_CTRL_DATA1 0x01 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_FB2REC_IQT_QMATRIX_DATA 0x02 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2RFETCH_FETCH_CTRL 0x03 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_IQT2DMA_DATA 0x04 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_IQT2INTRA_RESIDUAL 0x05 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_IQT2INTRA_TU_CTRL 0x06 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_IQTDMA2FBIF_RD_REQ 0x07 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTER_MV_CTRL 0x08 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTER_PART_CTRL 0x09 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTRA_CU_CTRL 0x10 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_INTF_SEL_IQT2INTER_TU_CTRL 0x11 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_0(dev) (0x008499a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_0__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_0_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_1(dev) (0x008499a8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_1__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_1_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_2(dev) (0x008499ac+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_2__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_2_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_3(dev) (0x008499b0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_3__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTC_GOLDEN_3_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP(dev) (0x008499b4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C0 0:0 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C0_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C0_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C1 1:1 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C1_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C1_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C2 2:2 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C2_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C2_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C3 3:3 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C3_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTC_COMP_C3_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTC_CONTROL(dev) (0x008499b8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTC_CONTROL__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTC_CONTROL_EN 0:0 /* RWIUF */ #define NV_PNVDEC_DBG_CRC_PARTC_CONTROL_EN_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_DBG_CRC_PARTC_CONTROL_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF(dev) (0x008499c0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL 5:0 /* RWIUF */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_INTER2FILTER_CU_CTRL 0x00 /* RWI-V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_DMA2INTRA_DATA 0x01 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_INTRA2DMA_DATA 0x02 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_INTRA2FILTER_TILE_INFO 0x03 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_INTRADMA2FBIF_RD_REQ 0x04 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_INTRADMA2FBIF_WR 0x05 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_INTER2FILTER_MV_CTRL 0x06 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_RECON2FILTER_DATA 0x07 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_TILEINFO 0x08 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_INTF_SEL_INTER2FILTER_TU_CTRL 0x09 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_0(dev) (0x008499c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_0__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_0_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_1(dev) (0x008499c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_1__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_1_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_2(dev) (0x008499cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_2__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_2_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_3(dev) (0x008499d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_3__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTD_GOLDEN_3_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP(dev) (0x008499d4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C0 0:0 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C0_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C0_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C1 1:1 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C1_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C1_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C2 2:2 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C2_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C2_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C3 3:3 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C3_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTD_COMP_C3_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTD_CONTROL(dev) (0x008499d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTD_CONTROL__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTD_CONTROL_EN 0:0 /* RWIUF */ #define NV_PNVDEC_DBG_CRC_PARTD_CONTROL_EN_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_DBG_CRC_PARTD_CONTROL_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF(dev) (0x008499e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL 5:0 /* RWIUF */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2CDEF_COL_DATA 0x00 /* RWI-V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_CDEF2DMA_COL_DATA 0x01 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DBLK2DMA_TILE_INFO 0x02 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2DBLK_LEFT_NB 0x03 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DBLK2DMA_LEFT_NB 0x04 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2DBLK_TOP_NB 0x05 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DBLK2DMA_TOP_NB 0x06 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2FGS_COL_DATA 0x07 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_FGSPARAMIN 0x08 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_FGS2DMA_COL_DATA 0x09 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2TFC_FGS_CTRL 0x10 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2TFC_FGS_DATA 0x11 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2HUS_COL_DATA 0x12 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_HUS2DMA_COL_DATA 0x13 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_INTRABC_SYNC 0x14 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2LR_COL_DATA 0x15 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_LR2DMA_COL_DATA 0x16 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2DMA_HISTOGRAM_DATA 0x17 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2TFC_CTRL 0x18 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2TFC_DATA 0x19 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2SAO_LEFT_COLUMN_DATA 0x20 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_SAO2DMA_LEFT_COLUMN_DATA 0x21 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_TFC_RPT 0x22 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_HUS2DMA_COL_DATA_SIZE 0x23 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_FILTERDMA_MUX_DMA2FBIF_WR 0x24 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_INTF_SEL_FILTERDMA_MUX_DMA2FBIF_RD 0x25 /* RW--V */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_0(dev) (0x008499e4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_0__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_0_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_1(dev) (0x008499e8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_1__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_1_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_2(dev) (0x008499ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_2__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_2_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_3(dev) (0x008499f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_3__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTE_GOLDEN_3_VAL 31:0 /* RW-UF */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP(dev) (0x008499f4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C0 0:0 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C0_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C0_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C1 1:1 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C1_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C1_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C2 2:2 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C2_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C2_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C3 3:3 /* R--UF */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C3_PASS 0x1 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTE_COMP_C3_FAIL 0x0 /* R---V */ #define NV_PNVDEC_DBG_CRC_PARTE_CONTROL(dev) (0x008499f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_DBG_CRC_PARTE_CONTROL__SIZE_1 2 /* */ #define NV_PNVDEC_DBG_CRC_PARTE_CONTROL_EN 0:0 /* RWIUF */ #define NV_PNVDEC_DBG_CRC_PARTE_CONTROL_EN_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_DBG_CRC_PARTE_CONTROL_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_AVD_SWREG84(dev) (0x00849a00+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG84__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG84_SUBSTREAM_OFFSET 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG85(dev) (0x00849a04+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG85__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG85_LAST_SUBSTREAM_IN_FRAME 0:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG86(dev) (0x00849a08+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG86__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG86_SUBSTREAM_FIRST_TILE_IDX 7:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG86_SUBSTREAM_LAST_TILE_IDX 15:8 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG87(dev) (0x00849a0c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG87__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG87_TILEINFO_BASE_MSB 31:0 /* RWXVF */ #define NV_PNVDEC_AVD_SWREG88(dev) (0x00849a10+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_AVD_SWREG88__SIZE_1 2 /* */ #define NV_PNVDEC_AVD_SWREG88_DEC_VERT_HUS_PONG_OFFSET 31:0 /* RWXVF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON(dev) (0x0084a000+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_WIDTH_IN_MBS 7:0 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_FRAME_HEIGHT_IN_MBS 15:8 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_TYPE 17:16 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_TYPE_FRAME 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_TYPE_TOP_FIELD 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_TYPE_BOTTOM_FIELD 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING 19:18 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG_D 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG_I 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG_P 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG_B 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VC1_SKIPPED 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VC1_I_OR_BI 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VC1_P 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VC1_B 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG4_SKIPPED 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG4_I 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG4_P 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG4_B 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VP8_I 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VP8_P 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE 22:20 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_MPEG1 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_MPEG2 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_VC1 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_H264 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_MPEG4 0x4 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_VP8 0x5 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PROFILE 25:24 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PROFILE_VC1_SIMPLE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PROFILE_VC1_MAIN 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PROFILE_VC1_ADVANCED 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_PROFILE_MPEG4_SHORT_HEADER 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_SSM_EN 26:26 /* RWIVF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_SSM_EN_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_SSM_EN_DISABLE 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA 27:27 /* RWIVF */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA_OFF 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA_ON 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_PIC_INFO_COMMON_CHROMA_FORMAT_IDC 29:28 /* RWIVF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264(dev) (0x0084a004+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PIC_INFO_H264__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_CABAC 0:0 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_CABAC_CAVLC 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_CABAC_CABAC 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_MBAFF_FRAME_FLAG 9:9 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_NALUNIT_TYPE 16:12 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_CONSTRAINED_INTRA_PRED_FLAG 17:17 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_CABAC_INIT_IDC 19:18 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_CHROMA_FORMAT_IDC 21:20 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_DIRECT_8X8_INFERENCE_FLAG 22:22 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_TRANSFORM_8X8_MODE_FLAG 23:23 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_H264_BITDEPTH_MINUS_8 27:24 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2(dev) (0x0084a008+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2_INTRA_DC_PRECISION 1:0 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2_FRAME_PRED_FRAME_DCT 2:2 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2_INTRA_VLC_FORMAT 3:3 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2_CONCEALMENT_MOTION_VEC 4:4 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2_F_CODE00 19:16 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2_F_CODE01 23:20 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2_F_CODE10 27:24 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_MPEG2_F_CODE11 31:28 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB(dev) (0x0084a00c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_SLICE_ADDR 6:0 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_NUM_REF 7:7 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_NUM_REF_ONE_REF_PIC 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_NUM_REF_TWO_REF_PIC 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_FCM 9:8 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_FCM_PROGRESSIVE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_FCM_FRAME_INTERLACE 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_FCM_FIELD_INTERLACE 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_FCM_MPEG4_INTERLACE 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_REF_DIST 11:10 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_REF_FIELD 12:12 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_REF_FIELD_TEMP_CLOSEST 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_REF_FIELD_SECOND_MOST_TEMP_CLOSEST 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_FIELD_TX 16:16 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_FIELD_TX_RAW 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_FIELD_TX_BITPLANE 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1GB_SLICE_ADDRX 31:24 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T(dev) (0x0084a010+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_CBP_TAB 2:0 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_MV_TAB 6:4 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TWO_MV_BP_TAB 9:8 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_FOUR_MV_BP_TAB 11:10 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_MB_MODE_TAB 14:12 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_DC_TAB 16:16 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_DC_TAB_LOW_MOTION 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_DC_TAB_HIGH_MOTION 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_ESC_LVL_SZ_TAB 17:17 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_ESC_LVL_SZ_TAB_TABLE59 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_ESC_LVL_SZ_TAB_TABLE60 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1 21:20 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1_HIGH_RATE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1_LOW_MOTION 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1_HIGH_MOTION 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1_MID_RATE 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2 23:22 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2_HIGH_RATE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2_LOW_MOTION 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2_HIGH_MOTION 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2_MID_RATE 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q(dev) (0x0084a014+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_FRAME 0:0 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_BINARY_LEVEL 1:1 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE 3:2 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_4_EDGE 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_2_EDGE 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_1_EDGE 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_ALL_MB 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_SDB_EDGE 5:4 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_PICTURE_QUANTIZER_STEP 20:16 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1Q_ALT_PICTURE_QUANTIZER_STEP 28:24 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P(dev) (0x0084a018+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE 1:0 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE_NORM_HORZ_NORM_VERT 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE_EXT_HORZ_NORM_VERT 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE_NORM_HORZ_EXT_VERT 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE_EXT_HORZ_EXT_VERT 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_MV_RANGE 3:2 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE 5:4 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE_MIXED_MV 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE_1_MV 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE_1_MV_HALF_PEL 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE_1_MV_HALF_PEL_BILINEAR 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE 7:6 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_8X8 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_8X4 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_4X8 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_4X4 0x3 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_TRANSFORM_TYPE_FLAG 8:8 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_FOUR_MV_SWITCH 9:9 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_COND_OVER_MB 10:10 /* RWXUF */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_COND_OVER_MB_PICTURE_LEVEL 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_COND_OVER_MB_MB_LEVEL 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_PIC_INFO_VC1P_SYNCMARKER 11:11 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO(dev) (0x0084a01c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SLICE_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SLICE_INFO_SLICE_TYPE 1:0 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SLICE_TYPE_P 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SLICE_TYPE_B 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SLICE_TYPE_I 0x2 /* RWX-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SLICE_NUM 14:2 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_NUM_REF_IDXL0_ACTIVE_MINUS1 19:15 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_NUM_REF_IDXL1_ACTIVE_MINUS1 24:20 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SLICE_QPY 30:25 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_ROWXPICWIDTH_MBS 14:2 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SLICE_ROW 22:15 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_QUANT_SCALE_CODE 29:25 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_EXT(dev) (0x0084a020+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SLICE_INFO_EXT__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SLICE_INFO_EXT_SLICE_NUM 2:0 /* RWXUF */ #define NV_PNVDEC_VLD1_EDOB_MB_INFO(dev) (0x0084a024+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_EDOB_MB_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_EDOB_MB_INFO_MB_ADDR 15:0 /* RWXUF */ #define NV_PNVDEC_VLD1_EDOB_MB_INFO_SLICE_FIRST_MB_FLAG 16:16 /* RWXUF */ #define NV_PNVDEC_VLD1_EDOB_MB_INFO_MB_RSTN 17:17 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC(dev) (0x0084a028+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_BASE_MODE 1:0 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_BASE_MODE_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_BASE_MODE_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_BASE_MODE_ADAPTIVE 0x2 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_RES_PRED 3:2 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_RES_PRED_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_RES_PRED_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_RES_PRED_ADAPTIVE 0x2 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_MOTION_PRED 5:4 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_MOTION_PRED_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_MOTION_PRED_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_MOTION_PRED_ADAPTIVE 0x2 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CBP_PRED 6:6 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CBP_PRED_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CBP_PRED_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_ACSCANSTARTADJ 7:7 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_ACSCANSTARTADJ_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_ACSCANSTARTADJ_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_SCAN_START 11:8 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_SCAN_START_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_SCAN_END 15:12 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_SCAN_END_INIT 0xf /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_SKIP_MAX 28:16 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_SKIP 29:29 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_SKIP_DISABLED 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_SKIP_ENABLED 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP(dev) (0x0084a02c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP_XMIN 7:0 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP_XMIN_INIT 0x01 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP_XMAX 15:8 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP_XMAX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP_YMIN 23:16 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP_YMIN_INIT 0x01 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP_YMAX 31:24 /* RWIUF */ #define NV_PNVDEC_VLD1_SLICE_INFO_SVC_CROP_YMAX_INIT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_EDOB_MB_POS(dev) (0x0084a030+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_EDOB_MB_POS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_EDOB_MB_POS_MB_X 7:0 /* RWXUF */ #define NV_PNVDEC_VLD1_EDOB_MB_POS_MB_Y 15:8 /* RWXUF */ #define NV_PNVDEC_VLD1_MB_INFO(dev) (0x0084a034+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_MB_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_MB_INFO_MB_ADDR 15:0 /* RWXUF */ #define NV_PNVDEC_VLD1_MB_INFO_SLICE_FIRST_MB_FLAG 16:16 /* RWXUF */ #define NV_PNVDEC_VLD1_MB_POS(dev) (0x0084a038+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_MB_POS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_MB_POS_MB_X 7:0 /* RWXUF */ #define NV_PNVDEC_VLD1_MB_POS_MB_Y 15:8 /* RWXUF */ #define NV_PNVDEC_VLD1_PARSE_CMD(dev) (0x0084a03c+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_VLD1_PARSE_CMD__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD 4:0 /* -WXUF */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_UE 0x00 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_SE 0x01 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_U 0x02 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_NAL_HEAD 0x03 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_VP8_PIC_HEAD 0x03 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_BYTE_ALIGNED 0x04 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_MORE_RBSP_DATA 0x05 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_MB_SKIP_FLAG_AE 0x06 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_END_OF_SLICE_FLAG_AE 0x07 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_START_CABAC_INIT 0x08 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_SKIP_MB 0x09 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_NON_SKIP_MB 0x0a /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_PARSE_PRED_WEIGHT_TABLE 0x0b /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_H264_PARSE_SLICE_DATA 0x0c /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_VC1_PARSE_MACROBLOCKS 0x0c /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_MPEG2_PARSE_SLICEDATA 0x0c /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_VP8_PARSE_PICDATA 0x0c /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_MPEG2_RESERVED 0x0d /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_MPEG2_NEXT_BITS 0x0e /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_MPEG2_PARSE_PICTURE_DATA 0x0f /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_VC1_PARSE_PICTURE_HEADER 0x10 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_VC1_PARSE_BITPLANE 0x11 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_SEND_EOS 0x12 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_INSERT_ERROR_MB 0x13 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_CMD_NOP 0x14 /* -WX-V */ #define NV_PNVDEC_VLD1_PARSE_CMD_PARAM 10:5 /* -WXUF */ #define NV_PNVDEC_VLD1_PARSE_CMD_PARAM_READ_MB_FIELD_DECODE_FLAG 5:5 /* -WXUF */ #define NV_PNVDEC_VLD1_PARSE_CMD_PARAM_VC1_TARGET_PLANE 6:5 /* -WXUF */ #define NV_PNVDEC_VLD1_STATUS(dev) (0x0084a040+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD1_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_STATUS_BUSY 0:0 /* R-XUF */ #define NV_PNVDEC_VLD1_STATUS_SLICE_BUSY 1:1 /* R-XUF */ #define NV_PNVDEC_VLD1_STATUS_EDOB_BUSY 2:2 /* R-XUF */ #define NV_PNVDEC_VLD1_STATUS_VC1_PIC_BUSY 3:3 /* R-XUF */ #define NV_PNVDEC_VLD1_STATUS_EDOB_NON_EMPTY 4:4 /* R-XUF */ #define NV_PNVDEC_VLD1_STATUS_MEMACC_BUSY 5:5 /* R-XUF */ #define NV_PNVDEC_VLD1_STATUS_FIFOCTRL_BUSY 6:6 /* R-XUF */ #define NV_PNVDEC_VLD1_STATUS_HIST_BUSY 7:7 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT(dev) (0x0084a044+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD1_RESULT__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_RESULT_RESULT_DATA 31:0 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_NAL_UNIT_TYPE 4:0 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_NAL_REF_IDC 6:5 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_FORBIDDEN_ZERO_BIT 7:7 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_COLOR_SPACE 0:0 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_CLAMPING_TYPE 1:1 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_SEGMENTATION_ENABLED 2:2 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_SEGMENT_FEATURE_MODE 3:3 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_FILTER_TYPE 4:4 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_LOOP_FILTER_LEVEL 10:5 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_SHARPNESS_LEVEL 13:11 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_LOG2_NBR_OF_DCT_PARTITIONS 15:14 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_REFRESH_GOLDEN_FRAME 16:16 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_REFRESH_ALTERNATE_FRAME 17:17 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_COPY_BUFFER_TO_GOLDEN 19:18 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_COPY_BUFFER_TO_ALTERNATE 21:20 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_SIGN_BIAS_GOLDEN 22:22 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_SIGN_BIAS_ALTERNATE 23:23 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_REFRESH_ENTROPY_PROB 24:24 /* R-XUF */ #define NV_PNVDEC_VLD1_RESULT_REFRESH_LAST 25:25 /* R-XUF */ #define NV_PNVDEC_VLD1_INTRPT_EN(dev) (0x0084a048+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_INTRPT_EN__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_INTRPT_EN_WATCHDOG_TIMER_EN 0:0 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_EN_BUFF_EMPTY_EN 1:1 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_EN_BIT_ERROR_EN 2:2 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_EN_LIMIT_EN 3:3 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_EN_SLICE_DONE_EN 4:4 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_STATUS(dev) (0x0084a04c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_INTRPT_STATUS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_INTRPT_STATUS_WATCHDOG_TIMER 0:0 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_STATUS_BUFF_EMPTY 1:1 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_STATUS_BIT_ERROR 2:2 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_STATUS_LIMIT 3:3 /* RWXUF */ #define NV_PNVDEC_VLD1_INTRPT_STATUS_SLICE_DONE 4:4 /* RWXUF */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE(dev) (0x0084a050+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE 31:0 /* RWXUF */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_NONE 0x00000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_SYNCMARKER 0x00000001 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_CBPCY 0x00000002 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTRA_DCCOEF 0x00000004 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ACCOEF1 0x00000008 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_RLL 0x00000010 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ACCOEF2 0x00000020 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_D_LEVEL 0x00000040 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_D_RUN 0x00000080 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ESCLVLSZ 0x00000100 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTRA_INVALID_IDX 0x00000200 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_TTBLK 0x00000400 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_SUBBLKPAT 0x00000800 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_SUBBLKPAT_8X4_4X8 0x00001000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_MVDATA 0x00002000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_INVALID_IDX 0x00004000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_INSUF_BP_BUF 0x00008000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_SLICE_END_MBADDR 0x00010000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_TTMB 0x00020000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_INV_INTRAFLAG_BMV2 0x00040000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_MBMODE 0x00080000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_TWOMVBP 0x00100000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_FOURMVBP 0x00200000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_MVDATA_PF1R 0x00400000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_MVDATA_PF2R 0x00800000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_MIXEDMV 0x01000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_ONEMV 0x02000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_BP_IMODE6_TABLE81 0x04000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MP4_MB_VIDEOPACKETHEADER 0x08000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MP4_MB_MCBPC 0x00020000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MP4_MB_MODBMBTYPE 0x00040000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MP4_MB_MCBPY 0x00080000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_SLICE_END 0x00000001 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_ADDR_INC 0x00000002 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MB_TYPE 0x00000004 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MT_TYPE 0x00000008 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MVX_GET 0x00000010 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MVY_GET 0x00000020 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_CBP_GET 0x00000040 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_QFS_GET 0x00000080 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MARKER_BIT 0x00000100 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_NB_PARAM 0x00000200 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_SKIP_MBS 0x00000400 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_SLICE_END_AT_SMALLER_MB_ADDR 0x00000001 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_SKIP_RUN 0x00000002 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_I_SLICE 0x00000004 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_P_SLICE 0x00000008 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_B_SLICE 0x00000010 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_SI_SLICE 0x00000020 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_SP_SLICE 0x00000040 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_QP_DELTA_OUT_OF_RANGE 0x00000080 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_RESIDUAL_COEFF_COUNT 0x00000100 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_TYPE 0x00000200 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_MB_REF_IDX_L0 0x00000400 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_MB_REF_IDX_L1 0x00000800 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_REF_IDX_L0 0x00001000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_REF_IDX_L1 0x00002000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN0 0x00004000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN1 0x00008000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN2 0x00010000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN3 0x00020000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOTAL_ZEROS 0x00040000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_RUN_BEFORE 0x00080000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_FIXED_PTRN_BIT_STRING 0x00100000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_CODED_BLOCK_PATTERN 0x00200000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_LARGE_LUMA_LOG_WD 0x00400000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_LARGE_CHR_LOG_WD 0x00800000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_LUMA_WEIGHT 0x01000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_LUMA_OFFSET 0x02000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_CHROMA_WEIGHT 0x04000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_CHROMA_OFFSET 0x08000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_EXCEED_SLICE_OFFSET_LIMIT 0x10000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_MB_DATA_EXCEED_EDOB_FIFO_LIMIT 0x20000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_UNCLASSIFIED 0x40000000 /* RWX-V */ #define NV_PNVDEC_VLD1_BIT_ERROR_CODE_CODE_SW_ERROR 0x80000000 /* RWX-V */ #define NV_PNVDEC_VLD1_SCP_CFG(dev) (0x0084a054+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SCP_CFG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SCP_CFG_PARSE_CMD_MODE 16:16 /* R-IUF */ #define NV_PNVDEC_VLD1_SCP_CFG_PARSE_CMD_MODE_INSECURE 0x0 /* R-I-V */ #define NV_PNVDEC_VLD1_SCP_CFG_PARSE_CMD_MODE_SECURE 0x1 /* R---V */ #define NV_PNVDEC_VLD1_TIMEOUT_VALUE(dev) (0x0084a058+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_TIMEOUT_VALUE__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_TIMEOUT_VALUE_MB_DECODE_TIMEOUT 31:0 /* RWXUF */ #define NV_PNVDEC_VLD1_RESET_CTL(dev) (0x0084a05c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_RESET_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_RESET_CTL_SOFT_RESET 0:0 /* -WXUF */ #define NV_PNVDEC_VLD1_RESET_CTL_HARD_RESET 1:1 /* -WXUF */ #define NV_PNVDEC_VLD1_RESET_CTL_SLICE_RESET 2:2 /* -WXUF */ #define NV_PNVDEC_VLD1_IDMA_BUFF_A(dev,i) (0x0084a060+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_VLD1_IDMA_BUFF_A__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_IDMA_BUFF_A__SIZE_2 4 /* */ #define NV_PNVDEC_VLD1_IDMA_BUFF_A_COUNT 23:0 /* RWXUF */ #define NV_PNVDEC_VLD1_IDMA_BUFF_A_ADDR_HIGH 31:24 /* RWXUF */ #define NV_PNVDEC_VLD1_IDMA_BUFF_B(dev,i) (0x0084a064+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_VLD1_IDMA_BUFF_B__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_IDMA_BUFF_B__SIZE_2 4 /* */ #define NV_PNVDEC_VLD1_IDMA_BUFF_B_VALID 0:0 /* RWXUF */ #define NV_PNVDEC_VLD1_IDMA_BUFF_B_ENCRYPT 1:1 /* RWXUF */ #define NV_PNVDEC_VLD1_IDMA_BUFF_B_ADDR_LOW 31:2 /* RWXUF */ #define NV_PNVDEC_VLD1_CURR_IDMA_INFO(dev) (0x0084a0a0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_CURR_IDMA_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_CURR_IDMA_INFO_CURR_IDMA_BIT_INDEX 2:0 /* RWXUF */ #define NV_PNVDEC_VLD1_CURR_IDMA_INFO_CURR_IDMA_BUFF_OFFSET 26:3 /* RWXUF */ #define NV_PNVDEC_VLD1_CURR_IDMA_INFO_CURR_IDMA_BUFF_INDEX 28:27 /* RWXUF */ #define NV_PNVDEC_VLD1_CLEAR_INPUT_BUFFERS(dev) (0x0084a0a4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_CLEAR_INPUT_BUFFERS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS 0:0 /* RWXUF */ #define NV_PNVDEC_VLD1_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS_DONE 0x0 /* RW--V */ #define NV_PNVDEC_VLD1_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS_FLUSH 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_CLEAR_INPUT_BUFFERS_BUFF_ID 2:1 /* RWIUF */ #define NV_PNVDEC_VLD1_CLEAR_INPUT_BUFFERS_BUFF_ID_DEFAULT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_HIST_START_ADDR(dev) (0x0084a0c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_HIST_START_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_HIST_START_ADDR_START_ADDR_HIGH 31:0 /* RWXUF */ #define NV_PNVDEC_VLD1_HIST_SIZE(dev) (0x0084a0cc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_HIST_SIZE__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_HIST_SIZE_SIZE 11:0 /* RWXUF */ #define NV_PNVDEC_VLD1_HIST_CTL(dev) (0x0084a0d0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_HIST_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_HIST_CTL_ENABLE 0:0 /* RWXUF */ #define NV_PNVDEC_VLD1_HIST_CTL_ENABLE_DIS 0x0 /* RW--V */ #define NV_PNVDEC_VLD1_HIST_CTL_ENABLE_EN 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_HIST_CTL_LINEBUF_ENABLE 1:1 /* RWXUF */ #define NV_PNVDEC_VLD1_HIST_CTL_LINEBUF_ENABLE_DIS 0x0 /* RW--V */ #define NV_PNVDEC_VLD1_HIST_CTL_LINEBUF_ENABLE_EN 0x1 /* RW--V */ #define NV_PNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP(dev) (0x0084a0d4+(dev)*16384) /* -W-4A */ #define NV_PNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_OFFSET 11:0 /* -WXUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_RW 12:12 /* -WXUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA(dev) (0x0084a0d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_RESULT_DATA 31:0 /* RWXUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG(dev) (0x0084a0dc+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_MEMACC_ST 2:0 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_FIFOCTRL_ST 5:3 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_MEMACC_REQ0_OUTSTANDING 6:6 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_MEMACC_REQ1_OUTSTANDING 7:7 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_MEMACC_SCP_PKTS_PEND 12:8 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_MB_STATE 17:13 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_RES_BLK_TYPE 20:18 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_CBC_VRAM_PS 24:21 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_DEBUG_CAVLD1_STATE 28:25 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0(dev) (0x0084a0e0+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MB_STATE 7:0 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_CBPCY_STATE 9:8 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MVD_STATE 13:12 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MVDPF1R_STATE 17:16 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MVDPF2R_STATE 21:20 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MVP_STATE 27:24 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_ACP_STATE 29:28 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1(dev) (0x0084a0e4+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_INTRA_STATE 2:0 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_INTER_STATE 6:4 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_VLCAC_STATE 11:8 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_OUTIF_STATE 15:12 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_BP_STATE 18:16 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_BP_RD_STATE 21:20 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG(dev) (0x0084a0e8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG_MB_STATE 3:0 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG_MBI_STATE 5:4 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG_QFS_STATE 8:6 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG_OUTIF_STATE 12:9 /* R-XUF */ #define NV_PNVDEC_VLD1_BIT_ERROR_MASK(dev) (0x0084a0ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_BIT_ERROR_MASK__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_BIT_ERROR_MASK_MASKFIELD 31:0 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_LIMIT(dev) (0x0084a0f0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SLICE_LIMIT__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SLICE_LIMIT_SLICE_BYTE_COUNT 31:0 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_ERROR_CTL(dev) (0x0084a0f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SLICE_ERROR_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SLICE_ERROR_CTL_NEXT_SLICE_MB_ADDR 16:0 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_ERROR_CTL_SET_SW_ERROR 31:31 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_ERROR_CTL_SET_SW_ERROR_CLR 0x0 /* RWX-V */ #define NV_PNVDEC_VLD1_SLICE_ERROR_CTL_SET_SW_ERROR_SET 0x1 /* RWX-V */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG(dev) (0x0084a0f8+(dev)*16384) /* R--4A */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG_MP4_STATE 3:0 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG_MP4IP_STATE 7:4 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG_BP_ILLEGAL_READ 8:8 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG_BP_ILLEGAL_WRITE 9:9 /* R-XUF */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY(dev,i,j) (0x0084a0fc+(dev)*16384+(i)*4+(j)*0) /* RW-4A */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_2 4 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_3 64 /* */ #define NV_PNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_VLD1_PROBBUF_WRITE_REG(dev) (0x0084a110+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PROBBUF_WRITE_REG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PROBBUF_WRITE_REG_DATA 31:0 /* -W-UF */ #define NV_PNVDEC_VLD1_PROBBUF_READ_REG(dev) (0x0084a114+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PROBBUF_READ_REG__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PROBBUF_READ_REG_DATA 31:0 /* R--UF */ #define NV_PNVDEC_VLD1_PROBBUF_RW_OFFSET(dev) (0x0084a118+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_PROBBUF_RW_OFFSET__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PROBBUF_RW_OFFSET_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_A(dev,i) (0x0084a120+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_A__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_A__SIZE_2 8 /* */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_A_COUNT 23:0 /* RWXUF */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_A_ADDR_HIGH 31:24 /* RWXUF */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_B(dev,i) (0x0084a124+(dev)*16384+(i)*8) /* RW-4A */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_B__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_B__SIZE_2 8 /* */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_B_VALID 0:0 /* RWXUF */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_B_ENCRYPT 1:1 /* RWXUF */ #define NV_PNVDEC_VLD1_IDMA1_BUFF_B_ADDR_LOW 31:2 /* RWXUF */ #define NV_PNVDEC_VLD1_CURR_IDMA1_INFO(dev) (0x0084a160+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_CURR_IDMA1_INFO__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_CURR_IDMA1_INFO_CURR_IDMA_BIT_INDEX 2:0 /* RWXUF */ #define NV_PNVDEC_VLD1_CURR_IDMA1_INFO_CURR_IDMA_BUFF_OFFSET 26:3 /* RWXUF */ #define NV_PNVDEC_VLD1_CURR_IDMA1_INFO_CURR_IDMA_BUFF_INDEX 29:27 /* RWXUF */ #define NV_PNVDEC_VLD1_SEGMENT_ID_START_ADDR(dev) (0x0084a164+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SEGMENT_ID_START_ADDR__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SEGMENT_ID_START_ADDR_START_ADDR_HIGH 31:0 /* RWXUF */ #define NV_PNVDEC_VLD1_STREAM_LEN(dev) (0x0084a168+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_STREAM_LEN__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_STREAM_LEN_VALUE 31:0 /* RWXUF */ #define NV_PNVDEC_VLD1_SLICE_INFO2(dev) (0x0084a16c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_SLICE_INFO2__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_WEIGHTED_PRED_IDC 3:2 /* RWXVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_DIRECT_SPATIAL_MVPRED 4:4 /* RWXVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_SLICE_ALPHAC0_OFFSDIV2 8:5 /* RWXVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_SLICE_BETA_OFFSDIV2 12:9 /* RWXVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_QPY 18:13 /* RWXVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_BOTTOM_IS_CLOSER 19:19 /* RWIVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_BOTTOM_IS_CLOSER_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_REFPIC_IS_BOTTOMFIELD 20:20 /* RWIVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_REFPIC_IS_BOTTOMFIELD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_COLPIC_IS_SHORTTERM 21:21 /* RWIVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_COLPIC_IS_SHORTTERM_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_REFPIC_IS_FIELD 22:22 /* RWIVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_REFPIC_IS_FIELD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_DIS_DEBLOCKING_FLT_IDC 26:24 /* RWIVF */ #define NV_PNVDEC_VLD1_SLICE_INFO2_H264_DIS_DEBLOCKING_FLT_IDC_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP(dev,i) (0x0084a170+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP__SIZE_2 4 /* */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_0 4:0 /* RWIVF */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_0_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_1 12:8 /* RWIVF */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_1_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_2 20:16 /* RWIVF */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_2_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_3 28:24 /* RWIVF */ #define NV_PNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_3_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP(dev,i) (0x0084a180+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP__SIZE_2 4 /* */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_0 4:0 /* RWIVF */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_0_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_1 12:8 /* RWIVF */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_1_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_2 20:16 /* RWIVF */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_2_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_3 28:24 /* RWIVF */ #define NV_PNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_3_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_DISTSCALEFACTORS(dev,i) (0x0084a190+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_VLD1_DISTSCALEFACTORS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_DISTSCALEFACTORS__SIZE_2 8 /* */ #define NV_PNVDEC_VLD1_DISTSCALEFACTORS_REFPIC_0 15:0 /* RWIVF */ #define NV_PNVDEC_VLD1_DISTSCALEFACTORS_REFPIC_0_DEFAULT 0x0000 /* RWI-V */ #define NV_PNVDEC_VLD1_DISTSCALEFACTORS_REFPIC_1 31:16 /* RWIVF */ #define NV_PNVDEC_VLD1_DISTSCALEFACTORS_REFPIC_1_DEFAULT 0x0000 /* RWI-V */ #define NV_PNVDEC_VLD1_MVRCOLADDR(dev) (0x0084a200+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_MVRCOLADDR__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_MVRCOLADDR_RCOL_ADDR 31:0 /* RW-UF */ #define NV_PNVDEC_VLD1_MVRCOLPARAM(dev) (0x0084a204+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_MVRCOLPARAM__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_MVRCOLPARAM_RCOL_LWIDTH 7:0 /* RW-UF */ #define NV_PNVDEC_VLD1_MVRCOLPARAM_RCOL_NLIN 8:8 /* RW-VF */ #define NV_PNVDEC_VLD1_MVRCOLLINE(dev) (0x0084a208+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_MVRCOLLINE__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_MVRCOLLINE_RCOL_LREM 7:0 /* RWXUF */ #define NV_PNVDEC_VLD1_MVRCOLLINE_RCOL_LCNT 16:8 /* RWXUF */ #define NV_PNVDEC_VLD1_MVRCOLOFFS(dev) (0x0084a20c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_VLD1_MVRCOLOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_MVRCOLOFFS_RCOL_OFFS 11:0 /* RW-UF */ #define NV_PNVDEC_VLD1_MVRCOLOFFS_RCOL_LODD 12:12 /* RW-VF */ #define NV_PNVDEC_VLD1_MVRCOLOFFS_4K_RCOL_OFFS 15:0 /* RW-UF */ #define NV_PNVDEC_VLD1_MVRCOLOFFS_4K_RCOL_LODD 16:16 /* RW-VF */ #define NV_PNVDEC_VLD1_MVRCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1(dev,i) (0x0084a210+(dev)*16384+(i)*4) /* RW-4A */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1__SIZE_1 2 /* */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1__SIZE_2 64 /* */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_0 7:0 /* RWIVF */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_0_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_1 15:8 /* RWIVF */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_1_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_2 23:16 /* RWIVF */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_2_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_3 31:24 /* RWIVF */ #define NV_PNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_3_DEFAULT 0x00 /* RWI-V */ #define NV_PNVDEC_MV1_MVLOCAL_MEMORY(dev,i,j) (0x0084a800+(dev)*16384+(i)*4+(j)*0) /* RW-4A */ #define NV_PNVDEC_MV1_MVLOCAL_MEMORY__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVLOCAL_MEMORY__SIZE_2 12 /* */ #define NV_PNVDEC_MV1_MVLOCAL_MEMORY__SIZE_3 64 /* */ #define NV_PNVDEC_MV1_MVLOCAL_MEMORY_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVFRMPARAM(dev) (0x0084a844+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVFRMPARAM__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVFRMPARAM_PICWIDTHINMBS 7:0 /* RWXUF */ #define NV_PNVDEC_MV1_MVFRMPARAM_PICWIDTHINMBS_1MB 0x01 /* RWX-V */ #define NV_PNVDEC_MV1_MVFRMPARAM_PICWIDTHINMBS_256MB 0x00 /* RWX-V */ #define NV_PNVDEC_MV1_MVFRMPARAM_PICHEIGHTINMBS 15:8 /* RWXUF */ #define NV_PNVDEC_MV1_MVFRMPARAM_PICHEIGHTINMBS_1MB 0x01 /* RWX-V */ #define NV_PNVDEC_MV1_MVFRMPARAM_PICHEIGHTINMBS_256MB 0x00 /* RWX-V */ #define NV_PNVDEC_MV1_MVCTRL0(dev) (0x0084a850+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVCTRL0__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVCTRL0_H264_APPLEOOLD_FLAG 0:0 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL0_H264_APPLEOOLD_FLAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL0_H264_REFPIC_FLAG 1:1 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL0_H264_REFPIC_FLAG_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL0_H264_CONSTRAINED_INTRA_PRED 2:2 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL0_H264_CONSTRAINED_INTRA_PRED_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL0_H264_CUR_BOTTOM_FIRST 3:3 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL0_H264_CUR_BOTTOM_FIRST_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL0_H264_CHROMA_QPIDXOFF 8:4 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL0_H264_SEC_CHROMA_QPIDXOFF 13:9 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL0_H264_DIRECT_8X8_INFERENCE_FLAG 14:14 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL0_H264_QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG 15:15 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL1(dev) (0x0084a854+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVCTRL1__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVCTRL1_H264_WEIGHTED_PRED_IDC 3:2 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_DIRECT_SPATIAL_MVPRED 4:4 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_SLICE_ALPHAC0_OFFSDIV2 8:5 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_SLICE_BETA_OFFSDIV2 12:9 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_QPY 18:13 /* RWXVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_BOTTOM_IS_CLOSER 19:19 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_BOTTOM_IS_CLOSER_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL1_H264_REFPIC_IS_BOTTOMFIELD 20:20 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_REFPIC_IS_BOTTOMFIELD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL1_H264_COLPIC_IS_SHORTTERM 21:21 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_COLPIC_IS_SHORTTERM_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL1_H264_REFPIC_IS_FIELD 22:22 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_REFPIC_IS_FIELD_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL1_H264_DIS_DEBLOCKING_FLT_IDC 26:24 /* RWIVF */ #define NV_PNVDEC_MV1_MVCTRL1_H264_DIS_DEBLOCKING_FLT_IDC_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVCTRL2(dev) (0x0084a85c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVCTRL2__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVCTRL2_H264_BOTTOMFIRST 15:0 /* RWXVF */ #define NV_PNVDEC_MV1_MVWT_CNTRL(dev) (0x0084a878+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVWT_CNTRL__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVWT_CNTRL_CHROMA_LOG2_WEIGHT_DENOM 2:0 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_CNTRL_LUMA_LOG2_WEIGHT_DENOM 5:3 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_CNTRL_WEIGHT_DENOM_WR_EN 6:6 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_CNTRL_ADR 14:8 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_CNTRL_ADR_WR_EN 15:15 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_CNTRL_LOADED 16:16 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_DATA(dev) (0x0084a87c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVWT_DATA__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVWT_DATA_LUMA_OFFSET 7:0 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_DATA_LUMA_WEIGHT 15:8 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_DATA_CHROMA_WEIGHT_FLAG 16:16 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_DATA_LUMA_WEIGHT_FLAG 17:17 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_DATA_CHROMA_V_OFFSET 7:0 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_DATA_CHROMA_V_WEIGHT 15:8 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_DATA_CHROMA_U_OFFSET 23:16 /* RW-VF */ #define NV_PNVDEC_MV1_MVWT_DATA_CHROMA_U_WEIGHT 31:24 /* RW-VF */ #define NV_PNVDEC_MV1_MVRCOLADDR(dev) (0x0084a880+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVRCOLADDR__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVRCOLADDR_RCOL_ADDR 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVRCOLPARAM(dev) (0x0084a884+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVRCOLPARAM__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVRCOLPARAM_RCOL_LWIDTH 7:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVRCOLPARAM_RCOL_NLIN 8:8 /* RW-VF */ #define NV_PNVDEC_MV1_MVRCOLLINE(dev) (0x0084a888+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVRCOLLINE__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVRCOLLINE_RCOL_LREM 7:0 /* RWXUF */ #define NV_PNVDEC_MV1_MVRCOLLINE_RCOL_LCNT 16:8 /* RWXUF */ #define NV_PNVDEC_MV1_MVRCOLOFFS(dev) (0x0084a88c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVRCOLOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVRCOLOFFS_RCOL_OFFS 11:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVRCOLOFFS_RCOL_LODD 12:12 /* RW-VF */ #define NV_PNVDEC_MV1_MVRCOLOFFS_4K_RCOL_OFFS 15:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVRCOLOFFS_4K_RCOL_LODD 16:16 /* RW-VF */ #define NV_PNVDEC_MV1_MVRCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_PNVDEC_MV1_MVWCOLADDR(dev) (0x0084a890+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVWCOLADDR__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVWCOLADDR_WCOL_ADDR 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVWCOLPARAM(dev) (0x0084a894+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVWCOLPARAM__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVWCOLPARAM_WCOL_LWIDTH 7:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVWCOLPARAM_WCOL_MBAFF 8:8 /* RW-VF */ #define NV_PNVDEC_MV1_MVWCOLPARAM_WCOL_FIELD 9:9 /* RW-VF */ #define NV_PNVDEC_MV1_MVWCOLPARAM_4MV 10:10 /* RWIVF */ #define NV_PNVDEC_MV1_MVWCOLPARAM_4MV_DIS 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVWCOLPARAM_4MV_EN 0x1 /* RW--V */ #define NV_PNVDEC_MV1_MVWCOLPARAM_WRITEENABLE 11:11 /* RWIVF */ #define NV_PNVDEC_MV1_MVWCOLPARAM_WRITEENABLE_DIS 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVWCOLPARAM_WRITEENABLE_EN 0x1 /* RW--V */ #define NV_PNVDEC_MV1_MVWCOLLINE(dev) (0x0084a898+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVWCOLLINE__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVWCOLLINE_WCOL_LREM 7:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVWCOLLINE_WCOL_LCNT 16:8 /* RW-UF */ #define NV_PNVDEC_MV1_MVWCOLOFFS(dev) (0x0084a89c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVWCOLOFFS__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVWCOLOFFS_WCOL_OFFS 12:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVWCOLOFFS_WCOL_LODD 13:13 /* RW-VF */ #define NV_PNVDEC_MV1_MVWCOLOFFS_4K_WCOL_OFFS 15:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVWCOLOFFS_4K_WCOL_LODD 16:16 /* RW-VF */ #define NV_PNVDEC_MV1_MVWCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_PNVDEC_MV1_MV_MB_COUNTER(dev) (0x0084a8c4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MV_MB_COUNTER__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MV_MB_COUNTER_INTRA 15:0 /* RWIVF */ #define NV_PNVDEC_MV1_MV_MB_COUNTER_INTRA_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_MV1_MV_MB_COUNTER_SKIP 31:16 /* RWIVF */ #define NV_PNVDEC_MV1_MV_MB_COUNTER_SKIP_INIT 0x0000 /* RWI-V */ #define NV_PNVDEC_MV1_MV_MB_COUNTER1(dev) (0x0084a8c8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MV_MB_COUNTER1__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MV_MB_COUNTER1_REG 16:0 /* RWIVF */ #define NV_PNVDEC_MV1_MV_MB_COUNTER1_REG_INIT 0x00000 /* RWI-V */ #define NV_PNVDEC_MV1_MVILPOFFSETMVX(dev,i) (0x0084a8d4+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPOFFSETMVX__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPOFFSETMVX__SIZE_2 8 /* */ #define NV_PNVDEC_MV1_MVILPOFFSETMVX_DATA 27:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPOFFSETMVY(dev,i) (0x0084a8d4+(dev)*16384+(i)*0) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPOFFSETMVY__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPOFFSETMVY__SIZE_2 8 /* */ #define NV_PNVDEC_MV1_MVILPOFFSETMVY_DATA 25:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPDIM(dev) (0x0084a8d8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPDIM__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPDIM_STRIDEM1 7:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPDIM_WIDTHM1 23:16 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPDIM_HEIGHTM1 31:24 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPMBCTL_REF(dev) (0x0084a8dc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPMBCTL_REF__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPMBCTL_REF_OFFS 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPMBCTL_CUR(dev) (0x0084a8e0+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPMBCTL_CUR__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPMBCTL_CUR_OFFS 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPSLICE_MODE_CUR(dev) (0x0084a8e4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPSLICE_MODE_CUR__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPSLICE_MODE_CUR_OFFS 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL(dev) (0x0084a8e8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL_RD_ENABLE 0:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL_WR_ENABLE 1:1 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL_CROPCHANGE 2:2 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL_RESTRRESCHANGE 3:3 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL_DIR8X8INF 4:4 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL_REFCLAMP_ENABLE 15:15 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL_REFWIDTHM1 23:16 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPLAYER_CTL_REFHEIGHTM1 31:24 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL(dev) (0x0084a8ec+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE 1:0 /* RWXUF */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE_INIT 0x0 /* RWX-V */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE_P 0x0 /* RWX-V */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE_B 0x1 /* RWX-V */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE_I 0x2 /* RWX-V */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_NOILP 2:2 /* RWIUF */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_NOILP_INIT 0x0 /* RWI-V */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_NUMENTRIES 7:4 /* RWIUF */ #define NV_PNVDEC_MV1_MVILPSLICE_CTL_NUMENTRIES_INIT 0x8 /* RWI-V */ #define NV_PNVDEC_MV1_MVILPOFFSETX_LO(dev) (0x0084a8f4+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPOFFSETX_LO__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPOFFSETX_LO_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPOFFSETY_LO(dev) (0x0084a8f8+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPOFFSETY_LO__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPOFFSETY_LO_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPOFFSET_HI(dev) (0x0084a8fc+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPOFFSET_HI__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPOFFSET_HI_X 1:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPOFFSET_HI_Y 17:16 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPSCALEX(dev) (0x0084a900+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPSCALEX__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPSCALEX_DATA 24:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPSCALEY(dev) (0x0084a904+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPSCALEY__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPSCALEY_DATA 24:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL0_LO(dev) (0x0084a908+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL0_LO__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL0_LO_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL0_HI(dev) (0x0084a90c+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL0_HI__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL0_HI_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL1_LO(dev) (0x0084a910+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL1_LO__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL1_LO_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL1_HI(dev) (0x0084a914+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL1_HI__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVILPREFIDXMAPL1_HI_DATA 31:0 /* RW-UF */ #define NV_PNVDEC_MV1_MVSFCLAYOUT(dev) (0x0084a918+(dev)*16384) /* RW-4A */ #define NV_PNVDEC_MV1_MVSFCLAYOUT__SIZE_1 2 /* */ #define NV_PNVDEC_MV1_MVSFCLAYOUT_DATA 15:0 /* RWIUF */ #define NV_PNVDEC_MV1_MVSFCLAYOUT_DATA_INIT 0xffff /* RWI-V */ #endif // __ga102_dev_nvdec_pri_h__