/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_nvdec_csb_h__ #define __ga102_dev_nvdec_csb_h__ /* This file is autogenerated. Do not edit */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK 0x0000a000 /* RWI4R */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK 0x0000a100 /* RWI4R */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x0000a200 /* RWI4R */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK 0x0000a300 /* RWI4R */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x0000a400 /* RWI4R */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x0000a500 /* RWI4R */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK 0x00003a00 /* RWI4R */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK 0x00003b00 /* RWI4R */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse2" /* */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CNVDEC_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK 0x0000a600 /* RWI4R */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0000a700 /* RWI4R */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x0000f400 /* RWI4R */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x0000fc00 /* RWI4R */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x0000fd00 /* RWI4R */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x0000fe00 /* RWI4R */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x0000ff00 /* RWI4R */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(i) (0x0000f600+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_1 2 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x00006300+(i)*1024) /* RW-4A */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x0000ac00+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK 0x00006400 /* RW-4R */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x00006500 /* RW-4R */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK 0x00006600 /* RW-4R */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x00006700 /* RW-4R */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK 0x00006800 /* RW-4R */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x00006900 /* RW-4R */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x00006a00 /* RW-4R */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK 0x00006f00 /* RW-4R */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x00007800 /* RW-4R */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x00007900 /* RW-4R */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK 0x00007a00 /* RW-4R */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK 0x00007b00 /* RW-4R */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x00007c00 /* RW-4R */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK 0x00007d00 /* RW-4R */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x00007e00 /* RW-4R */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK 0x00007f00 /* RW-4R */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CNVDEC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK 0x00008800 /* RW-4R */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x00008900 /* RW-4R */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK 0x00008b00 /* RW-4R */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSSET 0x00000000 /* -W-4R */ #define NV_CNVDEC_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ1_SET 1 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ2_SET 1 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ3_SET 1 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ4_SET 1 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ5_SET 1 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ6_SET 1 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ7_SET 1 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */ #define NV_CNVDEC_FALCON_IRQSSET_EXT_EXTIRQ8_SET 1 /* */ #define NV_CNVDEC_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSSET_SHA 17:17 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR 0x00000100 /* -W-4R */ #define NV_CNVDEC_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQSTAT 0x00000200 /* R--4R */ #define NV_CNVDEC_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMODE 0x00000300 /* RW-4R */ #define NV_CNVDEC_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_INIT 0x000000fc /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 1 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 1 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 1 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 1 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 1 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 1 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 1 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 1 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0 /* */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SHA 17:17 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SHA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SHA_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQMODE_LVL_SHA_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK 0x00003800 /* RW-4R */ #define NV_CNVDEC_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x00006900 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 1 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0 /* */ #define NV_CNVDEC_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQSCMASK_SHA 17:17 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQSCMASK_SHA_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQSCMASK_SHA_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL(i) (0x0000f800+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_INTR_CTRL__SIZE_1 2 /* */ #define NV_CNVDEC_FALCON_INTR_CTRL__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_INTR_CTRL_VECTOR 11:0 /* RW-VF */ #define NV_CNVDEC_FALCON_INTR_CTRL_GFID 25:20 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_GFID_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_GSP 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_GSP_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_GSP_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_CTRL_CPU 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_INTR_CTRL_CPU_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_INTR_CTRL_CPU_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_INTR_RETRIGGER(i) (0x0000fa00+(i)*256) /* -W-4A */ #define NV_CNVDEC_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */ #define NV_CNVDEC_FALCON_INTR_RETRIGGER__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */ #define NV_CNVDEC_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET 0x00000400 /* -W-4R */ #define NV_CNVDEC_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CNVDEC_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMSET_SHA 17:17 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMSET_SHA_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR 0x00000500 /* -W-4R */ #define NV_CNVDEC_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CNVDEC_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMCLR_SHA 17:17 /* -WXVF */ #define NV_CNVDEC_FALCON_IRQMCLR_SHA_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_IRQMASK 0x00000600 /* R--4R */ #define NV_CNVDEC_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQMASK_SHA 17:17 /* R-IVF */ #define NV_CNVDEC_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IRQDEST 0x00000700 /* RW-4R */ #define NV_CNVDEC_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2 0x00000f00 /* RW-4R */ #define NV_CNVDEC_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CNVDEC_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_HOST_SHA 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST2_HOST_SHA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST2_HOST_SHA_FALCON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_HOST_SHA_HOST 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_SHA 17:17 /* RWIVF */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_SHA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_SHA_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IRQDEST2_TARGET_SHA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_GPTMRINT 0x00000800 /* RW-4R */ #define NV_CNVDEC_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CNVDEC_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_GPTMRVAL 0x00000900 /* RW-4R */ #define NV_CNVDEC_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CNVDEC_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_GPTMRCTL 0x00000a00 /* RW-4R */ #define NV_CNVDEC_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CNVDEC_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_PTIMER0 0x00000b00 /* R--4R */ #define NV_CNVDEC_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x00006f00 /* */ #define NV_CNVDEC_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_PTIMER1 0x00000c00 /* R--4R */ #define NV_CNVDEC_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x00006f00 /* */ #define NV_CNVDEC_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_WDTMRVAL 0x00000d00 /* RW-4R */ #define NV_CNVDEC_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0000a700 /* */ #define NV_CNVDEC_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMRCTL 0x00000e00 /* RW-4R */ #define NV_CNVDEC_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0000a700 /* */ #define NV_CNVDEC_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDDATA 0x00001900 /* R--4R */ #define NV_CNVDEC_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_CNVDEC_FALCON_MTHDID 0x00001a00 /* RW-4R */ #define NV_CNVDEC_FALCON_MTHDID__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_CNVDEC_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_CNVDEC_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_CNVDEC_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_CNVDEC_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_MTHDWDAT 0x00001b00 /* RW-4R */ #define NV_CNVDEC_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_MTHDCOUNT 0x00001c00 /* R--4R */ #define NV_CNVDEC_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_CNVDEC_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_MTHDPOP 0x00001d00 /* -W-4R */ #define NV_CNVDEC_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_CNVDEC_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_MTHDRAMSZ 0x00001e00 /* RW-4R */ #define NV_CNVDEC_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_CNVDEC_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_CURCTX 0x00001400 /* RW-4R */ #define NV_CNVDEC_FALCON_CURCTX__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_CNVDEC_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_CNVDEC_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_NXTCTX 0x00001500 /* RW-4R */ #define NV_CNVDEC_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_CNVDEC_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_CNVDEC_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_CTXACK 0x00001600 /* -W-4R */ #define NV_CNVDEC_FALCON_CTXACK__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_CNVDEC_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_CNVDEC_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_CURCTX2 0x0000f200 /* RW-4R */ #define NV_CNVDEC_FALCON_CURCTX2__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_CURCTX2_CTXGFID 5:0 /* RWIVF */ #define NV_CNVDEC_FALCON_CURCTX2_CTXGFID_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_NXTCTX2 0x0000f300 /* RW-4R */ #define NV_CNVDEC_FALCON_NXTCTX2__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_NXTCTX2_CTXGFID 5:0 /* RWIVF */ #define NV_CNVDEC_FALCON_NXTCTX2_CTXGFID_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_MAILBOX0 0x00001000 /* RW-4R */ #define NV_CNVDEC_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_MAILBOX1 0x00001100 /* RW-4R */ #define NV_CNVDEC_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_ITFEN 0x00001200 /* RW-4R */ #define NV_CNVDEC_FALCON_ITFEN__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_CNVDEC_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_CNVDEC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IDLESTATE 0x00001300 /* RW-4R */ #define NV_CNVDEC_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x00007800 /* */ #define NV_CNVDEC_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_CNVDEC_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_CNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_CNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_IDLESTATE_INT_BUSY_SHA 24:24 /* R-IVF */ #define NV_CNVDEC_FALCON_IDLESTATE_INT_BUSY_SHA_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IDLESTATE_INT_BUSY_SHA_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_FHSTATE 0x00001700 /* R--4R */ #define NV_CNVDEC_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x00007900 /* */ #define NV_CNVDEC_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_CNVDEC_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_CNVDEC_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_CNVDEC_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_CNVDEC_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_PRIVSTATE 0x00001800 /* RW-4R */ #define NV_CNVDEC_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x0000f400 /* */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_VPR_FORCE_STICKY 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SFTRESET 0x00001f00 /* RW-4R */ #define NV_CNVDEC_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_CNVDEC_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL 0x00002900 /* RW-4R */ #define NV_CNVDEC_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_CNVDEC_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_CNVDEC_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_CNVDEC_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_CNVDEC_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_CNVDEC_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_CNVDEC_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_ADDR 0x00002b00 /* RW-4R */ #define NV_CNVDEC_FALCON_ADDR__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_ADDR_LSB 5:0 /* RWIVF */ #define NV_CNVDEC_FALCON_ADDR_LSB_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_CNVDEC_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_ADDR_EXT 11:0 /* */ #define NV_CNVDEC_FALCON_DMACTL 0x00004300 /* RW-4R */ #define NV_CNVDEC_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_CNVDEC_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_CNVDEC_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */ #define NV_CNVDEC_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_CNVDEC_FALCON_DMATRFBASE 0x00004400 /* RW-4R */ #define NV_CNVDEC_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMATRFMOFFS 0x00004500 /* RW-4R */ #define NV_CNVDEC_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMATRFCMD 0x00004600 /* RW-4R */ #define NV_CNVDEC_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_CNVDEC_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMATRFFBOFFS 0x00004700 /* RW-4R */ #define NV_CNVDEC_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB 0x00004800 /* RW-4R */ #define NV_CNVDEC_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP 0x00004900 /* RW-4R */ #define NV_CNVDEC_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMATRFBASE1 0x00004a00 /* RW-4R */ #define NV_CNVDEC_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMATRFBASE1_BASE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x0000b000 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x0000b100 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x0000b200 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x0000b300 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x0000b400 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x0000b500 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x0000b600 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x0000b700 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CTL 0x0000b800 /* RW-4R */ #define NV_CNVDEC_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMAINFO_ERR_TAG_HIGH 0x0000b900 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_CNVDEC_FALCON_DMAINFO_ERR_TAG_LOW 0x0000ba00 /* R--4R */ #define NV_CNVDEC_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CNVDEC_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_IMEMC(i) (0x00006000+(i)*1024) /* RW-4A */ #define NV_CNVDEC_FALCON_IMEMC__SIZE_1 1 /* */ #define NV_CNVDEC_FALCON_IMEMC__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_CNVDEC_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_CNVDEC_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_CNVDEC_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_CNVDEC_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IMEMD(i) (0x00006100+(i)*1024) /* RW-4A */ #define NV_CNVDEC_FALCON_IMEMD__SIZE_1 1 /* */ #define NV_CNVDEC_FALCON_IMEMD__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_IMEMT(i) (0x00006200+(i)*1024) /* RW-4A */ #define NV_CNVDEC_FALCON_IMEMT__SIZE_1 1 /* */ #define NV_CNVDEC_FALCON_IMEMT__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_CNVDEC_FALCON_DMEMC(i) (0x00007000+(i)*512) /* RW-4A */ #define NV_CNVDEC_FALCON_DMEMC__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_DMEMC__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_CNVDEC_FALCON_DMEMC_OFFS_INIT 0 /* */ #define NV_CNVDEC_FALCON_DMEMC_BLK 23:8 /* */ #define NV_CNVDEC_FALCON_DMEMC_BLK_INIT 0 /* */ #define NV_CNVDEC_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_CNVDEC_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_CNVDEC_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_CNVDEC_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_CNVDEC_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_DMEMD(i) (0x00007100+(i)*512) /* RW-4A */ #define NV_CNVDEC_FALCON_DMEMD__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_DMEMD__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_DMEMT(i) (0x00008400+(i)*256) /* -W-4A */ #define NV_CNVDEC_FALCON_DMEMT__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_DMEMT__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_CNVDEC_FALCON_DMEML(i) (0x0000a800+(i)*256) /* -W-4A */ #define NV_CNVDEC_FALCON_DMEML__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_DMEML__PRIV_LEVEL_MASK NV_CNVDEC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CNVDEC_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_CNVDEC_FALCON_DMEM_DUMMY 0x00009600 /* R--4R */ #define NV_CNVDEC_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_CNVDEC_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x0000a100 /* */ #define NV_CNVDEC_FALCON_IMEM_DUMMY 0x00006d00 /* R--4R */ #define NV_CNVDEC_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_CNVDEC_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x0000a000 /* */ #define NV_CNVDEC_FALCON_DIO_RESET_DELAY 0x00009d00 /* RW-4R */ #define NV_CNVDEC_FALCON_DIO_RESET_DELAY__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_DIO_RESET_DELAY_VALUE 15:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DIO_RESET_DELAY_VALUE_INIT 0x00000100 /* RWI-V */ #define NV_CNVDEC_FALCON_DOC_CTRL 0x0000d000 /* RW-4R */ #define NV_CNVDEC_FALCON_DOC_CTRL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_DOC_CTRL_COUNT 7:0 /* R--VF */ #define NV_CNVDEC_FALCON_DOC_CTRL_RESET 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_DOC_CTRL_RESET_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DOC_CTRL_STOP 17:17 /* RWIVF */ #define NV_CNVDEC_FALCON_DOC_CTRL_STOP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DOC_CTRL_EMPTY 18:18 /* R-IVF */ #define NV_CNVDEC_FALCON_DOC_CTRL_EMPTY_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_DOC_CTRL_WR_FINISHED 19:19 /* R-IVF */ #define NV_CNVDEC_FALCON_DOC_CTRL_WR_FINISHED_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_DOC_CTRL_RD_FINISHED 20:20 /* R-IVF */ #define NV_CNVDEC_FALCON_DOC_CTRL_RD_FINISHED_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_DOC_CTRL_WR_ERROR 21:21 /* RWIVF */ #define NV_CNVDEC_FALCON_DOC_CTRL_WR_ERROR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DOC_CTRL_RD_ERROR 22:22 /* RWIVF */ #define NV_CNVDEC_FALCON_DOC_CTRL_RD_ERROR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DOC_CTRL_PROTOCOL_ERROR 23:23 /* RWIVF */ #define NV_CNVDEC_FALCON_DOC_CTRL_PROTOCOL_ERROR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DOC_D0 0x0000d100 /* RW-4R */ #define NV_CNVDEC_FALCON_DOC_D0__PRIV_LEVEL_MASK 0x00003b00 /* */ #define NV_CNVDEC_FALCON_DOC_D0_DATA 31:0 /* RW-VF */ #define NV_CNVDEC_FALCON_DOC_D1 0x0000d200 /* RW-4R */ #define NV_CNVDEC_FALCON_DOC_D1__PRIV_LEVEL_MASK 0x00003b00 /* */ #define NV_CNVDEC_FALCON_DOC_D1_DATA 31:0 /* RW-VF */ #define NV_CNVDEC_FALCON_DOC_D2 0x0000d300 /* RW-4R */ #define NV_CNVDEC_FALCON_DOC_D2__PRIV_LEVEL_MASK 0x00003b00 /* */ #define NV_CNVDEC_FALCON_DOC_D2_DATA 15:0 /* RW-VF */ #define NV_CNVDEC_FALCON_DIC_CTRL 0x0000d400 /* RW-4R */ #define NV_CNVDEC_FALCON_DIC_CTRL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_DIC_CTRL_COUNT 7:0 /* R--VF */ #define NV_CNVDEC_FALCON_DIC_CTRL_RESET 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_DIC_CTRL_RESET_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DIC_CTRL_VALID 19:19 /* R-IVF */ #define NV_CNVDEC_FALCON_DIC_CTRL_VALID_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_DIC_CTRL_POP 20:20 /* -W-VF */ #define NV_CNVDEC_FALCON_DIC_D0 0x0000d500 /* RW-4R */ #define NV_CNVDEC_FALCON_DIC_D0__PRIV_LEVEL_MASK 0x00003b00 /* */ #define NV_CNVDEC_FALCON_DIC_D0_DATA 31:0 /* RW-VF */ #define NV_CNVDEC_FALCON_DIC_D1 0x0000d600 /* RW-4R */ #define NV_CNVDEC_FALCON_DIC_D1__PRIV_LEVEL_MASK 0x00003b00 /* */ #define NV_CNVDEC_FALCON_DIC_D1_DATA 31:0 /* RW-VF */ #define NV_CNVDEC_FALCON_DIC_D2 0x0000d700 /* RW-4R */ #define NV_CNVDEC_FALCON_DIC_D2__PRIV_LEVEL_MASK 0x00003b00 /* */ #define NV_CNVDEC_FALCON_DIC_D2_DATA 15:0 /* RW-VF */ #define NV_CNVDEC_FALCON_DIO_ERR 0x0000d800 /* R--4R */ #define NV_CNVDEC_FALCON_DIO_ERR__PRIV_LEVEL_MASK 0x00003b00 /* */ #define NV_CNVDEC_FALCON_DIO_ERR_INFO 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x0000c000+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x0000fc00 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x0000c400+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x0000fd00 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x0000c800+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x0000fe00 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x0000cc00+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x0000ff00 /* */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PRGNVER 0x0000f500 /* R-I4R */ #define NV_CNVDEC_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_CNVDEC_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */ #define NV_CNVDEC_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_CNVDEC_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_CNVDEC_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG 0x00004200 /* R--4R */ #define NV_CNVDEC_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_CNVDEC_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_CNVDEC_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG1 0x00004b00 /* R--4R */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000003 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000010 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_CNVDEC_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2 0x00003d00 /* R--4R */ #define NV_CNVDEC_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_HWCFG3 0x00009e00 /* R--4R */ #define NV_CNVDEC_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_CNVDEC_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_CNVDEC_FALCON_CGCTL 0x00002800 /* RW-4R */ #define NV_CNVDEC_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2 0x00004d00 /* RWI4R */ #define NV_CNVDEC_FALCON_CG2__PRIV_LEVEL_MASK 0x00007a00 /* */ #define NV_CNVDEC_FALCON_CG2_SLCG 17:1 /* */ #define NV_CNVDEC_FALCON_CG2_SLCG_ENABLED 0 /* */ #define NV_CNVDEC_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */ #define NV_CNVDEC_FALCON_CG2_SLCG__PROD 0x000A0 /* */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_SHA 18:18 /* RWIVF */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_SHA__PROD 1 /* */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_SHA_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CG2_SLCG_FALCON_SHA_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_ENGID 0x00004f00 /* R--4R */ #define NV_CNVDEC_FALCON_ENGID_INSTID 7:0 /* R-IVF */ #define NV_CNVDEC_FALCON_ENGID_INSTID_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID 15:8 /* R--VF */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_SEC 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_DPU 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_NVDEC 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_PWR_PMU 0x00000004 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_FBFACLON 0x00000005 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_NVENC 0x00000006 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_GPCCS 0x00000007 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_FECS 0x00000008 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_MINION 0x00000009 /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_XUSB 0x0000000a /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_GSP 0x0000000b /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_NVJPG 0x0000000c /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_OFA 0x0000000d /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_PSC 0x0000000e /* R---V */ #define NV_CNVDEC_FALCON_ENGID_FAMILYID_SOE 0x0000000f /* R---V */ #define NV_CNVDEC_FALCON_SCTL 0x00009000 /* RW-4R */ #define NV_CNVDEC_FALCON_SCTL__PRIV_LEVEL_MASK 0x0000a600 /* */ #define NV_CNVDEC_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_CNVDEC_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_CNVDEC_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */ #define NV_CNVDEC_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL1 0x00009400 /* RW-4R */ #define NV_CNVDEC_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_CNVDEC_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_CNVDEC_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL 0x00003900 /* RW-4R */ #define NV_CNVDEC_FALCON_HSCTL__PRIV_LEVEL_MASK 0x00003a00 /* */ #define NV_CNVDEC_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_OS 0x00002000 /* RW-4R */ #define NV_CNVDEC_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_RM 0x00002100 /* RW-4R */ #define NV_CNVDEC_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SOFT_PM 0x00002200 /* RW-4R */ #define NV_CNVDEC_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CNVDEC_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_CNVDEC_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SOFT_MODE 0x00002300 /* RW-4R */ #define NV_CNVDEC_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CNVDEC_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PMM 0x00002a00 /* RW-4R */ #define NV_CNVDEC_FALCON_PMM__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_CODE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_IPND 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_SB 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x00000009 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0000000a /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0000000b /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0000000d /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0000000e /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x00000010 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x00000011 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_CNVDEC_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x00000009 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0x0000000a /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0x0000000b /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_CNVDEC_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL 19:16 /* RWIVF */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_FB_BSY 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_RDAT_WAIT 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ32BYTE 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ64BYTE 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ128BYTE 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_FB_BSY_SC 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_RDAT_WAIT_SC 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ32BYTE_SC 0x00000009 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ64BYTE_SC 0x0000000a /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_DSTAT_SEL_REQ128BYTE_SC 0x0000000b /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_WREQ 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RREQ 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_WREQ_SC 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x00000009 /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0x0000000a /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0x0000000b /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0x0000000d /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_RREQ_SC 0x0000000e /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_CNVDEC_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DEBUG1 0x00002400 /* RW-4R */ #define NV_CNVDEC_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CNVDEC_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */ #define NV_CNVDEC_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_CNVDEC_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_CNVDEC_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DEBUGINFO 0x00002500 /* RW-4R */ #define NV_CNVDEC_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_SP_MIN 0x00009c00 /* RW-4R */ #define NV_CNVDEC_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x00007c00 /* */ #define NV_CNVDEC_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_EXCI 0x00003400 /* R--4R */ #define NV_CNVDEC_FALCON_EXCI__PRIV_LEVEL_MASK 0x00007d00 /* */ #define NV_CNVDEC_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_BROM_CALL_INS 0x00000015 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_KMEM_VIOLATION_INS 0x00000016 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXCAUSE_BMEM_PERMISSION_INS 0x00000017 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_CNVDEC_FALCON_EXCI2 0x00002f00 /* R--4R */ #define NV_CNVDEC_FALCON_EXCI2__PRIV_LEVEL_MASK 0x00007d00 /* */ #define NV_CNVDEC_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_CNVDEC_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SVEC_SPR 0x00003500 /* R--4R */ #define NV_CNVDEC_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x00007e00 /* */ #define NV_CNVDEC_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_CNVDEC_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_CPUCTL 0x00004000 /* RW-4R */ #define NV_CNVDEC_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x0000a200 /* */ #define NV_CNVDEC_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_CNVDEC_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_CNVDEC_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_CNVDEC_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_CNVDEC_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_CNVDEC_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_CNVDEC_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_CNVDEC_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_CPUCTL_ALIAS 0x00004c00 /* -W-4R */ #define NV_CNVDEC_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_CNVDEC_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CNVDEC_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_CNVDEC_FALCON_STACKCFG 0x00004e00 /* RW-4R */ #define NV_CNVDEC_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_CNVDEC_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_BOOTVEC 0x00004100 /* RW-4R */ #define NV_CNVDEC_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x00006500 /* */ #define NV_CNVDEC_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL 0x00009500 /* RW-4R */ #define NV_CNVDEC_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x00006a00 /* */ #define NV_CNVDEC_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_CNVDEC_FALCON_DBGCTL_VAL_INIT 0 /* */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_CNVDEC_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT1 0x00002600 /* RW-4R */ #define NV_CNVDEC_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CNVDEC_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT2 0x00002700 /* RW-4R */ #define NV_CNVDEC_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CNVDEC_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT3 0x00002c00 /* RW-4R */ #define NV_CNVDEC_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CNVDEC_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT4 0x00002d00 /* RW-4R */ #define NV_CNVDEC_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CNVDEC_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT5 0x00002e00 /* RW-4R */ #define NV_CNVDEC_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CNVDEC_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD 0x00008000 /* RW-4R */ #define NV_CNVDEC_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_CNVDEC_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_CNVDEC_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_ADDR 0x00008100 /* RW-4R */ #define NV_CNVDEC_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CNVDEC_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_WDATA 0x00008200 /* RW-4R */ #define NV_CNVDEC_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CNVDEC_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_ICD_RDATA 0x00008300 /* R--4R */ #define NV_CNVDEC_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_CNVDEC_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_CNVDEC_FALCON_RSTAT0 0x00003600 /* R--4R */ #define NV_CNVDEC_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x00008900 /* */ #define NV_CNVDEC_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3 0x00003700 /* R--4R */ #define NV_CNVDEC_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_CNVDEC_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_CNVDEC_FALCON_TRACEIDX 0x00005200 /* RW-4R */ #define NV_CNVDEC_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CNVDEC_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_CNVDEC_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_CNVDEC_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_CNVDEC_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_TRACEPC 0x00005300 /* R--4R */ #define NV_CNVDEC_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CNVDEC_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_CNVDEC_FALCON_TRACEINFO 0x00005f00 /* R--4R */ #define NV_CNVDEC_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CNVDEC_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_CNVDEC_FALCON_IMCTL 0x00005000 /* RW-4R */ #define NV_CNVDEC_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_CNVDEC_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_CNVDEC_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_IMCTL_DEBUG 0x00005700 /* RW-4R */ #define NV_CNVDEC_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_CNVDEC_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_CNVDEC_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_IMSTAT 0x00005100 /* RW-4R */ #define NV_CNVDEC_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_IMFILLRNG0 0x00005400 /* RW-4R */ #define NV_CNVDEC_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IMFILLRNG0_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_CNVDEC_FALCON_IMFILLRNG0_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMFILLRNG1 0x00005500 /* RW-4R */ #define NV_CNVDEC_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IMFILLRNG1_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_CNVDEC_FALCON_IMFILLRNG1_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_IMFILLCTL 0x00005600 /* RW-4R */ #define NV_CNVDEC_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_CNVDEC_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMCTL 0x00009800 /* RW-4R */ #define NV_CNVDEC_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_CNVDEC_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_CNVDEC_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_DMSTAT 0x00009900 /* RW-4R */ #define NV_CNVDEC_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_DMVACTL 0x00009a00 /* RW-4R */ #define NV_CNVDEC_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x00006600 /* */ #define NV_CNVDEC_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMVACTL_BOUND_INIT 0x000000a0 /* RWI-V */ #define NV_CNVDEC_FALCON_DMCYA 0x00009b00 /* RW-4R */ #define NV_CNVDEC_FALCON_DMCYA__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CNVDEC_FALCON_DMCYA_LDSTVA_DIS 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_DMCYA_LDSTVA_DIS_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_DMCYA_LDSTVA_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_DMCYA_ROB_DIS 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_DMCYA_ROB_DIS_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMCYA_ROB_DIS_TRUE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMCYA_ROBWB_DIS 2:2 /* RWIVF */ #define NV_CNVDEC_FALCON_DMCYA_ROBWB_DIS_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMCYA_ROBWB_DIS_TRUE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_DMCYA_ROBSPR_DIS 3:3 /* RWIVF */ #define NV_CNVDEC_FALCON_DMCYA_ROBSPR_DIS_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_DMCYA_ROBSPR_DIS_TRUE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERRSTAT 0x00009100 /* RW-4R */ #define NV_CNVDEC_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CNVDEC_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_CNVDEC_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_CNVDEC_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_CSBERR_ADDR 0x00009300 /* R--4R */ #define NV_CNVDEC_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CNVDEC_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_CSBERR_INFO 0x00009200 /* R--4R */ #define NV_CNVDEC_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CNVDEC_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_KMEM_PDUK_IDX 0 #define NV_CNVDEC_FALCON_KMEM_PMUK_IDX 1 #define NV_CNVDEC_FALCON_KMEM_KEK_IDX 2 #define NV_CNVDEC_FALCON_KMEM_EK_LOW_IDX 3 #define NV_CNVDEC_FALCON_KMEM_EK_HIGH_IDX 4 #define NV_CNVDEC_FALCON_KMEM_MPK_LOW_IDX 6 #define NV_CNVDEC_FALCON_KMEM_MPK_HIGH_IDX 7 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_READ 0:0 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_READ_ENABLE 0x00000001 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_READ_DISABLE 0x00000000 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE 1:1 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE_ENABLE 0x00000001 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE_DISABLE 0x00000000 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_READ 2:2 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_READ_ENABLE 0x00000001 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_READ_DISABLE 0x00000000 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE 3:3 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE_ENABLE 0x00000001 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE_DISABLE 0x00000000 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_READ 4:4 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_READ_ENABLE 0x00000001 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_READ_DISABLE 0x00000000 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE 5:5 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE_ENABLE 0x00000001 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE_DISABLE 0x00000000 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_READ 6:6 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_READ_ENABLE 0x00000001 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_READ_DISABLE 0x00000000 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE 7:7 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE_ENABLE 0x00000001 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE_DISABLE 0x00000000 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_ACL_K0 8:8 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_ACL_K3 9:9 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_RECYCLABLE 10:10 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_PRIV_EN 11:11 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_NS_63LOADABLE 12:12 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_LS_63LOADABLE 13:13 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_HS_63LOADABLE 14:14 #define NV_CNVDEC_FALCON_KMEM_PROTECTINFO_UCODEIDMASK 31:15 #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK 0x00079400 /* RWI4R */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK 0x00079700 /* RWI4R */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK 0x00079500 /* RWI4R */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK 0x00074a00 /* RWI4R */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK__SETLVL_SIGNAL "setlvlm" /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK__CLRLVL_SIGNAL "clrlvlm" /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG 0x00070100 /* RW-4R */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_MODE 31:24 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA1 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA224 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA256 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA384 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA512 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA512_224 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_MODE_SHA512_256 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_ALG 15:12 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_ALG_SHA 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_ENC_ALG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_DST 4:2 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_CONFIG_DST_HASH_REG 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CONFIG_DST_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_CONFIG__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_TASK_CONFIG 0x00070200 /* RWI4R */ #define NV_CNVDEC_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_TASK_CONFIG__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_IN_ADDR 0x00070300 /* RW-4R */ #define NV_CNVDEC_FALCON_SHA_IN_ADDR_VAL 31:0 /* RWXVF */ #define NV_CNVDEC_FALCON_SHA_IN_ADDR__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_IN_ADDR_HI 0x00070400 /* RW-4R */ #define NV_CNVDEC_FALCON_SHA_IN_ADDR_HI_MSB 31:24 /* RWXVF */ #define NV_CNVDEC_FALCON_SHA_IN_ADDR_HI_SZ 23:0 /* RWXVF */ #define NV_CNVDEC_FALCON_SHA_IN_ADDR_HI__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_MSG_LENGTH(i) (0x00070700+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_SHA_MSG_LENGTH__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_SHA_MSG_LENGTH_VAL 31:0 /* RW-VF */ #define NV_CNVDEC_FALCON_SHA_MSG_LENGTH__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_MSG_LEFT(i) (0x00070b00+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_SHA_MSG_LEFT__SIZE_1 4 /* */ #define NV_CNVDEC_FALCON_SHA_MSG_LEFT_VAL 31:0 /* RW-VF */ #define NV_CNVDEC_FALCON_SHA_MSG_LEFT__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_HASH_RESULT(i) (0x00070f00+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_SHA_HASH_RESULT__SIZE_1 16 /* */ #define NV_CNVDEC_FALCON_SHA_HASH_RESULT_VAL 31:0 /* RW-VF */ #define NV_CNVDEC_FALCON_SHA_HASH_RESULT__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_OPERATION 0x00071f00 /* RWI4R */ #define NV_CNVDEC_FALCON_SHA_OPERATION_LAST_BUF 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_OPERATION_LAST_BUF_TRUE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_OPERATION_LAST_BUF_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_OPERATION_SOFTRESET 6:6 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_OPERATION_SOFTRESET_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_OPERATION_SOFTRESET_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_OPERATION_HALT 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_OPERATION_HALT_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_OPERATION_HALT_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_OPERATION_OP 2:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_OPERATION_OP_NOP 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_OPERATION_OP_START 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_OPERATION_OP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_OPERATION__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_STATUS 0x00072000 /* R-I4R */ #define NV_CNVDEC_FALCON_SHA_STATUS__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_STATUS_STATE 2:0 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_STATUS_STATE_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_STATUS_STATE_IDLE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_SHA_STATUS_STATE_BUSY 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_STATUS_STATE_HALTED 0x00000007 /* R---V */ #define NV_CNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR 0x00072100 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */ #define NV_CNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI 0x00072200 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_CNVDEC_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN 0x00072300 /* RW-4R */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_SET 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_UNSET 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_SET 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_UNSET 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR 0x00072400 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */ #define NV_CNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI 0x00072500 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_CNVDEC_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS 0x00074c00 /* RWI4R */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_LEVEL_ERR 12:12 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_LEVEL_ERR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_LEVEL_ERR_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_LEVEL_ERR_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_MULTI_HIT 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_MULTI_HIT_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_MULTI_HIT_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_MULTI_HIT_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_MISS 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_MISS_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_MISS_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_MISS_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_PA_FAULT 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_PA_FAULT_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_PA_FAULT_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_PA_FAULT_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_FBIF_ERR 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_FBIF_ERR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_FBIF_ERR_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_FBIF_ERR_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_NS_ACCESS 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_NS_ACCESS_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_NS_ACCESS_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS_NS_ACCESS_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_STATUS__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_ADDR 0x00074800 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_ERR_ADDR_VAL 31:0 /* R-XVF */ #define NV_CNVDEC_FALCON_SHA_ERR_ADDR__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_ERR_ADDR_HI 0x00074900 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_ERR_ADDR_HI_MSB 31:24 /* R-XVF */ #define NV_CNVDEC_FALCON_SHA_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS 0x00074d00 /* RWI4R */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS_ERR_STATUS 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS_ERR_STATUS_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS_ERR_STATUS_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS_ERR_STATUS_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS_OP_DONE 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS_OP_DONE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS_OP_DONE_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS_OP_DONE_CLEAR 1 /* */ #define NV_CNVDEC_FALCON_SHA_INT_STATUS__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_INT_ENABLE 0x00074e00 /* RWI4R */ #define NV_CNVDEC_FALCON_SHA_INT_ENABLE_ERR_STATUS 16:16 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_INT_ENABLE_ERR_STATUS_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_INT_ENABLE_ERR_STATUS_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_INT_ENABLE_OP_DONE 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_INT_ENABLE_OP_DONE_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_INT_ENABLE_OP_DONE_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_INT_ENABLE__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_MUTEX 0x00074000 /* -W-4R */ #define NV_CNVDEC_FALCON_SHA_MUTEX_VAL 7:0 /* -W-VF */ #define NV_CNVDEC_FALCON_SHA_MUTEX__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_MUTEX_RELEASE 0x00074100 /* -W-4R */ #define NV_CNVDEC_FALCON_SHA_MUTEX_RELEASE_VAL 7:0 /* -W-VF */ #define NV_CNVDEC_FALCON_SHA_MUTEX_RELEASE__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_MUTEX_STATUS 0x00074200 /* R-I4R */ #define NV_CNVDEC_FALCON_SHA_MUTEX_STATUS__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_MUTEX_STATUS_LOCKED 7:0 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_MUTEX_STATUS_LOCKED_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG 0x00074400 /* RW-4R */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_FB_BASE 24:16 /* RWXVF */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION 7:7 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_CTXDMA 6:4 /* RWXVF */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_SRC 1:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_SRC_DMEM 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_SRC_IMEM 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG_SRC_FB 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_SRC_CONFIG__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_REQ_CTRL 0x00074500 /* RW-4R */ #define NV_CNVDEC_FALCON_SHA_REQ_CTRL_WINDOW 31:16 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_REQ_CTRL_WINDOW_INIT 0x00001000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_REQ_CTRL_LIMIT 15:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_REQ_CTRL_LIMIT_INIT 0x00000800 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_REQ_CTRL__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_CTRL 0x00072600 /* RWI4R */ #define NV_CNVDEC_FALCON_SHA_CTRL__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_CTRL_FB_DIS 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_CTRL_FB_DIS_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_CTRL_FB_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CYA 0x00074600 /* RWI4R */ #define NV_CNVDEC_FALCON_SHA_CYA_BW_THROTTLE_DIS 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_SHA_CYA_BW_THROTTLE_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_SHA_CYA_BW_THROTTLE_DIS_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_SHA_CYA__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO 0x00074700 /* R-I4R */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_PW_HALTED 13:13 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_PW_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_PW_HALTED_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_IDMA_HALTED 12:12 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_IDMA_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_IDMA_HALTED_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_ALU_HALTED 11:11 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_ALU_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_ALU_HALTED_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_PW_IDLE 10:10 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_PW_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_PW_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_IDMA_IDLE 9:9 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_IDMA_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_IDMA_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_ALU_IDLE 8:8 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_ALU_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_ALU_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_CORE_STATUS 6:4 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_CORE_STATUS_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_CORE_STATUS_BUSY 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_SECURE_LEVEL 1:0 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_INFO_SECURE_LEVEL_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_0 0x00075000 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_0__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_0_SHA_SHA_PREPROC_STATE 11:10 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_0_SHA_WD_NUMBER 9:6 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_0_SHA_SHA_HASH_STATE 5:3 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_0_SHA_BYTE_COUNTER 2:0 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1 0x00075100 /* R-I4R */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN 18:18 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN 17:17 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS 14:14 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_2 0x00075200 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_2__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_SIZE 23:0 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_ADDR 31:24 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_3 0x00075300 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_3__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_3_SHA_IDMA_RESP_DMA_ADDR 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_4 0x00075400 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_4__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_4_SHA_IDMA_RESP_DMA_ADDR 8:0 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_4_SHA_IDMA_CORRECTED_RESP_DMA_SIZE 31:11 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_5 0x00075500 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_5__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_5_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 31:0 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6 0x00075600 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 12:0 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_FREE_COUNT 21:16 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH 24:24 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE 25:25 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE 26:26 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA 27:27 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_LASTBUF 28:28 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0 29:29 /* R-IVF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7 0x00075700 /* R--4R */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7__PRIV_LEVEL_MASK 0x00074a00 /* */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_PVLD 25:25 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_READ 24:24 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PRDY 23:23 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PVLD 22:22 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PRDY 21:21 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PVLD 20:20 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_VALID 15:15 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_STALL 14:14 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_PVLD 9:9 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_STALL 8:8 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PVLD 7:7 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PRDY 6:6 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PVLD 5:5 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PRDY 4:4 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_REQ 1:1 /* R--VF */ #define NV_CNVDEC_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_BUSY 0:0 /* R--VF */ #define NV_CNVDEC_FALCON_VER 0x00076200 /* R-I4R */ #define NV_CNVDEC_FALCON_VER_MAJOR 3:0 /* R-IVF */ #define NV_CNVDEC_FALCON_VER_MAJOR_DEFT 0x00000002 /* R-I-V */ #define NV_CNVDEC_FALCON_VER_MINOR 17:4 /* R-IVF */ #define NV_CNVDEC_FALCON_VER_MINOR_DEFT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_VER_BUGFIX 31:18 /* R-IVF */ #define NV_CNVDEC_FALCON_VER_BUGFIX_DEFT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_MOD_SEL 0x00076000 /* RWI4R */ #define NV_CNVDEC_FALCON_MOD_SEL_ALGO 7:0 /* RWIVF */ #define NV_CNVDEC_FALCON_MOD_SEL_ALGO_AES 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_MOD_SEL_ALGO_RSA3K 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_MOD_EN 0x00076100 /* RW-4R */ #define NV_CNVDEC_FALCON_MOD_EN_AES 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_MOD_EN_AES_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_MOD_EN_AES_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_MOD_EN_RSA3K 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_MOD_EN_RSA3K_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_MOD_EN_RSA3K_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_PKCBROM_VER 0x00076300 /* R--4R */ #define NV_CNVDEC_FALCON_PKCBROM_VER_DEV 11:0 /* R--VF */ #define NV_CNVDEC_FALCON_PKCBROM_VER_ECO 15:12 /* R--VF */ #define NV_CNVDEC_FALCON_PKCBROM_VER_MINOR 23:16 /* R--VF */ #define NV_CNVDEC_FALCON_PKCBROM_VER_MAJOR 31:24 /* R--VF */ #define NV_CNVDEC_FALCON_VHRCFG_BASE 0x00076400 /* R-I4R */ #define NV_CNVDEC_FALCON_VHRCFG_BASE_VAL 31:0 /* R-IVF */ #define NV_CNVDEC_FALCON_VHRCFG_BASE_VAL_SEC 0x00008200 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_BASE_VAL_PWR_PMU 0x000083f0 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_BASE_VAL_NVDEC 0x00008490 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_BASE_VAL_GSP 0x000087a0 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_BASE_VAL_SOE 0x00008200 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_BASE_VAL_PSC 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_BASE_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM 0x00077a00 /* R-I4R */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM_VAL 31:0 /* R-IVF */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM_VAL_SEC 0x0000000a /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM_VAL_PWR_PMU 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM_VAL_NVDEC 0x00000010 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM_VAL_GSP 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM_VAL_SOE 0x0000000a /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM_VAL_PSC 0x00000000 /* R---V */ #define NV_CNVDEC_FALCON_VHRCFG_ENTNUM_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_BMEMBASE 0x00076500 /* R-I4R */ #define NV_CNVDEC_FALCON_BMEMBASE_VAL 31:0 /* R-IVF */ #define NV_CNVDEC_FALCON_BMEMBASE_VAL_DEFT 0x02100000 /* R-I-V */ #define NV_CNVDEC_FALCON_BROM_CURR_UCODE_ID 0x00076600 /* RWI4R */ #define NV_CNVDEC_FALCON_BROM_CURR_UCODE_ID__PRIV_LEVEL_MASK 0x00079400 /* */ #define NV_CNVDEC_FALCON_BROM_CURR_UCODE_ID_VAL 7:0 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_CURR_UCODE_ID_VAL_DEFT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_CURR_UCODE_ID_VAL_MAX 0x00000010 /* RW--V */ #define NV_CNVDEC_FALCON_UCODE_VERSION(i) (0x00076a00+(i)*256) /* R-I4A */ #define NV_CNVDEC_FALCON_UCODE_VERSION__SIZE_1 16 /* */ #define NV_CNVDEC_FALCON_UCODE_VERSION_VER 7:0 /* R-IVF */ #define NV_CNVDEC_FALCON_UCODE_VERSION_VER_DEF 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK 0x00076700 /* RWI4R */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK__PRIV_LEVEL_MASK 0x00079400 /* */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_SEC 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_SEC_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_SEC_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_DPU 1:1 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_DPU_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_DPU_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVDEC 2:2 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVDEC_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVDEC_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_PMU 3:3 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_PMU_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_PMU_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_FBFALCON 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_FBFALCON_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_FBFALCON_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVENC 5:5 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVENC_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVENC_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_GPCCS 6:6 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_GPCCS_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_GPCCS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_FECS 7:7 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_FECS_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_FECS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_MINION 8:8 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_MINION_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_MINION_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_XUSB 9:9 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_XUSB_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_XUSB_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_GSP 10:10 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_GSP_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_GSP_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVJPG 11:11 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVJPG_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_NVJPG_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_OFA 12:12 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_OFA_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_OFA_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_PSC 13:13 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_PSC_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_PSC_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_SOE 14:14 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_SOE_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_ENGIDMASK_SOE_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL 0x00077b00 /* RWI4R */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL__PRIV_LEVEL_MASK 0x00079700 /* */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_VALID 0:0 /* R-IVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY 1:1 /* R-IVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD 4:4 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_VALID 8:8 /* R-IVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY 9:9 /* R-IVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD 12:12 /* RWIVF */ #define NV_CNVDEC_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FALCON_PR_CTKID 0x00077c00 /* R-I4R */ #define NV_CNVDEC_FALCON_PR_CTKID_VAL 7:0 /* R-IVF */ #define NV_CNVDEC_FALCON_PR_CTKID_VAL_DEF 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_BROM_FUNID 0x00076800 /* R-I4R */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID 7:0 /* R-IVF */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID_DEFT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID_DECFUSEKEY 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID_GENTK 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID_DECMPK 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID_SIGBYMPK 0x00000004 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID_CLRMPK 0x00000005 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID_ECDSASIGN 0x00000006 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_ID_ECDSAVERIF 0x00000007 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_CALLER_LVL 9:8 /* R-IVF */ #define NV_CNVDEC_FALCON_BROM_FUNID_CALLER_LVL_0 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_BROM_FUNID_CALLER_LVL_1 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_CALLER_LVL_2 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_BROM_FUNID_CALLER_LVL_3 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_BROM_PARAADDR(i) (0x00078400+(i)*256) /* RWI4A */ #define NV_CNVDEC_FALCON_BROM_PARAADDR__SIZE_1 1 /* */ #define NV_CNVDEC_FALCON_BROM_PARAADDR__PRIV_LEVEL_MASK 0x00079400 /* */ #define NV_CNVDEC_FALCON_BROM_PARAADDR_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_PARAADDR_VAL_DEFT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_RETCODE 0x00076900 /* RW-4R */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR 7:0 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_SUCCESS 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLFUNID 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_PA_FAULT 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NOT_IN_DMEM 0x00000003 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NO_ENOUGH_SPACE 0x00000004 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_VA_NOT_VALID 0x00000005 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_4BYTES 0x00000006 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_16BYTES 0x00000007 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_32BYTES 0x00000008 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_OUTPUT_NOT_ALLOWED 0x00000009 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_TK_PTR_IS_NS_READABLE 0x0000000a /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_NOT_CALLED_BY_HS 0x0000000b /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_CALL_FROM_LVL0 0x0000000c /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLUCODEID 0x0000000d /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_DISPOSE_MPK_FAIL 0x0000000e /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_CTKID_INVALID 0x0000000f /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLTKID 0x00000010 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_INVLDPMUK 0x00000011 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_INVLDPDUK 0x00000012 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_INVLDMPK 0x00000013 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_SIGFAIL 0x00000014 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_PDI_INVALID 0x00000015 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_LOAD_KMEM2SCP_FAIL 0x00000016 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_WRONG_PROTECTINFO 0x00000017 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_KSLT_K3_IS_0 0x00000018 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF16B 0x00000019 /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF32B 0x0000001a /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_RSVD_ZEROS 0x0000001b /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_MPK_IS_VALID 0x0000001c /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_SCP_ERR 0x0000001d /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_256BYTES 0x0000001e /* RW--V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERRID 19:8 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERRID_DEFT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_FUNID 23:20 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_RETCODE_FUNID_DEFT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERRINFO 31:24 /* RWIVF */ #define NV_CNVDEC_FALCON_BROM_RETCODE_ERRINFO_DEFT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEMBASE 0x00077d00 /* R-I4R */ #define NV_CNVDEC_FALCON_KMEMBASE_VAL 31:0 /* R-IVF */ #define NV_CNVDEC_FALCON_KMEMBASE_VAL_DEF 0x02000000 /* R-I-V */ #define NV_CNVDEC_FALCON_KMEMC(i) (0x00077e00+(i)*256) /* RWI4A */ #define NV_CNVDEC_FALCON_KMEMC__SIZE_1 2 /* */ #define NV_CNVDEC_FALCON_KMEMC__PRIV_LEVEL_MASK 0x00079500 /* */ #define NV_CNVDEC_FALCON_KMEMC_OFFS 15:2 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEMC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEMC_OFFS_PROTINFO 0x00000400 /* RW--V */ #define NV_CNVDEC_FALCON_KMEMC_OFFS_MAX 0x000005ff /* RW--V */ #define NV_CNVDEC_FALCON_KMEMC_AINCW 24:24 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_KMEMC_AINCW_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEMC_AINCR 25:25 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_KMEMC_AINCR_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEMC_ERR 28:26 /* R-IVF */ #define NV_CNVDEC_FALCON_KMEMC_ERR_SUCCESS 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_KMEMC_ERR_1 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_KMEMC_ERR_2 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_KMEMC_ERR_3 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_KMEMC_ERR_4 0x00000004 /* R---V */ #define NV_CNVDEC_FALCON_KMEMC_ERR_5 0x00000005 /* R---V */ #define NV_CNVDEC_FALCON_KMEMC_ERR_6 0x00000006 /* R---V */ #define NV_CNVDEC_FALCON_KMEMD(i) (0x00078000+(i)*256) /* RW-4A */ #define NV_CNVDEC_FALCON_KMEMD__SIZE_1 2 /* */ #define NV_CNVDEC_FALCON_KMEMD__PRIV_LEVEL_MASK 0x00079500 /* */ #define NV_CNVDEC_FALCON_KMEMD_DATA 31:0 /* RW-VF */ #define NV_CNVDEC_FALCON_KMEM_CTL 0x00078200 /* RWI4R */ #define NV_CNVDEC_FALCON_KMEM_CTL__PRIV_LEVEL_MASK 0x00079500 /* */ #define NV_CNVDEC_FALCON_KMEM_CTL_IDX 7:0 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_CTL_IDX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_CTL_CMD 19:16 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_CTL_CMD_NOP 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_CTL_CMD_DISPOSE 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_CTL_CMD_LOADTO63 0x00000002 /* RW--V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT 23:20 /* R-IVF */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_NOP 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_DISPOSE_DONE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_RECYCLABLE_IS_0 0x00000002 /* R---V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_PRIVDISABLED 0x00000003 /* R---V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_NOTWRITEABLE 0x00000004 /* R---V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_LOADTO63_DONE 0x00000005 /* R---V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_LOADABLE_IS_0 0x00000006 /* R---V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_PRIVDISABLED 0x00000007 /* R---V */ #define NV_CNVDEC_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_UCODIDMASK_IS_0 0x00000008 /* R---V */ #define NV_CNVDEC_FALCON_KMEMCFG 0x00078300 /* R-I4R */ #define NV_CNVDEC_FALCON_KMEMCFG_NUMOFKSLT 15:0 /* R-IVF */ #define NV_CNVDEC_FALCON_KMEMCFG_NUMOFKSLT_DEFT 0x00000100 /* R-I-V */ #define NV_CNVDEC_FALCON_KMEMCFG_KSLT_LENGTH 21:16 /* R-IVF */ #define NV_CNVDEC_FALCON_KMEMCFG_KSLT_LENGTH_DEFT 0x00000010 /* R-I-V */ #define NV_CNVDEC_FALCON_KMEMCFG_PROTECTINFO_LENGTH 25:22 /* R-IVF */ #define NV_CNVDEC_FALCON_KMEMCFG_PROTECTINFO_LENGTH_DEFT 0x00000008 /* R-I-V */ #define NV_CNVDEC_FALCON_KMEMCFG_BROM_USED_SLOTS 31:26 /* R-IVF */ #define NV_CNVDEC_FALCON_KMEMCFG_BROM_USED_SLOTS_DEFT 0x00000010 /* R-I-V */ #define NV_CNVDEC_FALCON_KMEM_VALID(i) (0x00078600+(i)*256) /* R-I4A */ #define NV_CNVDEC_FALCON_KMEM_VALID__SIZE_1 8 /* */ #define NV_CNVDEC_FALCON_KMEM_VALID__PRIV_LEVEL_MASK 0x00079500 /* */ #define NV_CNVDEC_FALCON_KMEM_VALID_VAL 31:0 /* R-IVF */ #define NV_CNVDEC_FALCON_KMEM_VALID_VAL_DEFT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_KMEM_VIOLATION_CTL 0x00078e00 /* RWI4R */ #define NV_CNVDEC_FALCON_KMEM_VIOLATION_CTL__PRIV_LEVEL_MASK 0x00079500 /* */ #define NV_CNVDEC_FALCON_KMEM_VIOLATION_CTL_ACT 0:0 /* RWIVF */ #define NV_CNVDEC_FALCON_KMEM_VIOLATION_CTL_ACT_HALT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FALCON_KMEM_VIOLATION_CTL_ACT_EXC 0x00000001 /* RW--V */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF 0x00078f00 /* R-I4R */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP 0:0 /* R-IVF */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_READ 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_WRITE 0x00000001 /* R---V */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL 5:4 /* R-IVF */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID 15:8 /* R-IVF */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX 23:16 /* R-IVF */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET 24:24 /* R-IVF */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_KSLT 0x00000000 /* R-I-V */ #define NV_CNVDEC_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_PROTINFO 0x00000001 /* R---V */ #define NV_CNVDEC_DBFCTL 0x0001b000 /* RW-4R */ #define NV_CNVDEC_DBFCTL_CODEC 2:0 /* RWIUF */ #define NV_CNVDEC_DBFCTL_CODEC_MPEG1 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFCTL_CODEC_MPEG2 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFCTL_CODEC_VC1 0x00000002 /* RW--V */ #define NV_CNVDEC_DBFCTL_CODEC_H264 0x00000003 /* RW--V */ #define NV_CNVDEC_DBFCTL_CODEC_MPEG4 0x00000004 /* RW--V */ #define NV_CNVDEC_DBFCTL_CODEC_VP8 0x00000005 /* RW--V */ #define NV_CNVDEC_DBFCTL_PQUANT 7:3 /* RWIUF */ #define NV_CNVDEC_DBFCTL_PQUANT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFCTL_INTERLACED 8:8 /* RWIUF */ #define NV_CNVDEC_DBFCTL_INTERLACED_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFCTL_MBAFF_FRAME 9:9 /* RWIUF */ #define NV_CNVDEC_DBFCTL_MBAFF_FRAME_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFCTL_MBAFF_FRAME_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFCTL_APPLE_OOLD_REF 10:10 /* RWIUF */ #define NV_CNVDEC_DBFCTL_APPLE_OOLD_REF_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFCTL_APPLE_OOLD_REF_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFCTL_MODE 12:11 /* RWIUF */ #define NV_CNVDEC_DBFCTL_MODE_NORMAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFCTL_MODE_SIMPLE 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFCTL_MODE_DISABLE 0x00000002 /* RW--V */ #define NV_CNVDEC_DBFCTL_SVC 11:11 /* RWIUF */ #define NV_CNVDEC_DBFCTL_SVC_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFCTL_SVC_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFINTRPTEN 0x0001b100 /* RW-4R */ #define NV_CNVDEC_DBFINTRPTEN_CFGERR 0:0 /* RWIUF */ #define NV_CNVDEC_DBFINTRPTEN_CFGERR_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFINTRPTEN_CFGERR_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFINTRPTEN_DMAERR 4:4 /* RWIUF */ #define NV_CNVDEC_DBFINTRPTEN_DMAERR_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFINTRPTEN_DMAERR_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFINTRPTEN_MVERR 8:8 /* RWIUF */ #define NV_CNVDEC_DBFINTRPTEN_MVERR_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFINTRPTEN_MVERR_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFINTRPTSTAT 0x0001b200 /* RW-4R */ #define NV_CNVDEC_DBFINTRPTSTAT_CFGERR 0:0 /* RWIUF */ #define NV_CNVDEC_DBFINTRPTSTAT_CFGERR_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFINTRPTSTAT_CFGERR_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFINTRPTSTAT_DMAERR 4:4 /* RWIUF */ #define NV_CNVDEC_DBFINTRPTSTAT_DMAERR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFINTRPTSTAT_DMAERR_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFINTRPTSTAT_MVERR 8:8 /* RWIUF */ #define NV_CNVDEC_DBFINTRPTSTAT_MVERR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFINTRPTSTAT_MVERR_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDBG1 0x0001b300 /* R--4R */ #define NV_CNVDEC_DBFDBG1_CUR_LUMA_ST 2:0 /* R-XUF */ #define NV_CNVDEC_DBFDBG1_CUR_CHRO_ST 5:3 /* R-XUF */ #define NV_CNVDEC_DBFDBG1_CUR_INPUT_ST 8:6 /* R-XUF */ #define NV_CNVDEC_DBFDBG1_PR_FCNT 16:9 /* R-XUF */ #define NV_CNVDEC_DBFDBG1_PR_FDONE 17:17 /* R-XUF */ #define NV_CNVDEC_DBFDBG1_INPUT_DONE 18:18 /* R-XUF */ #define NV_CNVDEC_DBFDBG1_OUTPUT_DONE 19:19 /* R-XUF */ #define NV_CNVDEC_MCLUMSCALE(i) (0x0001a000+(i)*256) /* RW-4A */ #define NV_CNVDEC_MCLUMSCALE__SIZE_1 3 /* */ #define NV_CNVDEC_MCLUMSCALE_SCALE1 5:0 /* RWXVF */ #define NV_CNVDEC_MCLUMSCALE_SCALE2 13:8 /* RWXVF */ #define NV_CNVDEC_MCLUMSHIFT(i) (0x0001a400+(i)*256) /* RW-4A */ #define NV_CNVDEC_MCLUMSHIFT__SIZE_1 3 /* */ #define NV_CNVDEC_MCLUMSHIFT_SHIFT1 5:0 /* RWXVF */ #define NV_CNVDEC_MCLUMSHIFT_SHIFT2 13:8 /* RWXVF */ #define NV_CNVDEC_MCCTL 0x0001a800 /* RW-4R */ #define NV_CNVDEC_MCCTL_RANGEADJUST 1:0 /* RWXVF */ #define NV_CNVDEC_MCCTL_RANGERND 2:2 /* RWXVF */ #define NV_CNVDEC_MCCTL_REGCFG 4:4 /* RWXVF */ #define NV_CNVDEC_MCCTL_REGCFG_WAIT 0x00000000 /* RWX-V */ #define NV_CNVDEC_MCCTL_REGCFG_DONE 0x00000001 /* RWX-V */ #define NV_CNVDEC_MCCTL_CODEC 7:5 /* RWIVF */ #define NV_CNVDEC_MCCTL_CODEC_MPEG1 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCCTL_CODEC_MPEG2 0x00000001 /* RW--V */ #define NV_CNVDEC_MCCTL_CODEC_VC1 0x00000002 /* RW--V */ #define NV_CNVDEC_MCCTL_CODEC_H264 0x00000003 /* RW--V */ #define NV_CNVDEC_MCCTL_CODEC_MPEG4 0x00000004 /* RW--V */ #define NV_CNVDEC_MCCTL_CODEC_VP8 0x00000005 /* RW--V */ #define NV_CNVDEC_MCINTRPTEN 0x0001a900 /* RW-4R */ #define NV_CNVDEC_MCINTRPTEN_CONFIGERR 0:0 /* RWXUF */ #define NV_CNVDEC_MCINTRPTEN_CONFIGERR_OFF 0x00000000 /* RWX-V */ #define NV_CNVDEC_MCINTRPTEN_CONFIGERR_ON 0x00000001 /* RWX-V */ #define NV_CNVDEC_MCINTRPTSTAT 0x0001aa00 /* RW-4R */ #define NV_CNVDEC_MCINTRPTSTAT_CONFIGERR 0:0 /* RWXUF */ #define NV_CNVDEC_MCINTRPTSTAT_CONFIGERR_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_MCINTRPTSTAT_CONFIGERR_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_MCDBG1 0x0001ab00 /* R--4R */ #define NV_CNVDEC_MCDBG1_CSB_IF_FSM 1:0 /* R-XUF */ #define NV_CNVDEC_MCDBG1_CSB_IF_FSM_INIT 0x00000002 /* R-I-V */ #define NV_CNVDEC_MCDBG1_RD_OUTBUF_FSM 4:2 /* R-XUF */ #define NV_CNVDEC_MCDBG1_BLK_VALID_STATUS 10:5 /* R-XUF */ #define NV_CNVDEC_MCDBG1_RD_BLK_VALID_STATUS 16:11 /* R-XUF */ #define NV_CNVDEC_MCDBG1_REF_BUF_FULL_STATUS 17:17 /* R-XUF */ #define NV_CNVDEC_MCDBG1_CMD4WP_BUF_RD_STATUS 18:18 /* R-XUF */ #define NV_CNVDEC_MCDBG1_CMD4WP_BUF_RD_STATUS_INIT 0x00000001 /* R-I-V */ #define NV_CNVDEC_MCDBG1_RD_OUTBUF_SEL 19:19 /* R-XUF */ #define NV_CNVDEC_MCDBG1_REF_BUF_EMPTY 20:20 /* R-XUF */ #define NV_CNVDEC_MCDBG1_REF_BUF_EMPTY_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_MCDBG1_CMD4FLT_BUF_EMPTY 21:21 /* R-XUF */ #define NV_CNVDEC_MCDBG1_CMD4FLT_BUF_EMPTY_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_MCDBG1_CMD4FLT_REG_EMPTY 22:22 /* R-XUF */ #define NV_CNVDEC_MCDBG1_CMD4FLT_REG_EMPTY_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_MCDBG1_DATA_PATH_IDLE 23:23 /* R-XUF */ #define NV_CNVDEC_MCDBG1_DATA_PATH_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_MCDBG1_WP_DATA_VALID_STG0 24:24 /* R-XUF */ #define NV_CNVDEC_MCDBG1_WP_DATA_VALID_STG1 25:25 /* R-XUF */ #define NV_CNVDEC_MCDBG1_WP_DATA_VALID_STG2 26:26 /* R-XUF */ #define NV_CNVDEC_MCDBG1_WP_DATA_VALID_STG3 27:27 /* R-XUF */ #define NV_CNVDEC_MCDBG1_WP_DATA_VALID_STG4 28:28 /* R-XUF */ #define NV_CNVDEC_MCDBG1_OUTBUF0_EMPTY 29:29 /* R-XUF */ #define NV_CNVDEC_MCDBG1_OUTBUF0_EMPTY_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_MCDBG1_OUTBUF1_EMPTY 30:30 /* R-XUF */ #define NV_CNVDEC_MCDBG1_OUTBUF1_EMPTY_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_MCDBG1_CMD4WP_BUF_EMPTY_REG 31:31 /* R-XUF */ #define NV_CNVDEC_MCDBG1_CMD4WP_BUF_EMPTY_REG_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_VERSION 0x0004c700 /* RW-4R */ #define NV_CNVDEC_VERSION_DEV 7:0 /* RWIVF */ #define NV_CNVDEC_VERSION_DEV_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VERSION_ECO 15:8 /* RWIVF */ #define NV_CNVDEC_VERSION_ECO_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VERSION_MINOR 23:16 /* RWIVF */ #define NV_CNVDEC_VERSION_MINOR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VERSION_MAJOR 31:24 /* RWIVF */ #define NV_CNVDEC_VERSION_MAJOR_INIT 0x00000005 /* RWI-V */ #define NV_CNVDEC_CAP_REG0 0x0004c100 /* RW-4R */ #define NV_CNVDEC_CAP_REG0_SECURE_RB 1:1 /* RWIVF */ #define NV_CNVDEC_CAP_REG0_SECURE_RB_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CAP_REG0_SECURE_RB_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CAP_REG0_VP8 2:2 /* RWIVF */ #define NV_CNVDEC_CAP_REG0_VP8_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CAP_REG0_VP8_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CAP_REG0_VP9_HBD 4:4 /* RWIVF */ #define NV_CNVDEC_CAP_REG0_VP9_HBD_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CAP_REG0_VP9_HBD_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CAP_REG0_HS_DIS 5:5 /* RWIVF */ #define NV_CNVDEC_CAP_REG0_HS_DIS_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_CAP_REG0_HS_DIS_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_CAP_REG0_RESERVED 31:6 /* RWIVF */ #define NV_CNVDEC_CAP_REG0_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_CAP_REG1 0x0004c200 /* RW-4R */ #define NV_CNVDEC_CAP_REG1_RESERVED 31:0 /* RWIVF */ #define NV_CNVDEC_CAP_REG1_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_CAP_REG2 0x0004c300 /* RW-4R */ #define NV_CNVDEC_CAP_REG2_RESERVED 31:0 /* RWIVF */ #define NV_CNVDEC_CAP_REG2_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_CAP_REG3 0x0004c400 /* RW-4R */ #define NV_CNVDEC_CAP_REG3_RESERVED 31:0 /* RWIVF */ #define NV_CNVDEC_CAP_REG3_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PERF_DECODE_FRAME 0x0004cd00 /* RW-4R */ #define NV_CNVDEC_PERF_DECODE_FRAME_V 31:0 /* RWIVF */ #define NV_CNVDEC_OTF_MODE 0x0004ce00 /* RW-4R */ #define NV_CNVDEC_OTF_MODE_EN 0:0 /* RWIVF */ #define NV_CNVDEC_PERF_DECODE_BW_LIMIT 0x0004cf00 /* RW-4R */ #define NV_CNVDEC_PERF_DECODE_BW_LIMIT_V 31:0 /* RWIVF */ #define NV_CNVDEC_CG 0x0004c800 /* RWE4R */ #define NV_CNVDEC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_CNVDEC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_CNVDEC_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_CNVDEC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_CNVDEC_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_CNVDEC_CG_IDLE_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG_STATE_CG_EN 7:7 /* */ #define NV_CNVDEC_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_CNVDEC_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_CNVDEC_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_CNVDEC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_CNVDEC_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_CNVDEC_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_CNVDEC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_CNVDEC_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_CNVDEC_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_CNVDEC_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_CNVDEC_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_CNVDEC_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_CNVDEC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_CNVDEC_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_CNVDEC_CG_WAKEUP_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_CNVDEC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_CNVDEC_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_CNVDEC_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_CNVDEC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_CNVDEC_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_CNVDEC_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_CNVDEC_CG_THROT_CLK_EN 28:28 /* */ #define NV_CNVDEC_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_CNVDEC_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_CNVDEC_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_CNVDEC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_CNVDEC_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_CNVDEC_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_CNVDEC_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_CNVDEC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_CNVDEC_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_CNVDEC_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_CNVDEC_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_CNVDEC_CG_HALT_CG_EN 31:31 /* */ #define NV_CNVDEC_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_CNVDEC_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_CNVDEC_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_CNVDEC_CG1 0x0004c900 /* RWE4R */ #define NV_CNVDEC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_CNVDEC_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_CNVDEC_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG1_SLCG 1:1 /* RWEVF */ #define NV_CNVDEC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */ #define NV_CNVDEC_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2 0x0004ca00 /* RW-4R */ #define NV_CNVDEC_CG2_SLCG 31:0 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG2_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_EDOB_DIS 0:0 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_EDOB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_EDOB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_EDOB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_SCP_DIS 1:1 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_SCP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_SCP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_SCP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_MEMACC_DIS 2:2 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_MEMACC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_MEMACC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_MEMACC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_FFCTL_DIS 3:3 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_FFCTL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_FFCTL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_FFCTL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_CBC_DIS 4:4 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_CBC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_CBC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_CBC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_CBCODATA_DIS 5:5 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_CBCODATA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_CBCODATA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_CBCODATA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_CVC_DIS 6:6 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_CVC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_CVC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_CVC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_MBPRED_DIS 7:7 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_MBPRED_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_MBPRED_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_MBPRED_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_MPG_DIS 8:8 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_MPG_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_MPG_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_MPG_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_SUBMBPRED_DIS 9:9 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_SUBMBPRED_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_SUBMBPRED_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_SUBMBPRED_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_VC1_DIS 10:10 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_VC1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_VC1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_VC1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_CVCNB_DIS 11:11 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_CVCNB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_CVCNB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_CVCNB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_RSDCTL_DIS 12:12 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_RSDCTL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_RSDCTL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_RSDCTL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_HIST_DIS 13:13 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_VLD_HIST_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_VLD_HIST_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_VLD_HIST_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_H264_DIS 14:14 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_H264_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_H264_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_H264_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MDXVA_DIS 15:15 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MDXVA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MDXVA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MDXVA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MPEG4_DIS 16:16 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MPEG4_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MPEG4_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MPEG4_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MPEG2_DIS 17:17 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MPEG2_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MPEG2_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_MPEG2_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VC1_DIS 18:18 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VC1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VC1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VC1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VDXVA_DIS 19:19 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VDXVA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VDXVA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VDXVA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VP8_DIS 20:20 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VP8_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VP8_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_SEQ_VP8_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_NMB_DIS 21:21 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_NMB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_NMB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_NMB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_CMB_DIS 22:22 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_CMB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_CMB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_CMB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_PMB_DIS 23:23 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_PMB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_PMB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_PMB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_MMB_DIS 24:24 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_MMB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_MMB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_MMB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_LMWT_DIS 25:25 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_LMWT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_LMWT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_LMWT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_CPA_DIS 26:26 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_CPA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_CPA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_CPA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_RCOL_DIS 27:27 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_RCOL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_RCOL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_RCOL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_WCOL_DIS 28:28 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_WCOL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_WCOL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_WCOL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_CPD_DIS 29:29 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_CPD_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_CPD_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_CPD_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_OSP_DBL_DIS 30:30 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_OSP_DBL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_OSP_DBL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_OSP_DBL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_OSP_RDS_DIS 31:31 /* RWIVF */ #define NV_CNVDEC_CG2_SLCG_MV_OSP_RDS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG2_SLCG_MV_OSP_RDS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG2_SLCG_MV_OSP_RDS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3 0x0004cb00 /* RW-4R */ #define NV_CNVDEC_CG3_SLCG 31:0 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG3_SLCG__PROD 0x00800000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_REC_DIS 0:0 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_REC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_REC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_REC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_MCS_DIS 1:1 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_MCS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_MCS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_MCS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_IS_DIS 2:2 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_MV_IS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_IS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_MV_IS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_ILPMB_DIS 3:3 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_MV_ILPMB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_ILPMB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_MV_ILPMB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_ILP_DIS 4:4 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_ILP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_ILP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_MV_OSP_ILP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_IQT_IQ_DIS 5:5 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_IQT_IQ_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_IQT_IQ_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_IQT_IQ_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_IQT_IT_DIS 6:6 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_IQT_IT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_IQT_IT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_IQT_IT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MCF_DIS 7:7 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_MCF_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MCF_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_MCF_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MCC_DIS 8:8 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_MCC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MCC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_MCC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MC_DIS 9:9 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_MC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_MC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_MC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_H264_DIS 10:10 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_H264_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_H264_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_H264_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_MPG_DIS 11:11 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_MPG_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_MPG_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_MPG_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_VC1_DIS 12:12 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_VC1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_VC1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_VC1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_HB_DIS 13:13 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_HB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_HB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_HB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_HIST_DIS 14:14 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_HIST_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_HIST_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_HIST_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_MV2REC_DIS 15:15 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_MV2REC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_MV2REC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_MV2REC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_REC2DBF_DIS 16:16 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_REC2DBF_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_REC2DBF_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_REC2DBF_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_RECIP_DIS 17:17 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_RECIP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_RECIP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_RECIP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_ILP_DIS 18:18 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_REC_ILP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_REC_ILP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_REC_ILP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_DBF_DIS 19:19 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_DBF_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_DBF_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_DBF_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_HIST_DIS 20:20 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_HIST_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_HIST_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_HIST_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_ILP_DIS 21:21 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_ILP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_ILP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_ILP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_DBFDMA_DIS 22:22 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_DBFDMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_DBFDMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_DBFDMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_CFG_DIS 23:23 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_CFG_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_CFG_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_CFG_DIS__PROD 0x00000001 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_ECDMA_DIS 24:24 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_ECDMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_ECDMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_ECDMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_LEGACY_DMA_MUX_DIS 25:25 /* RWIVF */ #define NV_CNVDEC_CG3_SLCG_LEGACY_DMA_MUX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG3_SLCG_LEGACY_DMA_MUX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG3_SLCG_LEGACY_DMA_MUX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_PMM 0x0002d700 /* RW-4R */ #define NV_CNVDEC_PMM_SEL0 9:0 /* RWIUF */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_REQ_ISSUED 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_REQ_ISSUED_SC 0x00000001 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_PRED_WAITING 0x00000002 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_PRED_WAITING_SC 0x00000003 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_PRED_STARTING 0x00000004 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_PRED_STARTING_SC 0x00000005 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_P2STALL_ALLOC 0x00000006 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_P2STALL_ALLOC_SC 0x00000007 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_P2STALL_FETCH 0x00000008 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_P2STALL_FETCH_SC 0x00000009 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_P2STALL_ADMWR 0x0000000a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_P2STALL_ADMWR_SC 0x0000000b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_LINE_STORED 0x0000000c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_LINE_STORED_SC 0x0000000d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_LINE_DISCARDED 0x0000000e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_LINE_DISCARDED_SC 0x0000000f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_REQ_MRQFULL 0x00000010 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_REQ_MRQFULL_SC 0x00000011 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_REQ_REQLIMIT 0x00000012 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_REQ_REQLIMIT_SC 0x00000013 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_START 0x00000014 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_START_SC 0x00000015 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_DONE 0x00000016 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_DONE_SC 0x00000017 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_MBDONE 0x00000018 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_MBDONE_SC 0x00000019 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_QSTALL 0x0000001a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_QSTALL_SC 0x0000001b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_IDLE 0x0000001c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_FB_MCF_RET_IDLE_SC 0x0000001d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_IDLE 0x0000001e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_IDLE_SC 0x0000001f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_READ_MV_STARVED 0x00000020 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_READ_MV_STARVED_SC 0x00000021 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_READ_DBF_STARVED 0x00000022 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_READ_DBF_STARVED_SC 0x00000023 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_READ_IQT_STARVED 0x00000024 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_READ_IQT_STARVED_SC 0x00000025 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_READ_REC_STARVED 0x00000026 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_READ_REC_STARVED_SC 0x00000027 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_WRITE_MV_FULL 0x00000028 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_WRITE_MV_FULL_SC 0x00000029 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_WRITE_DBF_FULL 0x0000002a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_WRITE_DBF_FULL_SC 0x0000002b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_WRITE_IQT_FULL 0x0000002c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_WRITE_IQT_FULL_SC 0x0000002d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_WRITE_REC_FULL 0x0000002e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_HIST_WRITE_REC_FULL_SC 0x0000002f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_IDLE 0x00000030 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_IDLE_SC 0x00000031 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_HALTED 0x00000032 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_HALTED_SC 0x00000033 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_WD_EXPIRED 0x00000034 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_WD_EXPIRED_SC 0x00000035 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_SOFT_PM1 0x00000036 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_SOFT_PM1_SC 0x00000037 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_SOFT_PM0 0x00000038 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_SOFT_PM0_SC 0x00000039 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_CONSUMED_WORD 0x0000003a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_CONSUMED_WORD_SC 0x0000003b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_COPY_NXT2CUR 0x0000003c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_COPY_NXT2CUR_SC 0x0000003d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_STALLED_ON_IS 0x0000003e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_STALLED_ON_IS_SC 0x0000003f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_COLOC_RD 0x00000040 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_COLOC_RD_SC 0x00000041 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_COLOC_WR 0x00000042 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_COLOC_WR_SC 0x00000043 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_RDS 0x00000044 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_RDS_SC 0x00000045 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_DBL 0x00000046 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_DBL_SC 0x00000047 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_MCS 0x00000048 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_MCS_SC 0x00000049 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_REC 0x0000004a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_REC_SC 0x0000004b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_HIST_RD 0x0000004c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_HIST_RD_SC 0x0000004d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_HIST_WR 0x0000004e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_HIST_WR_SC 0x0000004f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_READ_MV 0x00000050 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_READ_MV_SC 0x00000051 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_READ_HIST 0x00000052 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_READ_HIST_SC 0x00000053 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_WRITE_REC 0x00000054 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_WRITE_REC_SC 0x00000055 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_WRITE_HIST 0x00000056 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_WRITE_HIST_SC 0x00000057 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_IDLE 0x00000058 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_IDLE_SC 0x00000059 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_MACROBLOCK_START 0x0000005a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_MACROBLOCK_START_SC 0x0000005b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_MV 0x0000005c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_MV_SC 0x0000005d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_IQT 0x0000005e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_IQT_SC 0x0000005f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_MC 0x00000060 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_MC_SC 0x00000061 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_HIST 0x00000062 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_HIST_SC 0x00000063 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_HIST 0x00000064 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_HIST_SC 0x00000065 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_DBF 0x00000066 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_DBF_SC 0x00000067 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_IDLE 0x00000068 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_IDLE_SC 0x00000069 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_MACROBLOCK_END 0x0000006a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_MACROBLOCK_END_SC 0x0000006b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_STALLED_READ 0x0000006c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_STALLED_READ_SC 0x0000006d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_STALLED_WRITE 0x0000006e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_STALLED_WRITE_SC 0x0000006f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_MACROBLOCK_START 0x00000070 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_MACROBLOCK_START_SC 0x00000071 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_MACROBLOCK_END 0x00000072 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_MACROBLOCK_END_SC 0x00000073 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_IDLE 0x00000074 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_IDLE_SC 0x00000075 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_DATAPATH_VALID 0x00000076 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MC_DATAPATH_VALID_SC 0x00000077 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_STALLED_DBFDMA_READ 0x00000078 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_STALLED_DBFDMA_READ_SC 0x00000079 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_STALLED_REC_READ 0x0000007a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_STALLED_REC_READ_SC 0x0000007b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_STALLED_WRITE 0x0000007c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_STALLED_WRITE_SC 0x0000007d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_IDLE 0x0000007e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_IDLE_SC 0x0000007f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_MACROBLOCK_START 0x00000080 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_MACROBLOCK_START_SC 0x00000081 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_MACROBLOCK_BUSY 0x00000082 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_MACROBLOCK_BUSY_SC 0x00000083 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_PICTURE_START 0x00000084 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_PICTURE_START_SC 0x00000085 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_PICTURE_END 0x00000086 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBF_PICTURE_END_SC 0x00000087 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_STALLED_READ 0x00000088 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_STALLED_READ_SC 0x00000089 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_STALLED_WRITE 0x0000008a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_STALLED_WRITE_SC 0x0000008b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_IDLE 0x0000008c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_IDLE_SC 0x0000008d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_PICTURE_START 0x0000008e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_PICTURE_START_SC 0x0000008f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_PICTURE_END 0x00000090 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_PICTURE_END_SC 0x00000091 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_WRITE_FBIF 0x00000092 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_WRITE_FBIF_SC 0x00000093 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_READ_FBIF 0x00000094 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_IQT_STALLED_READ_FBIF_SC 0x00000095 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_STALLED_WRITE_ILP 0x00000096 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_DBFDMA_STALLED_WRITE_ILP_SC 0x00000097 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_CTRL_IDLE 0x00000098 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_CTRL_IDLE_SC 0x00000099 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_DMA_IDLE 0x0000009a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_DMA_IDLE_SC 0x0000009b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_FILTER_IDLE 0x0000009c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_FILTER_IDLE_SC 0x0000009d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_OUTBUF_IDLE 0x0000009e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_OUTBUF_IDLE_SC 0x0000009f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_WRDMA_IDLE 0x000000a0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_WRDMA_IDLE_SC 0x000000a1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_IDLE 0x000000a2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_IDLE_SC 0x000000a3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_DBFDMA2ILPDMA_MB_ONGOING 0x000000a4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_DBFDMA2ILPDMA_MB_ONGOING_SC 0x000000a5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_REC2ILPDMA_MB_ONGOING 0x000000a6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_REC2ILPDMA_MB_ONGOING_SC 0x000000a7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_ILPDMA2FB_ONGOING 0x000000a8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_ILPDMA2FB_ONGOING_SC 0x000000a9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_DMA_MB_START 0x000000aa /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_DMA_MB_START_SC 0x000000ab /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_DMA_MB_END 0x000000ac /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_DMA_MB_END_SC 0x000000ad /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_REGFIELD_MB_START 0x000000ae /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_REGFIELD_MB_START_SC 0x000000af /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_REGFIELD_MB_END 0x000000b0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_REGFIELD_MB_END_SC 0x000000b1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_SURFACE_NOTAVAIL 0x000000b2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_SURFACE_NOTAVAIL_SC 0x000000b3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_STALLED_ON_MV 0x000000b4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_STALLED_ON_MV_SC 0x000000b5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_STALLED_ON_REC 0x000000b6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_STALLED_ON_REC_SC 0x000000b7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_WAIT_FBIF 0x000000b8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_ILP_WAIT_FBIF_SC 0x000000b9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_ILPMB_RD 0x000000ba /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_ILPMB_RD_SC 0x000000bb /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_ILPMB_WR 0x000000bc /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MV_ME_WAIT_ILPMB_WR_SC 0x000000bd /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_ILP 0x000000be /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_READ_ILP_SC 0x000000bf /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_ILP 0x000000c0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_MSD_REC_STALLED_WRITE_ILP_SC 0x000000c1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_STALLED_READ 0x000000c2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_STALLED_EDOB 0x000000c3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_EDOB_STALLED_WRITE 0x000000c4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_EDOB_STALLED_LIMIT 0x000000c5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_AND_EDOB_STALLED 0x000000c6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_SLICEPARSER_BUSY 0x000000c7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_IDLE 0x000000c8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_SLICE_START 0x000000c9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_SLICE_END 0x000000ca /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_MACROBLOCK_START 0x000000cb /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_MACROBLOCK_END 0x000000cc /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_4BYTES_USED 0x000000cd /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_STALLED_READ_SC 0x000000ce /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_STALLED_EDOB_SC 0x000000cf /* RW--V */ #define NV_CNVDEC_PMM_SEL0_EDOB_STALLED_WRITE_SC 0x000000d0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_EDOB_STALLED_LIMIT_SC 0x000000d1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_AND_EDOB_STALLED_SC 0x000000d2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_SLICEPARSER_BUSY_SC 0x000000d3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_IDLE_SC 0x000000d4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_SLICE_START_SC 0x000000d5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_SLICE_END_SC 0x000000d6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_MACROBLOCK_START_SC 0x000000d7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_MACROBLOCK_END_SC 0x000000d8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_VLD_4BYTES_USED_SC 0x000000d9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_FRAME_START 0x000000da /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_FRAME_END 0x000000db /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_IQT_STALL_EMD 0x000000dc /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_IQT_WAIT_EMD 0x000000dd /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PRED_STALL_IQT 0x000000de /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PRED_WAIT_IQT 0x000000df /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_MVD_STALL_EMD 0x000000e0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_MVD_WAIT_EMD 0x000000e1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PREFETCH_STALL_MVD 0x000000e2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PREFETCH_WAIT_MVD 0x000000e3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PRED_WAIT_MCF 0x000000e4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PRED_INTRA_STALL_INTER 0x000000e5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_FILTER_STALL_PRED 0x000000e6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_FILTER_WAIT_PRED 0x000000e7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_SAO_STALL_FILTER 0x000000e8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_FRAME_START_SC 0x000000e9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_FRAME_END_SC 0x000000ea /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_IQT_STALL_EMD_SC 0x000000eb /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_IQT_WAIT_EMD_SC 0x000000ec /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PRED_STALL_IQT_SC 0x000000ed /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PRED_WAIT_IQT_SC 0x000000ee /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_MVD_STALL_EMD_SC 0x000000ef /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_MVD_WAIT_EMD_SC 0x000000f0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PREFETCH_STALL_MVD_SC 0x000000f1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PREFETCH_WAIT_MVD_SC 0x000000f2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PRED_WAIT_MCF_SC 0x000000f3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_PRED_INTRA_STALL_INTER_SC 0x000000f4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_FILTER_STALL_PRED_SC 0x000000f5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_FILTER_WAIT_PRED_SC 0x000000f6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_GIP_SAO_STALL_FILTER_SC 0x000000f7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x000000f8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x000000f9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_STATIC_PATTERN_1_1_GROUP_SC 0x000000fa /* RW--V */ #define NV_CNVDEC_PMM_SEL0_STATIC_PATTERN_0_1_GROUP_SC 0x000000fb /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLMVDATA_DMA2MVD_AV1_STALLING 0x00000100 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLMVDATA_DMA2MVD_AV1_STALLING_SC 0x00000101 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLMVDATA_DMA2MVD_AV1_STARVING 0x00000102 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLMVDATA_DMA2MVD_AV1_STARVING_SC 0x00000103 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLMVDATA_MVD2DMA_AV1_STALLING 0x00000104 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLMVDATA_MVD2DMA_AV1_STALLING_SC 0x00000105 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLMVDATA_MVD2DMA_AV1_STARVING 0x00000106 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLMVDATA_MVD2DMA_AV1_STARVING_SC 0x00000107 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLOC_CTRL_OUT_STALLING 0x00000108 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLOC_CTRL_OUT_STALLING_SC 0x00000109 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLOC_CTRL_OUT_STARVING 0x0000010a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLOC_CTRL_OUT_STARVING_SC 0x0000010b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLOC_MV_REF_PIC_BASE_STALLING 0x0000010c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLOC_MV_REF_PIC_BASE_STALLING_SC 0x0000010d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLOC_MV_REF_PIC_BASE_STARVING 0x0000010e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_COLOC_MV_REF_PIC_BASE_STARVING_SC 0x0000010f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2STREAMIF_DATA_STALLING 0x00000110 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2STREAMIF_DATA_STALLING_SC 0x00000111 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2STREAMIF_DATA_STARVING 0x00000112 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2STREAMIF_DATA_STARVING_SC 0x00000113 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2FILTER_CTB_CTRL_STALLING 0x00000114 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2FILTER_CTB_CTRL_STALLING_SC 0x00000115 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2FILTER_CTB_CTRL_STARVING 0x00000116 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2FILTER_CTB_CTRL_STARVING_SC 0x00000117 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2INTRA_PALETTE_DATA_STALLING 0x00000118 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2INTRA_PALETTE_DATA_STALLING_SC 0x00000119 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2INTRA_PALETTE_DATA_STARVING 0x0000011a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2INTRA_PALETTE_DATA_STARVING_SC 0x0000011b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2IQT_COEFF_STALLING 0x0000011c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2IQT_COEFF_STALLING_SC 0x0000011d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2IQT_COEFF_STARVING 0x0000011e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2IQT_COEFF_STARVING_SC 0x0000011f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2IQT_TU_CTRL_STALLING 0x00000120 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2IQT_TU_CTRL_STALLING_SC 0x00000121 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2IQT_TU_CTRL_STARVING 0x00000122 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP2IQT_TU_CTRL_STARVING_SC 0x00000123 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_RD_STALLING 0x00000124 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_RD_STALLING_SC 0x00000125 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_RD_STARVING 0x00000126 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_RD_STARVING_SC 0x00000127 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_WR_STALLING 0x00000128 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_WR_STALLING_SC 0x00000129 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_WR_STARVING 0x0000012a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_EP_DMA2FBIF_WR_STARVING_SC 0x0000012b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_CUCTRL_STALLING 0x0000012c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_CUCTRL_STALLING_SC 0x0000012d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_CUCTRL_STARVING 0x0000012e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_CUCTRL_STARVING_SC 0x0000012f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_MVCTRL_STALLING 0x00000130 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_MVCTRL_STALLING_SC 0x00000131 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_MVCTRL_STARVING 0x00000132 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MVD2PREFETCH_MVCTRL_STARVING_SC 0x00000133 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_STREAM_FIFO_STALLING 0x00000134 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_STREAM_FIFO_STALLING_SC 0x00000135 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_STREAM_FIFO_STARVING 0x00000136 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_STREAM_FIFO_STARVING_SC 0x00000137 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_STREAMIF2SA_DATA_STALLING 0x00000138 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_STREAMIF2SA_DATA_STALLING_SC 0x00000139 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_STREAMIF2SA_DATA_STARVING 0x0000013a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_STREAMIF2SA_DATA_STARVING_SC 0x0000013b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_SEGMENT_OUT_STALLING 0x0000013c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_SEGMENT_OUT_STALLING_SC 0x0000013d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_SEGMENT_OUT_STARVING 0x0000013e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_SEGMENT_OUT_STARVING_SC 0x0000013f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CU_CONTROL_INTER_STALLING 0x00000140 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CU_CONTROL_INTER_STALLING_SC 0x00000141 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CU_CONTROL_INTER_STARVING 0x00000142 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CU_CONTROL_INTER_STARVING_SC 0x00000143 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2IQT_DATA_STALLING 0x00000144 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2IQT_DATA_STALLING_SC 0x00000145 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2IQT_DATA_STARVING 0x00000146 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2IQT_DATA_STARVING_SC 0x00000147 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FETCH_CONTROL_OUT_STALLING 0x00000148 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FETCH_CONTROL_OUT_STALLING_SC 0x00000149 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FETCH_CONTROL_OUT_STARVING 0x0000014a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FETCH_CONTROL_OUT_STARVING_SC 0x0000014b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2DMA_DATA_STALLING 0x0000014c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2DMA_DATA_STALLING_SC 0x0000014d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2DMA_DATA_STARVING 0x0000014e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2DMA_DATA_STARVING_SC 0x0000014f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2INTRA_RESIDUAL_STALLING 0x00000150 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2INTRA_RESIDUAL_STALLING_SC 0x00000151 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2INTRA_RESIDUAL_STARVING 0x00000152 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2INTRA_RESIDUAL_STARVING_SC 0x00000153 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2INTRA_TU_CTRL_STALLING 0x00000154 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2INTRA_TU_CTRL_STALLING_SC 0x00000155 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2INTRA_TU_CTRL_STARVING 0x00000156 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQT2INTRA_TU_CTRL_STARVING_SC 0x00000157 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQTDMA2FBIF_RD_REQ_STALLING 0x00000158 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQTDMA2FBIF_RD_REQ_STALLING_SC 0x00000159 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQTDMA2FBIF_RD_REQ_STARVING 0x0000015a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_IQTDMA2FBIF_RD_REQ_STARVING_SC 0x0000015b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MV_CONTROL_INTER_STALLING 0x0000015c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MV_CONTROL_INTER_STALLING_SC 0x0000015d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MV_CONTROL_INTER_STARVING 0x0000015e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MV_CONTROL_INTER_STARVING_SC 0x0000015f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PART_CONTROL_INTER_STALLING 0x00000160 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PART_CONTROL_INTER_STALLING_SC 0x00000161 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PART_CONTROL_INTER_STARVING 0x00000162 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PART_CONTROL_INTER_STARVING_SC 0x00000163 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PREFETCH2INTRA_CU_CTRL_STALLING 0x00000164 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PREFETCH2INTRA_CU_CTRL_STALLING_SC 0x00000165 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PREFETCH2INTRA_CU_CTRL_STARVING 0x00000166 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PREFETCH2INTRA_CU_CTRL_STARVING_SC 0x00000167 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TU_CONTROL_INTER_STALLING 0x00000168 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TU_CONTROL_INTER_STALLING_SC 0x00000169 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TU_CONTROL_INTER_STARVING 0x0000016a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TU_CONTROL_INTER_STARVING_SC 0x0000016b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CU_CONTROL_FILTER_OUT_STALLING 0x0000016c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CU_CONTROL_FILTER_OUT_STALLING_SC 0x0000016d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CU_CONTROL_FILTER_OUT_STARVING 0x0000016e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CU_CONTROL_FILTER_OUT_STARVING_SC 0x0000016f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2INTRA_DATA_STALLING 0x00000170 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2INTRA_DATA_STALLING_SC 0x00000171 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2INTRA_DATA_STARVING 0x00000172 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2INTRA_DATA_STARVING_SC 0x00000173 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRA2DMA_DATA_STALLING 0x00000174 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRA2DMA_DATA_STALLING_SC 0x00000175 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRA2DMA_DATA_STARVING 0x00000176 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRA2DMA_DATA_STARVING_SC 0x00000177 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRA2FILTER_TILE_INFO_STALLING 0x00000178 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRA2FILTER_TILE_INFO_STALLING_SC 0x00000179 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRA2FILTER_TILE_INFO_STARVING 0x0000017a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRA2FILTER_TILE_INFO_STARVING_SC 0x0000017b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_RD_REQ_STALLING 0x0000017c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_RD_REQ_STALLING_SC 0x0000017d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_RD_REQ_STARVING 0x0000017e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_RD_REQ_STARVING_SC 0x0000017f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_WR_STALLING 0x00000180 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_WR_STALLING_SC 0x00000181 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_WR_STARVING 0x00000182 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_INTRADMA2FBIF_WR_STARVING_SC 0x00000183 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MV_CONTROL_FILTER_OUT_STALLING 0x00000184 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MV_CONTROL_FILTER_OUT_STALLING_SC 0x00000185 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MV_CONTROL_FILTER_OUT_STARVING 0x00000186 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_MV_CONTROL_FILTER_OUT_STARVING_SC 0x00000187 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_RECON2FILTER_DATA_STALLING 0x00000188 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_RECON2FILTER_DATA_STALLING_SC 0x00000189 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_RECON2FILTER_DATA_STARVING 0x0000018a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_RECON2FILTER_DATA_STARVING_SC 0x0000018b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TILEINFO_STALLING 0x0000018c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TILEINFO_STALLING_SC 0x0000018d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TILEINFO_STARVING 0x0000018e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TILEINFO_STARVING_SC 0x0000018f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TU_CONTROL_FILTER_OUT_STALLING 0x00000190 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TU_CONTROL_FILTER_OUT_STALLING_SC 0x00000191 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TU_CONTROL_FILTER_OUT_STARVING 0x00000192 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_TU_CONTROL_FILTER_OUT_STARVING_SC 0x00000193 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CDEF_LEFT_NB_OUT_STALLING 0x00000194 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CDEF_LEFT_NB_OUT_STALLING_SC 0x00000195 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CDEF_LEFT_NB_OUT_STARVING 0x00000196 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_CDEF_LEFT_NB_OUT_STARVING_SC 0x00000197 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK2DMA_TILE_INFO_STALLING 0x00000198 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK2DMA_TILE_INFO_STALLING_SC 0x00000199 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK2DMA_TILE_INFO_STARVING 0x0000019a /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK2DMA_TILE_INFO_STARVING_SC 0x0000019b /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK_LEFT_NB_OUT_STALLING 0x0000019c /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK_LEFT_NB_OUT_STALLING_SC 0x0000019d /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK_LEFT_NB_OUT_STARVING 0x0000019e /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK_LEFT_NB_OUT_STARVING_SC 0x0000019f /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK_TOP_NB_OUT_STALLING 0x000001a0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK_TOP_NB_OUT_STALLING_SC 0x000001a1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK_TOP_NB_OUT_STARVING 0x000001a2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DBLK_TOP_NB_OUT_STARVING_SC 0x000001a3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2FGS_LU_STALLING 0x000001a4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2FGS_LU_STALLING_SC 0x000001a5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2FGS_LU_STARVING 0x000001a6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2FGS_LU_STARVING_SC 0x000001a7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2FGS_NOISE_DATA_STALLING 0x000001a8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2FGS_NOISE_DATA_STALLING_SC 0x000001a9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2FGS_NOISE_DATA_STARVING 0x000001aa /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_DMA2FGS_NOISE_DATA_STARVING_SC 0x000001ab /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FBIF_RD_REQ_STALLING 0x000001ac /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FBIF_RD_REQ_STALLING_SC 0x000001ad /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FBIF_RD_REQ_STARVING 0x000001ae /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FBIF_RD_REQ_STARVING_SC 0x000001af /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FBIF_WR_REQ_STALLING 0x000001b0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FBIF_WR_REQ_STALLING_SC 0x000001b1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FBIF_WR_REQ_STARVING 0x000001b2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FBIF_WR_REQ_STARVING_SC 0x000001b3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS2DMA_LU_STALLING 0x000001b4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS2DMA_LU_STALLING_SC 0x000001b5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS2DMA_LU_STARVING 0x000001b6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS2DMA_LU_STARVING_SC 0x000001b7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS_PP2TF_CTRL_STALLING 0x000001b8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS_PP2TF_CTRL_STALLING_SC 0x000001b9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS_PP2TF_CTRL_STARVING 0x000001ba /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS_PP2TF_CTRL_STARVING_SC 0x000001bb /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS_PP2TF_DATA_STALLING 0x000001bc /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS_PP2TF_DATA_STALLING_SC 0x000001bd /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS_PP2TF_DATA_STARVING 0x000001be /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_FGS_PP2TF_DATA_STARVING_SC 0x000001bf /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_HUS_LEFT_NB_OUT_STALLING 0x000001c0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_HUS_LEFT_NB_OUT_STALLING_SC 0x000001c1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_HUS_LEFT_NB_OUT_STARVING 0x000001c2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_HUS_LEFT_NB_OUT_STARVING_SC 0x000001c3 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_LR_LEFT_NB_OUT_STALLING 0x000001c4 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_LR_LEFT_NB_OUT_STALLING_SC 0x000001c5 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_LR_LEFT_NB_OUT_STARVING 0x000001c6 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_LR_LEFT_NB_OUT_STARVING_SC 0x000001c7 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PP2HIST_DMA_STALLING 0x000001c8 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PP2HIST_DMA_STALLING_SC 0x000001c9 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PP2HIST_DMA_STARVING 0x000001ca /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PP2HIST_DMA_STARVING_SC 0x000001cb /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PP2TF_CTRL_STALLING 0x000001cc /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PP2TF_CTRL_STALLING_SC 0x000001cd /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PP2TF_CTRL_STARVING 0x000001ce /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_PP2TF_CTRL_STARVING_SC 0x000001cf /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_SAO_LEFT_NB_OUT_STALLING 0x000001d0 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_SAO_LEFT_NB_OUT_STALLING_SC 0x000001d1 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_SAO_LEFT_NB_OUT_STARVING 0x000001d2 /* RW--V */ #define NV_CNVDEC_PMM_SEL0_AVD_SAO_LEFT_NB_OUT_STARVING_SC 0x000001d3 /* RW--V */ #define NV_CNVDEC_PMM_SEL1 19:10 /* RWIUF */ #define NV_CNVDEC_PMM_SEL1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM_SEL2 29:20 /* RWIUF */ #define NV_CNVDEC_PMM_SEL2_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM_BUSEN 31:31 /* RWIUF */ #define NV_CNVDEC_PMM_BUSEN_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM_BUSEN_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_PMM1 0x0002d600 /* RW-4R */ #define NV_CNVDEC_PMM1_SEL0 9:0 /* RWIUF */ #define NV_CNVDEC_PMM1_SEL0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM1_SEL1 19:10 /* RWIUF */ #define NV_CNVDEC_PMM1_SEL1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM1_SEL2 29:20 /* RWIUF */ #define NV_CNVDEC_PMM1_SEL2_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM2 0x0002d500 /* RW-4R */ #define NV_CNVDEC_PMM2_SEL0 9:0 /* RWIUF */ #define NV_CNVDEC_PMM2_SEL0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM2_SEL1 19:10 /* RWIUF */ #define NV_CNVDEC_PMM2_SEL1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM2_SEL2 29:20 /* RWIUF */ #define NV_CNVDEC_PMM2_SEL2_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM3 0x0002d400 /* RW-4R */ #define NV_CNVDEC_PMM3_SEL0 9:0 /* RWIUF */ #define NV_CNVDEC_PMM3_SEL0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM3_SEL1 19:10 /* RWIUF */ #define NV_CNVDEC_PMM3_SEL1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM3_SEL2 29:20 /* RWIUF */ #define NV_CNVDEC_PMM3_SEL2_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM_LTA 0x0002d300 /* RW-4R */ #define NV_CNVDEC_PMM_LTA_LOCAL_TRIGGERA 31:31 /* RWIUF */ #define NV_CNVDEC_PMM_LTA_LOCAL_TRIGGERA_INIT_VAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM_LTA_LOCAL_BKMKA 15:0 /* RWIUF */ #define NV_CNVDEC_PMM_LTA_LOCAL_BKMKA_INIT_VAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM_LTB 0x0002d200 /* RW-4R */ #define NV_CNVDEC_PMM_LTB_LOCAL_TRIGGERB 31:31 /* RWIUF */ #define NV_CNVDEC_PMM_LTB_LOCAL_TRIGGERB_INIT_VAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_PMM_LTB_LOCAL_BKMKB 15:0 /* RWIUF */ #define NV_CNVDEC_PMM_LTB_LOCAL_BKMKB_INIT_VAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECCTL 0x0002c000 /* RW-4R */ #define NV_CNVDEC_RECCTL_CODEC 2:0 /* RWIVF */ #define NV_CNVDEC_RECCTL_CODEC_MPEG1 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECCTL_CODEC_MPEG2 0x00000001 /* RW--V */ #define NV_CNVDEC_RECCTL_CODEC_VC1 0x00000002 /* RW--V */ #define NV_CNVDEC_RECCTL_CODEC_H264 0x00000003 /* RW--V */ #define NV_CNVDEC_RECCTL_CODEC_MPEG4 0x00000004 /* RW--V */ #define NV_CNVDEC_RECCTL_CODEC_VP8 0x00000005 /* RW--V */ #define NV_CNVDEC_RECCTL_REGCFG 3:3 /* RWIVF */ #define NV_CNVDEC_RECCTL_REGCFG_WAIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECCTL_REGCFG_DONE 0x00000001 /* RW--V */ #define NV_CNVDEC_RECCTL_OVRHORZ 4:4 /* RWIVF */ #define NV_CNVDEC_RECCTL_OVRHORZ_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECCTL_MBAFF 5:5 /* RWIVF */ #define NV_CNVDEC_RECCTL_MBAFF_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECCTL_LOSSLESS_I8X8_PREFILT 6:6 /* RWIVF */ #define NV_CNVDEC_RECCTL_LOSSLESS_I8X8_PREFILT_ENABLE 0x00000001 /* RWI-V */ #define NV_CNVDEC_RECCTL_LOSSLESS_I8X8_PREFILT_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_RECCTL_INTRA_ALLOW_RES_PRED 7:7 /* RWIVF */ #define NV_CNVDEC_RECCTL_INTRA_ALLOW_RES_PRED_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_RECCTL_INTRA_ALLOW_RES_PRED_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECCTL_ILP_ENABLE 8:8 /* RWIVF */ #define NV_CNVDEC_RECCTL_ILP_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECCTL_DBF_DISABLE 9:9 /* RWIVF */ #define NV_CNVDEC_RECCTL_DBF_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECCTL_MCS_DISABLE 10:10 /* RWIVF */ #define NV_CNVDEC_RECCTL_MCS_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECINTEN 0x0002c100 /* RW-4R */ #define NV_CNVDEC_RECINTEN_IRQ_CFGWR 0:0 /* RW-VF */ #define NV_CNVDEC_RECINTEN_IRQ_CFGWR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_RECINTCSW 0x0002c200 /* RW-4R */ #define NV_CNVDEC_RECINTCSW_IRQ_CFGWR 0:0 /* RW-VF */ #define NV_CNVDEC_RECDBG1 0x0002c300 /* R--4R */ #define NV_CNVDEC_RECDBG1_H264_CUR_ST 2:0 /* R-XUF */ #define NV_CNVDEC_RECDBG1_INIT_CUR_ST 4:3 /* R-XUF */ #define NV_CNVDEC_RECDBG1_DP_CUR_ST 6:5 /* R-XUF */ #define NV_CNVDEC_RECDBG1_DI_CUR_ST 8:7 /* R-XUF */ #define NV_CNVDEC_RECDBG1_MPEG_CUR_ST 9:9 /* R-XUF */ #define NV_CNVDEC_RECDBG1_HIST2REC_RD_CUR_ST 11:10 /* R-XUF */ #define NV_CNVDEC_RECDBG1_MV2REC_RD_CUR_ST 12:12 /* R-XUF */ #define NV_CNVDEC_RECDBG1_REC2DBF_RD_CUR_ST 15:13 /* R-XUF */ #define NV_CNVDEC_RECDBG1_REC2DBF_RD_CUR_ST_IDLE 0x00000001 /* R-I-V */ #define NV_CNVDEC_RECDBG1_REC2HIST_RD_CUR_ST 18:16 /* R-XUF */ #define NV_CNVDEC_RECDBG1_IQT_CUR_ST 19:19 /* R-XUF */ #define NV_CNVDEC_RECDBG1_VC1_CUR_ST 22:20 /* R-XUF */ #define NV_CNVDEC_RECDBG1_LES_CUR_ST 24:23 /* R-XUF */ #define NV_CNVDEC_RECDBG1_TES_CUR_ST 26:25 /* R-XUF */ #define NV_CNVDEC_RECDBG1_RSI_CUR_ST 28:27 /* R-XUF */ #define NV_CNVDEC_RECDBG1_RCTL_CUR_ST 30:29 /* R-XUF */ #define NV_CNVDEC_RECDBG2 0x0002c400 /* R--4R */ #define NV_CNVDEC_RECDBG2_CFG_CUR_ST 1:0 /* R-XUF */ #define NV_CNVDEC_RECDBG2_CFG_CUR_ST_RD 0x00000002 /* R-I-V */ #define NV_CNVDEC_RECDBG2_INTER_CUR_ST 3:2 /* R-XUF */ #define NV_CNVDEC_RECDBG2_REC_IDLE 4:4 /* R-XUF */ #define NV_CNVDEC_RECDBG2_REC_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_RECDBG2_RECIP_IDLE 5:5 /* R-XUF */ #define NV_CNVDEC_RECDBG2_RECIP_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_RECDBG2_MV2REC_IDLE 6:6 /* R-XUF */ #define NV_CNVDEC_RECDBG2_MV2REC_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_RECDBG2_REC2DBF_IDLE 7:7 /* R-XUF */ #define NV_CNVDEC_RECDBG2_REC2DBF_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_RECDBG2_REC2HIST_IDLE 8:8 /* R-XUF */ #define NV_CNVDEC_RECDBG2_REC2HIST_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_RECDBG2_ILP2REC_RD_CUR_ST 9:9 /* R-XUF */ #define NV_CNVDEC_RECDBG2_ILP2REC_RD_CUR_ST_PK0 0x00000000 /* R-I-V */ #define NV_CNVDEC_RECDBG2_ILP2REC_RD_CUR_ST_PK1 0x00000001 /* R---V */ #define NV_CNVDEC_RECDBG2_REC2ILP_RD_CUR_ST 11:10 /* R-XUF */ #define NV_CNVDEC_RECDBG2_REC2ILP_RD_CUR_ST_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_RECDBG2_REC2ILP_RD_CUR_ST_CTRL 0x00000001 /* R---V */ #define NV_CNVDEC_RECDBG2_REC2ILP_RD_CUR_ST_DATA 0x00000002 /* R---V */ #define NV_CNVDEC_RECDBG2_REC2ILP_RD_CUR_ST_EMPT 0x00000003 /* R---V */ #define NV_CNVDEC_RECDBG2_REC2ILP_IDLE 12:12 /* R-XUF */ #define NV_CNVDEC_RECDBG2_REC2ILP_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON 0x00010000 /* RW-4R */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_WIDTH_IN_MBS 7:0 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_FRAME_HEIGHT_IN_MBS 15:8 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_TYPE 17:16 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_TYPE_FRAME 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_TYPE_TOP_FIELD 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_TYPE_BOTTOM_FIELD 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING 19:18 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG_D 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG_I 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG_B 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1_SKIPPED 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1_I_OR_BI 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VC1_B 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG4_SKIPPED 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG4_I 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG4_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_MPEG4_B 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VP8_I 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PIC_CODING_VP8_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE 22:20 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_MPEG1 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_MPEG2 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_VC1 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_H264 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_MPEG4 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_STREAM_TYPE_VP8 0x00000005 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PROFILE 25:24 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PROFILE_VC1_SIMPLE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PROFILE_VC1_MAIN 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PROFILE_VC1_ADVANCED 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_PROFILE_MPEG4_SHORT_HEADER 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_SSM_EN 26:26 /* RWIVF */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_SSM_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_SSM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA 27:27 /* RWIVF */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_PIC_INFO_H264 0x00010100 /* RW-4R */ #define NV_CNVDEC_VLD_PIC_INFO_H264_CABAC 0:0 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_H264_CABAC_CAVLC 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_H264_CABAC_CABAC 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_H264_MBAFF_FRAME_FLAG 9:9 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_H264_NALUNIT_TYPE 16:12 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_H264_CONSTRAINED_INTRA_PRED_FLAG 17:17 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_H264_CABAC_INIT_IDC 19:18 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_H264_CHROMA_FORMAT_IDC 21:20 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_H264_DIRECT_8X8_INFERENCE_FLAG 22:22 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_H264_TRANSFORM_8X8_MODE_FLAG 23:23 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2 0x00010200 /* RW-4R */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2_INTRA_DC_PRECISION 1:0 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2_FRAME_PRED_FRAME_DCT 2:2 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2_INTRA_VLC_FORMAT 3:3 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2_CONCEALMENT_MOTION_VEC 4:4 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2_F_CODE00 19:16 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2_F_CODE01 23:20 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2_F_CODE10 27:24 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_MPEG2_F_CODE11 31:28 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB 0x00010300 /* RW-4R */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_SLICE_ADDR 6:0 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_NUM_REF 7:7 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_NUM_REF_ONE_REF_PIC 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_NUM_REF_TWO_REF_PIC 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_FCM 9:8 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_FCM_PROGRESSIVE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_FCM_FRAME_INTERLACE 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_FCM_FIELD_INTERLACE 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_FCM_MPEG4_INTERLACE 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_REF_DIST 11:10 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_REF_FIELD 12:12 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_REF_FIELD_TEMP_CLOSEST 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_REF_FIELD_SECOND_MOST_TEMP_CLOSEST 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_FIELD_TX 16:16 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_FIELD_TX_RAW 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_FIELD_TX_BITPLANE 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1GB_SLICE_ADDRX 31:24 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T 0x00010400 /* RW-4R */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_CBP_TAB 2:0 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_MV_TAB 6:4 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TWO_MV_BP_TAB 9:8 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_FOUR_MV_BP_TAB 11:10 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_MB_MODE_TAB 14:12 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_DC_TAB 16:16 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_DC_TAB_LOW_MOTION 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_DC_TAB_HIGH_MOTION 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_ESC_LVL_SZ_TAB 17:17 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_ESC_LVL_SZ_TAB_TABLE59 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_ESC_LVL_SZ_TAB_TABLE60 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1 21:20 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1_HIGH_RATE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1_LOW_MOTION 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1_HIGH_MOTION 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB1_MID_RATE 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2 23:22 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2_HIGH_RATE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2_LOW_MOTION 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2_HIGH_MOTION 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1T_TRANS_AC_TAB2_MID_RATE 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q 0x00010500 /* RW-4R */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_FRAME 0:0 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_BINARY_LEVEL 1:1 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE 3:2 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_4_EDGE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_2_EDGE 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_1_EDGE 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_ALL_MB 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_SDB_EDGE 5:4 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_PICTURE_QUANTIZER_STEP 20:16 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1Q_ALT_PICTURE_QUANTIZER_STEP 28:24 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P 0x00010600 /* RW-4R */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE 1:0 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE_NORM_HORZ_NORM_VERT 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE_EXT_HORZ_NORM_VERT 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE_NORM_HORZ_EXT_VERT 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_DMV_RANGE_EXT_HORZ_EXT_VERT 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_MV_RANGE 3:2 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_MV_MODE 5:4 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_MV_MODE_MIXED_MV 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_MV_MODE_1_MV 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_MV_MODE_1_MV_HALF_PEL 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_MV_MODE_1_MV_HALF_PEL_BILINEAR 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE 7:6 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_8X8 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_8X4 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_4X8 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_4X4 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_TRANSFORM_TYPE_FLAG 8:8 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_TRANSFORM_TYPE_FLAB_MB_LEVEL 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_TRANSFORM_TYPE_FLAB_FRAME_LEVEL 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_FOUR_MV_SWITCH 9:9 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_COND_OVER_MB 10:10 /* RWXUF */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_COND_OVER_MB_PICTURE_LEVEL 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_COND_OVER_MB_MB_LEVEL 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_PIC_INFO_VC1P_SYNCMARKER 11:11 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO 0x00010700 /* RW-4R */ #define NV_CNVDEC_VLD_SLICE_INFO_SLICE_TYPE 1:0 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SLICE_TYPE_P 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SLICE_TYPE_B 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SLICE_TYPE_I 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SLICE_NUM 14:2 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_NUM_REF_IDXL0_ACTIVE_MINUS1 19:15 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_NUM_REF_IDXL1_ACTIVE_MINUS1 24:20 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SLICE_QPY 30:25 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_ROWXPICWIDTH_MBS 14:2 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SLICE_ROW 22:15 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_QUANT_SCALE_CODE 29:25 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_EXT 0x00010800 /* RW-4R */ #define NV_CNVDEC_VLD_SLICE_INFO_EXT_SLICE_NUM 2:0 /* RWXUF */ #define NV_CNVDEC_VLD_EDOB_MB_INFO 0x00010900 /* RW-4R */ #define NV_CNVDEC_VLD_EDOB_MB_INFO_MB_ADDR 15:0 /* RWXUF */ #define NV_CNVDEC_VLD_EDOB_MB_INFO_SLICE_FIRST_MB_FLAG 16:16 /* RWXUF */ #define NV_CNVDEC_VLD_EDOB_MB_INFO_MB_RSTN 17:17 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC 0x00010a00 /* RW-4R */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_BASE_MODE 1:0 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_BASE_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_BASE_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_BASE_MODE_ADAPTIVE 0x00000002 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_RES_PRED 3:2 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_RES_PRED_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_RES_PRED_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_RES_PRED_ADAPTIVE 0x00000002 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_MOTION_PRED 5:4 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_MOTION_PRED_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_MOTION_PRED_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_MOTION_PRED_ADAPTIVE 0x00000002 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CBP_PRED 6:6 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CBP_PRED_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CBP_PRED_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_ACSCANSTARTADJ 7:7 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_ACSCANSTARTADJ_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_ACSCANSTARTADJ_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_SCAN_START 11:8 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_SCAN_START_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_SCAN_END 15:12 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_SCAN_END_INIT 0x0000000f /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_SKIP_MAX 28:16 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_SKIP 29:29 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_SKIP_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_SKIP_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP 0x00010b00 /* RW-4R */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP_XMIN 7:0 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP_XMIN_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP_XMAX 15:8 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP_XMAX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP_YMIN 23:16 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP_YMIN_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP_YMAX 31:24 /* RWIUF */ #define NV_CNVDEC_VLD_SLICE_INFO_SVC_CROP_YMAX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_EDOB_MB_POS 0x00010c00 /* RW-4R */ #define NV_CNVDEC_VLD_EDOB_MB_POS_MB_X 7:0 /* RWXUF */ #define NV_CNVDEC_VLD_EDOB_MB_POS_MB_Y 15:8 /* RWXUF */ #define NV_CNVDEC_VLD_MB_INFO 0x00010d00 /* RW-4R */ #define NV_CNVDEC_VLD_MB_INFO_MB_ADDR 15:0 /* RWXUF */ #define NV_CNVDEC_VLD_MB_INFO_SLICE_FIRST_MB_FLAG 16:16 /* RWXUF */ #define NV_CNVDEC_VLD_MB_POS 0x00010e00 /* RW-4R */ #define NV_CNVDEC_VLD_MB_POS_MB_X 7:0 /* RWXUF */ #define NV_CNVDEC_VLD_MB_POS_MB_Y 15:8 /* RWXUF */ #define NV_CNVDEC_VLD_PARSE_CMD 0x00010f00 /* -W-4R */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD 4:0 /* -WXUF */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_UE 0x00000000 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_SE 0x00000001 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_U 0x00000002 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_NAL_HEAD 0x00000003 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_VP8_PIC_HEAD 0x00000003 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_BYTE_ALIGNED 0x00000004 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_MORE_RBSP_DATA 0x00000005 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_MB_SKIP_FLAG_AE 0x00000006 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_END_OF_SLICE_FLAG_AE 0x00000007 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_START_CABAC_INIT 0x00000008 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_SKIP_MB 0x00000009 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_NON_SKIP_MB 0x0000000a /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_PARSE_PRED_WEIGHT_TABLE 0x0000000b /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_H264_PARSE_SLICE_DATA 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_VC1_PARSE_MACROBLOCKS 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_MPEG2_PARSE_SLICEDATA 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_VP8_PARSE_PICDATA 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_MPEG2_RESERVED 0x0000000d /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_MPEG2_NEXT_BITS 0x0000000e /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_MPEG2_PARSE_PICTURE_DATA 0x0000000f /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_VC1_PARSE_PICTURE_HEADER 0x00000010 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_VC1_PARSE_BITPLANE 0x00000011 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_SEND_EOS 0x00000012 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_INSERT_ERROR_MB 0x00000013 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_CMD_NOP 0x00000014 /* -WX-V */ #define NV_CNVDEC_VLD_PARSE_CMD_PARAM 10:5 /* -WXUF */ #define NV_CNVDEC_VLD_PARSE_CMD_PARAM_READ_MB_FIELD_DECODE_FLAG 5:5 /* -WXUF */ #define NV_CNVDEC_VLD_PARSE_CMD_PARAM_VC1_TARGET_PLANE 6:5 /* -WXUF */ #define NV_CNVDEC_VLD_STATUS 0x00011000 /* R--4R */ #define NV_CNVDEC_VLD_STATUS_BUSY 0:0 /* R-XUF */ #define NV_CNVDEC_VLD_STATUS_SLICE_BUSY 1:1 /* R-XUF */ #define NV_CNVDEC_VLD_STATUS_EDOB_BUSY 2:2 /* R-XUF */ #define NV_CNVDEC_VLD_STATUS_VC1_PIC_BUSY 3:3 /* R-XUF */ #define NV_CNVDEC_VLD_STATUS_EDOB_NON_EMPTY 4:4 /* R-XUF */ #define NV_CNVDEC_VLD_STATUS_MEMACC_BUSY 5:5 /* R-XUF */ #define NV_CNVDEC_VLD_STATUS_FIFOCTRL_BUSY 6:6 /* R-XUF */ #define NV_CNVDEC_VLD_STATUS_HIST_BUSY 7:7 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT 0x00011100 /* R--4R */ #define NV_CNVDEC_VLD_RESULT_RESULT_DATA 31:0 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_NAL_UNIT_TYPE 4:0 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_NAL_REF_IDC 6:5 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_FORBIDDEN_ZERO_BIT 7:7 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_COLOR_SPACE 0:0 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_CLAMPING_TYPE 1:1 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_SEGMENTATION_ENABLED 2:2 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_SEGMENT_FEATURE_MODE 3:3 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_FILTER_TYPE 4:4 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_LOOP_FILTER_LEVEL 10:5 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_SHARPNESS_LEVEL 13:11 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_LOG2_NBR_OF_DCT_PARTITIONS 15:14 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_REFRESH_GOLDEN_FRAME 16:16 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_REFRESH_ALTERNATE_FRAME 17:17 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_COPY_BUFFER_TO_GOLDEN 19:18 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_COPY_BUFFER_TO_ALTERNATE 21:20 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_SIGN_BIAS_GOLDEN 22:22 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_SIGN_BIAS_ALTERNATE 23:23 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_REFRESH_ENTROPY_PROB 24:24 /* R-XUF */ #define NV_CNVDEC_VLD_RESULT_REFRESH_LAST 25:25 /* R-XUF */ #define NV_CNVDEC_VLD_INTRPT_EN 0x00011200 /* RW-4R */ #define NV_CNVDEC_VLD_INTRPT_EN_WATCHDOG_TIMER_EN 0:0 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_EN_BUFF_EMPTY_EN 1:1 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_EN_BIT_ERROR_EN 2:2 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_EN_LIMIT_EN 3:3 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_EN_SLICE_DONE_EN 4:4 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_STATUS 0x00011300 /* RW-4R */ #define NV_CNVDEC_VLD_INTRPT_STATUS_WATCHDOG_TIMER 0:0 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_STATUS_BUFF_EMPTY 1:1 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_STATUS_BIT_ERROR 2:2 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_STATUS_LIMIT 3:3 /* RWXUF */ #define NV_CNVDEC_VLD_INTRPT_STATUS_SLICE_DONE 4:4 /* RWXUF */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE 0x00011400 /* RW-4R */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE 31:0 /* RWXUF */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_NONE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_SYNCMARKER 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_CBPCY 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTRA_DCCOEF 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ACCOEF1 0x00000008 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_RLL 0x00000010 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ACCOEF2 0x00000020 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_D_LEVEL 0x00000040 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_D_RUN 0x00000080 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ESCLVLSZ 0x00000100 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTRA_INVALID_IDX 0x00000200 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_TTBLK 0x00000400 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_SUBBLKPAT 0x00000800 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_SUBBLKPAT_8X4_4X8 0x00001000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_MVDATA 0x00002000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_INVALID_IDX 0x00004000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_INSUF_BP_BUF 0x00008000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MP4_SLICE_END_MBADDR 0x00010000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_TTMB 0x00020000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_INV_INTRAFLAG_BMV2 0x00040000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_MBMODE 0x00080000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_TWOMVBP 0x00100000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_FOURMVBP 0x00200000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_MVDATA_PF1R 0x00400000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_MVDATA_PF2R 0x00800000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_MIXEDMV 0x01000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_MB_ONEMV 0x02000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_VC1_BP_IMODE6_TABLE81 0x04000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MP4_MB_VIDEOPACKETHEADER 0x08000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MP4_MB_MCBPC 0x00020000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MP4_MB_MODBMBTYPE 0x00040000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MP4_MB_MCBPY 0x00080000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_SLICE_END 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_ADDR_INC 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MB_TYPE 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MT_TYPE 0x00000008 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MVX_GET 0x00000010 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MVY_GET 0x00000020 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_CBP_GET 0x00000040 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_QFS_GET 0x00000080 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_MB_MARKER_BIT 0x00000100 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_NB_PARAM 0x00000200 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MPG_SKIP_MBS 0x00000400 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_SLICE_END_AT_SMALLER_MB_ADDR 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_SKIP_RUN 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_I_SLICE 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_P_SLICE 0x00000008 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_B_SLICE 0x00000010 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_SI_SLICE 0x00000020 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_SP_SLICE 0x00000040 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_MB_QP_DELTA_OUT_OF_RANGE 0x00000080 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_RESIDUAL_COEFF_COUNT 0x00000100 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_TYPE 0x00000200 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_MB_REF_IDX_L0 0x00000400 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_MB_REF_IDX_L1 0x00000800 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_REF_IDX_L0 0x00001000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_REF_IDX_L1 0x00002000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN0 0x00004000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN1 0x00008000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN2 0x00010000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN3 0x00020000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOTAL_ZEROS 0x00040000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_RUN_BEFORE 0x00080000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_FIXED_PTRN_BIT_STRING 0x00100000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_INVALID_CODED_BLOCK_PATTERN 0x00200000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_LARGE_LUMA_LOG_WD 0x00400000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_LARGE_CHR_LOG_WD 0x00800000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_LUMA_WEIGHT 0x01000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_LUMA_OFFSET 0x02000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_CHROMA_WEIGHT 0x04000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_CHROMA_OFFSET 0x08000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_EXCEED_SLICE_OFFSET_LIMIT 0x10000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_MB_DATA_EXCEED_EDOB_FIFO_LIMIT 0x20000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_UNCLASSIFIED 0x40000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_CODE_SW_ERROR 0x80000000 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_VP8 31:0 /* RWXUF */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_VP8_BUFF2GOLD 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_VP8_BUFF2ALT 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_VP8_INVALID_TOKEN 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_VP8_EXCEED_TOKEN_LIMIT 0x00000008 /* RWX-V */ #define NV_CNVDEC_VLD_BIT_ERROR_CODE_VP8_ZERO_NO_EOB 0x00000010 /* RWX-V */ #define NV_CNVDEC_VLD_SCP_CFG 0x00011500 /* RW-4R */ #define NV_CNVDEC_VLD_SCP_CFG_PARSE_CMD_MODE 16:16 /* R-IUF */ #define NV_CNVDEC_VLD_SCP_CFG_PARSE_CMD_MODE_INSECURE 0x00000000 /* R-I-V */ #define NV_CNVDEC_VLD_SCP_CFG_PARSE_CMD_MODE_SECURE 0x00000001 /* R---V */ #define NV_CNVDEC_VLD_TIMEOUT_VALUE 0x00011600 /* RW-4R */ #define NV_CNVDEC_VLD_TIMEOUT_VALUE_MB_DECODE_TIMEOUT 31:0 /* RWXUF */ #define NV_CNVDEC_VLD_RESET_CTL 0x00011700 /* RW-4R */ #define NV_CNVDEC_VLD_RESET_CTL_SOFT_RESET 0:0 /* -WXUF */ #define NV_CNVDEC_VLD_RESET_CTL_HARD_RESET 1:1 /* -WXUF */ #define NV_CNVDEC_VLD_RESET_CTL_SLICE_RESET 2:2 /* -WXUF */ #define NV_CNVDEC_VLD_IDMA_BUFF_A(i) (0x00011800+(i)*512) /* RW-4A */ #define NV_CNVDEC_VLD_IDMA_BUFF_A__SIZE_1 4 /* */ #define NV_CNVDEC_VLD_IDMA_BUFF_A_COUNT 23:0 /* RWXUF */ #define NV_CNVDEC_VLD_IDMA_BUFF_A_ADDR_HIGH 31:24 /* RWXUF */ #define NV_CNVDEC_VLD_IDMA_BUFF_B(i) (0x00011900+(i)*512) /* RW-4A */ #define NV_CNVDEC_VLD_IDMA_BUFF_B__SIZE_1 4 /* */ #define NV_CNVDEC_VLD_IDMA_BUFF_B_VALID 0:0 /* RWXUF */ #define NV_CNVDEC_VLD_IDMA_BUFF_B_ENCRYPT 1:1 /* RWXUF */ #define NV_CNVDEC_VLD_IDMA_BUFF_B_ADDR_LOW 31:2 /* RWXUF */ #define NV_CNVDEC_VLD_CURR_IDMA_INFO 0x00012800 /* RW-4R */ #define NV_CNVDEC_VLD_CURR_IDMA_INFO_CURR_IDMA_BIT_INDEX 2:0 /* RWXUF */ #define NV_CNVDEC_VLD_CURR_IDMA_INFO_CURR_IDMA_BUFF_OFFSET 26:3 /* RWXUF */ #define NV_CNVDEC_VLD_CURR_IDMA_INFO_CURR_IDMA_BUFF_INDEX 28:27 /* RWXUF */ #define NV_CNVDEC_VLD_CLEAR_INPUT_BUFFERS 0x00012900 /* RW-4R */ #define NV_CNVDEC_VLD_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS 0:0 /* RWXUF */ #define NV_CNVDEC_VLD_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS_DONE 0x00000000 /* RW--V */ #define NV_CNVDEC_VLD_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS_FLUSH 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_CLEAR_INPUT_BUFFERS_BUFF_ID 2:1 /* RWXUF */ #define NV_CNVDEC_VLD_CLEAR_INPUT_BUFFERS_BUFF_ID_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD_HIST_START_ADDR 0x00013200 /* RW-4R */ #define NV_CNVDEC_VLD_HIST_START_ADDR_START_ADDR_HIGH 31:0 /* RWXUF */ #define NV_CNVDEC_VLD_HIST_SIZE 0x00013300 /* RW-4R */ #define NV_CNVDEC_VLD_HIST_SIZE_SIZE 11:0 /* RWXUF */ #define NV_CNVDEC_VLD_HIST_CTL 0x00013400 /* RW-4R */ #define NV_CNVDEC_VLD_HIST_CTL_ENABLE 0:0 /* RWXUF */ #define NV_CNVDEC_VLD_HIST_CTL_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_CNVDEC_VLD_HIST_CTL_ENABLE_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_HIST_CTL_LINEBUF_ENABLE 1:1 /* RWXUF */ #define NV_CNVDEC_VLD_HIST_CTL_LINEBUF_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_CNVDEC_VLD_HIST_CTL_LINEBUF_ENABLE_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP 0x00013500 /* -W-4R */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_OFFSET 11:0 /* -WXUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_VRAM_ADDR 0x00000e00 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_VRAM_PARAMS 0x00000e04 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_CBC_PARAMS 0x00000e08 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_SOFT_RESET_CMD 0x00000e0c /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_BDEC_STATE_RESTORE 0x00000e10 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_CTX_MEM_LOAD_CMD 0x00000e14 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_CTX_MEM_LOAD_DATA 0x00000e18 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_CTX_MEM_READ_DATA 0x00000e1c /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_BSEV_RESULT_PUSH_DATA 0x00000e20 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_DEBUG_CONTROL 0x00000e24 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_DEBUG_DATA 0x00000e28 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_OP_RW 12:12 /* -WXUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA 0x00013600 /* RW-4R */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_RESULT_DATA 31:0 /* RWXUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_CTXVAR 0x00000000 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_CMDIF 0x00000002 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_RESIDUAL 0x00000003 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_MBPRED 0x00000004 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_SUBMBPRED 0x00000005 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_VRAMIF 0x00000006 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_DATAIF 0x00000007 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC_BINCTRL0 0x00000008 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC_BINCTRL1 0x00000009 /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC0 0x0000000a /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC1 0x0000000b /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC2 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC3 0x0000000d /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_IBIN 0x0000000e /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_READBITS 0x0000000f /* -WX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG 0x00013700 /* R--4R */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_MEMACC_ST 2:0 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_FIFOCTRL_ST 5:3 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_MEMACC_REQ0_OUTSTANDING 6:6 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_MEMACC_REQ1_OUTSTANDING 7:7 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_MEMACC_SCP_PKTS_PEND 12:8 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_MB_STATE 17:13 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_RES_BLK_TYPE 20:18 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_CBC_VRAM_PS 24:21 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_DEBUG_CAVLD_STATE 28:25 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0 0x00013800 /* R--4R */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MB_STATE 7:0 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_CBPCY_STATE 9:8 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MVD_STATE 13:12 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MVDPF1R_STATE 17:16 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MVDPF2R_STATE 21:20 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_MVP_STATE 27:24 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG0_ACP_STATE 29:28 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1 0x00013900 /* R--4R */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_INTRA_STATE 2:0 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_INTER_STATE 6:4 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_VLCAC_STATE 11:8 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_OUTIF_STATE 15:12 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_BP_STATE 18:16 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_VC1_DEBUG1_BP_RD_STATE 21:20 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPG_DEBUG 0x00013a00 /* R--4R */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPG_DEBUG_MB_STATE 3:0 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPG_DEBUG_MBI_STATE 5:4 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPG_DEBUG_QFS_STATE 8:6 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPG_DEBUG_OUTIF_STATE 12:9 /* R-XUF */ #define NV_CNVDEC_VLD_BIT_ERROR_MASK 0x00013b00 /* RW-4R */ #define NV_CNVDEC_VLD_BIT_ERROR_MASK_MASKFIELD 31:0 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_LIMIT 0x00013c00 /* RW-4R */ #define NV_CNVDEC_VLD_SLICE_LIMIT_SLICE_BYTE_COUNT 31:0 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_ERROR_CTL 0x00013d00 /* RW-4R */ #define NV_CNVDEC_VLD_SLICE_ERROR_CTL_NEXT_SLICE_MB_ADDR 16:0 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_ERROR_CTL_SET_SW_ERROR 31:31 /* RWXUF */ #define NV_CNVDEC_VLD_SLICE_ERROR_CTL_SET_SW_ERROR_CLR 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD_SLICE_ERROR_CTL_SET_SW_ERROR_SET 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG 0x00013e00 /* R--4R */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG_MP4_STATE 3:0 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG_MP4IP_STATE 7:4 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG_BP_ILLEGAL_READ 8:8 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_DEBUG_BP_ILLEGAL_WRITE 9:9 /* R-XUF */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY(i,j) (0x00013f00+(i)*256+(j)*4) /* RW-4A */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_1 4 /* */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_2 64 /* */ #define NV_CNVDEC_VLD_ENTROPYDEC_MPEG4_BITPLANE_MEMORY_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_VLD_PROBBUF_WRITE_REG 0x00014400 /* RW-4R */ #define NV_CNVDEC_VLD_PROBBUF_WRITE_REG_DATA 31:0 /* -W-UF */ #define NV_CNVDEC_VLD_PROBBUF_READ_REG 0x00014500 /* RW-4R */ #define NV_CNVDEC_VLD_PROBBUF_READ_REG_DATA 31:0 /* R--UF */ #define NV_CNVDEC_VLD_PROBBUF_RW_OFFSET 0x00014600 /* RW-4R */ #define NV_CNVDEC_VLD_PROBBUF_RW_OFFSET_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_VLD_IDMA1_BUFF_A(i) (0x00014800+(i)*512) /* RW-4A */ #define NV_CNVDEC_VLD_IDMA1_BUFF_A__SIZE_1 8 /* */ #define NV_CNVDEC_VLD_IDMA1_BUFF_A_COUNT 23:0 /* RWXUF */ #define NV_CNVDEC_VLD_IDMA1_BUFF_A_ADDR_HIGH 31:24 /* RWXUF */ #define NV_CNVDEC_VLD_IDMA1_BUFF_B(i) (0x00014900+(i)*512) /* RW-4A */ #define NV_CNVDEC_VLD_IDMA1_BUFF_B__SIZE_1 8 /* */ #define NV_CNVDEC_VLD_IDMA1_BUFF_B_VALID 0:0 /* RWXUF */ #define NV_CNVDEC_VLD_IDMA1_BUFF_B_ENCRYPT 1:1 /* RWXUF */ #define NV_CNVDEC_VLD_IDMA1_BUFF_B_ADDR_LOW 31:2 /* RWXUF */ #define NV_CNVDEC_VLD_CURR_IDMA1_INFO 0x00015800 /* RW-4R */ #define NV_CNVDEC_VLD_CURR_IDMA1_INFO_CURR_IDMA_BIT_INDEX 2:0 /* RWXUF */ #define NV_CNVDEC_VLD_CURR_IDMA1_INFO_CURR_IDMA_BUFF_OFFSET 26:3 /* RWXUF */ #define NV_CNVDEC_VLD_CURR_IDMA1_INFO_CURR_IDMA_BUFF_INDEX 29:27 /* RWXUF */ #define NV_CNVDEC_VLD_SEGMENT_ID_START_ADDR 0x00015900 /* RW-4R */ #define NV_CNVDEC_VLD_SEGMENT_ID_START_ADDR_START_ADDR_HIGH 31:0 /* RWXUF */ #define NV_CNVDEC_VLD_STREAM_LEN 0x00015a00 /* RW-4R */ #define NV_CNVDEC_VLD_STREAM_LEN_VALUE 31:0 /* RWXUF */ #define NV_CNVDEC_DBFDMA_SFC_WIDTH 0x0001e100 /* RW-4R */ #define NV_CNVDEC_DBFDMA_SFC_WIDTH_LUMA 11:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_SFC_WIDTH_CHROMA 27:16 /* RW-VF */ #define NV_CNVDEC_DBFDMA_TOP_SFC_LUMA 0x0001e400 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TOP_SFC_LUMA_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_TOP_SFC_CHROMA 0x0001e500 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TOP_SFC_CHROMA_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_BOT_SFC_LUMA 0x0001e600 /* RW-4R */ #define NV_CNVDEC_DBFDMA_BOT_SFC_LUMA_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_BOT_SFC_CHROMA 0x0001e700 /* RW-4R */ #define NV_CNVDEC_DBFDMA_BOT_SFC_CHROMA_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL 0x0001e800 /* RW-4R */ #define NV_CNVDEC_DBFDMA_RW_CTL_RD_OFFS_L 1:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL_RD_OFFS_C 5:4 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL_WR_OFFS_L 9:8 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL_WR_OFFS_C 13:12 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL_WR_HEIGHT_L 18:16 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL_WR_HEIGHT_C 22:20 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL_TILE_FORMAT 24:23 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL_TILE_FORMAT_TBL 0x00000000 /* RW--V */ #define NV_CNVDEC_DBFDMA_RW_CTL_TILE_FORMAT_KBL 0x00000001 /* RWI-V */ #define NV_CNVDEC_DBFDMA_RW_CTL_TILE_FORMAT_16x16 0x00000002 /* RW--V */ #define NV_CNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT 27:25 /* RW-VF */ #define NV_CNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_2 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_4 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_8 0x00000002 /* RW--V */ #define NV_CNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_16 0x00000003 /* RW--V */ #define NV_CNVDEC_DBFDMA_RW_CTL_GOB_HEIGHT_GOB_32 0x00000004 /* RW--V */ #define NV_CNVDEC_DBFDMA_CTL 0x0001e900 /* RW-4R */ #define NV_CNVDEC_DBFDMA_CTL_FRM_WIDTH 7:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_CTL_TYPE 9:8 /* RW-VF */ #define NV_CNVDEC_DBFDMA_CTL_TYPE_FRAME 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_TYPE_FIELD_TOP 0x00000002 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_TYPE_FIELD_BOT 0x00000003 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_FRM_WRITE 10:10 /* RW-VF */ #define NV_CNVDEC_DBFDMA_CTL_FRM_WRITE_DISABLE 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_FRM_WRITE_ENABLE 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_DBL_ROWS 11:11 /* RW-VF */ #define NV_CNVDEC_DBFDMA_CTL_DBL_ROWS_DISABLE 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_DBL_ROWS_ENABLE 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_APPLE_OOLD 12:12 /* RW-VF */ #define NV_CNVDEC_DBFDMA_CTL_APPLE_OOLD_DISABLE 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_APPLE_OOLD_ENABLE 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_FLAG 13:13 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_FLAG_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_FLAG_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPY 16:14 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPY_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_FLAG 17:17 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_FLAG_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_FLAG_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV 20:18 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_VC_RANGE_MAPUV_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_USE_INTERNAL_BUFF 21:21 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_USE_INTERNAL_BUFF_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_TFOUTPUT 22:22 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_TFOUTPUT_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_DITHER_Y 23:23 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_DITHER_Y_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_DITHER_U 24:24 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_DITHER_U_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_DITHER_V 25:25 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_DITHER_V_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_HISTOGRAM 26:26 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_HISTOGRAM_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_4LINE 27:27 /* RWIUF */ #define NV_CNVDEC_DBFDMA_CTL_ENABLE_4LINE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_FETCH 0x0001ea00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_FETCH_COUNTER 16:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_INTRPTEN 0x0001eb00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_INTRPTEN_OFFSETERR 0:0 /* RWXUF */ #define NV_CNVDEC_DBFDMA_INTRPTEN_OFFSETERR_ON 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTEN_OFFSETERR_OFF 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTEN_CFGWRERR 4:4 /* RWXUF */ #define NV_CNVDEC_DBFDMA_INTRPTEN_CFGWRERR_ON 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTEN_CFGWRERR_OFF 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTEN_ROWEND 8:8 /* RWXUF */ #define NV_CNVDEC_DBFDMA_INTRPTEN_ROWEND_ON 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTEN_ROWEND_OFF 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT 0x0001ec00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_OFFSETERR 0:0 /* RWXUF */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_OFFSETERR_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_OFFSETERR_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_CFGWRERR 4:4 /* RWXUF */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_CFGWRERR_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_CFGWRERR_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_ROWEND 8:8 /* RWXUF */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_ROWEND_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_DBFDMA_INTRPTSTAT_ROWEND_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_DBFDMA_DBG1 0x0001ed00 /* R--4R */ #define NV_CNVDEC_DBFDMA_DBG1_DBFDMA_READ_CS 1:0 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_DBFDMA_WRITE_CS 5:2 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_RBUF_READ_CS 8:6 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_WR_IDLE_N 9:9 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_WR_IDLE_N_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_DBFDMA_DBG1_RD_IDLE_N 10:10 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_RD_IDLE_N_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_DBFDMA_DBG1_RD_FIFO_EMPTY 11:11 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_RD_FIFO_EMPTY_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_DBFDMA_DBG1_CFG_FETCH_RD_IS_0 12:12 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_CFG_FETCH_RD_IS_0_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_DBFDMA_DBG1_CFG_FETCH_RFW_IS_0 13:13 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_CFG_FETCH_RFW_IS_0_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_DBFDMA_DBG1_CFG_FETCH_WR_IS_0 14:14 /* R-XUF */ #define NV_CNVDEC_DBFDMA_DBG1_CFG_FETCH_WR_IS_0_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_DBFDMA_ROW_COUNTER 0x0001ee00 /* R--4R */ #define NV_CNVDEC_DBFDMA_ROW_COUNTER_REG 11:0 /* R-XUF */ #define NV_CNVDEC_DBFDMA_MB_COUNTER 0x0001ef00 /* R--4R */ #define NV_CNVDEC_DBFDMA_MB_COUNTER_REG 16:0 /* R-XUF */ #define NV_CNVDEC_DBFDMA_SFC_WIDTH_FIELD_UNFILTERED 0x0001f000 /* RW-4R */ #define NV_CNVDEC_DBFDMA_SFC_WIDTH_FIELD_UNFILTERED_LUMA 11:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_SFC_WIDTH_FIELD_UNFILTERED_CHROMA 27:16 /* RW-VF */ #define NV_CNVDEC_DBFDMA_TOP_SFC_LUMA_UNFILTERED 0x0001f100 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TOP_SFC_LUMA_UNFILTERED_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_TOP_SFC_CHROMA_UNFILTERED 0x0001f200 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TOP_SFC_CHROMA_UNFILTERED_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_BOT_SFC_LUMA_UNFILTERED 0x0001f300 /* RW-4R */ #define NV_CNVDEC_DBFDMA_BOT_SFC_LUMA_UNFILTERED_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_BOT_SFC_CHROMA_UNFILTERED 0x0001f400 /* RW-4R */ #define NV_CNVDEC_DBFDMA_BOT_SFC_CHROMA_UNFILTERED_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO 0x0001f500 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_PIC_STRIDE 7:0 /* RWIUF */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_PIC_STRIDE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE 18:16 /* RWIUF */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_1D 0x00000000 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_PITCH_LINEAR_2D 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_16X16 0x00000002 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_BLOCK_LINEAR_TEXTURE 0x00000003 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_NAIVE_BLOCK_LINEAR 0x00000004 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_RESERVED_0 0x00000005 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_RESERVED_1 0x00000006 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_TILING_MODE_RESERVED_2 0x00000007 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_STRUCTURE 19:19 /* RWIUF */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_STRUCTURE_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_STRUCTURE_FRAME 0x00000000 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_STRUCTURE_FIELD 0x00000001 /* RW--V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_PIC_HEIGHT 31:24 /* RWIUF */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_PIC_INFO_PIC_HEIGHT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_LUMA_TOP_FIELD 0x0001f600 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_LUMA_TOP_FIELD_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_LUMA_BOTTOM_FIELD 0x0001f700 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_LUMA_BOTTOM_FIELD_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_CHROMA_TOP_FIELD 0x0001f800 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_CHROMA_TOP_FIELD_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_CHROMA_BOTTOM_FIELD 0x0001f900 /* RW-4R */ #define NV_CNVDEC_DBFDMA_TF_OUTPUT_CHROMA_BOTTOM_FIELD_BASE 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_START 0x0001fa00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_START_X 11:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_START_X_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_START_Y 27:16 /* RW-VF */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_START_Y_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_END 0x0001fb00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_END_X 11:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_END_X_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_END_Y 27:16 /* RW-VF */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_WINDOW_END_Y_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_RESULT 0x0001fc00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_RESULT_REG 23:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_RESULT_REG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_RESULT_OFFSET 0x0001fd00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_RESULT_OFFSET_REG 7:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_HISTOGRAM_RESULT_OFFSET_REG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBFDMA_DITHER_MATRIX_WRITE_DATA 0x0001fe00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_DITHER_MATRIX_WRITE_DATA_REG 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_DITHER_MATRIX_WRITE_OFFSET 0x0001ff00 /* RW-4R */ #define NV_CNVDEC_DBFDMA_DITHER_MATRIX_WRITE_OFFSET_REG 31:0 /* RW-VF */ #define NV_CNVDEC_DBFDMA_DITHER_MATRIX_WRITE_OFFSET_REG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_HIST_CFG 0x0001d000 /* RW-4R */ #define NV_CNVDEC_HIST_CFG_CODEC 2:0 /* RW-VF */ #define NV_CNVDEC_HIST_CFG_CODEC_MPEG1 0x00000000 /* RWX-V */ #define NV_CNVDEC_HIST_CFG_CODEC_MPEG2 0x00000001 /* RWX-V */ #define NV_CNVDEC_HIST_CFG_CODEC_VC1 0x00000002 /* RWX-V */ #define NV_CNVDEC_HIST_CFG_CODEC_H264 0x00000003 /* RWX-V */ #define NV_CNVDEC_HIST_CFG_CODEC_MPEG4 0x00000004 /* RWX-V */ #define NV_CNVDEC_HIST_CFG_CODEC_VP8 0x00000005 /* RWX-V */ #define NV_CNVDEC_HIST_CFG_MBAFF 3:3 /* RW-VF */ #define NV_CNVDEC_HIST_CFG_MVDEL 4:4 /* RW-VF */ #define NV_CNVDEC_HIST_CFG_IQTDEL 5:5 /* RW-VF */ #define NV_CNVDEC_HIST_CFG_RECDEL 6:6 /* RW-VF */ #define NV_CNVDEC_HIST_CFG_DBFDEL 7:7 /* RW-VF */ #define NV_CNVDEC_HIST_CFG_DXVA 8:8 /* RW-VF */ #define NV_CNVDEC_HIST_CFG_PICWIDTHINMBS 23:16 /* RW-VF */ #define NV_CNVDEC_HIST_CFG_PICHEIGHTINMBS 31:24 /* RW-VF */ #define NV_CNVDEC_HIST_CTL 0x0001d100 /* RW-4R */ #define NV_CNVDEC_HIST_CTL_ENABLE 0:0 /* RW-VF */ #define NV_CNVDEC_HIST_CTL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_HIST_CTL_RST_HISTW 1:1 /* RW-VF */ #define NV_CNVDEC_HIST_CTL_RST_HISTW_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_HIST_CTL_RST_HISTR 2:2 /* RW-VF */ #define NV_CNVDEC_HIST_CTL_RST_HISTR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_HIST_CTL_DBF_DISABLE 3:3 /* RW-VF */ #define NV_CNVDEC_HIST_CTL_DBF_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_HIST_CTL_LINEBUF_ENABLE 4:4 /* RWXUF */ #define NV_CNVDEC_HIST_CTL_LINEBUF_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_CNVDEC_HIST_CTL_LINEBUF_ENABLE_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_HIST_BUF_START 0x0001d200 /* RW-4R */ #define NV_CNVDEC_HIST_BUF_START_ADDR 31:0 /* RWXVF */ #define NV_CNVDEC_HIST_BUF_SIZE 0x0001d300 /* RW-4R */ #define NV_CNVDEC_HIST_BUF_SIZE_SIZE 15:0 /* RWXVF */ #define NV_CNVDEC_HIST_DBG0 0x0001d400 /* R--4R */ #define NV_CNVDEC_HIST_DBG0_MV_RD_STATE 3:0 /* R-XVF */ #define NV_CNVDEC_HIST_DBG0_MV_RD_HWVLD 4:4 /* R-XVF */ #define NV_CNVDEC_HIST_DBG0_MV_RD_HOVLD 5:5 /* R-XVF */ #define NV_CNVDEC_HIST_DBG0_MV_RD_RDREQ 6:6 /* R-XVF */ #define NV_CNVDEC_HIST_DBG0_MV_RD_LDREQ 7:7 /* R-XVF */ #define NV_CNVDEC_HIST_DBG0_MV_RD_RECCNT 11:8 /* R-XVF */ #define NV_CNVDEC_HIST_DBG0_MV_RD_REQCNT 15:12 /* R-XVF */ #define NV_CNVDEC_HIST_DBG0_MV_RD_COLCNT 23:16 /* R-XVF */ #define NV_CNVDEC_HIST_DBG0_MV_RD_ROWCNT 31:24 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1 0x0001d500 /* R--4R */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_STATE 3:0 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_HWVLD 4:4 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_HOVLD 5:5 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_RDREQ 6:6 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_LDREQ 7:7 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_RECCNT 11:8 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_REQCNT 15:12 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_COLCNT 23:16 /* R-XVF */ #define NV_CNVDEC_HIST_DBG1_IQT_RD_ROWCNT 31:24 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2 0x0001d600 /* R--4R */ #define NV_CNVDEC_HIST_DBG2_REC_RD_STATE 3:0 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2_REC_RD_HWVLD 4:4 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2_REC_RD_HOVLD 5:5 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2_REC_RD_RDREQ 6:6 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2_REC_RD_LDREQ 7:7 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2_REC_RD_RECCNT 11:8 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2_REC_RD_REQCNT 15:12 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2_REC_RD_COLCNT 23:16 /* R-XVF */ #define NV_CNVDEC_HIST_DBG2_REC_RD_ROWCNT 31:24 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3 0x0001d700 /* R--4R */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_STATE 3:0 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_HWVLD 4:4 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_HOVLD 5:5 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_RDREQ 6:6 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_LDREQ 7:7 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_DBFCNT 11:8 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_REQCNT 15:12 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_COLCNT 23:16 /* R-XVF */ #define NV_CNVDEC_HIST_DBG3_DBF_RD_ROWCNT 31:24 /* R-XVF */ #define NV_CNVDEC_HIST_DBG4 0x0001d800 /* R--4R */ #define NV_CNVDEC_HIST_DBG4_MV_WR_STATE 3:0 /* R-XVF */ #define NV_CNVDEC_HIST_DBG4_MV_WR_HIVLD 6:6 /* R-XVF */ #define NV_CNVDEC_HIST_DBG4_MV_WR_HOVLD 7:7 /* R-XVF */ #define NV_CNVDEC_HIST_DBG4_MV_WR_RECCNT 11:8 /* R-XVF */ #define NV_CNVDEC_HIST_DBG4_IQT_WR_STATE 19:16 /* R-XVF */ #define NV_CNVDEC_HIST_DBG4_IQT_WR_HIVLD 22:22 /* R-XVF */ #define NV_CNVDEC_HIST_DBG4_IQT_WR_HOVLD 23:23 /* R-XVF */ #define NV_CNVDEC_HIST_DBG4_IQT_WR_RECCNT 27:24 /* R-XVF */ #define NV_CNVDEC_HIST_DBG5 0x0001d900 /* R--4R */ #define NV_CNVDEC_HIST_DBG5_REC_WR_STATE 3:0 /* R-XVF */ #define NV_CNVDEC_HIST_DBG5_REC_WR_HIVLD 6:6 /* R-XVF */ #define NV_CNVDEC_HIST_DBG5_REC_WR_HOVLD 7:7 /* R-XVF */ #define NV_CNVDEC_HIST_DBG5_REC_WR_RECCNT 11:8 /* R-XVF */ #define NV_CNVDEC_HIST_DBG5_DBF_WR_STATE 19:16 /* R-XVF */ #define NV_CNVDEC_HIST_DBG5_DBF_WR_HIVLD 22:22 /* R-XVF */ #define NV_CNVDEC_HIST_DBG5_DBF_WR_HOVLD 23:23 /* R-XVF */ #define NV_CNVDEC_HIST_DBG5_DBF_WR_RECCNT 27:24 /* R-XVF */ #define NV_CNVDEC_HIST_DBG6 0x0001da00 /* R--4R */ #define NV_CNVDEC_HIST_DBG6_RXFER_FBCNT 9:0 /* R-XVF */ #define NV_CNVDEC_HIST_DBG6_RXFER_PICDONE 10:10 /* R-XVF */ #define NV_CNVDEC_HIST_DBG6_RXFER_HISTR_IDLE 11:11 /* R-XVF */ #define NV_CNVDEC_HIST_DBG6_RXFER_STARTREQ 12:12 /* R-XVF */ #define NV_CNVDEC_HIST_DBG6_RXFER_RCOUNT 15:13 /* R-XVF */ #define NV_CNVDEC_HIST_DBG6_RXFER_COLCNT 23:16 /* R-XVF */ #define NV_CNVDEC_HIST_DBG6_RXFER_ROWCNT 31:24 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7 0x0001db00 /* R--4R */ #define NV_CNVDEC_HIST_DBG7_WXFER_STATE 1:0 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7_WXFER_HISTAV 2:2 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7_WXFER_MEMVLD 3:3 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7_WXFER_OVLD 4:4 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7_WXFER_ACKCNT 7:5 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7_WXFER_HISTW_IDLE 8:8 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7_WXFER_FBREC 11:9 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7_WXFER_MEMOFFS 15:12 /* R-XVF */ #define NV_CNVDEC_HIST_DBG7_WXFER_FBOFFS 31:16 /* R-XVF */ #define NV_CNVDEC_IQTINTRPTEN 0x0002a000 /* RW-4R */ #define NV_CNVDEC_IQTINTRPTEN_IQCOEFERR 0:0 /* RWXUF */ #define NV_CNVDEC_IQTINTRPTEN_IQCOEFERR_OFF 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTEN_IQCOEFERR_ON 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTEN_IQIDXERR 4:4 /* RWXUF */ #define NV_CNVDEC_IQTINTRPTEN_IQIDXERR_OFF 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTEN_IQIDXERR_ON 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTEN_CFGWRERR 8:8 /* RWXUF */ #define NV_CNVDEC_IQTINTRPTEN_CFGWRERR_OFF 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTEN_CFGWRERR_ON 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTSTAT 0x0002a100 /* RW-4R */ #define NV_CNVDEC_IQTINTRPTSTAT_IQCOEFERR 0:0 /* RWXUF */ #define NV_CNVDEC_IQTINTRPTSTAT_IQCOEFERR_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTSTAT_IQCOEFERR_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTSTAT_IQIDXERR 4:4 /* RWXUF */ #define NV_CNVDEC_IQTINTRPTSTAT_IQIDXERR_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTSTAT_IQIDXERR_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTSTAT_CFGWRERR 8:8 /* RWXUF */ #define NV_CNVDEC_IQTINTRPTSTAT_CFGWRERR_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTINTRPTSTAT_CFGWRERR_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTDBG1 0x0002a200 /* R--4R */ #define NV_CNVDEC_IQTDBG1_HISTIF_PRED_BUFA_CS 2:0 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_HISTIF_PRED_BUFB_CS 5:3 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_IQUANT_IQUANT_CS 8:6 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_IQT_READ_CS 11:9 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX 14:12 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_0 0x00000000 /* R---V */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_1 0x00000001 /* R---V */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_2 0x00000002 /* R---V */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_3 0x00000003 /* R---V */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_4 0x00000004 /* R---V */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_5 0x00000005 /* R-I-V */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_6 0x00000006 /* R---V */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_IDX_7 0x00000007 /* R---V */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_INTRA 15:15 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_MODE 18:16 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_BLK_SHAPE 20:19 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_MB_ACPRED 21:21 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_MB_FIELD 22:22 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_MB_LEFTEDGE 23:23 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_MB_TOPEDGE 24:24 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_MB_PCM 25:25 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_MB_QUANTY 31:26 /* R-XUF */ #define NV_CNVDEC_IQTDBG1_READ_MV2IQT_MB_QUANTY_INIT 0x0000003f /* R-I-V */ #define NV_CNVDEC_IQTDBG2 0x0002a300 /* R--4R */ #define NV_CNVDEC_IQTDBG2_READ_MV2IQT_MB_QUANTCB 5:0 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_READ_MV2IQT_MB_QUANTCB_INIT 0x0000003f /* R-I-V */ #define NV_CNVDEC_IQTDBG2_READ_MV2IQT_MB_QUANTCR 11:6 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_READ_MV2IQT_MB_QUANTCR_INIT 0x0000003f /* R-I-V */ #define NV_CNVDEC_IQTDBG2_IT_SEQ_STATE 15:12 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_IT_ENG_STATE 19:16 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_IT_OUT_STATE 22:20 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_IQ2IT_BLK_SHAPE 24:23 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_IQ2IT_BLK_IDX 27:25 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_IQ2IT_INTRA 28:28 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_ST_HISTIF_A_IDLE 29:29 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_ST_HISTIF_A_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_IQTDBG2_ST_HISTIF_B_IDLE 30:30 /* R-XUF */ #define NV_CNVDEC_IQTDBG2_ST_HISTIF_B_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_IQTDBG3 0x0002a400 /* R--4R */ #define NV_CNVDEC_IQTDBG3_SVC_RD_CS 1:0 /* R-XUF */ #define NV_CNVDEC_IQTDBG3_SVC_DMA_DECOMPRESS_CS 6:2 /* R-XUF */ #define NV_CNVDEC_IQTDBG3_SVC_DMA_WR_HDR_CS 8:7 /* R-XUF */ #define NV_CNVDEC_IQTDBG3_SVC_PKG_OUT_CS 11:9 /* R-XUF */ #define NV_CNVDEC_IQTDBG3_SVC_TOFBIF_CS 14:12 /* R-XUF */ #define NV_CNVDEC_IQTDBG3_SVC_PCM_WR_CS 16:15 /* R-XUF */ #define NV_CNVDEC_IQTDBG3_SVC_RD 17:17 /* R-XUF */ #define NV_CNVDEC_IQTDBG3_SVC_RD_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_IQTDBG3_SVC_RD_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_IQTDBG3_SVC_WR 18:18 /* R-XUF */ #define NV_CNVDEC_IQTDBG3_SVC_WR_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_IQTDBG3_SVC_WR_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_IQTTYPE 0x0002a500 /* RW-4R */ #define NV_CNVDEC_IQTTYPE_CODEC 2:0 /* RWIVF */ #define NV_CNVDEC_IQTTYPE_CODEC_MPEG1 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTTYPE_CODEC_MPEG2 0x00000001 /* RW--V */ #define NV_CNVDEC_IQTTYPE_CODEC_VC1 0x00000002 /* RW--V */ #define NV_CNVDEC_IQTTYPE_CODEC_H264 0x00000003 /* RW--V */ #define NV_CNVDEC_IQTTYPE_CODEC_MPEG4 0x00000004 /* RW--V */ #define NV_CNVDEC_IQTTYPE_CODEC_VP8 0x00000005 /* RW--V */ #define NV_CNVDEC_IQTTYPE_DXVA 5:4 /* RWIVF */ #define NV_CNVDEC_IQTTYPE_DXVA_VLD 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTTYPE_DXVA_IDCT 0x00000001 /* RW--V */ #define NV_CNVDEC_IQTTYPE_DXVA_MOCO 0x00000002 /* RW--V */ #define NV_CNVDEC_IQTTYPE_DXVA_IDCT_ISC 0x00000003 /* RW--V */ #define NV_CNVDEC_IQTTYPE_ZCOEFF 8:8 /* RWIVF */ #define NV_CNVDEC_IQTTYPE_ZCOEFF_ENABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTTYPE_ZCOEFF_DISABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_IQTTYPE_LOSSLESS 9:9 /* RWIVF */ #define NV_CNVDEC_IQTTYPE_LOSSLESS_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTTYPE_LOSSLESS_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_IQTTYPE_LOSSLESS_ZERO_CHROMA_CYA 10:10 /* RWIVF */ #define NV_CNVDEC_IQTTYPE_LOSSLESS_ZERO_CHROMA_CYA_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTTYPE_LOSSLESS_ZERO_CHROMA_CYA_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_IQTTYPE_DIVX 31:31 /* RWIVF */ #define NV_CNVDEC_IQTTYPE_DIVX_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTTYPE_DIVX_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_IQTMP2 0x0002a600 /* RW-4R */ #define NV_CNVDEC_IQTMP2_QSCALE_TYPE 0:0 /* RWXUF */ #define NV_CNVDEC_IQTMP2_QSCALE_TYPE_LINEAR 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTMP2_QSCALE_TYPE_NON_LINEAR 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTMP2_ALTERNATE_SCAN 1:1 /* RWXUF */ #define NV_CNVDEC_IQTMP2_ALTERNATE_SCAN_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTMP2_ALTERNATE_SCAN_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTMP2_INTRA_DC_PRECISION 3:2 /* RWXUF */ #define NV_CNVDEC_IQTMP2_INTRA_DC_PRECISION_0 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTMP2_INTRA_DC_PRECISION_1 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTMP2_INTRA_DC_PRECISION_2 0x00000002 /* RWX-V */ #define NV_CNVDEC_IQTMP2_INTRA_DC_PRECISION_3 0x00000003 /* RWX-V */ #define NV_CNVDEC_IQTVC1 0x0002a700 /* RW-4R */ #define NV_CNVDEC_IQTVC1_NON_UNIFORM_Q 0:0 /* RWXUF */ #define NV_CNVDEC_IQTVC1_NON_UNIFORM_Q_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTVC1_NON_UNIFORM_Q_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTVC1_ADVANCED_PROFILE 1:1 /* RWXUF */ #define NV_CNVDEC_IQTVC1_ADVANCED_PROFILE_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTVC1_ADVANCED_PROFILE_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTVC1_FRAME_CODING_MODE 3:2 /* RWXUF */ #define NV_CNVDEC_IQTVC1_FRAME_CODING_MODE_PROG 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTVC1_FRAME_CODING_MODE_FRAME_INTL 0x00000002 /* RWX-V */ #define NV_CNVDEC_IQTVC1_FRAME_CODING_MODE_FIELD_INTL 0x00000003 /* RWX-V */ #define NV_CNVDEC_IQTVC1_IPICTURE 4:4 /* RWXUF */ #define NV_CNVDEC_IQTVC1_IPICTURE_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTVC1_IPICTURE_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTVC1_BIAS 5:5 /* RWXUF */ #define NV_CNVDEC_IQTVC1_BIAS_FALSE 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTVC1_BIAS_TRUE 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTVC1_PRED_DC_DEFAULT 27:16 /* RWXUF */ #define NV_CNVDEC_IQTQMEM 0x0002a800 /* -W-4R */ #define NV_CNVDEC_IQTQMEM_DATA 31:0 /* -WXUF */ #define NV_CNVDEC_IQTQMEMCTRL 0x0002a900 /* RW-4R */ #define NV_CNVDEC_IQTQMEMCTRL_MSEL 0:0 /* RWIUF */ #define NV_CNVDEC_IQTQMEMCTRL_IQ 0x00000000 /* RWX-V */ #define NV_CNVDEC_IQTQMEMCTRL_FALCON 0x00000001 /* RWX-V */ #define NV_CNVDEC_IQTDCTCTRL 0x0002aa00 /* RW-4R */ #define NV_CNVDEC_IQTDCTCTRL_MICROCODE_MSEL 0:0 /* RWIUF */ #define NV_CNVDEC_IQTDCTCTRL_MICROCODE_MSEL_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTDCTCTRL_MICROCODE_MSEL_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_IQTDCTCTRL_REGCFG 4:4 /* RWIUF */ #define NV_CNVDEC_IQTDCTCTRL_REGCFG_WAIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTDCTCTRL_REGCFG_DONE 0x00000001 /* RW--V */ #define NV_CNVDEC_IQTDMA 0x0002ab00 /* RW-4R */ #define NV_CNVDEC_IQTDMA_WIDTHM1 7:0 /* RWIUF */ #define NV_CNVDEC_IQTDMA_WIDTHM1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTDMA_ENABLE 31:31 /* RWIUF */ #define NV_CNVDEC_IQTDMA_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTRDOFFS 0x0002ac00 /* RW-4R */ #define NV_CNVDEC_IQTRDOFFS_ADDR 31:0 /* RWIUF */ #define NV_CNVDEC_IQTRDOFFS_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTRDCNT 0x0002ad00 /* RW-4R */ #define NV_CNVDEC_IQTRDCNT_DATA 31:0 /* RWIUF */ #define NV_CNVDEC_IQTRDCNT_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTWROFFS 0x0002ae00 /* RW-4R */ #define NV_CNVDEC_IQTWROFFS_ADDR 31:0 /* RWIUF */ #define NV_CNVDEC_IQTWROFFS_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTWRCNT 0x0002af00 /* RW-4R */ #define NV_CNVDEC_IQTWRCNT_DATA 31:0 /* R-IUF */ #define NV_CNVDEC_IQTWRCNT_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_IQTRDCROP 0x0002b000 /* RW-4R */ #define NV_CNVDEC_IQTRDCROP_LEFT 7:0 /* RWIUF */ #define NV_CNVDEC_IQTRDCROP_LEFT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTRDCROP_TOP 15:8 /* RWIUF */ #define NV_CNVDEC_IQTRDCROP_TOP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTRDCROP_RIGHT 23:16 /* RWIUF */ #define NV_CNVDEC_IQTRDCROP_RIGHT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTRDCROP_BOTTOM 31:24 /* RWIUF */ #define NV_CNVDEC_IQTRDCROP_BOTTOM_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTWRCROP 0x0002b100 /* RW-4R */ #define NV_CNVDEC_IQTWRCROP_LEFT 7:0 /* RWIUF */ #define NV_CNVDEC_IQTWRCROP_LEFT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTWRCROP_TOP 15:8 /* RWIUF */ #define NV_CNVDEC_IQTWRCROP_TOP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTWRCROP_RIGHT 23:16 /* RWIUF */ #define NV_CNVDEC_IQTWRCROP_RIGHT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_IQTWRCROP_BOTTOM 31:24 /* RWIUF */ #define NV_CNVDEC_IQTWRCROP_BOTTOM_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL 0x0001c000 /* RW-4R */ #define NV_CNVDEC_MCFETCH_MCFCTL_FRAMEREAD 0:0 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_FETCH16X2 4:4 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_FETCH16X2_ON 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL_FETCH16X2_OFF 0x00000001 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_TILE_FORMAT 6:5 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_TILE_FORMAT_TBL 0x00000000 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_TILE_FORMAT_KBL 0x00000001 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL_TILE_FORMAT_16x16 0x00000002 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_MCC_INVALID 7:7 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_MCC_INVALID_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_MCC_INVALID_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL_ECO_1249580_DIS 8:8 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_ECO_1249580_DIS_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_ECO_1249580_DIS_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GIP 9:9 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_GIP_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GIP_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GT_MAIN8 10:10 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_GT_MAIN8_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GT_MAIN8_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT 13:11 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_2 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_4 0x00000001 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_8 0x00000002 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_16 0x00000003 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_GOB_HEIGHT_GOB_32 0x00000004 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_CHROMA_FORMAT 15:14 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_CHROMA_FORMAT_420 0x00000000 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_CHROMA_FORMAT_444 0x00000001 /* RWI-V */ #define NV_CNVDEC_MCFETCH_MCFCTL_ECDMA 16:16 /* RW-VF */ #define NV_CNVDEC_MCFETCH_MCFCTL_ECDMA_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_MCFETCH_MCFCTL_ECDMA_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_MCFETCH_FRMSFCW 0x0001c100 /* RW-4R */ #define NV_CNVDEC_MCFETCH_FRMSFCW_LUMA 11:0 /* RW-VF */ #define NV_CNVDEC_MCFETCH_FRMSFCW_CHROMA 27:16 /* RW-VF */ #define NV_CNVDEC_MCFETCH_FLDSFCW 0x0001c200 /* RW-4R */ #define NV_CNVDEC_MCFETCH_FLDSFCW_LUMA 11:0 /* RW-VF */ #define NV_CNVDEC_MCFETCH_FLDSFCW_CHROMA 27:16 /* RW-VF */ #define NV_CNVDEC_MCFETCH_FRMSIZE 0x0001c300 /* RW-4R */ #define NV_CNVDEC_MCFETCH_FRMSIZE_WIDTHM1 12:0 /* RW-VF */ #define NV_CNVDEC_MCFETCH_FRMSIZE_HEIGHTM1 28:16 /* RW-VF */ #define NV_CNVDEC_MCFETCH_DBG_STAT(i) (0x0001c400+(i)*4) /* R--4A */ #define NV_CNVDEC_MCFETCH_DBG_STAT__SIZE_1 16 /* */ #define NV_CNVDEC_MCFETCH_DBG_STAT_DATA 31:0 /* R--UF */ #define NV_CNVDEC_MCFETCH_CACHE_REQ 0x0001cc00 /* RW-4R */ #define NV_CNVDEC_MCFETCH_CACHE_REQ_NUM 31:0 /* RW-VF */ #define NV_CNVDEC_MCFETCH_CACHE_HIT 0x0001cd00 /* RW-4R */ #define NV_CNVDEC_MCFETCH_CACHE_HIT_NUM 31:0 /* RW-VF */ #define NV_CNVDEC_MVLOCAL_MEMORY(i,j) (0x00038000+(i)*256+(j)*4) /* RW-4A */ #define NV_CNVDEC_MVLOCAL_MEMORY__SIZE_1 12 /* */ #define NV_CNVDEC_MVLOCAL_MEMORY__SIZE_2 64 /* */ #define NV_CNVDEC_MVLOCAL_MEMORY_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MVSEQSTART 0x00039000 /* RW-4R */ #define NV_CNVDEC_MVSEQSTART_SLICE_ENABLE 0:0 /* RW-UF */ #define NV_CNVDEC_MVSEQSTART_SLICE_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVSEQSTART_INIT_ENABLE 4:4 /* RW-UF */ #define NV_CNVDEC_MVSEQSTART_INIT_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVFRMPARAM 0x00039100 /* RW-4R */ #define NV_CNVDEC_MVFRMPARAM_PICWIDTHINMBS 7:0 /* RWXUF */ #define NV_CNVDEC_MVFRMPARAM_PICWIDTHINMBS_1MB 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_PICWIDTHINMBS_256MB 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_PICHEIGHTINMBS 15:8 /* RWXUF */ #define NV_CNVDEC_MVFRMPARAM_PICHEIGHTINMBS_1MB 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_PICHEIGHTINMBS_256MB 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PICCODING 18:16 /* RWXUF */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PICCODING_I 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PICCODING_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PICCODING_B 0x00000003 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PICCODING_D 0x00000004 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_PTYPE 22:20 /* RWXUF */ #define NV_CNVDEC_MVFRMPARAM_PTYPE_I 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_PTYPE_P 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_PTYPE_B 0x00000002 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_PTYPE_BI 0x00000003 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_PTYPE_SKIPPED 0x00000004 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PTYPE 22:20 /* RWXUF */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PTYPE_RESERVED 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PTYPE_TOP_FIELD 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PTYPE_BOTTOM_FIELD 0x00000002 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_MPEG2_PTYPE_FRAME 0x00000003 /* RWX-V */ #define NV_CNVDEC_MVFRMPARAM_VC1_MAINPROFILE 24:24 /* RWXUF */ #define NV_CNVDEC_MVWDCOUNTER 0x00039200 /* RW-4R */ #define NV_CNVDEC_MVWDCOUNTER_WDCOUNT 15:0 /* RW-UF */ #define NV_CNVDEC_MVWDTIME 0x00039300 /* RW-4R */ #define NV_CNVDEC_MVWDTIME_WDTIME 15:0 /* RW-UF */ #define NV_CNVDEC_MVWDTIME_WDTIME_INFINITE 0x0000ffff /* RWI-V */ #define NV_CNVDEC_MVCTRL0 0x00039400 /* RW-4R */ #define NV_CNVDEC_MVCTRL0_VC1_DQMODE 1:0 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_VC1_DQMASK 7:4 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_VC1_DPQUANT 13:8 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_VC1_ALT_DPQUANT 21:16 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_VC1_ERRSFCIDX 31:25 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_VC1_ERRSFCIDX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_H264_APPLEOOLD_FLAG 0:0 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_H264_APPLEOOLD_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_H264_REFPIC_FLAG 1:1 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_H264_REFPIC_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_H264_CONSTRAINED_INTRA_PRED 2:2 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_H264_CONSTRAINED_INTRA_PRED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_H264_CUR_BOTTOM_FIRST 3:3 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_H264_CUR_BOTTOM_FIRST_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_H264_CHROMA_QPIDXOFF 8:4 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_H264_SEC_CHROMA_QPIDXOFF 13:9 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_SVC_NOTLAYERTYPE 15:14 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_NOTLAYERTYPE_TARGETLAYER 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_SVC_NOTLAYERTYPE_REFBASELAYER 0x00000001 /* RW--V */ #define NV_CNVDEC_MVCTRL0_SVC_NOTLAYERTYPE_BASELAYER_RES 0x00000002 /* RW--V */ #define NV_CNVDEC_MVCTRL0_SVC_NOTLAYERTYPE_BASELAYER_NORES 0x00000003 /* RW--V */ #define NV_CNVDEC_MVCTRL0_SVC_NOTBASELAYER 16:16 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_NOTBASELAYER_BASELAYER 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_SVC_NOTBASELAYER_NOTBASELAYER 0x00000001 /* RW--V */ #define NV_CNVDEC_MVCTRL0_SVC_INPLACEILP 17:17 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_INPLACEILP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_SVC_TCLVLPRED 18:18 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_TCLVLPRED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_SVC_TCLVLPREDNEXT 19:19 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_TCLVLPREDNEXT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_SVC_TCLVLPREDSLICE 20:20 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_TCLVLPREDSLICE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_SVC_RESCHANGE 21:21 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_RESCHANGE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_SVC_RESTRRESCHANGE 22:22 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_RESTRRESCHANGE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_SVC_INTERLAYERPRED 23:23 /* RWIVF */ #define NV_CNVDEC_MVCTRL0_SVC_INTERLAYERPRED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_H264_ERRSFCIDX 31:25 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_H264_ERRSFCIDX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_MPEG2_DIVX311 0:0 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG2_DIVX311_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_MPEG2_TOPFIELD_FIRST 1:1 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG2_TOPFIELD_FIRST_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_MPEG2_FULL_PEL_FWD_VECTOR 16:16 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG2_FULL_PEL_BWD_VECTOR 17:17 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG2_ERRSFCIDX 31:25 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG2_ERRSFCIDX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_MPEG4_DIVX_FLAG 0:0 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG4_DIVX_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_MPEG4_TOPFIELD_FIRST 1:1 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG4_TOPFIELD_FIRST_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_MPEG4_QUARTER_SAMPLE 2:2 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG4_QUARTER_SAMPLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL0_MPEG4_VOP_FCODE_FWD 6:4 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG4_VOP_FCODE_BWD 10:8 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG4_ERRSFCIDX 31:25 /* RWXVF */ #define NV_CNVDEC_MVCTRL0_MPEG4_ERRSFCIDX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1 0x00039500 /* RW-4R */ #define NV_CNVDEC_MVCTRL1_H264_WEIGHTED_PRED_IDC 3:2 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_DIRECT_SPATIAL_MVPRED 4:4 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_SLICE_ALPHAC0_OFFSDIV2 8:5 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_SLICE_BETA_OFFSDIV2 12:9 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_QPY 18:13 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_BOTTOM_IS_CLOSER 19:19 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_BOTTOM_IS_CLOSER_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_H264_REFPIC_IS_BOTTOMFIELD 20:20 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_REFPIC_IS_BOTTOMFIELD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_H264_COLPIC_IS_SHORTTERM 21:21 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_COLPIC_IS_SHORTTERM_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_H264_REFPIC_IS_FIELD 22:22 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_H264_REFPIC_IS_FIELD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_H264_DIS_DEBLOCKING_FLT_IDC 26:24 /* RWIVF */ #define NV_CNVDEC_MVCTRL1_H264_DIS_DEBLOCKING_FLT_IDC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_VC1_LOOPFILTER 0:0 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_LOOPFILTER_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_VC1_FASTUVMC 1:1 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_FASTUVMC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_VC1_OVERLAP 2:2 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_OVERLAP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_VC1_CONDOVER 3:3 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_CONDOVER_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_VC1_MVRANGE 5:4 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_MVMODE 10:8 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_MVMODE_MIXEDMV 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVCTRL1_VC1_MVMODE_1MV 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVCTRL1_VC1_MVMODE_1MV_HALFPEL 0x00000002 /* RWX-V */ #define NV_CNVDEC_MVCTRL1_VC1_MVMODE_1MV_HALFPEL_BILINEAR 0x00000003 /* RWX-V */ #define NV_CNVDEC_MVCTRL1_VC1_MVMODE_INTENSITY_COMPENSATION 0x00000004 /* RWX-V */ #define NV_CNVDEC_MVCTRL1_VC1_BFRACTION 20:16 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_REFDIST 28:24 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_NUMREF 30:30 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_NUMREF_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_VC1_REFFIELD 31:31 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_VC1_REFFIELD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL1_MPEG4_TRD0 15:0 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_MPEG4_TRD1 31:16 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_MPEG2_FCODE_00 3:0 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_MPEG2_FCODE_01 7:4 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_MPEG2_FCODE_10 11:8 /* RWXVF */ #define NV_CNVDEC_MVCTRL1_MPEG2_FCODE_11 15:12 /* RWXVF */ #define NV_CNVDEC_MVPSINFO 0x00039600 /* RW-4R */ #define NV_CNVDEC_MVPSINFO_CODEC 2:0 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_CODEC_MPEG1 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_CODEC_MPEG2 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_CODEC_VC1 0x00000002 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_CODEC_H264 0x00000003 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_CODEC_MPEG4 0x00000004 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_CODEC_VP8 0x00000005 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_DXVA 4:3 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_NOTBASELAYER 6:6 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_BPIC 6:6 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_SECFIELD 7:7 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_MBAFF_TFF 8:8 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_STYPE_FCM 10:9 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_STYPE_FCM_P 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_STYPE_FCM_B 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_STYPE_FCM_I 0x00000002 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_STYPE_FCM_PROG_FRAME 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_STYPE_FCM_INTL_FRAME 0x00000002 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_STYPE_FCM_INTL_FIELD 0x00000003 /* RWX-V */ #define NV_CNVDEC_MVPSINFO_COLOR_BILINEAR 11:11 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_DIR8X8INF_INTLFWD 12:12 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_FIELDPIC_INTLBWD 13:13 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_VERSION 13:11 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_BOTFIELD 14:14 /* RWXVF */ #define NV_CNVDEC_MVPSINFO_FRMSFCEN 15:15 /* RWXVF */ #define NV_CNVDEC_MVCTRL2 0x00039700 /* RW-4R */ #define NV_CNVDEC_MVCTRL2_H264_BOTTOMFIRST 15:0 /* RWXVF */ #define NV_CNVDEC_MVCTRL2_INTER_BS_STCOEFF_CHK 16:16 /* RWIVF */ #define NV_CNVDEC_MVCTRL2_INTER_BS_STCOEFF_CHK_REV_032009 0x00000001 /* RW--V */ #define NV_CNVDEC_MVCTRL2_INTER_BS_STCOEFF_CHK_REV_NEXTREV 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL2_INTER_XF8_NO_NZ_CHK 17:17 /* RWIVF */ #define NV_CNVDEC_MVCTRL2_INTER_XF8_NO_NZ_CHK_REV_032009 0x00000001 /* RW--V */ #define NV_CNVDEC_MVCTRL2_INTER_XF8_NO_NZ_CHK_REV_NEXTREV 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVCTRL2_MPEG4_TRB1 31:16 /* RWXVF */ #define NV_CNVDEC_MVCTRL2_MPEG4_TRB0 15:0 /* RWXVF */ #define NV_CNVDEC_MVRPLBASE 0x00039800 /* RW-4R */ #define NV_CNVDEC_MVRPLBASE_ADDR 10:0 /* RWXVF */ #define NV_CNVDEC_MVSPLBASE 0x00039900 /* RW-4R */ #define NV_CNVDEC_MVSPLBASE_ADDR 9:0 /* RWXVF */ #define NV_CNVDEC_MVSTATUS 0x00039a00 /* R--4R */ #define NV_CNVDEC_MVSTATUS_SEQ_BUSY 0:0 /* R--VF */ #define NV_CNVDEC_MVSTATUS_IS_BUSY 1:1 /* R--VF */ #define NV_CNVDEC_MVSTATUS_WCOL_BUSY 2:2 /* R--VF */ #define NV_CNVDEC_MVSTATUS_RCOL_BUSY 3:3 /* R--VF */ #define NV_CNVDEC_MVSTATUS_OSPRDS_BUSY 4:4 /* R--VF */ #define NV_CNVDEC_MVSTATUS_OSPDBL_BUSY 5:5 /* R--VF */ #define NV_CNVDEC_MVSTATUS_OSPREC_BUSY 6:6 /* R--VF */ #define NV_CNVDEC_MVSTATUS_OSPMCS_BUSY 7:7 /* R--VF */ #define NV_CNVDEC_MVSTATUS_H2M_BUSY 8:8 /* R--VF */ #define NV_CNVDEC_MVSTATUS_M2H_BUSY 9:9 /* R--VF */ #define NV_CNVDEC_MVSTATUS_ILPMBRD_BUSY 10:10 /* R--VF */ #define NV_CNVDEC_MVSTATUS_ILPMBWR_BUSY 11:11 /* R--VF */ #define NV_CNVDEC_MVSTATUS_OSPILP_BUSY 12:12 /* R--VF */ #define NV_CNVDEC_MVPSINFO2 0x00039b00 /* RW-4R */ #define NV_CNVDEC_MVPSINFO2_DBF_DISABLE 0:0 /* RW-VF */ #define NV_CNVDEC_MVPSINFO2_DBF_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVPSINFO2_MCS_DISABLE 1:1 /* RW-VF */ #define NV_CNVDEC_MVPSINFO2_MCS_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVPSINFO2_ILP_ENABLE 2:2 /* RW-VF */ #define NV_CNVDEC_MVPSINFO2_ILP_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTCSW 0x00039c00 /* RW-4R */ #define NV_CNVDEC_MVINTCSW_IRQ_WDTMR 0:0 /* RWXVF */ #define NV_CNVDEC_MVINTCSW_IRQ_ISDMA 1:1 /* RWXVF */ #define NV_CNVDEC_MVINTCSW_IRQ_RESERVED 2:2 /* RWXVF */ #define NV_CNVDEC_MVINTCSW_IRQ_EOSP 3:3 /* RWXVF */ #define NV_CNVDEC_MVINTCSW_IRQ_TERR 4:4 /* RWXVF */ #define NV_CNVDEC_MVINTCSW_IRQ_RESERR 5:5 /* RWXVF */ #define NV_CNVDEC_MVINTCSW_IRQ_BERR 6:6 /* RWXVF */ #define NV_CNVDEC_MVINTCSW_IRQ_MC_CFGERR 7:7 /* RWXVF */ #define NV_CNVDEC_MVINTCSW_IRQ_REC_CFGERR 8:8 /* RWXVF */ #define NV_CNVDEC_MVINTEN 0x00039d00 /* RW-4R */ #define NV_CNVDEC_MVINTEN_IRQ_WDTMR 0:0 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTEN_IRQ_ISDMA 1:1 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_ISDMA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTEN_IRQ_RESERVED 2:2 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTEN_IRQ_EOSP 3:3 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_EOSP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTEN_IRQ_TERR 4:4 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_TERR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTEN_IRQ_RESERR 5:5 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_RESERR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTEN_IRQ_BERR 6:6 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_BERR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTEN_IRQ_MC_CFGERR 7:7 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_MC_CFGERR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVINTEN_IRQ_REC_CFGERR 8:8 /* RW-VF */ #define NV_CNVDEC_MVINTEN_IRQ_REC_CFGERR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVWT_CNTRL 0x00039e00 /* RW-4R */ #define NV_CNVDEC_MVWT_CNTRL_CHROMA_LOG2_WEIGHT_DENOM 2:0 /* RW-VF */ #define NV_CNVDEC_MVWT_CNTRL_LUMA_LOG2_WEIGHT_DENOM 5:3 /* RW-VF */ #define NV_CNVDEC_MVWT_CNTRL_WEIGHT_DENOM_WR_EN 6:6 /* RW-VF */ #define NV_CNVDEC_MVWT_CNTRL_ADR 14:8 /* RW-VF */ #define NV_CNVDEC_MVWT_CNTRL_ADR_WR_EN 15:15 /* RW-VF */ #define NV_CNVDEC_MVWT_CNTRL_LOADED 16:16 /* RW-VF */ #define NV_CNVDEC_MVWT_DATA 0x00039f00 /* RW-4R */ #define NV_CNVDEC_MVWT_DATA_LUMA_OFFSET 7:0 /* RW-VF */ #define NV_CNVDEC_MVWT_DATA_LUMA_WEIGHT 15:8 /* RW-VF */ #define NV_CNVDEC_MVWT_DATA_CHROMA_WEIGHT_FLAG 16:16 /* RW-VF */ #define NV_CNVDEC_MVWT_DATA_LUMA_WEIGHT_FLAG 17:17 /* RW-VF */ #define NV_CNVDEC_MVWT_DATA_CHROMA_V_OFFSET 7:0 /* RW-VF */ #define NV_CNVDEC_MVWT_DATA_CHROMA_V_WEIGHT 15:8 /* RW-VF */ #define NV_CNVDEC_MVWT_DATA_CHROMA_U_OFFSET 23:16 /* RW-VF */ #define NV_CNVDEC_MVWT_DATA_CHROMA_U_WEIGHT 31:24 /* RW-VF */ #define NV_CNVDEC_MVRCOLADDR 0x0003a000 /* RW-4R */ #define NV_CNVDEC_MVRCOLADDR_RCOL_ADDR 31:0 /* RW-UF */ #define NV_CNVDEC_MVRCOLPARAM 0x0003a100 /* RW-4R */ #define NV_CNVDEC_MVRCOLPARAM_RCOL_LWIDTH 7:0 /* RW-UF */ #define NV_CNVDEC_MVRCOLPARAM_RCOL_NLIN 8:8 /* RW-VF */ #define NV_CNVDEC_MVRCOLLINE 0x0003a200 /* RW-4R */ #define NV_CNVDEC_MVRCOLLINE_RCOL_LREM 7:0 /* RWXUF */ #define NV_CNVDEC_MVRCOLLINE_RCOL_LCNT 16:8 /* RWXUF */ #define NV_CNVDEC_MVRCOLOFFS 0x0003a300 /* RW-4R */ #define NV_CNVDEC_MVRCOLOFFS_RCOL_OFFS 11:0 /* RW-UF */ #define NV_CNVDEC_MVRCOLOFFS_RCOL_LODD 12:12 /* RW-VF */ #define NV_CNVDEC_MVRCOLOFFS_4K_RCOL_OFFS 15:0 /* RW-UF */ #define NV_CNVDEC_MVRCOLOFFS_4K_RCOL_LODD 16:16 /* RW-VF */ #define NV_CNVDEC_MVRCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_CNVDEC_MVWCOLADDR 0x0003a400 /* RW-4R */ #define NV_CNVDEC_MVWCOLADDR_WCOL_ADDR 31:0 /* RW-UF */ #define NV_CNVDEC_MVWCOLPARAM 0x0003a500 /* RW-4R */ #define NV_CNVDEC_MVWCOLPARAM_WCOL_LWIDTH 7:0 /* RW-UF */ #define NV_CNVDEC_MVWCOLPARAM_WCOL_MBAFF 8:8 /* RW-VF */ #define NV_CNVDEC_MVWCOLPARAM_WCOL_FIELD 9:9 /* RW-VF */ #define NV_CNVDEC_MVWCOLPARAM_4MV 10:10 /* RW-VF */ #define NV_CNVDEC_MVWCOLPARAM_4MV_DIS 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVWCOLPARAM_4MV_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_MVWCOLPARAM_WRITEENABLE 11:11 /* RW-VF */ #define NV_CNVDEC_MVWCOLPARAM_WRITEENABLE_DIS 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVWCOLPARAM_WRITEENABLE_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_MVWCOLLINE 0x0003a600 /* RW-4R */ #define NV_CNVDEC_MVWCOLLINE_WCOL_LREM 7:0 /* RW-UF */ #define NV_CNVDEC_MVWCOLLINE_WCOL_LCNT 16:8 /* RW-UF */ #define NV_CNVDEC_MVWCOLOFFS 0x0003a700 /* RW-4R */ #define NV_CNVDEC_MVWCOLOFFS_WCOL_OFFS 12:0 /* RW-UF */ #define NV_CNVDEC_MVWCOLOFFS_WCOL_LODD 13:13 /* RW-VF */ #define NV_CNVDEC_MVWCOLOFFS_4K_WCOL_OFFS 15:0 /* RW-UF */ #define NV_CNVDEC_MVWCOLOFFS_4K_WCOL_LODD 16:16 /* RW-VF */ #define NV_CNVDEC_MVWCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_CNVDEC_MVISSTART 0x0003a800 /* RW-4R */ #define NV_CNVDEC_MVISSTART_BUF_ADDR 31:0 /* RW-VF */ #define NV_CNVDEC_MVISSIZE 0x0003a900 /* RW-4R */ #define NV_CNVDEC_MVISSIZE_BUF_SIZE 31:8 /* RW-VF */ #define NV_CNVDEC_MVISOFFS 0x0003aa00 /* RW-4R */ #define NV_CNVDEC_MVISOFFS_BUF_OFFS 31:2 /* RW-VF */ #define NV_CNVDEC_MVISCOUNT 0x0003ab00 /* RW-4R */ #define NV_CNVDEC_MVISCOUNT_BUF_COUNT 31:2 /* RW-VF */ #define NV_CNVDEC_MVISCTL 0x0003ac00 /* RW-4R */ #define NV_CNVDEC_MVISCTL_ENABLE 0:0 /* RW-VF */ #define NV_CNVDEC_MVISCTL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVISCTL_DMASUSPEND 1:1 /* -W-VF */ #define NV_CNVDEC_MVDBG_CTL 0x0003ad00 /* RW-4R */ #define NV_CNVDEC_MVDBG_CTL_RDSWAIT 0:0 /* RW-VF */ #define NV_CNVDEC_MVDBG_CTL_RDSWAIT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVDBG_CTL_MCSWAIT 1:1 /* RW-VF */ #define NV_CNVDEC_MVDBG_CTL_MCSWAIT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVERRORCTL 0x0003ae00 /* -W-4R */ #define NV_CNVDEC_MVERRORCTL_SET_ERROR_STATUS 0:0 /* -W-VF */ #define NV_CNVDEC_MVERRORCTL_CLR_ERROR_COUNTERS 1:1 /* -W-VF */ #define NV_CNVDEC_MVERRORCTL_CTS_ERROR_CORRECTION 4:4 /* -W-VF */ #define NV_CNVDEC_MVERRORMASK 0x0003af00 /* RW-4R */ #define NV_CNVDEC_MVERRORMASK_MVY_RANGE128 0:0 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_MVY_RANGE256 1:1 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_MVY_RANGE512 2:2 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_VLD_MBERROR 3:3 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_H264_INTRA16X16 4:4 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_H264_INTRA8X8 5:5 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_H264_INTRA4X4 6:6 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_H264_BIPRED 7:7 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_H264_NEI_MB 8:8 /* RW-VF */ #define NV_CNVDEC_MVERRORMASK_H264_NEI_PART 9:9 /* RW-VF */ #define NV_CNVDEC_MVERRORSTAT 0x0003b000 /* R--4R */ #define NV_CNVDEC_MVERRORSTAT_MVY_RANGE128 0:0 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_MVY_RANGE256 1:1 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_MVY_RANGE512 2:2 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_VLD_MBERROR 3:3 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_H264_INTRA16X16 4:4 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_H264_INTRA8X8 5:5 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_H264_INTRA4X4 6:6 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_H264_BIPRED 7:7 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_H264_NEI_MB 8:8 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_H264_NEI_PART 9:9 /* R--VF */ #define NV_CNVDEC_MVERRORSTAT_SW_ERR 31:31 /* R--VF */ #define NV_CNVDEC_MVERRORDBG 0x0003b100 /* R--4R */ #define NV_CNVDEC_MVERRORDBG_VLD_ERROR_MB_COUNT 15:0 /* R--VF */ #define NV_CNVDEC_MVERRORDBG_DEC_ERROR_MB_COUNT 31:16 /* R--VF */ #define NV_CNVDEC_MV_MB_COUNTER 0x0003b200 /* RW-4R */ #define NV_CNVDEC_MV_MB_COUNTER_INTRA 15:0 /* RW-VF */ #define NV_CNVDEC_MV_MB_COUNTER_INTRA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV_MB_COUNTER_SKIP 31:16 /* RW-VF */ #define NV_CNVDEC_MV_MB_COUNTER_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV_MB_COUNTER1 0x0003b300 /* RW-4R */ #define NV_CNVDEC_MV_MB_COUNTER1_REG 16:0 /* RW-VF */ #define NV_CNVDEC_MV_MB_COUNTER1_REG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVDBG_STATE(i) (0x0003b400+(i)*4) /* R--4A */ #define NV_CNVDEC_MVDBG_STATE__SIZE_1 13 /* */ #define NV_CNVDEC_MVDBG_STATE_DATA 31:0 /* R--UF */ #define NV_CNVDEC_MVILPSCALEMV1X(i) (0x0003b600+(i)*4) /* RW-4A */ #define NV_CNVDEC_MVILPSCALEMV1X__SIZE_1 8 /* */ #define NV_CNVDEC_MVILPSCALEMV1X_DATA 23:0 /* RW-UF */ #define NV_CNVDEC_MVILPSCALEMV1Y(i) (0x0003b620+(i)*4) /* RW-4A */ #define NV_CNVDEC_MVILPSCALEMV1Y__SIZE_1 8 /* */ #define NV_CNVDEC_MVILPSCALEMV1Y_DATA 23:0 /* RW-UF */ #define NV_CNVDEC_MVILPSCALEMV2X(i) (0x0003b640+(i)*4) /* RW-4A */ #define NV_CNVDEC_MVILPSCALEMV2X__SIZE_1 8 /* */ #define NV_CNVDEC_MVILPSCALEMV2X_DATA 26:0 /* RW-UF */ #define NV_CNVDEC_MVILPSCALEMV2Y(i) (0x0003b660+(i)*4) /* RW-4A */ #define NV_CNVDEC_MVILPSCALEMV2Y__SIZE_1 8 /* */ #define NV_CNVDEC_MVILPSCALEMV2Y_DATA 26:0 /* RW-UF */ #define NV_CNVDEC_MVILPOFFSETMVX(i) (0x0003b680+(i)*4) /* RW-4A */ #define NV_CNVDEC_MVILPOFFSETMVX__SIZE_1 8 /* */ #define NV_CNVDEC_MVILPOFFSETMVX_DATA 27:0 /* RW-UF */ #define NV_CNVDEC_MVILPOFFSETMVY(i) (0x0003b6a0+(i)*4) /* RW-4A */ #define NV_CNVDEC_MVILPOFFSETMVY__SIZE_1 8 /* */ #define NV_CNVDEC_MVILPOFFSETMVY_DATA 25:0 /* RW-UF */ #define NV_CNVDEC_MVILPDIM 0x0003b700 /* RW-4R */ #define NV_CNVDEC_MVILPDIM_STRIDEM1 7:0 /* RW-UF */ #define NV_CNVDEC_MVILPDIM_WIDTHM1 23:16 /* RW-UF */ #define NV_CNVDEC_MVILPDIM_HEIGHTM1 31:24 /* RW-UF */ #define NV_CNVDEC_MVILPMBCTL_REF 0x0003b800 /* RW-4R */ #define NV_CNVDEC_MVILPMBCTL_REF_OFFS 31:0 /* RW-UF */ #define NV_CNVDEC_MVILPMBCTL_CUR 0x0003b900 /* RW-4R */ #define NV_CNVDEC_MVILPMBCTL_CUR_OFFS 31:0 /* RW-UF */ #define NV_CNVDEC_MVILPSLICE_MODE_CUR 0x0003ba00 /* RW-4R */ #define NV_CNVDEC_MVILPSLICE_MODE_CUR_OFFS 31:0 /* RW-UF */ #define NV_CNVDEC_MVILPLAYER_CTL 0x0003bb00 /* RW-4R */ #define NV_CNVDEC_MVILPLAYER_CTL_RD_ENABLE 0:0 /* RW-UF */ #define NV_CNVDEC_MVILPLAYER_CTL_WR_ENABLE 1:1 /* RW-UF */ #define NV_CNVDEC_MVILPLAYER_CTL_CROPCHANGE 2:2 /* RW-UF */ #define NV_CNVDEC_MVILPLAYER_CTL_RESTRRESCHANGE 3:3 /* RW-UF */ #define NV_CNVDEC_MVILPLAYER_CTL_DIR8X8INF 4:4 /* RW-UF */ #define NV_CNVDEC_MVILPLAYER_CTL_REFCLAMP_ENABLE 15:15 /* RW-UF */ #define NV_CNVDEC_MVILPLAYER_CTL_REFWIDTHM1 23:16 /* RW-UF */ #define NV_CNVDEC_MVILPLAYER_CTL_REFHEIGHTM1 31:24 /* RW-UF */ #define NV_CNVDEC_MVILPSLICE_CTL 0x0003bc00 /* RW-4R */ #define NV_CNVDEC_MVILPSLICE_CTL_SLICETYPE 1:0 /* RW-UF */ #define NV_CNVDEC_MVILPSLICE_CTL_SLICETYPE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVILPSLICE_CTL_SLICETYPE_P 0x00000000 /* RWX-V */ #define NV_CNVDEC_MVILPSLICE_CTL_SLICETYPE_B 0x00000001 /* RWX-V */ #define NV_CNVDEC_MVILPSLICE_CTL_SLICETYPE_I 0x00000002 /* RWX-V */ #define NV_CNVDEC_MVILPSLICE_CTL_NOILP 2:2 /* RW-UF */ #define NV_CNVDEC_MVILPSLICE_CTL_NOILP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MVILPSLICE_CTL_NUMENTRIES 7:4 /* RW-UF */ #define NV_CNVDEC_MVILPSLICE_CTL_NUMENTRIES_INIT 0x00000008 /* RWI-V */ #define NV_CNVDEC_MVILPCROP 0x0003bd00 /* RW-4R */ #define NV_CNVDEC_MVILPCROP_LEFT 7:0 /* RW-UF */ #define NV_CNVDEC_MVILPCROP_TOP 15:8 /* RW-UF */ #define NV_CNVDEC_MVILPCROP_RIGHT 23:16 /* RW-UF */ #define NV_CNVDEC_MVILPCROP_BOTTOM 31:24 /* RW-UF */ #define NV_CNVDEC_MVILPOFFSETX_LO 0x0003be00 /* RW-4R */ #define NV_CNVDEC_MVILPOFFSETX_LO_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MVILPOFFSETY_LO 0x0003bf00 /* RW-4R */ #define NV_CNVDEC_MVILPOFFSETY_LO_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MVILPOFFSET_HI 0x0003c000 /* RW-4R */ #define NV_CNVDEC_MVILPOFFSET_HI_X 1:0 /* RW-UF */ #define NV_CNVDEC_MVILPOFFSET_HI_Y 17:16 /* RW-UF */ #define NV_CNVDEC_MVILPSCALEX 0x0003c100 /* RW-4R */ #define NV_CNVDEC_MVILPSCALEX_DATA 24:0 /* RW-UF */ #define NV_CNVDEC_MVILPSCALEY 0x0003c200 /* RW-4R */ #define NV_CNVDEC_MVILPSCALEY_DATA 24:0 /* RW-UF */ #define NV_CNVDEC_MVILPREFIDXMAPL0_LO 0x0003c300 /* RW-4R */ #define NV_CNVDEC_MVILPREFIDXMAPL0_LO_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MVILPREFIDXMAPL0_HI 0x0003c400 /* RW-4R */ #define NV_CNVDEC_MVILPREFIDXMAPL0_HI_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MVILPREFIDXMAPL1_LO 0x0003c500 /* RW-4R */ #define NV_CNVDEC_MVILPREFIDXMAPL1_LO_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MVILPREFIDXMAPL1_HI 0x0003c600 /* RW-4R */ #define NV_CNVDEC_MVILPREFIDXMAPL1_HI_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MVSFCLAYOUT 0x0003c700 /* RW-4R */ #define NV_CNVDEC_MVSFCLAYOUT_DATA 15:0 /* RW-UF */ #define NV_CNVDEC_MVSFCLAYOUT_DATA_INIT 0x0000ffff /* RWI-V */ #define NV_CNVDEC_SA_CONTROL(i) (0x0002d800+(i)*4) /* RW-4A */ #define NV_CNVDEC_SA_CONTROL__SIZE_1 2 /* */ #define NV_CNVDEC_SA_CONTROL_CMD_CHUNK_SZ 4:0 /* RW-UF */ #define NV_CNVDEC_SA_CONTROL_CIPHER_CNT 9:5 /* RW-UF */ #define NV_CNVDEC_SA_CONTROL_PLAIN_SZ 16:10 /* RW-UF */ #define NV_CNVDEC_SA_CONTROL_INST_CNT 25:20 /* RW-UF */ #define NV_CNVDEC_SA_CONTROL_INST_OFFSET 31:26 /* RW-UF */ #define NV_CNVDEC_SA_START(i) (0x0002d900+(i)*4) /* RW-4A */ #define NV_CNVDEC_SA_START__SIZE_1 2 /* */ #define NV_CNVDEC_SA_START_OFFSET 6:0 /* RW-UF */ #define NV_CNVDEC_SA_START_SECTION 8:8 /* RWIUF */ #define NV_CNVDEC_SA_START_SECTION_CIPHER 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_START_SECTION_PLAIN 0x00000001 /* RW--V */ #define NV_CNVDEC_SA_INST_ARRAY(i) (0x0002da00+(i)*4) /* RW-4A */ #define NV_CNVDEC_SA_INST_ARRAY__SIZE_1 4 /* */ #define NV_CNVDEC_SA_INST_ARRAY_OP_0 4:0 /* RW-UF */ #define NV_CNVDEC_SA_INST_ARRAY_RX_0 10:5 /* RW-UF */ #define NV_CNVDEC_SA_INST_ARRAY_RY_0 14:11 /* RW-UF */ #define NV_CNVDEC_SA_INST_ARRAY_OP_1 20:16 /* RW-UF */ #define NV_CNVDEC_SA_INST_ARRAY_RX_1 26:21 /* RW-UF */ #define NV_CNVDEC_SA_INST_ARRAY_RY_1 30:27 /* RW-UF */ #define NV_CNVDEC_SA_STATUS(i) (0x0002db00+(i)*4) /* RW-4A */ #define NV_CNVDEC_SA_STATUS__SIZE_1 2 /* */ #define NV_CNVDEC_SA_STATUS_IDLE 0:0 /* R--UF */ #define NV_CNVDEC_SA_STATUS_FLUSH_PENDING 1:1 /* R--UF */ #define NV_CNVDEC_SA_STATUS_PACKETS_OUTSTANDING 2:2 /* R--UF */ #define NV_CNVDEC_SA_STATUS_STOP_UNIT 4:4 /* RWIUF */ #define NV_CNVDEC_SA_STATUS_STOP_UNIT_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_STATUS_STOP_UNIT_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_SA_STATUS_UNIT_STATE 9:8 /* R--UF */ #define NV_CNVDEC_SA_STATUS_UNIT_STATE_IDLE 0x00000000 /* R---V */ #define NV_CNVDEC_SA_STATUS_CIPHER_OFFSET 14:10 /* R--UF */ #define NV_CNVDEC_SA_STATUS_PLAIN_OFFSET 23:15 /* R--UF */ #define NV_CNVDEC_SA_STATUS_CHUNK_OFFSET 30:24 /* R--UF */ #define NV_CNVDEC_SA_PASS2_OTF 0x0002dc00 /* RW-4R */ #define NV_CNVDEC_SA_PASS2_OTF_NON_SLICE_DATA 15:0 /* RW-UF */ #define NV_CNVDEC_SA_PASS2_OTF_SSM_EN 16:16 /* RWIVF */ #define NV_CNVDEC_SA_PASS2_OTF_SSM_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SA_PASS2_OTF_SSM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_PASS2_OTF_DRM_MODE 23:17 /* RW-UF */ #define NV_CNVDEC_SA_PASS2_OTF_IV_REG_IDX 27:24 /* RW-UF */ #define NV_CNVDEC_SA_PASS2_OTF_CTR_IV_OP_OUT_IDX 31:28 /* RW-UF */ #define NV_CNVDEC_SA_SSM_ENTRY 0x0002dd00 /* RW-4R */ #define NV_CNVDEC_SA_SSM_ENTRY_BASE_ADDRESS 31:0 /* RW-UF */ #define NV_CNVDEC_SA_SSM_IV 0x0002de00 /* RW-4R */ #define NV_CNVDEC_SA_SSM_IV_BASE_ADDRESS 31:0 /* RW-UF */ #define NV_CNVDEC_SA_PASS2_OTF2 0x0002df00 /* RW-4R */ #define NV_CNVDEC_SA_PASS2_OTF2_LOOP_TRACE_IDX 0:0 /* RWIVF */ #define NV_CNVDEC_SA_PASS2_OTF2_LOOP_TRACE_IDX_0 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_PASS2_OTF2_LOOP_TRACE_IDX_1 0x00000001 /* RW--V */ #define NV_CNVDEC_SA_PASS2_OTF2_CTR_IV_OP_DIS 1:1 /* RWIVF */ #define NV_CNVDEC_SA_PASS2_OTF2_CTR_IV_OP_DIS_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_PASS2_OTF2_CTR_IV_OP_DIS_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SA_PASS2_OTF2_CODEC 2:2 /* RWIVF */ #define NV_CNVDEC_SA_PASS2_OTF2_CODEC_IS_LEGACY 0x00000001 /* RW--V */ #define NV_CNVDEC_SA_PASS2_OTF2_CODEC_IS_HEVC_VP9 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_PASS2_OTF2_HALT 3:3 /* RWIVF */ #define NV_CNVDEC_SA_PASS2_OTF2_HALT_REQ 0x00000001 /* RW--V */ #define NV_CNVDEC_SA_PASS2_OTF2_HALT_DONE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_PASS2_OTF2_CLAMP_SCP_INPUT 4:4 /* RWIVF */ #define NV_CNVDEC_SA_PASS2_OTF2_CLAMP_SCP_INPUT_DIS 0x00000001 /* RW--V */ #define NV_CNVDEC_SA_PASS2_OTF2_CLAMP_SCP_INPUT_EN 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_PASS2_OTF3 0x0002e000 /* RW-4R */ #define NV_CNVDEC_SA_PASS2_OTF3_SSM_ENTRY_NUM 15:0 /* RW-UF */ #define NV_CNVDEC_SA_PASS2_OTF3_SSM_IV_NUM 31:16 /* RW-UF */ #define NV_CNVDEC_CTL_STAT 0x00034000 /* RW-4R */ #define NV_CNVDEC_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */ #define NV_CNVDEC_CTL_STAT_DEBUG_MODE_DISABLED 0x00000000 /* R---V */ #define NV_CNVDEC_CTL_CFG 0x00034100 /* RW-4R */ #define NV_CNVDEC_CTL_CFG_LOCKDOWN 0:0 /* R-IVF */ #define NV_CNVDEC_CTL_CFG_LOCKDOWN_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_CTL_CFG_LOCKDOWN_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_CTL_CFG_LOCKDOWN_SCP 4:4 /* R-IVF */ #define NV_CNVDEC_CTL_CFG_LOCKDOWN_SCP_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_CTL_CFG_LOCKDOWN_SCP_DISABLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_CTL_SCP 0x00034200 /* RW-4R */ #define NV_CNVDEC_CTL_SCP_TOGGLE_MASTER 0:0 /* RWIVF */ #define NV_CNVDEC_CTL_SCP_TOGGLE_MASTER_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_CTL_SCP_TOGGLE_MASTER_PENDING 0x00000001 /* RW--V */ #define NV_CNVDEC_CTL_SCP_CURRENT_MASTER 1:1 /* R-IVF */ #define NV_CNVDEC_CTL_SCP_CURRENT_MASTER_FALCON 0x00000000 /* R-I-V */ #define NV_CNVDEC_CTL_SCP_CURRENT_MASTER_EXT 0x00000001 /* R---V */ #define NV_CNVDEC_CTL_HDCP0 0x00034300 /* RW-4R */ #define NV_CNVDEC_CTL_HDCP0_KEY 31:0 /* ---VF */ #define NV_CNVDEC_CTL_HDCP1 0x00034400 /* RW-4R */ #define NV_CNVDEC_CTL_HDCP1_KEY 23:0 /* ---VF */ #define NV_CNVDEC_BAR0_CSR 0x00030000 /* RW-4R */ #define NV_CNVDEC_BAR0_CSR_CMD 1:0 /* RWIVF */ #define NV_CNVDEC_BAR0_CSR_CMD_READ 0x00000001 /* RW--V */ #define NV_CNVDEC_BAR0_CSR_CMD_WRITE 0x00000002 /* RW--V */ #define NV_CNVDEC_BAR0_CSR_CMD_POSTED_WRITE 0x00000003 /* RW--V */ #define NV_CNVDEC_BAR0_CSR_CMD_UNDEFINED 0x00000000 /* RWI-V */ #define NV_CNVDEC_BAR0_CSR_BYTE_ENABLE 7:4 /* RWIVF */ #define NV_CNVDEC_BAR0_CSR_BYTE_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_BAR0_CSR_STATUS 14:12 /* R-IVF */ #define NV_CNVDEC_BAR0_CSR_STATUS_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_BAR0_CSR_STATUS_BUSY 0x00000001 /* R---V */ #define NV_CNVDEC_BAR0_CSR_STATUS_TMOUT 0x00000002 /* R---V */ #define NV_CNVDEC_BAR0_CSR_STATUS_DIS 0x00000003 /* R---V */ #define NV_CNVDEC_BAR0_CSR_STATUS_ERR 0x00000004 /* R---V */ #define NV_CNVDEC_BAR0_CSR_TRIG 31:31 /* RWIVF */ #define NV_CNVDEC_BAR0_CSR_TRIG_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_BAR0_CSR_TRIG_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_BAR0_ADDR 0x00030100 /* RW-4R */ #define NV_CNVDEC_BAR0_ADDR_REG_ADDR 31:0 /* RWIVF */ #define NV_CNVDEC_BAR0_ADDR_REG_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_BAR0_DATA 0x00030200 /* RW-4R */ #define NV_CNVDEC_BAR0_DATA_RWDATA 31:0 /* RWIVF */ #define NV_CNVDEC_BAR0_DATA_RWDATA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_BAR0_TMOUT 0x00030300 /* RW-4R */ #define NV_CNVDEC_BAR0_TMOUT_CYCLES 31:0 /* RWIVF */ #define NV_CNVDEC_BAR0_TMOUT_CYCLES_INIT 0x01f2a737 /* RWI-V */ #define NV_CNVDEC_BAR0_TMOUT_CYCLES__PROD 0x01f2a737 /* RW--V */ #define NV_CNVDEC_SA_KEYSLOT_KEY000 0x00040000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY000_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY001 0x00040100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY001_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY002 0x00040200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY002_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY003 0x00040300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY003_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY010 0x00040400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY010_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY011 0x00040500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY011_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY012 0x00040600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY012_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY013 0x00040700 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY013_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY020 0x00040800 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY020_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY021 0x00040900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY021_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY022 0x00040a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY022_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY023 0x00040b00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY023_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY030 0x00040c00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY030_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY031 0x00040d00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY031_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY032 0x00040e00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY032_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY033 0x00040f00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY033_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY040 0x00041000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY040_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY041 0x00041100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY041_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY042 0x00041200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY042_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY043 0x00041300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY043_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY050 0x00041400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY050_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY051 0x00041500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY051_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY052 0x00041600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY052_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY053 0x00041700 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY053_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY060 0x00041800 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY060_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY061 0x00041900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY061_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY062 0x00041a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY062_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY063 0x00041b00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY063_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY070 0x00041c00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY070_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY071 0x00041d00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY071_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY072 0x00041e00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY072_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY073 0x00041f00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY073_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY100 0x00042000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY100_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY101 0x00042100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY101_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY102 0x00042200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY102_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY103 0x00042300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY103_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY110 0x00042400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY110_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY111 0x00042500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY111_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY112 0x00042600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY112_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY113 0x00042700 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY113_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY120 0x00042800 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY120_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY121 0x00042900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY121_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY122 0x00042a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY122_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY123 0x00042b00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY123_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY130 0x00042c00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY130_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY131 0x00042d00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY131_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY132 0x00042e00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY132_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY133 0x00042f00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY133_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY140 0x00043000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY140_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY141 0x00043100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY141_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY142 0x00043200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY142_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY143 0x00043300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY143_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY150 0x00043400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY150_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY151 0x00043500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY151_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY152 0x00043600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY152_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY153 0x00043700 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY153_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY160 0x00043800 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY160_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY161 0x00043900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY161_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY162 0x00043a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY162_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY163 0x00043b00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY163_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY170 0x00043c00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY170_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY171 0x00043d00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY171_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY172 0x00043e00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY172_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY173 0x00043f00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY173_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_FALCON 0x00044000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_FALCON_EN 31:0 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_FALCON_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_KEYSLOT_TZ 0x00044100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_TZ_EN 31:0 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_TZ_EN_INIT 0x0000ffff /* RWI-V */ #define NV_CNVDEC_SA_KEYSLOT_FALCON2 0x00044200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_FALCON2_EN 31:0 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_FALCON2_EN_INIT 0x0000ffff /* RWI-V */ #define NV_CNVDEC_SA_KEYSLOT_OTF 0x00044300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_OTF_EN 31:0 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_OTF_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_KEYSLOT_SEL 0x00044400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_SEL_V 4:0 /* RWXUF */ #define NV_CNVDEC_SA_KEYSLOT_PUSH 0x00044500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_PUSH_EN 0:0 /* RWXUF */ #define NV_CNVDEC_SA_KEYSLOT_PUSH_MODE 1:1 /* RWXUF */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW 0x00044600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW_RD_DIS 15:0 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW_RD_DIS_INIT 0x0000ffff /* RWI-V */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW_WR_DIS 31:16 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW_WR_DIS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VPR_ALL_OTF_GOTO_VPR 0x00044700 /* RW-4R */ #define NV_CNVDEC_VPR_ALL_OTF_GOTO_VPR_EN 0:0 /* RWXUF */ #define NV_CNVDEC_VPR_TZ_VPR_WR 0x00044800 /* RW-4R */ #define NV_CNVDEC_VPR_TZ_VPR_WR_EN 0:0 /* RWXUF */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW2 0x00044900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW2_RD_DIS 15:0 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW2_RD_DIS_INIT 0x0000ffff /* RWI-V */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW2_WR_DIS 31:16 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_GLOBAL_RW2_WR_DIS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_KEYSLOT_LOCK 0x00044a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_LOCK_EN 0:0 /* RWIVF */ #define NV_CNVDEC_SA_KEYSLOT_LOCK_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SA_KEYSLOT_KEY200 0x00044c00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY200_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY201 0x00044d00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY201_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY202 0x00044e00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY202_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY203 0x00044f00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY203_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY210 0x00045000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY210_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY211 0x00045100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY211_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY212 0x00045200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY212_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY213 0x00045300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY213_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY220 0x00045400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY220_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY221 0x00045500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY221_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY222 0x00045600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY222_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY223 0x00045700 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY223_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY230 0x00045800 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY230_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY231 0x00045900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY231_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY232 0x00045a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY232_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY233 0x00045b00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY233_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY240 0x00045c00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY240_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY241 0x00045d00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY241_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY242 0x00045e00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY242_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY243 0x00045f00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY243_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY250 0x00046000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY250_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY251 0x00046100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY251_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY252 0x00046200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY252_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY253 0x00046300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY253_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY260 0x00046400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY260_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY261 0x00046500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY261_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY262 0x00046600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY262_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY263 0x00046700 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY263_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY270 0x00046800 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY270_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY271 0x00046900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY271_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY272 0x00046a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY272_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY273 0x00046b00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY273_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY300 0x00046c00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY300_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY301 0x00046d00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY301_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY302 0x00046e00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY302_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY303 0x00046f00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY303_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY310 0x00047000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY310_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY311 0x00047100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY311_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY312 0x00047200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY312_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY313 0x00047300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY313_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY320 0x00047400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY320_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY321 0x00047500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY321_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY322 0x00047600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY322_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY323 0x00047700 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY323_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY330 0x00047800 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY330_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY331 0x00047900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY331_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY332 0x00047a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY332_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY333 0x00047b00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY333_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY340 0x00047c00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY340_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY341 0x00047d00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY341_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY342 0x00047e00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY342_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY343 0x00047f00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY343_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY350 0x00048000 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY350_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY351 0x00048100 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY351_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY352 0x00048200 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY352_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY353 0x00048300 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY353_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY360 0x00048400 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY360_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY361 0x00048500 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY361_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY362 0x00048600 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY362_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY363 0x00048700 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY363_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY370 0x00048800 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY370_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY371 0x00048900 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY371_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY372 0x00048a00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY372_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_SA_KEYSLOT_KEY373 0x00048b00 /* RW-4R */ #define NV_CNVDEC_SA_KEYSLOT_KEY373_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK 0x00019c00 /* RWI4R */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG(i) (0x00018000+(i)*256) /* RW-4A */ #define NV_CNVDEC_FBIF_TRANSCFG__SIZE_1 8 /* */ #define NV_CNVDEC_FBIF_TRANSCFG__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_TARGET_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_MEM_TYPE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_WR_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_RD_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_WACHK0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_WACHK0_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_TRANSCFG_WACHK0_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_WACHK1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_WACHK1_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_TRANSCFG_WACHK1_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_RACHK0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_RACHK0_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_TRANSCFG_RACHK0_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_RACHK1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_RACHK1_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_TRANSCFG_RACHK1_DISABLE 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_TRANSCFG_ENGINE_ID_FLAG 16:16 /* RWIVF */ #define NV_CNVDEC_FBIF_TRANSCFG_ENGINE_ID_FLAG_BAR2_FN0 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_TRANSCFG_ENGINE_ID_FLAG_OWN 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_INSTBLK 0x00018800 /* R--4R */ #define NV_CNVDEC_FBIF_INSTBLK_PTR 27:0 /* R--VF */ #define NV_CNVDEC_FBIF_INSTBLK_TARGET 29:28 /* R--VF */ #define NV_CNVDEC_FBIF_INSTBLK_TARGET_LOCAL_FB 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_BIND_STATUS 0x00018a00 /* R--4R */ #define NV_CNVDEC_FBIF_BIND_STATUS_STATUS 1:0 /* R-IVF */ #define NV_CNVDEC_FBIF_BIND_STATUS_STATUS_NOT_BIND 0x00000000 /* R-I-V */ #define NV_CNVDEC_FBIF_BIND_STATUS_STATUS_BOUND 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_BIND_STATUS_GFID 9:4 /* R--VF */ #define NV_CNVDEC_FBIF_BIND_STATUS_GFID_INIT 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_BIND_STATUS_ENGINE_ID 23:16 /* R--VF */ #define NV_CNVDEC_FBIF_CTL 0x00018900 /* RW-4R */ #define NV_CNVDEC_FBIF_CTL_FLUSH 0:0 /* RW-VF */ #define NV_CNVDEC_FBIF_CTL_FLUSH_SET 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_FLUSH_CLEAR 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */ #define NV_CNVDEC_FBIF_CTL_INVAL_CONTEXT_SET 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */ #define NV_CNVDEC_FBIF_CTL_CLR_BWCOUNT_SET 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_ENABLE 4:4 /* RWIVF */ #define NV_CNVDEC_FBIF_CTL_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_CTL_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */ #define NV_CNVDEC_FBIF_CTL_CLR_IDLEWDERR_SET 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_RESET 6:6 /* RW-VF */ #define NV_CNVDEC_FBIF_CTL_RESET_SET 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_RESET_CLEAR 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */ #define NV_CNVDEC_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_IDLE 8:8 /* R--VF */ #define NV_CNVDEC_FBIF_CTL_IDLE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_CTL_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */ #define NV_CNVDEC_FBIF_CTL_IDLEWDERR_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_CTL_IDLEWDERR_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_CTL_SRTOUT 10:10 /* R--VF */ #define NV_CNVDEC_FBIF_CTL_SRTOUT_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_CTL_SRTOUT_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */ #define NV_CNVDEC_FBIF_CTL_CLR_SRTOUT_SET 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_CLR_SRTOUT_CLEAR 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */ #define NV_CNVDEC_FBIF_CTL_SRTOVAL_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_THROTTLE 0x00018b00 /* RW-4R */ #define NV_CNVDEC_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */ #define NV_CNVDEC_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x00000064 /* RWI-V */ #define NV_CNVDEC_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */ #define NV_CNVDEC_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */ #define NV_CNVDEC_FBIF_THROTTLE_LEAK_SIZE_16B 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_THROTTLE_LEAK_SIZE_32B 0x00000001 /* RW--V */ #define NV_CNVDEC_FBIF_THROTTLE_LEAK_SIZE_64B 0x00000002 /* RWI-V */ #define NV_CNVDEC_FBIF_THROTTLE_LEAK_SIZE_128B 0x00000003 /* RW--V */ #define NV_CNVDEC_FBIF_REGIONCFG 0x00019b00 /* RW-4R */ #define NV_CNVDEC_FBIF_REGIONCFG__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_REGIONCFG_T0 3:0 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_T0_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_T1 7:4 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_T1_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_T2 11:8 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_T2_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_T3 15:12 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_T3_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_T4 19:16 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_T4_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_T5 23:20 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_T5_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_T6 27:24 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_T6_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_REGIONCFG_T7 31:28 /* RWIVF */ #define NV_CNVDEC_FBIF_REGIONCFG_T7_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_FBIF_CG1 0x00019d00 /* RW-4R */ #define NV_CNVDEC_FBIF_CG1_SLCG 3:0 /* */ #define NV_CNVDEC_FBIF_CG1_SLCG_ENABLED 0 /* */ #define NV_CNVDEC_FBIF_CG1_SLCG_DISABLED 0xF /* */ #define NV_CNVDEC_FBIF_CG1_SLCG__PROD 0x0 /* */ #define NV_CNVDEC_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */ #define NV_CNVDEC_FBIF_CG1_SLCG_MSD0_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CG1_SLCG_MSD0_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */ #define NV_CNVDEC_FBIF_CG1_SLCG_MSD1_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CG1_SLCG_MSD1_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */ #define NV_CNVDEC_FBIF_CG1_SLCG_FB0_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CG1_SLCG_FB0_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */ #define NV_CNVDEC_FBIF_CG1_SLCG_FB1_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_FBIF_CG1_SLCG_FB1_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_FBIF_ACHK_BLK(i) (0x00018c00+(i)*512) /* RW-4A */ #define NV_CNVDEC_FBIF_ACHK_BLK__SIZE_1 2 /* */ #define NV_CNVDEC_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */ #define NV_CNVDEC_FBIF_ACHK_CTL(i) (0x00018d00+(i)*512) /* RW-4A */ #define NV_CNVDEC_FBIF_ACHK_CTL__SIZE_1 2 /* */ #define NV_CNVDEC_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */ #define NV_CNVDEC_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */ #define NV_CNVDEC_FBIF_ACHK_CTL_TYPE_INSIDE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */ #define NV_CNVDEC_FBIF_ACHK_CTL_STATE_DISABLE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_ACHK_CTL_STATE_ENABLE 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */ #define NV_CNVDEC_FBIF_DBG_STAT0 0x00019000 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_STAT0__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE 3:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_IDLE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_CHECK 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_ALLOC 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_ISSUE 0x00000003 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_WDAT 0x00000004 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_FLT_FLUSH 0x00000005 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_HALT 0x00000006 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_INST 0x00000007 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_INST_ACK 0x00000008 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_OBJ 0x00000009 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DSP_STATE_FLUSH 0x0000000a /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_INST_VLD 4:4 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_INST_BOUND 5:5 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_RICF_HAS_DATA 6:6 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_ARQ_HAS_DATA 7:7 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_MRQ_HAS_DATA 8:8 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_FAULT_OR_HALT 9:9 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_ORQ_NOT_FULL 10:10 /* R-IUF */ #define NV_CNVDEC_FBIF_DBG_STAT0_ORQ_NOT_FULL_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_FBIF_DBG_STAT0_ORQ_NOT_FULL_FLASE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_FLUSH_OUTSTANDING 11:11 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_DISPATCH_IDLE 12:12 /* R-IUF */ #define NV_CNVDEC_FBIF_DBG_STAT0_DISPATCH_IDLE_TRUE 0x00000001 /* R-I-V */ #define NV_CNVDEC_FBIF_DBG_STAT0_DISPATCH_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_MWF_FSM_STATE 17:16 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_MWF_FSM_STATE_IDLE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_MWF_FSM_STATE_COMMIT 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_MWF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT0_MWF_HAS_DATA 18:18 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_MWF_COMMIT_COUNT 24:19 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_STALL_RQQ_FULL 25:25 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_STALL_WDF_FULL 26:26 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_STALL_FB_BUSY 27:27 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_STALL_ORQ_FULL 28:28 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_STALL_RDM_ALLOC 29:29 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_STALL_RDM_PORTQ 30:30 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT0_STALL_RDM_CLIENT 31:31 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1 0x00019100 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_STAT1__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_STAT1_FLT_STATE 1:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_FLT_FAULTED 2:2 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_FLT_BUSY 3:3 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_ACKF_HAS_DATA 4:4 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_ORQ_HAS_DATA 5:5 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_ALL_READS_DONE 6:6 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_FBR_IDLE 8:8 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_FBR_FAULTED 9:9 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_FBR_FB_BUSY 10:10 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_FBR_PKT2FB_VLD 11:11 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_FBR_RCV_DATA_VALID 12:12 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_FBR_RCV_DATA_TYPE 15:14 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_WDF_FSM_STATE 17:16 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_WDF_FSM_STATE_IDLE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT1_WDF_FSM_STATE_COMMIT 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT1_WDF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT1_WDF_HAS_DATA 18:18 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_WDF_COMMIT_COUNT 23:19 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_RDM_STATE 25:24 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_RDM_STATE_IDLE 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT1_RDM_STATE_WAITBUF 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT1_RDM_STATE_SAVEBUF 0x00000002 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT1_RDM_ANY_READY 26:26 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_RDM_DAQ_HAS_DATA 27:27 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_RDM_DEALLOC_COUNT 30:28 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT1_RDATA_WAIT 31:31 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT2 0x00019200 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_STAT2__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_STAT2_FAULTED_PORTID 5:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT2_FAULTED_SUBID 12:6 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT2_FAULTED_SRCQ 13:13 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_STAT2_FAULTED_SRCQ_ARQ 0x00000001 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT2_FAULTED_SRCQ_MRQ 0x00000000 /* R---V */ #define NV_CNVDEC_FBIF_DBG_STAT2_FAULTED_VLD 14:14 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_RDCOUNT_LO 0x00019400 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_RDCOUNT_LO_DATA 31:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_RDCOUNT_HI 0x00019500 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_RDCOUNT_HI_DATA 31:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_WRCOUNT_LO 0x00019600 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_WRCOUNT_LO_DATA 31:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_WRCOUNT_HI 0x00019700 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_WRCOUNT_HI_DATA 31:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_R32COUNT 0x00019800 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_R32COUNT__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_R32COUNT_DATA 31:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_R64COUNT 0x00019900 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_R64COUNT__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_R64COUNT_DATA 31:0 /* R--UF */ #define NV_CNVDEC_FBIF_DBG_R128COUNT 0x00019a00 /* R--4R */ #define NV_CNVDEC_FBIF_DBG_R128COUNT__PRIV_LEVEL_MASK 0x00019c00 /* */ #define NV_CNVDEC_FBIF_DBG_R128COUNT_DATA 31:0 /* R--UF */ #define NV_CNVDEC_FBIF_BW_ALLOC 0x00019300 /* RW-4R */ #define NV_CNVDEC_FBIF_BW_ALLOC_VAL 31:0 /* */ #define NV_CNVDEC_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */ #define NV_CNVDEC_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */ #define NV_CNVDEC_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */ #define NV_CNVDEC_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */ #define NV_CNVDEC_SCP_CTL0 0x00020000 /* RW-4R */ #define NV_CNVDEC_SCP_CTL0_CTL_EN 20:20 /* RWIVF */ #define NV_CNVDEC_SCP_CTL0_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CTL0_CTL_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CTL0_SEQ_EN 16:16 /* RWIVF */ #define NV_CNVDEC_SCP_CTL0_SEQ_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CTL0_SEQ_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CTL0_SF_CMD_IFACE_EN 14:14 /* RWIVF */ #define NV_CNVDEC_SCP_CTL0_SF_CMD_IFACE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CTL0_SF_CMD_IFACE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CTL0_SF_PUSH_IFACE_EN 12:12 /* RWIVF */ #define NV_CNVDEC_SCP_CTL0_SF_PUSH_IFACE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CTL0_SF_PUSH_IFACE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CTL0_SF_FETCH_IFACE_EN 10:10 /* RWIVF */ #define NV_CNVDEC_SCP_CTL0_SF_FETCH_IFACE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CTL0_SF_FETCH_IFACE_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CTL1 0x00020100 /* RW-4R */ #define NV_CNVDEC_SCP_CTL1_SF_PUSH_BYPASS 24:24 /* RWIVF */ #define NV_CNVDEC_SCP_CTL1_SF_PUSH_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL1_SF_PUSH_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL1_SF_FETCH_BYPASS 20:20 /* RWIVF */ #define NV_CNVDEC_SCP_CTL1_SF_FETCH_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL1_SF_FETCH_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL1_SF_FETCH_AS_ZERO 16:16 /* RWIVF */ #define NV_CNVDEC_SCP_CTL1_SF_FETCH_AS_ZERO_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL1_SF_FETCH_AS_ZERO_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL1_RNG_EN 12:12 /* RWIVF */ #define NV_CNVDEC_SCP_CTL1_RNG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL1_RNG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL1_RNG_FAKE_MODE 11:11 /* RWIVF */ #define NV_CNVDEC_SCP_CTL1_RNG_FAKE_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL1_RNG_FAKE_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL1_PIPE_RESET 8:8 /* RWIVF */ #define NV_CNVDEC_SCP_CTL1_PIPE_RESET_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL1_PIPE_RESET_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL1_PIPE_RESET_TASK 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_CTL1_SEQ_CLEAR 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_CTL1_SEQ_CLEAR_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL1_SEQ_CLEAR_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL1_SEQ_CLEAR_TASK 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_CTL_STAT 0x00020200 /* R--4R */ #define NV_CNVDEC_SCP_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */ #define NV_CNVDEC_SCP_CTL_STAT_DEBUG_MODE_DISABLED 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_CTL_STAT_AES_SCC_DIS 2:2 /* R--VF */ #define NV_CNVDEC_SCP_CTL_STAT_AES_SCC_DIS_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_STAT_AES_SCC_DIS_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_CTL_STAT_HSMODE 1:1 /* R--VF */ #define NV_CNVDEC_SCP_CTL_STAT_HSMODE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_STAT_HSMODE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_CTL_STAT_SBOOT 0:0 /* R--VF */ #define NV_CNVDEC_SCP_CTL_STAT_SBOOT_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_STAT_SBOOT_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_CTL_CFG 0x00020300 /* RW-4R */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT 1:1 /* R-IVF */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_PRE 2:2 /* R-IVF */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_PRE_ENABLED 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_PRE_DISABLED 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP 4:4 /* RWIVF */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_PRE 6:6 /* R-IVF */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_ENABLED 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_DISABLED 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CFG0 0x00020400 /* RW-4R */ #define NV_CNVDEC_SCP_CFG0_STALL_TIMEOUT 31:16 /* RWIVF */ #define NV_CNVDEC_SCP_CFG0_STALL_TIMEOUT_INIT 0x0000ffff /* RWI-V */ #define NV_CNVDEC_SCP_CFG0_CARRY_CHAIN 13:12 /* RWIVF */ #define NV_CNVDEC_SCP_CFG0_CARRY_CHAIN_32 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CFG0_CARRY_CHAIN_64 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CFG0_CARRY_CHAIN_96 0x00000002 /* RW--V */ #define NV_CNVDEC_SCP_CFG0_CARRY_CHAIN_128 0x00000003 /* RW--V */ #define NV_CNVDEC_SCP_CFG0_CMD_FLUSH 8:8 /* RWIVF */ #define NV_CNVDEC_SCP_CFG0_CMD_FLUSH_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CFG0_CMD_FLUSH_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CFG0_AES_ENDIAN 4:4 /* RWIVF */ #define NV_CNVDEC_SCP_CFG0_AES_ENDIAN_BIG 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CFG0_AES_ENDIAN_LITTLE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CFG0_PUSH_ENDIAN 3:3 /* RWIVF */ #define NV_CNVDEC_SCP_CFG0_PUSH_ENDIAN_BIG 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CFG0_PUSH_ENDIAN_LITTLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CFG0_FETCH_ENDIAN 2:2 /* RWIVF */ #define NV_CNVDEC_SCP_CFG0_FETCH_ENDIAN_BIG 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CFG0_FETCH_ENDIAN_LITTLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CFG0_CMAC_ENDIAN 1:1 /* RWIVF */ #define NV_CNVDEC_SCP_CFG0_CMAC_ENDIAN_BIG 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CFG0_CMAC_ENDIAN_LITTLE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CFG0_ADD_ENDIAN 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_CFG0_ADD_ENDIAN_BIG 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_CFG0_ADD_ENDIAN_LITTLE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_CTL_SCP 0x00020500 /* RW-4R */ #define NV_CNVDEC_SCP_CTL_SCP_TOGGLE_MASTER 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_CTL_SCP_TOGGLE_MASTER_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL_SCP_TOGGLE_MASTER_PENDING 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL_SCP_CURRENT_MASTER 1:1 /* R-IVF */ #define NV_CNVDEC_SCP_CTL_SCP_CURRENT_MASTER_FALCON 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL_SCP_CURRENT_MASTER_EXT 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_PKEY 0x00020600 /* RW-4R */ #define NV_CNVDEC_SCP_CTL_PKEY_REQUEST_RELOAD 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_CTL_PKEY_REQUEST_RELOAD_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL_PKEY_REQUEST_RELOAD_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_PKEY_REQUEST_RELOAD_TASK 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_CTL_PKEY_LOADED 1:1 /* R-IVF */ #define NV_CNVDEC_SCP_CTL_PKEY_LOADED_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL_PKEY_LOADED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_DEBUG 0x00020700 /* RW-4R */ #define NV_CNVDEC_SCP_CTL_DEBUG_LOCKDOWN_CYA 4:4 /* RWIVF */ #define NV_CNVDEC_SCP_CTL_DEBUG_LOCKDOWN_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL_DEBUG_LOCKDOWN_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA 8:8 /* RWIVF */ #define NV_CNVDEC_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0 0x00020800 /* RW-4R */ #define NV_CNVDEC_SCP_DEBUG0_PUSH_SECURE 31:31 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_PUSH_SECURE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_PUSH_SECURE_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_PUSH_VALID 30:30 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_PUSH_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_PUSH_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_PUSH_CNT 26:25 /* R-IVF */ #define NV_CNVDEC_SCP_DEBUG0_PUSH_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_DEBUG0_FETCH_SECURE 24:24 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_FETCH_SECURE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_FETCH_SECURE_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_FETCH_VALID 23:23 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_FETCH_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_FETCH_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_FETCH_CNT 22:19 /* R-IVF */ #define NV_CNVDEC_SCP_DEBUG0_FETCH_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_SECURE 18:18 /* R-IVF */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_SECURE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_SECURE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_VALID 17:17 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_PC 16:13 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_PC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_DEPTH 12:8 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_SEQ_DEPTH_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_TARGET 6:5 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_TARGET_NONE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_TARGET_PUSH 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_TARGET_FETCH 0x00000002 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_TARGET_SEQ 0x00000003 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_INDEX_AUTOINCREMENT 4:4 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_INDEX_AUTOINCREMENT_TRUE 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG0_INDEX_AUTOINCREMENT_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG0_INDEX 3:0 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG0_INDEX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG1 0x00020900 /* RW-4R */ #define NV_CNVDEC_SCP_DEBUG1_DATA 31:0 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG2 0x00020a00 /* R--4R */ #define NV_CNVDEC_SCP_DEBUG2_KU 15:12 /* R-IVF */ #define NV_CNVDEC_SCP_DEBUG2_KU_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_DEBUG2_SEQ_CNT 9:4 /* R-IVF */ #define NV_CNVDEC_SCP_DEBUG2_SEQ_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_DEBUG2_SEQ_STATE 1:0 /* R-IVF */ #define NV_CNVDEC_SCP_DEBUG2_SEQ_STATE_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_DEBUG2_SEQ_STATE_IDLE 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_DEBUG2_SEQ_STATE_LOAD 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_DEBUG2_SEQ_STATE_LOOP 0x00000002 /* R---V */ #define NV_CNVDEC_SCP_DEBUG_CMD 0x00020c00 /* RW-4R */ #define NV_CNVDEC_SCP_DEBUG_CMD_SECURE 31:31 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG_CMD_SECURE_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG_CMD_SECURE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG_CMD_VALID 28:28 /* RWIVF */ #define NV_CNVDEC_SCP_DEBUG_CMD_VALID_FALSE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_DEBUG_CMD_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_DEBUG_CMD_OP 24:20 /* RWXVF */ #define NV_CNVDEC_SCP_DEBUG_CMD_RX_IMM 13:8 /* RWXVF */ #define NV_CNVDEC_SCP_DEBUG_CMD_RY 3:0 /* RWXVF */ #define NV_CNVDEC_SCP_ACL_FETCH 0x00021000 /* R--4R */ #define NV_CNVDEC_SCP_ACL_FETCH_SECURE 23:16 /* R--VF */ #define NV_CNVDEC_SCP_ACL_FETCH_INSECURE 7:0 /* R--VF */ #define NV_CNVDEC_SCP_ACL_KEYABLE 0x00021100 /* R--4R */ #define NV_CNVDEC_SCP_ACL_KEYABLE_SECURE 23:16 /* R--VF */ #define NV_CNVDEC_SCP_ACL_KEYABLE_INSECURE 7:0 /* R--VF */ #define NV_CNVDEC_SCP_ACL_WRITE 0x00021200 /* R--4R */ #define NV_CNVDEC_SCP_ACL_WRITE_INSECURE 7:0 /* R--VF */ #define NV_CNVDEC_SCP_STATUS 0x00021400 /* R--4R */ #define NV_CNVDEC_SCP_STATUS_SCP_ACTIVE 0:0 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_SCP_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_SCP_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_CMD_ACTIVE 2:2 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_CMD_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_CMD_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_PUSH_ACTIVE 4:4 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_PUSH_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_PUSH_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_SEQ_ACTIVE 6:6 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_SEQ_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_SEQ_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_CTL_ACTIVE 8:8 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_CTL_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_CTL_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_FETCH_ACTIVE 10:10 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_FETCH_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_FETCH_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_AES_ACTIVE 14:14 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_AES_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_AES_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_RNG_ACTIVE 16:16 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_RNG_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_RNG_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_PKEY_LOADING_ACTIVE 18:18 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_PKEY_LOADING_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_PKEY_LOADING_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_SFK_LOADING_ACTIVE 20:20 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_SFK_LOADING_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_SFK_LOADING_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_SCC_TRNG_ACTIVE 26:26 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_SCC_TRNG_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_SCC_TRNG_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STATUS_SCC_PRNG_ACTIVE 28:28 /* R-IVF */ #define NV_CNVDEC_SCP_STATUS_SCC_PRNG_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STATUS_SCC_PRNG_ACTIVE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT0 0x00021500 /* R--4R */ #define NV_CNVDEC_SCP_STAT0_SF_CMD_VLD 14:14 /* R-IVF */ #define NV_CNVDEC_SCP_STAT0_SF_CMD_VLD_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT0_SF_CMD_VLD_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT0_SF_CMD_SECURE 12:12 /* R-XVF */ #define NV_CNVDEC_SCP_STAT0_SF_CMD_SECURE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT0_SF_CMD_SECURE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_STAT0_SF_PUSH_VLD 10:10 /* R-IVF */ #define NV_CNVDEC_SCP_STAT0_SF_PUSH_VLD_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT0_SF_PUSH_VLD_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT0_SF_PUSH_SECURE 8:8 /* R-XVF */ #define NV_CNVDEC_SCP_STAT0_SF_PUSH_SECURE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT0_SF_PUSH_SECURE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_STAT0_SF_FETCH_RDY 6:6 /* R-IVF */ #define NV_CNVDEC_SCP_STAT0_SF_FETCH_RDY_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT0_SF_FETCH_RDY_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT0_SF_FETCH_SECURE 4:4 /* R-XVF */ #define NV_CNVDEC_SCP_STAT0_SF_FETCH_SECURE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT0_SF_FETCH_SECURE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_STAT0_CMP 1:0 /* R-IVF */ #define NV_CNVDEC_SCP_STAT0_CMP_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT0_CMP_PASS 0x00000003 /* R---V */ #define NV_CNVDEC_SCP_STAT0_CMP_FAIL 0x00000002 /* R---V */ #define NV_CNVDEC_SCP_STAT1 0x00021600 /* R--4R */ #define NV_CNVDEC_SCP_STAT1_SEQ_OP 4:0 /* R-XVF */ #define NV_CNVDEC_SCP_STAT1_SF_OP 9:5 /* R-XVF */ #define NV_CNVDEC_SCP_STAT1_DISPATCH_OP 14:10 /* R-XVF */ #define NV_CNVDEC_SCP_STAT1_AES_OP 17:15 /* R-XVF */ #define NV_CNVDEC_SCP_STAT1_AES_OP_ENCRYPT 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_STAT1_AES_OP_DECRYPT 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT1_AES_OP_RKEY 0x00000002 /* R---V */ #define NV_CNVDEC_SCP_STAT1_AES_OP_RKEYI 0x00000003 /* R---V */ #define NV_CNVDEC_SCP_STAT1_HAZARD_STALL 24:24 /* R-IVF */ #define NV_CNVDEC_SCP_STAT1_HAZARD_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT1_HAZARD_STALL_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT1_PUSH_STALL 25:25 /* R-IVF */ #define NV_CNVDEC_SCP_STAT1_PUSH_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT1_PUSH_STALL_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT1_FETCH_STALL 26:26 /* R-IVF */ #define NV_CNVDEC_SCP_STAT1_FETCH_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT1_FETCH_STALL_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT1_RNG_STALL 27:27 /* R-IVF */ #define NV_CNVDEC_SCP_STAT1_RNG_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT1_RNG_STALL_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT1_WB_STALL 28:28 /* R-IVF */ #define NV_CNVDEC_SCP_STAT1_WB_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT1_WB_STALL_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT1_AES_STALL 29:29 /* R-IVF */ #define NV_CNVDEC_SCP_STAT1_AES_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT1_AES_STALL_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_STAT1_SECRET_STALL 30:30 /* R-IVF */ #define NV_CNVDEC_SCP_STAT1_SECRET_STALL_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_STAT1_SECRET_STALL_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_SECRET63_CTL 0x00021800 /* RW-4R */ #define NV_CNVDEC_SCP_SECRET63_CTL_SEL 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_SECRET63_CTL_SEL_PKEY 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_SECRET63_CTL_SEL_KMEM 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_RNG_STAT0 0x00021c00 /* RW-4R */ #define NV_CNVDEC_SCP_RNG_STAT0_RAW_RAND_READY 0:0 /* R-IVF */ #define NV_CNVDEC_SCP_RNG_STAT0_RAW_RAND_READY_READY 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_RNG_STAT0_RAW_RAND_READY_PROCESSING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_RNG_STAT0_RAW_RAND_READY_RANDBUF_NOTFULL 0x00000001 /* R-I-V */ #define NV_CNVDEC_SCP_RNG_STAT0_AUTOCAL_TAP_A 7:4 /* R-IVF */ #define NV_CNVDEC_SCP_RNG_STAT0_AUTOCAL_TAP_A_INIT 0x0000000f /* R-I-V */ #define NV_CNVDEC_SCP_RNG_STAT0_AUTOCAL_TAP_B 11:8 /* R-IVF */ #define NV_CNVDEC_SCP_RNG_STAT0_AUTOCAL_TAP_B_INIT 0x0000000f /* R-I-V */ #define NV_CNVDEC_SCP_RNG_STAT0_LFSR_STAT_A 12:12 /* R-IVF */ #define NV_CNVDEC_SCP_RNG_STAT0_LFSR_STAT_A_LEGAL 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_RNG_STAT0_LFSR_STAT_A_ILLEGAL 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_RNG_STAT0_LFSR_STAT_B 13:13 /* R-IVF */ #define NV_CNVDEC_SCP_RNG_STAT0_LFSR_STAT_B_LEGAL 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_RNG_STAT0_LFSR_STAT_B_ILLEGAL 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_A 16:16 /* RWIVF */ #define NV_CNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_A_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_A_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_A_CLEAR 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_B 20:20 /* RWIVF */ #define NV_CNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_B_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_B_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_RNG_STAT0_RCTR_SATURATED_B_CLEAR 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_RNG_STAT1 0x00021d00 /* R--4R */ #define NV_CNVDEC_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A 15:0 /* R-IUF */ #define NV_CNVDEC_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B 31:16 /* R-IUF */ #define NV_CNVDEC_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_INTR 0x00022000 /* RW-4R */ #define NV_CNVDEC_SCP_INTR_RAND_READY 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_RAND_READY_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_INTR_RAND_READY_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_INTR_RAND_READY_RESET 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_INTR_ACL_VIO 8:8 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_ACL_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_INTR_ACL_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_INTR_ACL_VIO_RESET 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_INTR_SECURITY_VIO 12:12 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_SECURITY_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_INTR_SECURITY_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_INTR_SECURITY_VIO_RESET 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_INTR_CMD_ERROR 16:16 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_CMD_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_INTR_CMD_ERROR_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_INTR_CMD_ERROR_RESET 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_INTR_STEP 20:20 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_STEP_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_INTR_STEP_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_INTR_STEP_RESET 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_INTR_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_RNDHOLDOFF_REQUESTED_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_INTR_RNDHOLDOFF_REQUESTED_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_INTR_RNDHOLDOFF_REQUESTED_RESET 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_INTR_STALL_TIMEOUT 28:28 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_STALL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_INTR_STALL_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_INTR_STALL_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_INTR_EN 0x00022100 /* RW-4R */ #define NV_CNVDEC_SCP_INTR_EN_RAND_READY 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_EN_RAND_READY_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_INTR_EN_RAND_READY_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_INTR_EN_ACL_VIO 8:8 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_EN_ACL_VIO_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_INTR_EN_ACL_VIO_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_INTR_EN_SECURITY_VIO 12:12 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_EN_SECURITY_VIO_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_INTR_EN_SECURITY_VIO_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_INTR_EN_CMD_ERROR 16:16 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_EN_CMD_ERROR_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_INTR_EN_CMD_ERROR_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_INTR_EN_STEP 20:20 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_EN_STEP_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_INTR_EN_STEP_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_INTR_EN_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_INTR_EN_STALL_TIMEOUT 28:28 /* RWIVF */ #define NV_CNVDEC_SCP_INTR_EN_STALL_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_INTR_EN_STALL_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_ACL_VIO 0x00022400 /* RW-4R */ #define NV_CNVDEC_SCP_ACL_VIO_VIOLATION 31:31 /* R-IVF */ #define NV_CNVDEC_SCP_ACL_VIO_VIOLATION_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_ACL_VIO_VIOLATION_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_ACL_VIO_CHMOD_RELAX_VIO 8:8 /* RWIVF */ #define NV_CNVDEC_SCP_ACL_VIO_CHMOD_RELAX_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_ACL_VIO_CHMOD_RELAX_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_ACL_VIO_CHMOD_RELAX_VIO_CLEAR 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_ACL_VIO_FETCH_VIO 4:4 /* RWIVF */ #define NV_CNVDEC_SCP_ACL_VIO_FETCH_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_ACL_VIO_FETCH_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_ACL_VIO_FETCH_VIO_CLEAR 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_ACL_VIO_WR_VIO 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_ACL_VIO_WR_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_ACL_VIO_WR_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_ACL_VIO_WR_VIO_CLEAR 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_SECURITY_VIO 0x00022500 /* R--4R */ #define NV_CNVDEC_SCP_SECURITY_VIO_VIOLATION 31:31 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_VIOLATION_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_VIOLATION_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_VIO_SC 26:25 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_VIO 24:24 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC 22:21 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO 20:20 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_SECURITY_VIO_FETCH_VIO_SC 18:17 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_FETCH_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_FETCH_VIO 16:16 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_FETCH_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_FETCH_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC 6:5 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO 4:4 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOAD_TRACE_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC 2:1 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO 0:0 /* R-IVF */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_SECURITY_VIO_LOOP_TRACE_VIO_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR 0x00022600 /* RW-4R */ #define NV_CNVDEC_SCP_CMD_ERROR_UNDEFINED 0:0 /* RWIVF */ #define NV_CNVDEC_SCP_CMD_ERROR_UNDEFINED_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CMD_ERROR_UNDEFINED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR_UNDEFINED_CLEAR 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_EMPTY 4:4 /* RWIVF */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_EMPTY_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_EMPTY_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_EMPTY_CLEAR 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_OVERFLOW 8:8 /* RWIVF */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_OVERFLOW_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_OVERFLOW_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_OVERFLOW_CLEAR 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING 12:12 /* RWIVF */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_CLEAR 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_CMD_ERROR_SIG_INSECURE 16:16 /* RWIVF */ #define NV_CNVDEC_SCP_CMD_ERROR_SIG_INSECURE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CMD_ERROR_SIG_INSECURE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR_SIG_INSECURE_CLEAR 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_CMD_ERROR_SIG_INVALID 20:20 /* RWIVF */ #define NV_CNVDEC_SCP_CMD_ERROR_SIG_INVALID_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CMD_ERROR_SIG_INVALID_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR_SIG_INVALID_CLEAR 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_CMD_ERROR_CHMOD_INSECURE 24:24 /* RWIVF */ #define NV_CNVDEC_SCP_CMD_ERROR_CHMOD_INSECURE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CMD_ERROR_CHMOD_INSECURE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR_CHMOD_INSECURE_CLEAR 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_CMD_ERROR_SECRET_INSECURE 28:28 /* RWIVF */ #define NV_CNVDEC_SCP_CMD_ERROR_SECRET_INSECURE_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CMD_ERROR_SECRET_INSECURE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CMD_ERROR_SECRET_INSECURE_CLEAR 0x00000001 /* -W--C */ #define NV_CNVDEC_SCP_RNDCTL0 0x00024000 /* RW-4R */ #define NV_CNVDEC_SCP_RNDCTL0_HOLDOFF_INIT_LOWER 31:0 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL0_HOLDOFF_INIT_LOWER_INIT 0x01c9c380 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL1 0x00024100 /* RW-4R */ #define NV_CNVDEC_SCP_RNDCTL1_HOLDOFF_INIT_UPPER 15:0 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL1_HOLDOFF_INIT_UPPER_ZERO 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL1_HOLDOFF_INTRA_MASK 31:16 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL1_HOLDOFF_INTRA_MASK_INIT 0x0000ffff /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL2 0x00024200 /* RW-4R */ #define NV_CNVDEC_SCP_RNDCTL2_COMPRESS_CNT 15:0 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL2_COMPRESS_CNT_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL3 0x00024300 /* RW-4R */ #define NV_CNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A 12:12 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_TRIGGER 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B 16:16 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_TRIGGER 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_RNDCTL4 0x00024400 /* -W-4R */ #define NV_CNVDEC_SCP_RNDCTL4_POLYNOMIAL_A 31:0 /* -WIUF */ #define NV_CNVDEC_SCP_RNDCTL4_POLYNOMIAL_A_INIT 0x80200003 /* -WI-V */ #define NV_CNVDEC_SCP_RNDCTL5 0x00024500 /* -W-4R */ #define NV_CNVDEC_SCP_RNDCTL5_LFSR_INIT_A 31:0 /* -WIUF */ #define NV_CNVDEC_SCP_RNDCTL5_LFSR_INIT_A_INIT 0xdeadbeef /* -WI-V */ #define NV_CNVDEC_SCP_RNDCTL6 0x00024600 /* -W-4R */ #define NV_CNVDEC_SCP_RNDCTL6_POLYNOMIAL_B 31:0 /* -WIUF */ #define NV_CNVDEC_SCP_RNDCTL6_POLYNOMIAL_B_INIT 0x80200003 /* -WI-V */ #define NV_CNVDEC_SCP_RNDCTL7 0x00024700 /* -W-4R */ #define NV_CNVDEC_SCP_RNDCTL7_LFSR_INIT_B 31:0 /* -WIUF */ #define NV_CNVDEC_SCP_RNDCTL7_LFSR_INIT_B_INIT 0xbeefdead /* -WI-V */ #define NV_CNVDEC_SCP_RNDCTL8 0x00024800 /* RW-4R */ #define NV_CNVDEC_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A 15:0 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B 31:16 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL9 0x00024900 /* RW-4R */ #define NV_CNVDEC_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A 15:0 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B 31:16 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL10 0x00024a00 /* RW-4R */ #define NV_CNVDEC_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A 15:0 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A_INIT 0x0000000f /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B 31:16 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B_INIT 0x0000000f /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11 0x00024b00 /* RW-4R */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_ENABLE 0:0 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE 1:1 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_SYNCH_RAND_A 2:2 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_SYNCH_RAND_A_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_SYNCH_RAND_A_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_SYNCH_RAND_A_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_SYNCH_RAND_B 3:3 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_SYNCH_RAND_B_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_SYNCH_RAND_B_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_SYNCH_RAND_B_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A 5:4 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_OSC 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_AUTOCAL 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_LFSR 0x00000002 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_ZERO 0x00000003 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B 7:6 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_OSC 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_AUTOCAL 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_LFSR 0x00000002 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_ZERO 0x00000003 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A 11:8 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A_INIT 0x0000000f /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B 15:12 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B_INIT 0x0000000f /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_MIN_AUTO_TAP 19:16 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_MIN_AUTO_TAP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY 23:20 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY 30:24 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_SAFE_MODE 31:31 /* RWIUF */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_CTL_P2PRX 0x00024c00 /* RW-4R */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_FALLBACK_MODE 0:0 /* R--VF */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_FALSE 0x00000000 /* R---V */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD 2:2 /* RWIVF */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_IDLE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_PENDING 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_TASK 0x00000001 /* -W--T */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_LOADED 3:3 /* R-IVF */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_LOADED_FALSE 0x00000000 /* R-I-V */ #define NV_CNVDEC_SCP_CTL_P2PRX_SFK_LOADED_TRUE 0x00000001 /* R---V */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG0 0x00025000 /* R--4R */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT 15:0 /* R-IVF */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT_INIT 0x00000020 /* R-I-V */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA 31:16 /* R-IVF */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA_INIT 0x0000000f /* R-I-V */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG1 0x00025100 /* R--4R */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX 31:0 /* R-IVF */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX_INIT 0x00000fff /* R-I-V */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG2 0x00025200 /* R--4R */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD 31:0 /* R-IVF */ #define NV_CNVDEC_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD_INIT 0x7fffffff /* R-I-V */ #define NV_CNVDEC_SCP_SCC_DEBUG_STAT0 0x00025300 /* R--4R */ #define NV_CNVDEC_SCP_SCC_DEBUG_STAT0_RSEED_TMOUT_CNT 31:0 /* R--VF */ #define NV_CNVDEC_SCP_SCC_DEBUG_STAT1 0x00025400 /* R--4R */ #define NV_CNVDEC_SCP_SCC_DEBUG_STAT1_RSEED_BIT_CNT 5:0 /* R--VF */ #define NV_CNVDEC_SCP_SCC_DEBUG_STAT1_RSEED_VALID 8:8 /* R--VF */ #define NV_CNVDEC_SCP_SCC_DEBUG_STAT1_RSEED_TMOUT 9:9 /* R--VF */ #define NV_CNVDEC_SCP_PUBKEYC 0x00025800 /* RW-4R */ #define NV_CNVDEC_SCP_PUBKEYC_RSA1_N_OFFS 0x00000000 /* */ #define NV_CNVDEC_SCP_PUBKEYC_RSA1_N_SIZE 0x00000180 /* */ #define NV_CNVDEC_SCP_PUBKEYC_RSA1_E_OFFS 0x00000180 /* */ #define NV_CNVDEC_SCP_PUBKEYC_RSA1_E_SIZE 0x00000020 /* */ #define NV_CNVDEC_SCP_PUBKEYC_ECC1_X_OFFS 0x000001a0 /* */ #define NV_CNVDEC_SCP_PUBKEYC_ECC1_X_SIZE 0x00000020 /* */ #define NV_CNVDEC_SCP_PUBKEYC_ECC1_Y_OFFS 0x000001c0 /* */ #define NV_CNVDEC_SCP_PUBKEYC_ECC1_Y_SIZE 0x00000020 /* */ #define NV_CNVDEC_SCP_PUBKEYC_OFFS 9:2 /* RWIVF */ #define NV_CNVDEC_SCP_PUBKEYC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_PUBKEYC_AINCR 31:31 /* RWIVF */ #define NV_CNVDEC_SCP_PUBKEYC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_PUBKEYC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_PUBKEYC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CNVDEC_SCP_PUBKEYD 0x00025900 /* R--4R */ #define NV_CNVDEC_SCP_PUBKEYD_DATA 31:0 /* R--VF */ #define NV_CNVDEC_SCP_PK_ADDR 0x00025c00 /* RWI4R */ #define NV_CNVDEC_SCP_PK_ADDR_OFFSET 11:0 /* RWIVF */ #define NV_CNVDEC_SCP_PK_ADDR_OFFSET_DEFT 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_PK_ADDR_AINCR 31:31 /* RWIVF */ #define NV_CNVDEC_SCP_PK_ADDR_AINCR_ENABLE 0x00000001 /* RW--V */ #define NV_CNVDEC_SCP_PK_ADDR_AINCR_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_SCP_PK_DATA 0x00025d00 /* R--4R */ #define NV_CNVDEC_SCP_PK_DATA_VAL 31:0 /* R--VF */ #define NV_CNVDEC_GIP_SWREG0 0x00050000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG0_RESET 0:0 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG0_RESET_TRUE 0x00000000 /* RW--V */ #define NV_CNVDEC_GIP_SWREG0_RESET_FALSE 0x00000001 /* RWI-V */ #define NV_CNVDEC_GIP_SWREG1 0x00050100 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG1_DEC_SUBSTREAM_DMA_DONE_INT 22:22 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_SUBSTREAM_DMA_RECFG_E 21:21 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_STRM_PREPARSER_INT 20:20 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_SLICEDONE_INT 19:19 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_TIMEOUT 18:18 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_ERROR_INT 16:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_DMA_DONE_INT 15:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_RDY_INT 12:12 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_STRM_CFG_E 1:1 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG1_DEC_E 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG2 0x00050200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PZ 23:20 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PZ_V 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PE 19:16 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PE_V 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PD 15:12 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PD_V 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PC 11:8 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PC_V 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PB 7:4 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PB_V 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PA 3:0 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG2_RETIME_LAT_PA_V 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_SWREG3 0x00050300 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG3_DEC_MODE 31:27 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG3_DEC_OUT_RS_DIS 16:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG3_DEC_OUT_DIS 15:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG3_FILTERING_DIS 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG3_FILTER_BYPASS 13:13 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG3_WRITE_MVS_E 12:12 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG4 0x00050400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG4_PIC_WIDTH_IN_CBS 31:19 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG4_PIC_HEIGHT_IN_CBS 18:6 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG4_REF_FRAMES 4:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG5 0x00050500 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG5_STRM_START_BIT 31:25 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG5_SCALING_LIST_E 24:24 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG5_CH_QP_OFFSET 23:19 /* RWISF */ #define NV_CNVDEC_GIP_SWREG5_CH_QP_OFFSET2 18:14 /* RWISF */ #define NV_CNVDEC_GIP_SWREG5_SIGN_DATA_HIDE 12:12 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG5_TEMPOR_MVP_E 11:11 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG5_MAX_CU_QPD_DEPTH 10:5 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG5_CU_QPD_E 4:4 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG6 0x00050600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG6_STREAM_LEN 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7 0x00050700 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG7_CABAC_INIT_PRESENT 31:31 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_BLACKWHITE_E 30:30 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_WEIGHT_PRED_E 28:28 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_WEIGHT_BIPR_IDC 27:26 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_FILT_SLICE_BORDER 25:25 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_FILT_TILE_BORDER 24:24 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_ASYM_PRED_E 23:23 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_SAO_E 22:22 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_PCM_FILT_DISABLE 21:21 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_SLICE_CHQP_FLAG 20:20 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_DEPEND_SLICE_E 19:19 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_FILT_OVERRIDE_E 18:18 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_STRONG_SMOOTH_E 17:17 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_FILT_OFFSET_BETA 16:12 /* RWISF */ #define NV_CNVDEC_GIP_SWREG7_FILT_OFFSET_TC 11:7 /* RWISF */ #define NV_CNVDEC_GIP_SWREG7_SLICE_HDR_EXT_E 6:6 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG7_SLICE_HDR_EBITS 5:3 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG8 0x00050800 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG8_CONST_INTRA_E 31:31 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG8_FILT_CTRL_PRES 30:30 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG8_MAX_EIGHTBITS_E 17:17 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG8_IDR_PIC_E 16:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG8_PCM_BITDEPTH_Y 15:12 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG8_PCM_BITDEPTH_C 11:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG8_BITDEPTH_Y 7:4 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG8_BITDEPTH_C 3:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG9 0x00050900 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG9_REFIDX1_ACTIVE 23:19 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG9_REFIDX0_ACTIVE 18:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG9_HDR_SKIP_LENGTH 13:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG10 0x00050a00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG10_START_CODE_E 31:31 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG10_NUM_TILE_COLS 26:20 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG10_NUM_TILE_ROWS 19:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG10_INIT_QP 8:2 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG10_TILE_ENABLE 1:1 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG10_ENTR_CODE_SYNCH_E 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG11 0x00050b00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG11_TRANSFORM_MODE 29:27 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG11_FILT_SHARPNESS 23:21 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG11_FILT_TYPE 19:19 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG11_MCOMP_FILT_TYPE 10:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG11_HIGH_PREC_MV_E 7:7 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG11_COMP_PRED_MODE 5:4 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG11_GREF_SIGN_BIAS 2:2 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG11_AREF_SIGN_BIAS 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12 0x00050c00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG12_REFER_LTERM_E 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12_MIN_CB_SIZE 15:13 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12_MAX_CB_SIZE 12:10 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12_MIN_PCM_SIZE 9:7 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12_MAX_PCM_SIZE 6:4 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12_PCM_E 3:3 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12_TRANSFORM_SKIP_E 2:2 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12_TRANSQ_BYPASS_E 1:1 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG12_REFPICLIST_MOD_E 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13 0x00050d00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG13_MIN_TRB_SIZE 15:13 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_MAX_TRB_SIZE 12:10 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_MAX_INTRA_HIERDEPTH 9:7 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_MAX_INTER_HIERDEPTH 6:4 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_PARALLEL_MERGE 3:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_QP_DELTA_Y_DC 28:23 /* RWISF */ #define NV_CNVDEC_GIP_SWREG13_QP_DELTA_CH_DC 22:17 /* RWISF */ #define NV_CNVDEC_GIP_SWREG13_QP_DELTA_CH_AC 16:11 /* RWISF */ #define NV_CNVDEC_GIP_SWREG13_LAST_SIGN_BIAS 10:10 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_LOSSLESS_E 9:9 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_COMP_PRED_VAR_REF1 8:7 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_COMP_PRED_VAR_REF0 6:5 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_COMP_PRED_FIXED_REF 4:3 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_SEGMENT_TEMP_UPD_E 2:2 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_SEGMENT_UPD_E 1:1 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG13_SEGMENT_E 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14 0x00050e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG14_INIT_RLIST_B2 29:25 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_INIT_RLIST_F2 24:20 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_INIT_RLIST_B1 19:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_INIT_RLIST_F1 14:10 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_INIT_RLIST_B0 9:5 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_INIT_RLIST_F0 4:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_FILT_LEVEL 23:18 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_REFPIC_SEG0 17:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_SKIP_SEG0 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_FILT_LEVEL_SEG0 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG14_QUANT_SEG0 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15 0x00050f00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG15_INIT_RLIST_B5 29:25 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_INIT_RLIST_F5 24:20 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_INIT_RLIST_B4 19:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_INIT_RLIST_F4 14:10 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_INIT_RLIST_B3 9:5 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_INIT_RLIST_F3 4:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_REFPIC_SEG1 17:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_SKIP_SEG1 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_FILT_LEVEL_SEG1 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG15_QUANT_SEG1 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16 0x00051000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG16_INIT_RLIST_B8 29:25 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_INIT_RLIST_F8 24:20 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_INIT_RLIST_B7 19:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_INIT_RLIST_F7 14:10 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_INIT_RLIST_B6 9:5 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_INIT_RLIST_F6 4:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_REFPIC_SEG2 17:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_SKIP_SEG2 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_FILT_LEVEL_SEG2 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG16_QUANT_SEG2 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17 0x00051100 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG17_INIT_RLIST_B11 29:25 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_INIT_RLIST_F11 24:20 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_INIT_RLIST_B10 19:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_INIT_RLIST_F10 14:10 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_INIT_RLIST_B9 9:5 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_INIT_RLIST_F9 4:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_REFPIC_SEG3 17:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_SKIP_SEG3 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_FILT_LEVEL_SEG3 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG17_QUANT_SEG3 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18 0x00051200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG18_INIT_RLIST_B14 29:25 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_INIT_RLIST_F14 24:20 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_INIT_RLIST_B13 19:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_INIT_RLIST_F13 14:10 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_INIT_RLIST_B12 9:5 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_INIT_RLIST_F12 4:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_REFPIC_SEG4 17:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_SKIP_SEG4 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_FILT_LEVEL_SEG4 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG18_QUANT_SEG4 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG19 0x00051300 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG19_INIT_RLIST_B15 9:5 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG19_INIT_RLIST_F15 4:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG19_REFPIC_SEG5 17:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG19_SKIP_SEG5 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG19_FILT_LEVEL_SEG5 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG19_QUANT_SEG5 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG20 0x00051400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG20_PARTIAL_CTB_X 31:31 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG20_PARTIAL_CTB_Y 30:30 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG20_PIC_WIDTH_4X4 27:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG20_PIC_HEIGHT_4X4 11:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG21 0x00051500 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG21_EXTERNAL_REF_MEM_DIS 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG21_SW_SKIP_START_LENGTH 13:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG29 0x00051d00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG29_IS_H264_DUP3 15:15 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_H264_DUP2 14:14 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_H264_DUP1 13:13 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_H264_DUP0 12:12 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_AV1_DUP3 11:11 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_AV1_DUP2 10:10 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_AV1_DUP1 9:9 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_AV1_DUP0 8:8 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_VP9_DUP3 7:7 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_VP9_DUP2 6:6 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_VP9_DUP1 5:5 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_VP9_DUP0 4:4 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_HEVC_DUP3 3:3 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_HEVC_DUP2 2:2 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_HEVC_DUP1 1:1 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG29_IS_HEVC_DUP0 0:0 /* RW-VF */ #define NV_CNVDEC_GIP_SWREG31 0x00051f00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG31_REFPIC_SEG6 17:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG31_SKIP_SEG6 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG31_FILT_LEVEL_SEG6 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG31_QUANT_SEG6 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG32 0x00052000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG32_REFPIC_SEG7 17:15 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG32_SKIP_SEG7 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG32_FILT_LEVEL_SEG7 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG32_QUANT_SEG7 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG33 0x00052100 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG33_LREF_WIDTH 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG33_LREF_HEIGHT 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG34 0x00052200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG34_GREF_WIDTH 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG34_GREF_HEIGHT 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG35 0x00052300 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG35_AREF_WIDTH 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG35_AREF_HEIGHT 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG36 0x00052400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG36_LREF_HOR_SCALE 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG36_LREF_VER_SCALE 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG37 0x00052500 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG37_GREF_HOR_SCALE 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG37_GREF_VER_SCALE 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG38 0x00052600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG38_AREF_HOR_SCALE 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG38_AREF_VER_SCALE 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG46 0x00052e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG46_CUR_POC_00 31:24 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG46_CUR_POC_01 23:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG46_CUR_POC_02 15:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG46_CUR_POC_03 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG46_FILT_REF_ADJ_0 30:24 /* RWISF */ #define NV_CNVDEC_GIP_SWREG46_FILT_REF_ADJ_1 22:16 /* RWISF */ #define NV_CNVDEC_GIP_SWREG46_FILT_REF_ADJ_2 14:8 /* RWISF */ #define NV_CNVDEC_GIP_SWREG46_FILT_REF_ADJ_3 6:0 /* RWISF */ #define NV_CNVDEC_GIP_SWREG47 0x00052f00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG47_CUR_POC_04 31:24 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG47_CUR_POC_05 23:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG47_CUR_POC_06 15:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG47_CUR_POC_07 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG47_FILT_MB_ADJ_0 30:24 /* RWISF */ #define NV_CNVDEC_GIP_SWREG47_FILT_MB_ADJ_1 22:16 /* RWISF */ #define NV_CNVDEC_GIP_SWREG47_FILT_MB_ADJ_2 14:8 /* RWISF */ #define NV_CNVDEC_GIP_SWREG47_FILT_MB_ADJ_3 6:0 /* RWISF */ #define NV_CNVDEC_GIP_SWREG48 0x00053000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG48_CUR_POC_08 31:24 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG48_CUR_POC_09 23:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG48_CUR_POC_10 15:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG48_CUR_POC_11 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG49 0x00053100 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG49_CUR_POC_12 31:24 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG49_CUR_POC_13 23:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG49_CUR_POC_14 15:8 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG49_CUR_POC_15 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG55 0x00053700 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG55_APF_DISABLE 31:31 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG55_APF_SINGLE_PU_MODE 30:30 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG55_APF_THRESHOLD 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_STATUS0 0x00053d00 /* R--4R */ #define NV_CNVDEC_GIP_STATUS0_OUTPUT_CTB_COUNT 31:0 /* R-IVF */ #define NV_CNVDEC_GIP_STATUS0_OUTPUT_CTB_COUNT_INIT 0x00000000 /* R-I-V */ #define NV_CNVDEC_GIP_SWREG62 0x00053e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG62_CU_PIXEL_START_X 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG62_CU_PIXEL_START_Y 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG63 0x00053f00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG63_RUNTIME_CYCLES 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG64 0x00054000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG64_DEC_OUT_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG66 0x00054200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG66_REFER0_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG68 0x00054400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG68_REFER1_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG70 0x00054600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG70_REFER2_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG72 0x00054800 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG72_REFER3_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG74 0x00054a00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG74_REFER4_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG76 0x00054c00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG76_REFER5_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG78 0x00054e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG78_REFER6_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG78_SEGMENT_WRITE_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG80 0x00055000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG80_REFER7_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG80_SEGMENT_READ_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG82 0x00055200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG82_REFER8_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG84 0x00055400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG84_REFER9_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG86 0x00055600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG86_REFER10_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG88 0x00055800 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG88_REFER11_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG90 0x00055a00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG90_REFER12_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG92 0x00055c00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG92_REFER13_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG94 0x00055e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG94_REFER14_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG96 0x00056000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG96_REFER15_YBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG98 0x00056200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG98_DEC_OUT_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG100 0x00056400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG100_REFER0_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG102 0x00056600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG102_REFER1_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG104 0x00056800 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG104_REFER2_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG106 0x00056a00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG106_REFER3_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG108 0x00056c00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG108_REFER4_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG110 0x00056e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG110_REFER5_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG112 0x00057000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG112_REFER6_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG114 0x00057200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG114_REFER7_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG116 0x00057400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG116_REFER8_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG118 0x00057600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG118_REFER9_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG120 0x00057800 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG120_REFER10_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG122 0x00057a00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG122_REFER11_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG124 0x00057c00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG124_REFER12_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG126 0x00057e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG126_REFER13_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG128 0x00058000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG128_REFER14_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG130 0x00058200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG130_REFER15_CBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG132 0x00058400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG132_DEC_OUT_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG134 0x00058600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG134_REFER0_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG136 0x00058800 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG136_REFER1_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG138 0x00058a00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG138_REFER2_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG140 0x00058c00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG140_REFER3_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG142 0x00058e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG142_REFER4_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG144 0x00059000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG144_REFER5_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG146 0x00059200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG146_REFER6_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG148 0x00059400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG148_REFER7_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG150 0x00059600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG150_REFER8_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG152 0x00059800 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG152_REFER9_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG154 0x00059a00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG154_REFER10_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG156 0x00059c00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG156_REFER11_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG158 0x00059e00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG158_REFER12_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG160 0x0005a000 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG160_REFER13_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG162 0x0005a200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG162_REFER14_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG164 0x0005a400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG164_REFER15_DBASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG166 0x0005a600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG166_TILE_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG168 0x0005a800 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG168_STREAM_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG170 0x0005aa00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG170_SCALE_LIST_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG170_CTX_COUNTER_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG172 0x0005ac00 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG172_PROB_TAB_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG178 0x0005b200 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG178_DEC_VERT_FILT_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG180 0x0005b400 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG180_DEC_VERT_SAO_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SWREG182 0x0005b600 /* RW-4R */ #define NV_CNVDEC_GIP_SWREG182_DEC_BSD_CTRL_BASE_MSB 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SURFACE_CTL 0x0005f000 /* RW-4R */ #define NV_CNVDEC_GIP_SURFACE_CTL_BITDEPTH 6:5 /* RWIVF */ #define NV_CNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT 4:2 /* RWIVF */ #define NV_CNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_2 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_4 0x00000001 /* RW--V */ #define NV_CNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_8 0x00000002 /* RW--V */ #define NV_CNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_16 0x00000003 /* RW--V */ #define NV_CNVDEC_GIP_SURFACE_CTL_GOB_HEIGHT_GOB_32 0x00000004 /* RW--V */ #define NV_CNVDEC_GIP_SURFACE_CTL_TILE_FORMAT 1:0 /* RWIVF */ #define NV_CNVDEC_GIP_SURFACE_CTL_TILE_FORMAT_TBL 0x00000000 /* RW--V */ #define NV_CNVDEC_GIP_SURFACE_CTL_TILE_FORMAT_KBL 0x00000001 /* RWI-V */ #define NV_CNVDEC_GIP_SURFACE_STRIDE 0x0005f100 /* RW-4R */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_LUMA 12:0 /* RW-VF */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_CHROMA 28:16 /* RW-VF */ #define NV_CNVDEC_GIP_SECURE 0x0005f200 /* RW-4R */ #define NV_CNVDEC_GIP_SECURE_OTF_EN 0:0 /* RW-VF */ #define NV_CNVDEC_GIP_SECURE_FLUSH_SA 1:1 /* RW-VF */ #define NV_CNVDEC_GIP_SECURE_CHUNK_SZ_SA 6:2 /* RW-VF */ #define NV_CNVDEC_GIP_SECURE_SSM_EN 7:7 /* RWIVF */ #define NV_CNVDEC_GIP_SECURE_SSM_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_GIP_SECURE_SSM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_SECURE_OTF_HALT_REQ 8:8 /* RW-VF */ #define NV_CNVDEC_GIP_SECURE_OTF_HALT_DONE 9:9 /* RW-VF */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF0 0x0005f300 /* RW-4R */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF0_LUMA 11:0 /* RW-VF */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF0_CHROMA 27:16 /* RW-VF */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF1 0x0005f400 /* RW-4R */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF1_LUMA 11:0 /* RW-VF */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF1_CHROMA 27:16 /* RW-VF */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF2 0x0005f500 /* RW-4R */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF2_LUMA 11:0 /* RW-VF */ #define NV_CNVDEC_GIP_SURFACE_STRIDE_REF2_CHROMA 27:16 /* RW-VF */ #define NV_CNVDEC_GIP_CAP_REG0 0x0005f600 /* RW-4R */ #define NV_CNVDEC_GIP_CAP_REG0_VP9 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_CAP_REG0_VP9_DISABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_GIP_CAP_REG0_VP9_ENABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_GIP_RDY_DELAY 0x0005f700 /* RW-4R */ #define NV_CNVDEC_GIP_RDY_DELAY_V 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_RDY_DELAY_V_RSTVAL 0x0000007f /* RWI-V */ #define NV_CNVDEC_GIP_TIMEOUT_REG 0x0005f800 /* RW-4R */ #define NV_CNVDEC_GIP_TIMEOUT_REG_V 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_TIMEOUT_REG_V_RSTVAL 0x10000000 /* RWI-V */ #define NV_CNVDEC_GIP_INTR_MASK 0x0005fb00 /* RW-4R */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_SUBSTREAM_DMA_DONE_INT 22:22 /* RWIVF */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_SUBSTREAM_DMA_DONE_INT_RSTVAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_TIMEOUT 18:18 /* RWIVF */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_TIMEOUT_RSTVAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_ERROR_INT 16:16 /* RWIVF */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_ERROR_INT_RSTVAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_DMA_DONE_INT 15:15 /* RWIVF */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_DMA_DONE_INT_RSTVAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_RDY_INT 12:12 /* RWIVF */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_RDY_INT_RSTVAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_E 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_INTR_MASK_DEC_E_RSTVAL 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_P444_SPS_EXT 0x00051600 /* RW-4R */ #define NV_CNVDEC_GIP_P444_SPS_EXT_CHROMA_FORMAT_IDC 1:0 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_SKIP_ROTATION_EN 2:2 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_SKIP_CONTEXT_EN 3:3 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_IBC_EN 4:4 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_IMPL_RDPCM_EN 5:5 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_EXPL_RDPCM_EN 6:6 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_EXT_PRECISION_EN 7:7 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_INTRA_SMOOTH_DIS 8:8 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_HIGH_PRECISION_OFFSET_EN 9:9 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_FAST_RICE_ADAPT_EN 10:10 /* RWIVF */ #define NV_CNVDEC_GIP_P444_SPS_EXT_CABAC_BYPASS_ALIGN_EN 11:11 /* RWIVF */ #define NV_CNVDEC_GIP_P444_PPS_EXT 0x00051700 /* RW-4R */ #define NV_CNVDEC_GIP_P444_PPS_EXT_MAX_TRANSFORM_SKIP_SIZE 3:0 /* RWIVF */ #define NV_CNVDEC_GIP_P444_PPS_EXT_CROSS_COMPONENT_PRED_EN 4:4 /* RWIVF */ #define NV_CNVDEC_GIP_P444_PPS_EXT_SAO_OFFSET_SCALE_LUMA 7:5 /* RWIVF */ #define NV_CNVDEC_GIP_P444_PPS_EXT_SAO_OFFSET_SCALE_CHROMA 10:8 /* RWIVF */ #define NV_CNVDEC_GIP_P444_PPS_QP_EXT 0x00051800 /* RW-4R */ #define NV_CNVDEC_GIP_P444_PPS_QP_EXT_ADJ_EN 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_P444_PPS_QP_EXT_ADJ_DEPTH 3:1 /* RWIVF */ #define NV_CNVDEC_GIP_P444_PPS_QP_EXT_ADJ_TABLE_SIZE 6:4 /* RWIVF */ #define NV_CNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE 0x00051900 /* RW-4R */ #define NV_CNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_0 4:0 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_1 9:5 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_2 14:10 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_3 19:15 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_4 24:20 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CB_QP_ADJ_TABLE_5 29:25 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE 0x00051a00 /* RW-4R */ #define NV_CNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_0 4:0 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_1 9:5 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_2 14:10 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_3 19:15 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_4 24:20 /* RWISF */ #define NV_CNVDEC_GIP_P444_PPS_CR_QP_ADJ_TABLE_5 29:25 /* RWISF */ #define NV_CNVDEC_GIP_FILTER_TOP_BUFFER 0x00051b00 /* RW-4R */ #define NV_CNVDEC_GIP_FILTER_TOP_BUFFER_OFFSET 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_SAO_TOP_BUFFER 0x00051c00 /* RW-4R */ #define NV_CNVDEC_GIP_SAO_TOP_BUFFER_OFFSET 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_HW_CTB_POS 0x0005bc00 /* RW-4R */ #define NV_CNVDEC_GIP_HW_CTB_POS_STARTY 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_HW_CTB_POS_STARTX 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_HW_SLICE_POS 0x0005bd00 /* RW-4R */ #define NV_CNVDEC_GIP_HW_SLICE_POS_STARTY 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_HW_SLICE_POS_STARTX 31:16 /* RWIVF */ #define NV_CNVDEC_GIP_ERR_CONCEAL_CTRL 0x0005be00 /* RW-4R */ #define NV_CNVDEC_GIP_ERR_CONCEAL_CTRL_ON 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_ERR_CONCEAL_CTRL_RECOV_START_POS 2:1 /* RWIVF */ #define NV_CNVDEC_GIP_ERR_CONCEAL_CTRL_HEVC_STRM_END_CYA 3:3 /* RWIVF */ #define NV_CNVDEC_GIP_ERR_CONCEAL_CTRL_HEVC_STRM_END_CYA_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_ERR_CONCEAL_CTRL_HEVC_STRM_END_CYA_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_GIP_ERR_MASK0 0x0005bf00 /* RW-4R */ #define NV_CNVDEC_GIP_ERR_MASK0_FIELD 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_ERR_MASK1 0x0005c000 /* RW-4R */ #define NV_CNVDEC_GIP_ERR_MASK1_FIELD 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_ERR_INFO 0x0005c100 /* RW-4R */ #define NV_CNVDEC_GIP_ERR_INFO_TYPE_FIELD 15:0 /* RWIVF */ #define NV_CNVDEC_GIP_ERR_INFO_HINT 19:16 /* RWIVF */ #define NV_CNVDEC_GIP_REAL_STREAM_LEN 0x0005c200 /* RW-4R */ #define NV_CNVDEC_GIP_REAL_STREAM_LEN_VALUE 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_INTRA_BLK_CNT 0x0005c800 /* RW-4R */ #define NV_CNVDEC_GIP_STAT_INTRA_BLK_CNT_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_INTER_BLK_CNT 0x0005c900 /* RW-4R */ #define NV_CNVDEC_GIP_STAT_INTER_BLK_CNT_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_SKIP_BLK_CNT 0x0005ca00 /* RW-4R */ #define NV_CNVDEC_GIP_STAT_SKIP_BLK_CNT_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_FWD_MVX_ABS_SUM 0x0005cb00 /* RW-4R */ #define NV_CNVDEC_GIP_STAT_FWD_MVX_ABS_SUM_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_FWD_MVY_ABS_SUM 0x0005cc00 /* RW-4R */ #define NV_CNVDEC_GIP_STAT_FWD_MVY_ABS_SUM_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_BWD_MVX_ABS_SUM 0x0005cd00 /* RW-4R */ #define NV_CNVDEC_GIP_STAT_BWD_MVX_ABS_SUM_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_BWD_MVY_ABS_SUM 0x0005ce00 /* RW-4R */ #define NV_CNVDEC_GIP_STAT_BWD_MVY_ABS_SUM_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_MV_HEVC_CFG 0x0005cf00 /* RW-4R */ #define NV_CNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_ENABLE 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_NUH_LAYER_ID 6:1 /* RWIVF */ #define NV_CNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_DEFAULT_REF_LAYERS_ACTIVE_FLAG 7:7 /* RWIVF */ #define NV_CNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_NUM_DIRECT_REF_LAYERS 13:8 /* RWIVF */ #define NV_CNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_MAX_ONE_ACTIVE_REF_LAYER_FLAG 14:14 /* RWIVF */ #define NV_CNVDEC_GIP_MV_HEVC_CFG_MV_HEVC_NUM_ACTIVE_REF_LAYER_PICS 20:15 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG 0x00052700 /* RW-4R */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_DEC_EN 0:0 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_DEC_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_FIRST_SLICE_FLAG 1:1 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_LAST_SLICE_FLAG 2:2 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_EC_EN 3:3 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_EC_EN_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_ERROR_SLICE_FLAG 4:4 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_CTX_SAVE_FLAG 5:5 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_CTX_RESTORE_FLAG 6:6 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_DO_SLICE_EC 7:7 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_DO_SLICE_EC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_EC_MV_TYPE 9:8 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_EC_SLICE_TYPE 11:10 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_DECODING_CFG_SLICE_STRM_RECFG_EN 12:12 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_CTB_COUNT 0x00052800 /* RW-4R */ #define NV_CNVDEC_GIP_HEVC_SLICE_CTB_COUNT_VAL 19:0 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_BS_OFFSET 0x00052900 /* RW-4R */ #define NV_CNVDEC_GIP_HEVC_SLICE_BS_OFFSET_VAL 31:0 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO1 0x00052a00 /* RW-4R */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO1_TILEWIDTH 9:0 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO1_TILEHEIGHT 19:10 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO1_TILECOL 24:20 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO1_TILEROW 29:25 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO2 0x00052b00 /* RW-4R */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO2_TILE_START_POSX 9:0 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO2_TILE_START_POSY 19:10 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO2_TILE_INDEX 28:20 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO3 0x00052c00 /* RW-4R */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO3_CTBX_IN_TILE 9:0 /* RWIVF */ #define NV_CNVDEC_GIP_HEVC_SLICE_TILEINFO3_CTBY_IN_TILE 19:10 /* RWIVF */ #define NV_CNVDEC_GIP_SLICE_START_ADDR 0x0005bb00 /* RW-4R */ #define NV_CNVDEC_GIP_SLICE_START_ADDR_VAL 19:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_MV_ABS_SUM_EXT 0x0005c700 /* RW-4R */ #define NV_CNVDEC_GIP_STAT_MV_ABS_SUM_EXT_FWD_MVX 7:0 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_MV_ABS_SUM_EXT_FWD_MVY 15:8 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_MV_ABS_SUM_EXT_BWD_MVX 23:16 /* RWIVF */ #define NV_CNVDEC_GIP_STAT_MV_ABS_SUM_EXT_BWD_MVY 31:24 /* RWIVF */ #define NV_CNVDEC_AVD_SWREG0 0x00060000 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG0_SB_SIZE 0:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ALLOW_FILTER_INTRA 1:1 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ENABLE_INTRA_EDGE_FILTER 2:2 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ALLOW_INTERINTRA 3:3 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ALLOW_MASKED_COMPOUND 4:4 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ENABLE_DUAL_FILTER 5:5 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ENABLE_JNT_COMP 6:6 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ENABLE_CDEF 8:8 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_PIC_TYPE 10:10 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_DISABLE_CDF_UPDATE 11:11 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ALLOW_SCREEN_CONTENT_TOOLS 12:12 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_FORCE_INTEGER_MV 13:13 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_ALLOW_INTRABC 14:14 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_SWITCHABLE_MOTION_MODE 15:15 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_TEMPORAL_MV_E 16:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_DELTA_Q_PRESENT 17:17 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_DELTA_Q_RES_LOG 19:18 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_DELTA_LF_PRESENT 20:20 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_DELTA_LF_MULTI 21:21 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_DELTA_LF_RES_LOG 23:22 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_USE_TEMPORAL0_MVS 24:24 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_USE_TEMPORAL1_MVS 25:25 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_USE_TEMPORAL2_MVS 26:26 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_REF_SCALING_ENABLE 27:27 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_HYBRID_PRED_ENABLE 28:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_COMP_PRED_ONLY 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_SHOW_FRAME 30:30 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG0_SKIP_MODE_FLAG 31:31 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1 0x00060100 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG1_SKIP_REF0 3:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_SKIP_REF1 7:4 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_PRESKIP_SEGID 8:8 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_LAST_ACTIVE_SEG 11:9 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_REDUCED_TX_SET_USED 12:12 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_AV1_TILE_ENABLE 13:13 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_DEC_STREAM_ERROR_DETECTION 16:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_DEC_MV_ERROR_DETECTION 17:17 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_DEC_COEFF_ERROR_DETECTION 18:18 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_MONOCHROME 20:20 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_USE_TEMPORAL3_MVS 21:21 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_ALLOW_WARP 23:23 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_ENABLE_HISTOGRAM 26:26 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_RCACHE_DISABLE 27:27 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_SECONDARY_OUTPUT_E 28:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_TILE_TRANSPOSE 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG1_SUBSTREAM_MODE_E 30:30 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG2 0x00060200 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG2_TEMPORAL_READ_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG3 0x00060300 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG3_TEMPORAL1_READ_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG4 0x00060400 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG4_TEMPORAL2_READ_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG5 0x00060500 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG5_TEMPORAL3_READ_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG6 0x00060600 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG6_TEMPORAL_WRITE_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG7 0x00060700 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG7_AV1_SEGMENT_READ_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG8 0x00060800 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG8_AV1_SEGMENT_WRITE_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG9 0x00060900 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG9_GLOBAL_MODEL_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG10 0x00060a00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG10_PROB_TABLE_WRITE_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG11 0x00060b00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG11_AV1_PIC_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG11_AV1_PIC_HEIGHT 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG12 0x00060c00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG12_SUPERRES_PIC_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG12_SUPERRES_IS_SCALED 16:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG12_SCALE_DENOM_MINUS9 19:17 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG12_AV1_PIC_WIDTH_PAD 22:20 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG12_AV1_PIC_HEIGHT_PAD 25:23 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG13 0x00060d00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG13_QUANT_BASE_QINDEX 7:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG13_QUANT_DELTA_Y_DC 14:8 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG13_QUANT_DELTA_UV_DC 21:15 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG13_QUANT_DELTA_UV_AC 28:22 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG14 0x00060e00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG14_QUANT_DELTA_V_DC 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG14_QUANT_DELTA_V_AC 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG14_QMLEVEL_Y 17:14 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG14_QMLEVEL_U 21:18 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG14_QMLEVEL_V 25:22 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG15 0x00060f00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG15_BASE_LF_LEVEL_0 5:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG15_BASE_LF_LEVEL_1 11:6 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG15_BASE_LF_LEVEL_2 17:12 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG15_BASE_LF_LEVEL_3 23:18 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG16 0x00061000 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG16_FILT_REF0_DELTA 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG16_FILT_REF1_DELTA 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG16_FILT_REF2_DELTA 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG16_FILT_REF3_DELTA 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG17 0x00061100 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG17_FILT_REF4_DELTA 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG17_FILT_REF5_DELTA 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG17_FILT_REF6_DELTA 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG17_FILT_REF7_DELTA 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG18 0x00061200 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG18_FILT_MODE0_DELTA 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG18_FILT_MODE1_DELTA 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG18_SEG_QUANT_SIGN 23:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG19 0x00061300 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG19_REF0_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG19_REF0_HEIGHT 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG20 0x00061400 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG20_REF1_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG20_REF1_HEIGHT 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG21 0x00061500 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG21_REF2_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG21_REF2_HEIGHT 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG22 0x00061600 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG22_REF3_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG22_REF3_HEIGHT 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG23 0x00061700 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG23_REF4_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG23_REF4_HEIGHT 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG24 0x00061800 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG24_REF5_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG24_REF5_HEIGHT 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG25 0x00061900 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG25_REF6_WIDTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG25_REF6_HEIGHT 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG26 0x00061a00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG26_SURFACE_STRIDE_REF3_LUMA 11:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG26_SURFACE_STRIDE_REF3_CHROMA 27:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG27 0x00061b00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG27_SURFACE_STRIDE_REF4_LUMA 11:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG27_SURFACE_STRIDE_REF4_CHROMA 27:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG28 0x00061c00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG28_SURFACE_STRIDE_REF5_LUMA 11:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG28_SURFACE_STRIDE_REF5_CHROMA 27:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG29 0x00061d00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG29_SURFACE_STRIDE_REF6_LUMA 11:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG29_SURFACE_STRIDE_REF6_CHROMA 27:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG30 0x00061e00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG30_AV1_TILE_COLS 7:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG30_AV1_TILE_ROWS 15:8 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG30_CDEF_DAMPING 17:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG30_CDEF_BITS 19:18 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG30_LR_TYPE 25:20 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG30_LR_UNIT_SIZE 31:26 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG31 0x00061f00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG31_CDEF_LUMA_PRIMARY_STRENGTH 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG32 0x00062000 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG32_CDEF_CHROMA_PRIMARY_STRENGTH 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG33 0x00062100 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG33_CDEF_LUMA_SECONDARY_STRENGTH 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG33_CDEF_CHROMA_SECONDARY_STRENGTH 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34 0x00062200 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG34_REF0_GM_MODE 1:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF1_GM_MODE 3:2 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF2_GM_MODE 5:4 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF3_GM_MODE 7:6 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF4_GM_MODE 9:8 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF5_GM_MODE 11:10 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF6_GM_MODE 13:12 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF0_SIGN_BIAS 14:14 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF1_SIGN_BIAS 15:15 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF2_SIGN_BIAS 16:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF3_SIGN_BIAS 17:17 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF4_SIGN_BIAS 18:18 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF5_SIGN_BIAS 19:19 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG34_REF6_SIGN_BIAS 20:20 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG35 0x00062300 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG35_REF0_HOR_SCALE 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG35_REF0_VER_SCALE 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG36 0x00062400 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG36_REF1_HOR_SCALE 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG36_REF1_VER_SCALE 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG37 0x00062500 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG37_REF2_HOR_SCALE 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG37_REF2_VER_SCALE 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG38 0x00062600 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG38_REF3_HOR_SCALE 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG38_REF3_VER_SCALE 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG39 0x00062700 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG39_REF4_HOR_SCALE 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG39_REF4_VER_SCALE 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG40 0x00062800 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG40_REF5_HOR_SCALE 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG40_REF5_VER_SCALE 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG41 0x00062900 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG41_REF6_HOR_SCALE 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG41_REF6_VER_SCALE 31:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG42 0x00062a00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG42_FILT_LEVEL_DELTA0_SEG0 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG42_FILT_LEVEL_DELTA0_SEG1 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG42_FILT_LEVEL_DELTA0_SEG2 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG42_FILT_LEVEL_DELTA0_SEG3 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG42_AV1_REFPIC_SEG0 31:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG43 0x00062b00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG43_FILT_LEVEL_DELTA0_SEG4 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG43_FILT_LEVEL_DELTA0_SEG5 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG43_FILT_LEVEL_DELTA0_SEG6 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG43_FILT_LEVEL_DELTA0_SEG7 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG43_AV1_REFPIC_SEG1 31:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG44 0x00062c00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG44_FILT_LEVEL_DELTA1_SEG0 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG44_FILT_LEVEL_DELTA1_SEG1 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG44_FILT_LEVEL_DELTA1_SEG2 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG44_FILT_LEVEL_DELTA1_SEG3 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG44_AV1_REFPIC_SEG2 31:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG45 0x00062d00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG45_FILT_LEVEL_DELTA1_SEG4 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG45_FILT_LEVEL_DELTA1_SEG5 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG45_FILT_LEVEL_DELTA1_SEG6 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG45_FILT_LEVEL_DELTA1_SEG7 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG45_AV1_REFPIC_SEG3 31:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG46 0x00062e00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG46_FILT_LEVEL_DELTA2_SEG0 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG46_FILT_LEVEL_DELTA2_SEG1 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG46_FILT_LEVEL_DELTA2_SEG2 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG46_FILT_LEVEL_DELTA2_SEG3 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG46_AV1_REFPIC_SEG4 31:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG47 0x00062f00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG47_FILT_LEVEL_DELTA2_SEG4 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG47_FILT_LEVEL_DELTA2_SEG5 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG47_FILT_LEVEL_DELTA2_SEG6 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG47_FILT_LEVEL_DELTA2_SEG7 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG47_AV1_REFPIC_SEG5 31:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG48 0x00063000 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG48_FILT_LEVEL_DELTA3_SEG0 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG48_FILT_LEVEL_DELTA3_SEG1 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG48_FILT_LEVEL_DELTA3_SEG2 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG48_FILT_LEVEL_DELTA3_SEG3 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG48_GLOBAL_MV_SEG0 28:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG48_GLOBAL_MV_SEG1 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG48_GLOBAL_MV_SEG2 30:30 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG48_GLOBAL_MV_SEG3 31:31 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG49 0x00063100 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG49_FILT_LEVEL_DELTA3_SEG4 6:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG49_FILT_LEVEL_DELTA3_SEG5 13:7 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG49_FILT_LEVEL_DELTA3_SEG6 20:14 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG49_FILT_LEVEL_DELTA3_SEG7 27:21 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG49_GLOBAL_MV_SEG4 28:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG49_GLOBAL_MV_SEG5 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG49_GLOBAL_MV_SEG6 30:30 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG49_GLOBAL_MV_SEG7 31:31 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG50 0x00063200 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG50_CUR_LAST_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG50_CUR_LAST2_OFFSET 17:9 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG50_CUR_LAST3_OFFSET 26:18 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG50_AV1_REFPIC_SEG6 30:27 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG51 0x00063300 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG51_CUR_GOLDEN_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG51_CUR_BWDREF_OFFSET 17:9 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG51_CUR_ALTREF2_OFFSET 26:18 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG51_AV1_REFPIC_SEG7 30:27 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG52 0x00063400 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG52_CUR_ALTREF_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG52_MF1_LAST_OFFSET 17:9 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG52_MF1_LAST_SIDE 18:18 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG52_MF1_LAST2_OFFSET 27:19 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG52_MF1_LAST2_SIDE 28:28 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG53 0x00063500 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG53_MF1_LAST3_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG53_MF1_LAST3_SIDE 9:9 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG53_MF1_GOLDEN_OFFSET 18:10 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG53_MF1_GOLDEN_SIDE 19:19 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG53_MF1_BWDREF_OFFSET 28:20 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG53_MF1_BWDREF_SIDE 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG54 0x00063600 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG54_MF1_ALTREF2_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG54_MF1_ALTREF2_SIDE 9:9 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG54_MF1_ALTREF_OFFSET 18:10 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG54_MF1_ALTREF_SIDE 19:19 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG54_MF2_LAST_OFFSET 28:20 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG54_MF2_LAST_SIDE 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG55 0x00063700 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG55_MF2_LAST2_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG55_MF2_LAST2_SIDE 9:9 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG55_MF2_LAST3_OFFSET 18:10 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG55_MF2_LAST3_SIDE 19:19 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG55_MF2_GOLDEN_OFFSET 28:20 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG55_MF2_GOLDEN_SIDE 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG56 0x00063800 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG56_MF2_BWDREF_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG56_MF2_BWDREF_SIDE 9:9 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG56_MF2_ALTREF2_OFFSET 18:10 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG56_MF2_ALTREF2_SIDE 19:19 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG56_MF2_ALTREF_OFFSET 28:20 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG56_MF2_ALTREF_SIDE 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG57 0x00063900 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG57_MF3_LAST_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG57_MF3_LAST_SIDE 9:9 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG57_MF3_LAST2_OFFSET 18:10 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG57_MF3_LAST2_SIDE 19:19 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG57_MF3_LAST3_OFFSET 28:20 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG57_MF3_LAST3_SIDE 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG58 0x00063a00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG58_MF3_GOLDEN_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG58_MF3_GOLDEN_SIDE 9:9 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG58_MF3_BWDREF_OFFSET 18:10 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG58_MF3_BWDREF_SIDE 19:19 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG58_MF3_ALTREF2_OFFSET 28:20 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG58_MF3_ALTREF2_SIDE 29:29 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG59 0x00063b00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG59_MF3_ALTREF_OFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG59_MF3_ALTREF_SIDE 9:9 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG59_MF1_TYPE 12:10 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG59_MF2_TYPE 15:13 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG59_MF3_TYPE 18:16 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG60 0x00063c00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG60_RCACHE_DEBUG_STAT_DATA 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG61 0x00063d00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG61_RCACHE_REQ_NUMBER 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG62 0x00063e00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG62_RCACHE_HIT_NUMBER 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG63 0x00063f00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG63_PRED_INTRA_TOPBUFFER_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG64 0x00064000 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG64_DEC_VERT_LR_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG65 0x00064100 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG65_DEC_VERT_CDEF_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG66 0x00064200 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG66_DEC_VERT_HUS_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG67 0x00064300 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG67_SUPERRES_LUMA_STEP 13:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG67_SUPERRES_CHROMA_STEP 27:14 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG68 0x00064400 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG68_SUPERRES_INIT_LUMA_SUBPEL_X 13:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG68_SUPERRES_INIT_CHROMA_SUBPEL_X 27:14 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG69 0x00064500 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG69_CUR_LAST_ROFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG69_CUR_LAST2_ROFFSET 17:9 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG69_CUR_LAST3_ROFFSET 26:18 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG70 0x00064600 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG70_CUR_GOLDEN_ROFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG70_CUR_BWDREF_ROFFSET 17:9 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG70_CUR_ALTREF2_ROFFSET 26:18 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG71 0x00064700 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG71_CUR_ALTREF_ROFFSET 8:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG72 0x00064800 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG72_CONTEXT_UPDATE_TILE_ID 11:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG73 0x00064900 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG73_HISTOGRAM_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74 0x00064a00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG74_APPLY_GRAIN 0:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74_OVERLAP_FLAG 1:1 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74_CLIP_TO_RESTRICTED_RANGE 2:2 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74_CHROMA_SCALING_FROM_LUMA 3:3 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74_NUM_Y_POINTS_B 4:4 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74_NUM_CB_POINTS_B 5:5 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74_NUM_CR_POINTS_B 6:6 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74_SCALING_SHIFT 10:7 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG74_CB_OFFSET 19:11 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG74_CR_OFFSET 28:20 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG75 0x00064b00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG75_CB_MULT 7:0 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG75_CB_LUMA_MULT 15:8 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG75_CR_MULT 23:16 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG75_CR_LUMA_MULT 31:24 /* RWXSF */ #define NV_CNVDEC_AVD_SWREG76 0x00064c00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG76_RANDOM_SEED 15:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG77 0x00064d00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG77_FILM_GRAIN_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG78 0x00064e00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG78_DISP_BUF_LU_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG79 0x00064f00 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG79_DISP_BUF_CH_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG80 0x00065000 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG80_DEC_VERT_FGS_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG81 0x00065100 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG81_DMA_SRC_INFO 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG82 0x00065200 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG82_DMA_DST_BASE 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG83 0x00065300 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG83_DMA_CMD_SIZE 23:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG83_DMA_CMD_LAST_FLAG 24:24 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG83_DMA_CMD_MODE 26:25 /* RWXVF */ #define NV_CNVDEC_CG4 0x00065400 /* RW-4R */ #define NV_CNVDEC_CG4_SLCG 31:0 /* RWIVF */ #define NV_CNVDEC_CG4_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG4_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_PROC_DIS 0:0 /* RWIVF */ #define NV_CNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_PROC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_PROC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_PROC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_CTRL_DIS 1:1 /* RWIVF */ #define NV_CNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_MASKOUTPUT_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_FETCH2D_DIS 2:2 /* RWIVF */ #define NV_CNVDEC_CG4_SLCG_RFETCH_FETCH2D_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_FETCH2D_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG4_SLCG_RFETCH_FETCH2D_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RCACHE_CACHE_DIS 3:3 /* RWIVF */ #define NV_CNVDEC_CG4_SLCG_RCACHE_CACHE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RCACHE_CACHE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG4_SLCG_RCACHE_CACHE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RCACHE_REQ_DIS 4:4 /* RWIVF */ #define NV_CNVDEC_CG4_SLCG_RCACHE_REQ_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_RCACHE_REQ_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG4_SLCG_RCACHE_REQ_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_ECDMA_DIS 5:5 /* RWIVF */ #define NV_CNVDEC_CG4_SLCG_ECDMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG4_SLCG_ECDMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG4_SLCG_ECDMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5 0x00065500 /* RW-4R */ #define NV_CNVDEC_CG5_SLCG 31:0 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG5_SLCG__PROD 0x00000040 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_HEVC_HEADER_DIS 0:0 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EMD_HEVC_HEADER_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_HEVC_HEADER_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EMD_HEVC_HEADER_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_HEVC_SLICE_DIS 1:1 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EMD_HEVC_SLICE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_HEVC_SLICE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EMD_HEVC_SLICE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_COUNTER_DIS 2:2 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EMD_COUNTER_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_COUNTER_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EMD_COUNTER_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_VPX_DIS 3:3 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EMD_VPX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_VPX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EMD_VPX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_GIP_EMD_GLUE_DIS 4:4 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_GIP_EMD_GLUE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_GIP_EMD_GLUE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_GIP_EMD_GLUE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_GLUE_DIS 5:5 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EMD_GLUE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_GLUE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EMD_GLUE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_PREPARSER_DIS 6:6 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EMD_PREPARSER_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EMD_PREPARSER_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EMD_PREPARSER_DIS__PROD 0x00000001 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_AOM_EMD_RAMS_DIS 7:7 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_AOM_EMD_RAMS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_AOM_EMD_RAMS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_AOM_EMD_RAMS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_HEVC_DIS 8:8 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_HEVC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_HEVC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_HEVC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_VP9_CUIN_DIS 9:9 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_VP9_CUIN_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_VP9_CUIN_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_VP9_CUIN_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_VP9_DIS 10:10 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_VP9_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_VP9_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_GIP_MVD_VP9_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_CTRL_DIS 11:11 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_DRL_DIS 12:12 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_DRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_DRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_DRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_DEMUX_DIS 13:13 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_DEMUX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_DEMUX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_DEMUX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_PROJ_DIS 14:14 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_PROJ_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_PROJ_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_PROJ_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_SERVE_DIS 15:15 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_SERVE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_SERVE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_SERVE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_STRM_CTXS_DIS 16:16 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MV_STRM_CTXS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_STRM_CTXS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MV_STRM_CTXS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_COL_IN_DIS 17:17 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_COL_IN_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_COL_IN_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_COL_IN_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_COL_OUT_DIS 18:18 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_COL_OUT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_COL_OUT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_COL_OUT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_CU_DIS 19:19 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_CU_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_CU_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_CU_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_MV_DIS 20:20 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_MV_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_MV_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MVD_GLUE_MV_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_TOP_MEM_DIS 21:21 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MVD_TOP_MEM_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MVD_TOP_MEM_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MVD_TOP_MEM_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_WARPED_MODEL_DIS 22:22 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_WARPED_MODEL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_WARPED_MODEL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_WARPED_MODEL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_COL_AV1_DIS 23:23 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_COL_AV1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_COL_AV1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_COL_AV1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_CORE_DIS 24:24 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_CORE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_CORE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_CORE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLOBAL_REQ_DIS 25:25 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLOBAL_REQ_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLOBAL_REQ_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLOBAL_REQ_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLOBAL_DIS 26:26 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLOBAL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLOBAL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLOBAL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLUE_DIS 27:27 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLUE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLUE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_GLUE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_MUX_DIS 28:28 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_MUX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_MUX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_EP_DMA_MUX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_VPC_MAIN_DIS 29:29 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_VPC_MAIN_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_VPC_MAIN_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_VPC_MAIN_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_CTRL_DEMUX_DIS 30:30 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_CTRL_DEMUX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_CTRL_DEMUX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_CTRL_DEMUX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_BUF_DIS 31:31 /* RW-VF */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_BUF_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_BUF_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG5_SLCG_MV_PRED_MF_BUF_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11 0x00065b00 /* RW-4R */ #define NV_CNVDEC_CG11_SLCG 31:0 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG11_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_PALETTE_DIS 0:0 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_PALETTE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_PALETTE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_PALETTE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_DAALA_EC_DEC_DIS 1:1 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_DAALA_EC_DEC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_DAALA_EC_DEC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_DAALA_EC_DEC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_DIS 2:2 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_CTX_DIS 3:3 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_CTX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_CTX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_CTX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_INTRA_MODE_DIS 4:4 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_INTRA_MODE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_INTRA_MODE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_INTRA_MODE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_MVD_CTRL_DIS 5:5 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_MVD_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_MVD_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_MVD_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_SEGMENT_DIS 6:6 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_SEGMENT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_SEGMENT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_SEGMENT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_TXSIZE_DIS 7:7 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_TXSIZE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_TXSIZE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CODED_TXSIZE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_DIS 8:8 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_CTRL_DIS 9:9 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_RAM_DIS 10:10 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_RAM_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_RAM_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_RAM_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_STACK_DIS 11:11 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_STACK_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_STACK_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_COEFF_STACK_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_DIS 12:12 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_SB_DIS 13:13 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_SB_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_SB_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_CTRL_SB_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_PALETTE_DIS 14:14 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_PALETTE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_PALETTE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_DEC_MSYM_PALETTE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_EP_IF_MUX_DIS 15:15 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_EP_IF_MUX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_EP_IF_MUX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_EP_IF_MUX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_EP_SCD_DIS 16:16 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_EP_SCD_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_EP_SCD_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_EP_SCD_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_IF_DIS 17:17 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_STREAM_IF_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_STREAM_IF_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_STREAM_IF_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_ERROR_DETECT_DIS 18:18 /* RW-VF */ #define NV_CNVDEC_CG11_SLCG_ERROR_DETECT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG11_SLCG_ERROR_DETECT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG11_SLCG_ERROR_DETECT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6 0x00065600 /* RW-4R */ #define NV_CNVDEC_CG6_SLCG 31:0 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG6_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_PREFETCH_FETCH2D_DIS 0:0 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_PREFETCH_FETCH2D_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_PREFETCH_FETCH2D_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_PREFETCH_FETCH2D_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_PREFETCH_PROC2D_DIS 1:1 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_PREFETCH_PROC2D_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_PREFETCH_PROC2D_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_PREFETCH_PROC2D_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_COEFF_SPLIT_DIS 2:2 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_COEFF_SPLIT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_COEFF_SPLIT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_COEFF_SPLIT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_CTRL2PRED_DIS 3:3 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_CTRL2PRED_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_CTRL2PRED_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_CTRL2PRED_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_SCAN_DIS 4:4 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_SCAN_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_SCAN_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_SCAN_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_AV1_DIS 5:5 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_AV1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_AV1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_AV1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_265_DIS 6:6 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_265_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_265_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_265_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_OUT_DIS 7:7 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_OUT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_OUT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_OUT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_CTRL_DIS 8:8 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_ZERO_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RBUF_DIS 9:9 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RBUF_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RBUF_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RBUF_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RREQ_DIS 10:10 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RREQ_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RREQ_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_ZERO_RUN_RREQ_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_LOSSLESS_DIS 11:11 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_LOSSLESS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_LOSSLESS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_LOSSLESS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_SCAN_DIS 12:12 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_SCAN_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_SCAN_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_SCANQUANT_SCAN_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_LOAD_DATA_DIS 13:13 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_LOAD_DATA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_LOAD_DATA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_LOAD_DATA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T0_DIS 15:15 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T0_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T0_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T0_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T1_DIS 16:16 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_MUX_T1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_265_DIS 17:17 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_265_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_265_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_265_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_AV1_DIS 18:18 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_AV1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_AV1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T0_AV1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_265_DIS 19:19 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_265_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_265_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_265_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_AV1_DIS 20:20 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_AV1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_AV1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_PROCESS_DATA_ACC_T1_AV1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_FORMAT_DATA_DIS 21:21 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_FORMAT_DATA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_FORMAT_DATA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_HOR_FORMAT_DATA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_PP_DIS 22:22 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_PP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_PP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_PP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_LOAD_DATA_DIS 23:23 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_LOAD_DATA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_LOAD_DATA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_LOAD_DATA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_265_DIS 24:24 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_265_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_265_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_265_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_AV1_DIS 25:25 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_AV1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_AV1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_FORMAT_DATA_AV1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T0_DIS 27:27 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T0_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T0_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T0_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T1_DIS 28:28 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_MUX_T1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_265_DIS 29:29 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_265_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_265_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_265_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_AV1_DIS 30:30 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_AV1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_AV1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T0_AV1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_265_DIS 31:31 /* RW-VF */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_265_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_265_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG6_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_265_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12 0x00065c00 /* RW-4R */ #define NV_CNVDEC_CG12_SLCG 31:0 /* RW-VF */ #define NV_CNVDEC_CG12_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG12_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_AV1_DIS 0:0 /* RW-VF */ #define NV_CNVDEC_CG12_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_AV1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_AV1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG12_SLCG_TRANS_IDCT_VER_PROCESS_DATA_ACC_T1_AV1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_265_DIS 1:1 /* RW-VF */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_265_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_265_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_265_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_OTH_DIS 2:2 /* RW-VF */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_OTH_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_OTH_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_OTH_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_OUT_DIS 3:3 /* RW-VF */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_OUT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_OUT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG12_SLCG_TRANS_TO_PRED_OUT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_IQT_DMA_DIS 4:4 /* RW-VF */ #define NV_CNVDEC_CG12_SLCG_IQT_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_IQT_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG12_SLCG_IQT_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_SCANQUANT_ZERO_RUN_ZERO_VP9_DIS 5:5 /* RW-VF */ #define NV_CNVDEC_CG12_SLCG_SCANQUANT_ZERO_RUN_ZERO_VP9_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_SCANQUANT_ZERO_RUN_ZERO_VP9_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG12_SLCG_SCANQUANT_ZERO_RUN_ZERO_VP9_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_PREFETCH_PREPROCESS_DIS 6:6 /* RW-VF */ #define NV_CNVDEC_CG12_SLCG_PREFETCH_PREPROCESS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG12_SLCG_PREFETCH_PREPROCESS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG12_SLCG_PREFETCH_PREPROCESS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7 0x00065700 /* RW-4R */ #define NV_CNVDEC_CG7_SLCG 31:0 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG7_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CALC_DIS 0:0 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CALC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CALC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CALC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CALHEVC_DIS 1:1 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CALHEVC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CALHEVC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CALHEVC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CFL_DIS 2:2 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CFL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CFL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CFL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CTRL_DIS 3:3 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_FILTER_DIS 4:4 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_FILTER_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_FILTER_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_FILTER_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_NEIGH_DIS 5:5 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_NEIGH_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_NEIGH_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_NEIGH_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_PREPROCESS_DIS 6:6 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_PREPROCESS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_PREPROCESS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_PREPROCESS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_PREHEVC_DIS 7:7 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_PREHEVC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_PREHEVC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_PREHEVC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_RECONST_DIS 8:8 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_RECONST_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_RECONST_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_RECONST_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_TU_DIS 9:9 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_TU_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_TU_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_TU_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLATE_DIS 10:10 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLATE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLATE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLATE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CONTROL_DIS 11:11 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CONTROL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CONTROL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CONTROL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CALC_DIS 12:12 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CALC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CALC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_CALC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_MEM_DIS 13:13 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_MEM_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_MEM_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COLLECT_MEM_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COMBINE_DIS 14:14 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COMBINE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COMBINE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_COMBINE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FETCH_DIS 15:15 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FETCH_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FETCH_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FETCH_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FIR_0_DIS 16:16 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FIR_0_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FIR_0_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FIR_0_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FIR_1_DIS 17:17 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FIR_1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FIR_1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_FIR_1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_MEM_DIS 18:18 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_MEM_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_MEM_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_MEM_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_OBMC_DIS 19:19 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_OBMC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_OBMC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_OBMC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_PAD_DIS 20:20 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_PAD_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_PAD_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_PAD_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_RECIEVE_DIS 21:21 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_RECIEVE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_RECIEVE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_RECIEVE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_SHIFT_DIS 22:22 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_SHIFT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_SHIFT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_SHIFT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_UNIT_DIS 23:23 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_UNIT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_UNIT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTER_UNIT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_DMA_DIS 24:24 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_TILE_INFO_ALLOC_DIS 25:25 /* RW-VF */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_TILE_INFO_ALLOC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_TILE_INFO_ALLOC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG7_SLCG_PRED_INTRA_TILE_INFO_ALLOC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8 0x00065800 /* RW-4R */ #define NV_CNVDEC_CG8_SLCG 31:0 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG8_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_BYPASS_CTRL_DIS 0:0 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_DBLK_BYPASS_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_BYPASS_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_DBLK_BYPASS_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_CB_R_DIS 1:1 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_CB_R_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_CB_R_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_CB_R_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_CB_S_DIS 2:2 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_CB_S_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_CB_S_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_CB_S_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_LB_R_DIS 3:3 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_LB_R_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_LB_R_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_LB_R_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_LB_S_DIS 4:4 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_LB_S_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_LB_S_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_DBLK_DMA_LB_S_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_GENPP_CTRL_DIS 5:5 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_DBLK_GENPP_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_GENPP_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_DBLK_GENPP_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_GENSAO_CTRL_DIS 6:6 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_DBLK_GENSAO_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_DBLK_GENSAO_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_DBLK_GENSAO_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_COMB_TUS_DIS 7:7 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_COMB_TUS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_COMB_TUS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_COMB_TUS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_PRE_CTRLS_DIS 8:8 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_PRE_CTRLS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_PRE_CTRLS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_PRE_CTRLS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_FLAT_SKIP_DIS 9:9 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_FLAT_SKIP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_FLAT_SKIP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_FLAT_SKIP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_FLAT_TUS_DIS 10:10 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_FLAT_TUS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_FLAT_TUS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_FLAT_TUS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_CTRL_DIS 11:11 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_DIS 12:12 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_UNPACK_DIS 13:13 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_UNPACK_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_UNPACK_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_HOR_UNPACK_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_CTRLS_DIS 14:14 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_CTRLS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_CTRLS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_CTRLS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_MVS_DIS 15:15 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_MVS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_MVS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_MVS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_PIXELS_DIS 16:16 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_PIXELS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_PIXELS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_PIXELS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_TUS_DIS 17:17 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_TUS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_TUS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_READ_TUS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_VER_CTRL_DIS 18:18 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_VER_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_VER_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_VER_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_VER_DIS 19:19 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILTER_VER_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILTER_VER_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILTER_VER_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILM_GRAIN_DIS 20:20 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_FILM_GRAIN_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_FILM_GRAIN_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_FILM_GRAIN_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_SAO_PREP_DIS 21:21 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_SAO_PREP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_SAO_PREP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_SAO_PREP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_SAO_FILTER_DIS 22:22 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_SAO_FILTER_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_SAO_FILTER_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_SAO_FILTER_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_DIS 23:23 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_HOR_SYNC_DIS 24:24 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_HOR_SYNC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_HOR_SYNC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_HOR_SYNC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_VER_SYNC_DIS 25:25 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_VER_SYNC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_VER_SYNC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_CDEF_CTRL_VER_SYNC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_FINDDIR_DIS 26:26 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_CDEF_FINDDIR_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_FINDDIR_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_CDEF_FINDDIR_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PARAMS_DIS 27:27 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_CDEF_PARAMS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PARAMS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PARAMS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PREP_DIS 28:28 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_CDEF_PREP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PREP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PREP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PROC_DIS 29:29 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_CDEF_PROC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PROC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_CDEF_PROC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_HUS_BLKINFO_DIS 30:30 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_HUS_BLKINFO_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_HUS_BLKINFO_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_HUS_BLKINFO_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_HUS_CTRL_DIS 31:31 /* RW-VF */ #define NV_CNVDEC_CG8_SLCG_HUS_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG8_SLCG_HUS_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG8_SLCG_HUS_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9 0x00065900 /* RW-4R */ #define NV_CNVDEC_CG9_SLCG 31:0 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG9_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_OUTPUT_DIS 0:0 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_HUS_OUTPUT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_OUTPUT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_HUS_OUTPUT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_PIPE_DIS 1:1 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_HUS_PIPE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_PIPE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_HUS_PIPE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_PREP_DIS 2:2 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_HUS_PREP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_PREP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_HUS_PREP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_SBINFO_DIS 3:3 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_HUS_SBINFO_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_SBINFO_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_HUS_SBINFO_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_SCALE_DIS 4:4 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_HUS_SCALE_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_SCALE_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_HUS_SCALE_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_SWITCH_DIS 5:5 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_HUS_SWITCH_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_SWITCH_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_HUS_SWITCH_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_CTRL_DIS 6:6 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_LR_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_LR_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_OUTPUT_DIS 7:7 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_LR_OUTPUT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_OUTPUT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_LR_OUTPUT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_PROC_DIS 8:8 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_LR_PROC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_PROC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_LR_PROC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_SGR_DIS 9:9 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_LR_SGR_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_SGR_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_LR_SGR_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_WIENER_DIS 10:10 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_LR_WIENER_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_WIENER_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_LR_WIENER_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_HIST_DIS 11:11 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_PP_HIST_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_HIST_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_PP_HIST_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_OUTPUT_DIS 12:12 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_PP_OUTPUT_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_OUTPUT_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_PP_OUTPUT_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_OUTPUT_FGS_DIS 13:13 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_PP_OUTPUT_FGS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_OUTPUT_FGS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_PP_OUTPUT_FGS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_PROC_DIS 14:14 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_PP_PROC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_PROC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_PP_PROC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_PROC_FGS_DIS 15:15 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_PP_PROC_FGS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_PROC_FGS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_PP_PROC_FGS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_CDEF_LEFTBUF_DMA_DIS 16:16 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_CDEF_LEFTBUF_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_CDEF_LEFTBUF_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_CDEF_LEFTBUF_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_DBLK_LEFTBUF_DMA_DIS 17:17 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_DBLK_LEFTBUF_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_DBLK_LEFTBUF_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_DBLK_LEFTBUF_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_DBLK_TOPBUF_DMA_DIS 18:18 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_DBLK_TOPBUF_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_DBLK_TOPBUF_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_DBLK_TOPBUF_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FGS_LEFTBUF_DMA_DIS 19:19 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_FGS_LEFTBUF_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FGS_LEFTBUF_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_FGS_LEFTBUF_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FGS_NOISE_DMA_DIS 20:20 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_FGS_NOISE_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FGS_NOISE_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_FGS_NOISE_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_DMA_MUX_DIS 21:21 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_FILTER_DMA_MUX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_DMA_MUX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_FILTER_DMA_MUX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_LEFTBUF_DMA_DIS 22:22 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_HUS_LEFTBUF_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_HUS_LEFTBUF_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_HUS_LEFTBUF_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_LEFTBUF_DMA_DIS 23:23 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_LR_LEFTBUF_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_LR_LEFTBUF_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_LR_LEFTBUF_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_HIST_DMA_DIS 24:24 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_PP_HIST_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_PP_HIST_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_PP_HIST_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_SAO_LEFTBUF_DMA_DIS 25:25 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_SAO_LEFTBUF_DMA_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_SAO_LEFTBUF_DMA_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_SAO_LEFTBUF_DMA_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_CALC_CTRLS_DIS 26:26 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_FILTER_CALC_CTRLS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_CALC_CTRLS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_FILTER_CALC_CTRLS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_AV1_DP_DIS 27:27 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_AV1_DP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_AV1_DP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_AV1_DP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_HEVC_DP_DIS 28:28 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_HEVC_DP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_HEVC_DP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_HEVC_DP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_MUX_DIS 29:29 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_MUX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_MUX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_FILTER_VER_MUX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_HOR_MUX_DIS 30:30 /* RW-VF */ #define NV_CNVDEC_CG9_SLCG_FILTER_HOR_MUX_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG9_SLCG_FILTER_HOR_MUX_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG9_SLCG_FILTER_HOR_MUX_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10 0x00065a00 /* RW-4R */ #define NV_CNVDEC_CG10_SLCG 31:0 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_DISABLED 0xffffffff /* RWI-V */ #define NV_CNVDEC_CG10_SLCG__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_FILTER_HOR_AV1_DP_DIS 0:0 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_FILTER_HOR_AV1_DP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_FILTER_HOR_AV1_DP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_FILTER_HOR_AV1_DP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_FILTER_HOR_HEVC_DP_DIS 1:1 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_FILTER_HOR_HEVC_DP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_FILTER_HOR_HEVC_DP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_FILTER_HOR_HEVC_DP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_HEVC_DIS 2:2 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_HEVC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_HEVC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_HEVC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_AV1_DIS 3:3 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_AV1_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_AV1_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_FILTER_CALC_CTRLS_AV1_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_TILE_INFO_ALLOC_DIS 4:4 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_TILE_INFO_ALLOC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_TILE_INFO_ALLOC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_TILE_INFO_ALLOC_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_SAO_CTRL_DIS 5:5 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_SAO_CTRL_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_SAO_CTRL_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_SAO_CTRL_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_HUS_CTRL_PREP_DIS 6:6 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_HUS_CTRL_PREP_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_HUS_CTRL_PREP_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_HUS_CTRL_PREP_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_HUS_CTRL_MID_DIS 7:7 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_HUS_CTRL_MID_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_HUS_CTRL_MID_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_HUS_CTRL_MID_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_TFC_WR_ACK_DIS 8:8 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_TFC_WR_ACK_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_TFC_WR_ACK_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_TFC_WR_ACK_DIS__PROD 0x00000001 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_TFC_PROC_DIS 9:9 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_TFC_PROC_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_TFC_PROC_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_TFC_PROC_DIS__PROD 0x00000001 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_LR_PARAMS_DIS 10:10 /* RW-VF */ #define NV_CNVDEC_CG10_SLCG_LR_PARAMS_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG10_SLCG_LR_PARAMS_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG10_SLCG_LR_PARAMS_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_CG_SLCG_CTRL 0x00065f00 /* RW-4R */ #define NV_CNVDEC_CG_SLCG_CTRL_SLCG_IDLE_DLY 8:0 /* RWIVF */ #define NV_CNVDEC_CG_SLCG_CTRL_SLCG_IDLE_DLY_RSTVAL 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG_SLCG_CTRL_IDLE_SLCG_DIS 9:9 /* RWIVF */ #define NV_CNVDEC_CG_SLCG_CTRL_IDLE_SLCG_DIS_ENABLED 0x00000000 /* RW--V */ #define NV_CNVDEC_CG_SLCG_CTRL_IDLE_SLCG_DIS_DISABLED 0x00000001 /* RWI-V */ #define NV_CNVDEC_CG_SLCG_CTRL_IDLE_SLCG_DIS__PROD 0x00000000 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF 0x00066000 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL 5:0 /* RWIUF */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_COLMVDATA_DMA2MVD_AV1 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_COLMVDATA_DMA2MVD 0x00000001 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_COLMVDATA_MVD2DMA_AV1 0x00000002 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_COLMVDATA_MVD2DMA 0x00000003 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_COLOC_CTRL_OUT 0x00000004 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_COLOC_MV_REF_PIC_BASE 0x00000005 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_DMA2STREAMIF_DATA 0x00000006 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2FILTER_CTB_CTRL 0x00000007 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2INTRA_PALETTE_DATA 0x00000008 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2INTRA_TILE_INFO 0x00000009 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2IQT_COEFF 0x00000010 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2IQT_TU_CTRL 0x00000011 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2LR_CB_PARAMS 0x00000012 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2LR_CR_PARAMS 0x00000013 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP2LR_PARAMS 0x00000014 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP_DMA2FBIF_RD 0x00000015 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_EP_DMA2FBIF_WR 0x00000016 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_GLOBAL_MODEL_DMA2MVD 0x00000017 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_MVD2PREFETCH_CUCTRL 0x00000018 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_MVD2PREFETCH_MVCTRL 0x00000019 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_PROB_TABLE_IN 0x00000020 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_PROB_TABLE_OUT 0x00000021 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_SEGMENT_IN 0x00000022 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_SEGMENT_OUT 0x00000023 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_STREAM_FIFO 0x00000024 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_STREAMIF2SA_DATA 0x00000025 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_TEMPORAL_REQ 0x00000026 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_TILE_SIZE_FIFO 0x00000027 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_INTF_SEL_TILE_OFFSET 0x00000028 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTB_GOLDEN_0 0x00066100 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTB_GOLDEN_0_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTB_GOLDEN_1 0x00066200 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTB_GOLDEN_1_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTB_GOLDEN_2 0x00066300 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTB_GOLDEN_2_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTB_GOLDEN_3 0x00066400 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTB_GOLDEN_3_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP 0x00066500 /* R--4R */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C0 0:0 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C0_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C0_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C1 1:1 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C1_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C1_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C2 2:2 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C2_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C2_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C3 3:3 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C3_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTB_COMP_C3_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTB_CONTROL 0x00066600 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTB_CONTROL_EN 0:0 /* RWIUF */ #define NV_CNVDEC_DBG_CRC_PARTB_CONTROL_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBG_CRC_PARTB_CONTROL_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF 0x00066800 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL 5:0 /* RWIUF */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTER_CU_CTRL_DATA0 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTER_CU_CTRL_DATA1 0x00000001 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_FB2REC_IQT_QMATRIX_DATA 0x00000002 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2RFETCH_FETCH_CTRL 0x00000003 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_IQT2DMA_DATA 0x00000004 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_IQT2INTRA_RESIDUAL 0x00000005 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_IQT2INTRA_TU_CTRL 0x00000006 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_IQTDMA2FBIF_RD_REQ 0x00000007 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTER_MV_CTRL 0x00000008 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTER_PART_CTRL 0x00000009 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_PREFETCH2INTRA_CU_CTRL 0x00000010 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_INTF_SEL_IQT2INTER_TU_CTRL 0x00000011 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTC_GOLDEN_0 0x00066900 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTC_GOLDEN_0_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTC_GOLDEN_1 0x00066a00 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTC_GOLDEN_1_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTC_GOLDEN_2 0x00066b00 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTC_GOLDEN_2_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTC_GOLDEN_3 0x00066c00 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTC_GOLDEN_3_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP 0x00066d00 /* R--4R */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C0 0:0 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C0_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C0_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C1 1:1 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C1_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C1_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C2 2:2 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C2_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C2_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C3 3:3 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C3_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTC_COMP_C3_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTC_CONTROL 0x00066e00 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTC_CONTROL_EN 0:0 /* RWIUF */ #define NV_CNVDEC_DBG_CRC_PARTC_CONTROL_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBG_CRC_PARTC_CONTROL_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF 0x00067000 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL 5:0 /* RWIUF */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_INTER2FILTER_CU_CTRL 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_DMA2INTRA_DATA 0x00000001 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_INTRA2DMA_DATA 0x00000002 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_INTRA2FILTER_TILE_INFO 0x00000003 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_INTRADMA2FBIF_RD_REQ 0x00000004 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_INTRADMA2FBIF_WR 0x00000005 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_INTER2FILTER_MV_CTRL 0x00000006 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_RECON2FILTER_DATA 0x00000007 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_TILEINFO 0x00000008 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_INTF_SEL_INTER2FILTER_TU_CTRL 0x00000009 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTD_GOLDEN_0 0x00067100 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTD_GOLDEN_0_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTD_GOLDEN_1 0x00067200 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTD_GOLDEN_1_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTD_GOLDEN_2 0x00067300 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTD_GOLDEN_2_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTD_GOLDEN_3 0x00067400 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTD_GOLDEN_3_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP 0x00067500 /* R--4R */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C0 0:0 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C0_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C0_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C1 1:1 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C1_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C1_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C2 2:2 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C2_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C2_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C3 3:3 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C3_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTD_COMP_C3_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTD_CONTROL 0x00067600 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTD_CONTROL_EN 0:0 /* RWIUF */ #define NV_CNVDEC_DBG_CRC_PARTD_CONTROL_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBG_CRC_PARTD_CONTROL_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF 0x00067800 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL 5:0 /* RWIUF */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2CDEF_COL_DATA 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_CDEF2DMA_COL_DATA 0x00000001 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DBLK2DMA_TILE_INFO 0x00000002 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2DBLK_LEFT_NB 0x00000003 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DBLK2DMA_LEFT_NB 0x00000004 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2DBLK_TOP_NB 0x00000005 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DBLK2DMA_TOP_NB 0x00000006 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2FGS_COL_DATA 0x00000007 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_FGSPARAMIN 0x00000008 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_FGS2DMA_COL_DATA 0x00000009 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2TFC_FGS_CTRL 0x00000010 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2TFC_FGS_DATA 0x00000011 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2HUS_COL_DATA 0x00000012 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_HUS2DMA_COL_DATA 0x00000013 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_INTRABC_SYNC 0x00000014 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2LR_COL_DATA 0x00000015 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_LR2DMA_COL_DATA 0x00000016 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2DMA_HISTOGRAM_DATA 0x00000017 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2TFC_CTRL 0x00000018 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_PP2TFC_DATA 0x00000019 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_DMA2SAO_LEFT_COLUMN_DATA 0x00000020 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_SAO2DMA_LEFT_COLUMN_DATA 0x00000021 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_TFC_RPT 0x00000022 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_HUS2DMA_COL_DATA_SIZE 0x00000023 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_FILTERDMA_MUX_DMA2FBIF_WR 0x00000024 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_INTF_SEL_FILTERDMA_MUX_DMA2FBIF_RD 0x00000025 /* RW--V */ #define NV_CNVDEC_DBG_CRC_PARTE_GOLDEN_0 0x00067900 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTE_GOLDEN_0_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTE_GOLDEN_1 0x00067a00 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTE_GOLDEN_1_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTE_GOLDEN_2 0x00067b00 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTE_GOLDEN_2_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTE_GOLDEN_3 0x00067c00 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTE_GOLDEN_3_VAL 31:0 /* RW-UF */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP 0x00067d00 /* R--4R */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C0 0:0 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C0_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C0_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C1 1:1 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C1_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C1_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C2 2:2 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C2_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C2_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C3 3:3 /* R--UF */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C3_PASS 0x00000001 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTE_COMP_C3_FAIL 0x00000000 /* R---V */ #define NV_CNVDEC_DBG_CRC_PARTE_CONTROL 0x00067e00 /* RW-4R */ #define NV_CNVDEC_DBG_CRC_PARTE_CONTROL_EN 0:0 /* RWIUF */ #define NV_CNVDEC_DBG_CRC_PARTE_CONTROL_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_DBG_CRC_PARTE_CONTROL_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_AVD_SWREG84 0x00068000 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG84_SUBSTREAM_OFFSET 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG85 0x00068100 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG85_LAST_SUBSTREAM_IN_FRAME 0:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG86 0x00068200 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG86_SUBSTREAM_FIRST_TILE_IDX 7:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG86_SUBSTREAM_LAST_TILE_IDX 15:8 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG87 0x00068300 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG87_TILEINFO_BASE_MSB 31:0 /* RWXVF */ #define NV_CNVDEC_AVD_SWREG88 0x00068400 /* RW-4R */ #define NV_CNVDEC_AVD_SWREG88_DEC_VERT_HUS_PONG_OFFSET 31:0 /* RWXVF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON 0x00080000 /* RW-4R */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_WIDTH_IN_MBS 7:0 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_FRAME_HEIGHT_IN_MBS 15:8 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_TYPE 17:16 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_TYPE_FRAME 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_TYPE_TOP_FIELD 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_TYPE_BOTTOM_FIELD 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING 19:18 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG_D 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG_I 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG_B 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VC1_SKIPPED 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VC1_I_OR_BI 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VC1_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VC1_B 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG4_SKIPPED 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG4_I 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG4_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_MPEG4_B 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VP8_I 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PIC_CODING_VP8_P 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE 22:20 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_MPEG1 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_MPEG2 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_VC1 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_H264 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_MPEG4 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_STREAM_TYPE_VP8 0x00000005 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PROFILE 25:24 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PROFILE_VC1_SIMPLE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PROFILE_VC1_MAIN 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PROFILE_VC1_ADVANCED 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_PROFILE_MPEG4_SHORT_HEADER 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_SSM_EN 26:26 /* RWIVF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_SSM_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_SSM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA 27:27 /* RWIVF */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA_OFF 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_SSM_EXPLICITEOSFLAG_CYA_ON 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_PIC_INFO_COMMON_CHROMA_FORMAT_IDC 29:28 /* RWIVF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264 0x00080100 /* RW-4R */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_CABAC 0:0 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_CABAC_CAVLC 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_CABAC_CABAC 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_MBAFF_FRAME_FLAG 9:9 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_NALUNIT_TYPE 16:12 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_CONSTRAINED_INTRA_PRED_FLAG 17:17 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_CABAC_INIT_IDC 19:18 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_CHROMA_FORMAT_IDC 21:20 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_DIRECT_8X8_INFERENCE_FLAG 22:22 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_TRANSFORM_8X8_MODE_FLAG 23:23 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_H264_BITDEPTH_MINUS_8 27:24 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2 0x00080200 /* RW-4R */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2_INTRA_DC_PRECISION 1:0 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2_FRAME_PRED_FRAME_DCT 2:2 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2_INTRA_VLC_FORMAT 3:3 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2_CONCEALMENT_MOTION_VEC 4:4 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2_F_CODE00 19:16 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2_F_CODE01 23:20 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2_F_CODE10 27:24 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_MPEG2_F_CODE11 31:28 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB 0x00080300 /* RW-4R */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_SLICE_ADDR 6:0 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_NUM_REF 7:7 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_NUM_REF_ONE_REF_PIC 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_NUM_REF_TWO_REF_PIC 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_FCM 9:8 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_FCM_PROGRESSIVE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_FCM_FRAME_INTERLACE 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_FCM_FIELD_INTERLACE 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_FCM_MPEG4_INTERLACE 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_REF_DIST 11:10 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_REF_FIELD 12:12 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_REF_FIELD_TEMP_CLOSEST 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_REF_FIELD_SECOND_MOST_TEMP_CLOSEST 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_FIELD_TX 16:16 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_FIELD_TX_RAW 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_FIELD_TX_BITPLANE 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1GB_SLICE_ADDRX 31:24 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T 0x00080400 /* RW-4R */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_CBP_TAB 2:0 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_MV_TAB 6:4 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TWO_MV_BP_TAB 9:8 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_FOUR_MV_BP_TAB 11:10 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_MB_MODE_TAB 14:12 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_DC_TAB 16:16 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_DC_TAB_LOW_MOTION 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_DC_TAB_HIGH_MOTION 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_ESC_LVL_SZ_TAB 17:17 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_ESC_LVL_SZ_TAB_TABLE59 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_ESC_LVL_SZ_TAB_TABLE60 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1 21:20 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1_HIGH_RATE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1_LOW_MOTION 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1_HIGH_MOTION 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB1_MID_RATE 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2 23:22 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2_HIGH_RATE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2_LOW_MOTION 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2_HIGH_MOTION 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1T_TRANS_AC_TAB2_MID_RATE 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q 0x00080500 /* RW-4R */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_FRAME 0:0 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_BINARY_LEVEL 1:1 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE 3:2 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_4_EDGE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_2_EDGE 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_1_EDGE 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_PROFILE_ALL_MB 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_DIFFERENTIAL_QUANTIZER_SDB_EDGE 5:4 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_PICTURE_QUANTIZER_STEP 20:16 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1Q_ALT_PICTURE_QUANTIZER_STEP 28:24 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P 0x00080600 /* RW-4R */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE 1:0 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE_NORM_HORZ_NORM_VERT 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE_EXT_HORZ_NORM_VERT 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE_NORM_HORZ_EXT_VERT 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_DMV_RANGE_EXT_HORZ_EXT_VERT 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_MV_RANGE 3:2 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE 5:4 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE_MIXED_MV 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE_1_MV 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE_1_MV_HALF_PEL 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_MV_MODE_1_MV_HALF_PEL_BILINEAR 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE 7:6 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_8X8 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_8X4 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_4X8 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_FRAME_LEVEL_TRANSFORM_TYPE_4X4 0x00000003 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_TRANSFORM_TYPE_FLAG 8:8 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_TRANSFORM_TYPE_FLAB_MB_LEVEL 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_TRANSFORM_TYPE_FLAB_FRAME_LEVEL 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_FOUR_MV_SWITCH 9:9 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_COND_OVER_MB 10:10 /* RWXUF */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_COND_OVER_MB_PICTURE_LEVEL 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_COND_OVER_MB_MB_LEVEL 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_PIC_INFO_VC1P_SYNCMARKER 11:11 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO 0x00080700 /* RW-4R */ #define NV_CNVDEC_VLD1_SLICE_INFO_SLICE_TYPE 1:0 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SLICE_TYPE_P 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SLICE_TYPE_B 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SLICE_TYPE_I 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SLICE_NUM 14:2 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_NUM_REF_IDXL0_ACTIVE_MINUS1 19:15 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_NUM_REF_IDXL1_ACTIVE_MINUS1 24:20 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SLICE_QPY 30:25 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_ROWXPICWIDTH_MBS 14:2 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SLICE_ROW 22:15 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_QUANT_SCALE_CODE 29:25 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_EXT 0x00080800 /* RW-4R */ #define NV_CNVDEC_VLD1_SLICE_INFO_EXT_SLICE_NUM 2:0 /* RWXUF */ #define NV_CNVDEC_VLD1_EDOB_MB_INFO 0x00080900 /* RW-4R */ #define NV_CNVDEC_VLD1_EDOB_MB_INFO_MB_ADDR 15:0 /* RWXUF */ #define NV_CNVDEC_VLD1_EDOB_MB_INFO_SLICE_FIRST_MB_FLAG 16:16 /* RWXUF */ #define NV_CNVDEC_VLD1_EDOB_MB_INFO_MB_RSTN 17:17 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC 0x00080a00 /* RW-4R */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_BASE_MODE 1:0 /* RWIUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_BASE_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_BASE_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_BASE_MODE_ADAPTIVE 0x00000002 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_RES_PRED 3:2 /* RWIUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_RES_PRED_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_RES_PRED_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_RES_PRED_ADAPTIVE 0x00000002 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_MOTION_PRED 5:4 /* RWIUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_MOTION_PRED_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_MOTION_PRED_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_MOTION_PRED_ADAPTIVE 0x00000002 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CBP_PRED 6:6 /* RWIUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CBP_PRED_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CBP_PRED_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_ACSCANSTARTADJ 7:7 /* RWIUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_ACSCANSTARTADJ_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_ACSCANSTARTADJ_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_SCAN_START 11:8 /* RWIUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_SCAN_START_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_SCAN_END 15:12 /* RWIUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_SCAN_END_INIT 0x0000000f /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_SKIP_MAX 28:16 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_SKIP 29:29 /* RWIUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_SKIP_DISABLED 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_SKIP_ENABLED 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP 0x00080b00 /* RW-4R */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP_XMIN 7:0 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP_XMIN_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP_XMAX 15:8 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP_XMAX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP_YMIN 23:16 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP_YMIN_INIT 0x00000001 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP_YMAX 31:24 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO_SVC_CROP_YMAX_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_EDOB_MB_POS 0x00080c00 /* RW-4R */ #define NV_CNVDEC_VLD1_EDOB_MB_POS_MB_X 7:0 /* RWXUF */ #define NV_CNVDEC_VLD1_EDOB_MB_POS_MB_Y 15:8 /* RWXUF */ #define NV_CNVDEC_VLD1_MB_INFO 0x00080d00 /* RW-4R */ #define NV_CNVDEC_VLD1_MB_INFO_MB_ADDR 15:0 /* RWXUF */ #define NV_CNVDEC_VLD1_MB_INFO_SLICE_FIRST_MB_FLAG 16:16 /* RWXUF */ #define NV_CNVDEC_VLD1_MB_POS 0x00080e00 /* RW-4R */ #define NV_CNVDEC_VLD1_MB_POS_MB_X 7:0 /* RWXUF */ #define NV_CNVDEC_VLD1_MB_POS_MB_Y 15:8 /* RWXUF */ #define NV_CNVDEC_VLD1_PARSE_CMD 0x00080f00 /* -W-4R */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD 4:0 /* -WXUF */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_UE 0x00000000 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_SE 0x00000001 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_U 0x00000002 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_NAL_HEAD 0x00000003 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_VP8_PIC_HEAD 0x00000003 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_BYTE_ALIGNED 0x00000004 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_MORE_RBSP_DATA 0x00000005 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_MB_SKIP_FLAG_AE 0x00000006 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_END_OF_SLICE_FLAG_AE 0x00000007 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_START_CABAC_INIT 0x00000008 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_SKIP_MB 0x00000009 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_NON_SKIP_MB 0x0000000a /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_PARSE_PRED_WEIGHT_TABLE 0x0000000b /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_H264_PARSE_SLICE_DATA 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_VC1_PARSE_MACROBLOCKS 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_MPEG2_PARSE_SLICEDATA 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_VP8_PARSE_PICDATA 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_MPEG2_RESERVED 0x0000000d /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_MPEG2_NEXT_BITS 0x0000000e /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_MPEG2_PARSE_PICTURE_DATA 0x0000000f /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_VC1_PARSE_PICTURE_HEADER 0x00000010 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_VC1_PARSE_BITPLANE 0x00000011 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_SEND_EOS 0x00000012 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_INSERT_ERROR_MB 0x00000013 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_CMD_NOP 0x00000014 /* -WX-V */ #define NV_CNVDEC_VLD1_PARSE_CMD_PARAM 10:5 /* -WXUF */ #define NV_CNVDEC_VLD1_PARSE_CMD_PARAM_READ_MB_FIELD_DECODE_FLAG 5:5 /* -WXUF */ #define NV_CNVDEC_VLD1_PARSE_CMD_PARAM_VC1_TARGET_PLANE 6:5 /* -WXUF */ #define NV_CNVDEC_VLD1_STATUS 0x00081000 /* R--4R */ #define NV_CNVDEC_VLD1_STATUS_BUSY 0:0 /* R-XUF */ #define NV_CNVDEC_VLD1_STATUS_SLICE_BUSY 1:1 /* R-XUF */ #define NV_CNVDEC_VLD1_STATUS_EDOB_BUSY 2:2 /* R-XUF */ #define NV_CNVDEC_VLD1_STATUS_VC1_PIC_BUSY 3:3 /* R-XUF */ #define NV_CNVDEC_VLD1_STATUS_EDOB_NON_EMPTY 4:4 /* R-XUF */ #define NV_CNVDEC_VLD1_STATUS_MEMACC_BUSY 5:5 /* R-XUF */ #define NV_CNVDEC_VLD1_STATUS_FIFOCTRL_BUSY 6:6 /* R-XUF */ #define NV_CNVDEC_VLD1_STATUS_HIST_BUSY 7:7 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT 0x00081100 /* R--4R */ #define NV_CNVDEC_VLD1_RESULT_RESULT_DATA 31:0 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_NAL_UNIT_TYPE 4:0 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_NAL_REF_IDC 6:5 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_FORBIDDEN_ZERO_BIT 7:7 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_COLOR_SPACE 0:0 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_CLAMPING_TYPE 1:1 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_SEGMENTATION_ENABLED 2:2 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_SEGMENT_FEATURE_MODE 3:3 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_FILTER_TYPE 4:4 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_LOOP_FILTER_LEVEL 10:5 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_SHARPNESS_LEVEL 13:11 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_LOG2_NBR_OF_DCT_PARTITIONS 15:14 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_REFRESH_GOLDEN_FRAME 16:16 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_REFRESH_ALTERNATE_FRAME 17:17 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_COPY_BUFFER_TO_GOLDEN 19:18 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_COPY_BUFFER_TO_ALTERNATE 21:20 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_SIGN_BIAS_GOLDEN 22:22 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_SIGN_BIAS_ALTERNATE 23:23 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_REFRESH_ENTROPY_PROB 24:24 /* R-XUF */ #define NV_CNVDEC_VLD1_RESULT_REFRESH_LAST 25:25 /* R-XUF */ #define NV_CNVDEC_VLD1_INTRPT_EN 0x00081200 /* RW-4R */ #define NV_CNVDEC_VLD1_INTRPT_EN_WATCHDOG_TIMER_EN 0:0 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_EN_BUFF_EMPTY_EN 1:1 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_EN_BIT_ERROR_EN 2:2 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_EN_LIMIT_EN 3:3 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_EN_SLICE_DONE_EN 4:4 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_STATUS 0x00081300 /* RW-4R */ #define NV_CNVDEC_VLD1_INTRPT_STATUS_WATCHDOG_TIMER 0:0 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_STATUS_BUFF_EMPTY 1:1 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_STATUS_BIT_ERROR 2:2 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_STATUS_LIMIT 3:3 /* RWXUF */ #define NV_CNVDEC_VLD1_INTRPT_STATUS_SLICE_DONE 4:4 /* RWXUF */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE 0x00081400 /* RW-4R */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE 31:0 /* RWXUF */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_NONE 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_SYNCMARKER 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_CBPCY 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTRA_DCCOEF 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ACCOEF1 0x00000008 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_RLL 0x00000010 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ACCOEF2 0x00000020 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_D_LEVEL 0x00000040 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_D_RUN 0x00000080 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_VLCAC_ESCLVLSZ 0x00000100 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTRA_INVALID_IDX 0x00000200 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_TTBLK 0x00000400 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_SUBBLKPAT 0x00000800 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_SUBBLKPAT_8X4_4X8 0x00001000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_MVDATA 0x00002000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_MB_INTER_INVALID_IDX 0x00004000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_INSUF_BP_BUF 0x00008000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MP4_SLICE_END_MBADDR 0x00010000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_TTMB 0x00020000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_INV_INTRAFLAG_BMV2 0x00040000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_MBMODE 0x00080000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_TWOMVBP 0x00100000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_FOURMVBP 0x00200000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_MVDATA_PF1R 0x00400000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_MVDATA_PF2R 0x00800000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_MIXEDMV 0x01000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_MB_ONEMV 0x02000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_VC1_BP_IMODE6_TABLE81 0x04000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MP4_MB_VIDEOPACKETHEADER 0x08000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MP4_MB_MCBPC 0x00020000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MP4_MB_MODBMBTYPE 0x00040000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MP4_MB_MCBPY 0x00080000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_SLICE_END 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_ADDR_INC 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MB_TYPE 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MT_TYPE 0x00000008 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MVX_GET 0x00000010 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MVY_GET 0x00000020 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_CBP_GET 0x00000040 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_QFS_GET 0x00000080 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_MB_MARKER_BIT 0x00000100 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_NB_PARAM 0x00000200 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MPG_SKIP_MBS 0x00000400 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_SLICE_END_AT_SMALLER_MB_ADDR 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_SKIP_RUN 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_I_SLICE 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_P_SLICE 0x00000008 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_B_SLICE 0x00000010 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_SI_SLICE 0x00000020 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_TYPE_RANGE_EXCEEDED_FOR_SP_SLICE 0x00000040 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_MB_QP_DELTA_OUT_OF_RANGE 0x00000080 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_RESIDUAL_COEFF_COUNT 0x00000100 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_TYPE 0x00000200 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_MB_REF_IDX_L0 0x00000400 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_MB_REF_IDX_L1 0x00000800 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_REF_IDX_L0 0x00001000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_SUB_MB_REF_IDX_L1 0x00002000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN0 0x00004000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN1 0x00008000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN2 0x00010000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOKEN3 0x00020000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_TOTAL_ZEROS 0x00040000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_VLC_RUN_BEFORE 0x00080000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_FIXED_PTRN_BIT_STRING 0x00100000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_INVALID_CODED_BLOCK_PATTERN 0x00200000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_LARGE_LUMA_LOG_WD 0x00400000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_LARGE_CHR_LOG_WD 0x00800000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_LUMA_WEIGHT 0x01000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_LUMA_OFFSET 0x02000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_CHROMA_WEIGHT 0x04000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_H264_WT_PRED_INVALID_CHROMA_OFFSET 0x08000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_VP8_BUFF2GOLD 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_VP8_BUFF2ALT 0x00000002 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_VP8_INVALID_TOKEN 0x00000004 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_VP8_EXCEED_TOKEN_LIMIT 0x00000008 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_VP8_ZERO_NO_EOB 0x00000010 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_EXCEED_SLICE_OFFSET_LIMIT 0x10000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_MB_DATA_EXCEED_EDOB_FIFO_LIMIT 0x20000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_UNCLASSIFIED 0x40000000 /* RWX-V */ #define NV_CNVDEC_VLD1_BIT_ERROR_CODE_CODE_SW_ERROR 0x80000000 /* RWX-V */ #define NV_CNVDEC_VLD1_SCP_CFG 0x00081500 /* RW-4R */ #define NV_CNVDEC_VLD1_SCP_CFG_PARSE_CMD_MODE 16:16 /* R-IUF */ #define NV_CNVDEC_VLD1_SCP_CFG_PARSE_CMD_MODE_INSECURE 0x00000000 /* R-I-V */ #define NV_CNVDEC_VLD1_SCP_CFG_PARSE_CMD_MODE_SECURE 0x00000001 /* R---V */ #define NV_CNVDEC_VLD1_TIMEOUT_VALUE 0x00081600 /* RW-4R */ #define NV_CNVDEC_VLD1_TIMEOUT_VALUE_MB_DECODE_TIMEOUT 31:0 /* RWXUF */ #define NV_CNVDEC_VLD1_RESET_CTL 0x00081700 /* RW-4R */ #define NV_CNVDEC_VLD1_RESET_CTL_SOFT_RESET 0:0 /* -WXUF */ #define NV_CNVDEC_VLD1_RESET_CTL_HARD_RESET 1:1 /* -WXUF */ #define NV_CNVDEC_VLD1_RESET_CTL_SLICE_RESET 2:2 /* -WXUF */ #define NV_CNVDEC_VLD1_IDMA_BUFF_A(i) (0x00081800+(i)*512) /* RW-4A */ #define NV_CNVDEC_VLD1_IDMA_BUFF_A__SIZE_1 4 /* */ #define NV_CNVDEC_VLD1_IDMA_BUFF_A_COUNT 23:0 /* RWXUF */ #define NV_CNVDEC_VLD1_IDMA_BUFF_A_ADDR_HIGH 31:24 /* RWXUF */ #define NV_CNVDEC_VLD1_IDMA_BUFF_B(i) (0x00081900+(i)*512) /* RW-4A */ #define NV_CNVDEC_VLD1_IDMA_BUFF_B__SIZE_1 4 /* */ #define NV_CNVDEC_VLD1_IDMA_BUFF_B_VALID 0:0 /* RWXUF */ #define NV_CNVDEC_VLD1_IDMA_BUFF_B_ENCRYPT 1:1 /* RWXUF */ #define NV_CNVDEC_VLD1_IDMA_BUFF_B_ADDR_LOW 31:2 /* RWXUF */ #define NV_CNVDEC_VLD1_CURR_IDMA_INFO 0x00082800 /* RW-4R */ #define NV_CNVDEC_VLD1_CURR_IDMA_INFO_CURR_IDMA_BIT_INDEX 2:0 /* RWXUF */ #define NV_CNVDEC_VLD1_CURR_IDMA_INFO_CURR_IDMA_BUFF_OFFSET 26:3 /* RWXUF */ #define NV_CNVDEC_VLD1_CURR_IDMA_INFO_CURR_IDMA_BUFF_INDEX 28:27 /* RWXUF */ #define NV_CNVDEC_VLD1_CLEAR_INPUT_BUFFERS 0x00082900 /* RW-4R */ #define NV_CNVDEC_VLD1_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS 0:0 /* RWXUF */ #define NV_CNVDEC_VLD1_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS_DONE 0x00000000 /* RW--V */ #define NV_CNVDEC_VLD1_CLEAR_INPUT_BUFFERS_CLEAR_BUFFS_FLUSH 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_CLEAR_INPUT_BUFFERS_BUFF_ID 2:1 /* RWXUF */ #define NV_CNVDEC_VLD1_CLEAR_INPUT_BUFFERS_BUFF_ID_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_HIST_START_ADDR 0x00083200 /* RW-4R */ #define NV_CNVDEC_VLD1_HIST_START_ADDR_START_ADDR_HIGH 31:0 /* RWXUF */ #define NV_CNVDEC_VLD1_HIST_SIZE 0x00083300 /* RW-4R */ #define NV_CNVDEC_VLD1_HIST_SIZE_SIZE 11:0 /* RWXUF */ #define NV_CNVDEC_VLD1_HIST_CTL 0x00083400 /* RW-4R */ #define NV_CNVDEC_VLD1_HIST_CTL_ENABLE 0:0 /* RWXUF */ #define NV_CNVDEC_VLD1_HIST_CTL_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_CNVDEC_VLD1_HIST_CTL_ENABLE_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_HIST_CTL_LINEBUF_ENABLE 1:1 /* RWXUF */ #define NV_CNVDEC_VLD1_HIST_CTL_LINEBUF_ENABLE_DIS 0x00000000 /* RW--V */ #define NV_CNVDEC_VLD1_HIST_CTL_LINEBUF_ENABLE_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP 0x00083500 /* -W-4R */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_OFFSET 11:0 /* -WXUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_VRAM_ADDR 0x00000e00 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_VRAM_PARAMS 0x00000e04 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_CBC_PARAMS 0x00000e08 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_SOFT_RESET_CMD 0x00000e0c /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_BDEC_STATE_RESTORE 0x00000e10 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_CTX_MEM_LOAD_CMD 0x00000e14 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_CTX_MEM_LOAD_DATA 0x00000e18 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_CTX_MEM_READ_DATA 0x00000e1c /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_BSEV_RESULT_PUSH_DATA 0x00000e20 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_DEBUG_CONTROL 0x00000e24 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_DEBUG_DATA 0x00000e28 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_OP_RW 12:12 /* -WXUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA 0x00083600 /* RW-4R */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_RESULT_DATA 31:0 /* RWXUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_CTXVAR 0x00000000 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_CMDIF 0x00000002 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_RESIDUAL 0x00000003 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_MBPRED 0x00000004 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_SUBMBPRED 0x00000005 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_VRAMIF 0x00000006 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_DATAIF 0x00000007 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC_BINCTRL0 0x00000008 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC_BINCTRL1 0x00000009 /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC0 0x0000000a /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC1 0x0000000b /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC2 0x0000000c /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_BDEC3 0x0000000d /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_IBIN 0x0000000e /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_CBC_DEBUG_DATA_DEBUG_READBITS 0x0000000f /* -WX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG 0x00083700 /* R--4R */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_MEMACC_ST 2:0 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_FIFOCTRL_ST 5:3 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_MEMACC_REQ0_OUTSTANDING 6:6 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_MEMACC_REQ1_OUTSTANDING 7:7 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_MEMACC_SCP_PKTS_PEND 12:8 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_MB_STATE 17:13 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_RES_BLK_TYPE 20:18 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_CBC_VRAM_PS 24:21 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_DEBUG_CAVLD1_STATE 28:25 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0 0x00083800 /* R--4R */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MB_STATE 7:0 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_CBPCY_STATE 9:8 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MVD_STATE 13:12 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MVDPF1R_STATE 17:16 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MVDPF2R_STATE 21:20 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_MVP_STATE 27:24 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG0_ACP_STATE 29:28 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1 0x00083900 /* R--4R */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_INTRA_STATE 2:0 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_INTER_STATE 6:4 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_VLCAC_STATE 11:8 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_OUTIF_STATE 15:12 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_BP_STATE 18:16 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_VC1_DEBUG1_BP_RD_STATE 21:20 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG 0x00083a00 /* R--4R */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG_MB_STATE 3:0 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG_MBI_STATE 5:4 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG_QFS_STATE 8:6 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPG_DEBUG_OUTIF_STATE 12:9 /* R-XUF */ #define NV_CNVDEC_VLD1_BIT_ERROR_MASK 0x00083b00 /* RW-4R */ #define NV_CNVDEC_VLD1_BIT_ERROR_MASK_MASKFIELD 31:0 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_LIMIT 0x00083c00 /* RW-4R */ #define NV_CNVDEC_VLD1_SLICE_LIMIT_SLICE_BYTE_COUNT 31:0 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_ERROR_CTL 0x00083d00 /* RW-4R */ #define NV_CNVDEC_VLD1_SLICE_ERROR_CTL_NEXT_SLICE_MB_ADDR 16:0 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_ERROR_CTL_SET_SW_ERROR 31:31 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_ERROR_CTL_SET_SW_ERROR_CLR 0x00000000 /* RWX-V */ #define NV_CNVDEC_VLD1_SLICE_ERROR_CTL_SET_SW_ERROR_SET 0x00000001 /* RWX-V */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG 0x00083e00 /* R--4R */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG_MP4_STATE 3:0 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG_MP4IP_STATE 7:4 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG_BP_ILLEGAL_READ 8:8 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_DEBUG_BP_ILLEGAL_WRITE 9:9 /* R-XUF */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY(i,j) (0x00083f00+(i)*256+(j)*4) /* RW-4A */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_1 4 /* */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY__SIZE_2 64 /* */ #define NV_CNVDEC_VLD1_ENTROPYDEC_MPEG4_BITPLANE_MEMORY_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_VLD1_PROBBUF_WRITE_REG 0x00084400 /* RW-4R */ #define NV_CNVDEC_VLD1_PROBBUF_WRITE_REG_DATA 31:0 /* -W-UF */ #define NV_CNVDEC_VLD1_PROBBUF_READ_REG 0x00084500 /* RW-4R */ #define NV_CNVDEC_VLD1_PROBBUF_READ_REG_DATA 31:0 /* R--UF */ #define NV_CNVDEC_VLD1_PROBBUF_RW_OFFSET 0x00084600 /* RW-4R */ #define NV_CNVDEC_VLD1_PROBBUF_RW_OFFSET_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_A(i) (0x00084800+(i)*512) /* RW-4A */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_A__SIZE_1 8 /* */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_A_COUNT 23:0 /* RWXUF */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_A_ADDR_HIGH 31:24 /* RWXUF */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_B(i) (0x00084900+(i)*512) /* RW-4A */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_B__SIZE_1 8 /* */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_B_VALID 0:0 /* RWXUF */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_B_ENCRYPT 1:1 /* RWXUF */ #define NV_CNVDEC_VLD1_IDMA1_BUFF_B_ADDR_LOW 31:2 /* RWXUF */ #define NV_CNVDEC_VLD1_CURR_IDMA1_INFO 0x00085800 /* RW-4R */ #define NV_CNVDEC_VLD1_CURR_IDMA1_INFO_CURR_IDMA_BIT_INDEX 2:0 /* RWXUF */ #define NV_CNVDEC_VLD1_CURR_IDMA1_INFO_CURR_IDMA_BUFF_OFFSET 26:3 /* RWXUF */ #define NV_CNVDEC_VLD1_CURR_IDMA1_INFO_CURR_IDMA_BUFF_INDEX 29:27 /* RWXUF */ #define NV_CNVDEC_VLD1_SEGMENT_ID_START_ADDR 0x00085900 /* RW-4R */ #define NV_CNVDEC_VLD1_SEGMENT_ID_START_ADDR_START_ADDR_HIGH 31:0 /* RWXUF */ #define NV_CNVDEC_VLD1_STREAM_LEN 0x00085a00 /* RW-4R */ #define NV_CNVDEC_VLD1_STREAM_LEN_VALUE 31:0 /* RWXUF */ #define NV_CNVDEC_VLD1_SLICE_INFO2 0x00085b00 /* RW-4R */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_WEIGHTED_PRED_IDC 3:2 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_DIRECT_SPATIAL_MVPRED 4:4 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_SLICE_ALPHAC0_OFFSDIV2 8:5 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_SLICE_BETA_OFFSDIV2 12:9 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_QPY 18:13 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_BOTTOM_IS_CLOSER 19:19 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_BOTTOM_IS_CLOSER_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_REFPIC_IS_BOTTOMFIELD 20:20 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_REFPIC_IS_BOTTOMFIELD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_COLPIC_IS_SHORTTERM 21:21 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_COLPIC_IS_SHORTTERM_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_REFPIC_IS_FIELD 22:22 /* RWXVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_REFPIC_IS_FIELD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_DIS_DEBLOCKING_FLT_IDC 26:24 /* RWIVF */ #define NV_CNVDEC_VLD1_SLICE_INFO2_H264_DIS_DEBLOCKING_FLT_IDC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP(i) (0x00085c00+(i)*256) /* RW-4A */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP__SIZE_1 4 /* */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_0 4:0 /* RWXVF */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_0_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_1 12:8 /* RWXVF */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_1_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_2 20:16 /* RWXVF */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_2_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_3 28:24 /* RWXVF */ #define NV_CNVDEC_VLD1_L0_REFPIC_MAP_REFIDX_3_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP(i) (0x00086000+(i)*256) /* RW-4A */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP__SIZE_1 4 /* */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_0 4:0 /* RWXVF */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_0_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_1 12:8 /* RWXVF */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_1_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_2 20:16 /* RWXVF */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_2_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_3 28:24 /* RWXVF */ #define NV_CNVDEC_VLD1_L1_REFPIC_MAP_REFIDX_3_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_DISTSCALEFACTORS(i) (0x00086400+(i)*256) /* RW-4A */ #define NV_CNVDEC_VLD1_DISTSCALEFACTORS__SIZE_1 8 /* */ #define NV_CNVDEC_VLD1_DISTSCALEFACTORS_REFPIC_0 15:0 /* RWXVF */ #define NV_CNVDEC_VLD1_DISTSCALEFACTORS_REFPIC_0_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_DISTSCALEFACTORS_REFPIC_1 31:16 /* RWXVF */ #define NV_CNVDEC_VLD1_DISTSCALEFACTORS_REFPIC_1_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_MVRCOLADDR 0x00086c00 /* RW-4R */ #define NV_CNVDEC_VLD1_MVRCOLADDR_RCOL_ADDR 31:0 /* RW-UF */ #define NV_CNVDEC_VLD1_MVRCOLPARAM 0x00086d00 /* RW-4R */ #define NV_CNVDEC_VLD1_MVRCOLPARAM_RCOL_LWIDTH 7:0 /* RW-UF */ #define NV_CNVDEC_VLD1_MVRCOLPARAM_RCOL_NLIN 8:8 /* RW-VF */ #define NV_CNVDEC_VLD1_MVRCOLLINE 0x00086e00 /* RW-4R */ #define NV_CNVDEC_VLD1_MVRCOLLINE_RCOL_LREM 7:0 /* RWXUF */ #define NV_CNVDEC_VLD1_MVRCOLLINE_RCOL_LCNT 16:8 /* RWXUF */ #define NV_CNVDEC_VLD1_MVRCOLOFFS 0x00086f00 /* RW-4R */ #define NV_CNVDEC_VLD1_MVRCOLOFFS_RCOL_OFFS 11:0 /* RW-UF */ #define NV_CNVDEC_VLD1_MVRCOLOFFS_RCOL_LODD 12:12 /* RW-VF */ #define NV_CNVDEC_VLD1_MVRCOLOFFS_4K_RCOL_OFFS 15:0 /* RW-UF */ #define NV_CNVDEC_VLD1_MVRCOLOFFS_4K_RCOL_LODD 16:16 /* RW-VF */ #define NV_CNVDEC_VLD1_MVRCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1(i) (0x00087000+(i)*256) /* RW-4A */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1__SIZE_1 64 /* */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_0 7:0 /* RWXVF */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_0_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_1 15:8 /* RWXVF */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_1_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_2 23:16 /* RWXVF */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_2_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_3 31:24 /* RWXVF */ #define NV_CNVDEC_VLD1_PREDWEIGHTTABLEMINUS1_IDX_3_DEFAULT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVLOCAL_MEMORY(i,j) (0x000a0000+(i)*256+(j)*4) /* RW-4A */ #define NV_CNVDEC_MV1_MVLOCAL_MEMORY__SIZE_1 12 /* */ #define NV_CNVDEC_MV1_MVLOCAL_MEMORY__SIZE_2 64 /* */ #define NV_CNVDEC_MV1_MVLOCAL_MEMORY_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVFRMPARAM 0x000a1100 /* RW-4R */ #define NV_CNVDEC_MV1_MVFRMPARAM_PICWIDTHINMBS 7:0 /* RWXUF */ #define NV_CNVDEC_MV1_MVFRMPARAM_PICWIDTHINMBS_1MB 0x00000001 /* RWX-V */ #define NV_CNVDEC_MV1_MVFRMPARAM_PICWIDTHINMBS_256MB 0x00000000 /* RWX-V */ #define NV_CNVDEC_MV1_MVFRMPARAM_PICHEIGHTINMBS 15:8 /* RWXUF */ #define NV_CNVDEC_MV1_MVFRMPARAM_PICHEIGHTINMBS_1MB 0x00000001 /* RWX-V */ #define NV_CNVDEC_MV1_MVFRMPARAM_PICHEIGHTINMBS_256MB 0x00000000 /* RWX-V */ #define NV_CNVDEC_MV1_MVCTRL0 0x000a1400 /* RW-4R */ #define NV_CNVDEC_MV1_MVCTRL0_H264_APPLEOOLD_FLAG 0:0 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL0_H264_APPLEOOLD_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL0_H264_REFPIC_FLAG 1:1 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL0_H264_REFPIC_FLAG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL0_H264_CONSTRAINED_INTRA_PRED 2:2 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL0_H264_CONSTRAINED_INTRA_PRED_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL0_H264_CUR_BOTTOM_FIRST 3:3 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL0_H264_CUR_BOTTOM_FIRST_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL0_H264_CHROMA_QPIDXOFF 8:4 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL0_H264_SEC_CHROMA_QPIDXOFF 13:9 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL0_H264_DIRECT_8X8_INFERENCE_FLAG 14:14 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL0_H264_QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG 15:15 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1 0x000a1500 /* RW-4R */ #define NV_CNVDEC_MV1_MVCTRL1_H264_WEIGHTED_PRED_IDC 3:2 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_DIRECT_SPATIAL_MVPRED 4:4 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_SLICE_ALPHAC0_OFFSDIV2 8:5 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_SLICE_BETA_OFFSDIV2 12:9 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_QPY 18:13 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_BOTTOM_IS_CLOSER 19:19 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_BOTTOM_IS_CLOSER_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL1_H264_REFPIC_IS_BOTTOMFIELD 20:20 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_REFPIC_IS_BOTTOMFIELD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL1_H264_COLPIC_IS_SHORTTERM 21:21 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_COLPIC_IS_SHORTTERM_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL1_H264_REFPIC_IS_FIELD 22:22 /* RWXVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_REFPIC_IS_FIELD_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL1_H264_DIS_DEBLOCKING_FLT_IDC 26:24 /* RWIVF */ #define NV_CNVDEC_MV1_MVCTRL1_H264_DIS_DEBLOCKING_FLT_IDC_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVCTRL2 0x000a1700 /* RW-4R */ #define NV_CNVDEC_MV1_MVCTRL2_H264_BOTTOMFIRST 15:0 /* RWXVF */ #define NV_CNVDEC_MV1_MVWT_CNTRL 0x000a1e00 /* RW-4R */ #define NV_CNVDEC_MV1_MVWT_CNTRL_CHROMA_LOG2_WEIGHT_DENOM 2:0 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_CNTRL_LUMA_LOG2_WEIGHT_DENOM 5:3 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_CNTRL_WEIGHT_DENOM_WR_EN 6:6 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_CNTRL_ADR 14:8 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_CNTRL_ADR_WR_EN 15:15 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_CNTRL_LOADED 16:16 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_DATA 0x000a1f00 /* RW-4R */ #define NV_CNVDEC_MV1_MVWT_DATA_LUMA_OFFSET 7:0 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_DATA_LUMA_WEIGHT 15:8 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_DATA_CHROMA_WEIGHT_FLAG 16:16 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_DATA_LUMA_WEIGHT_FLAG 17:17 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_DATA_CHROMA_V_OFFSET 7:0 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_DATA_CHROMA_V_WEIGHT 15:8 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_DATA_CHROMA_U_OFFSET 23:16 /* RW-VF */ #define NV_CNVDEC_MV1_MVWT_DATA_CHROMA_U_WEIGHT 31:24 /* RW-VF */ #define NV_CNVDEC_MV1_MVRCOLADDR 0x000a2000 /* RW-4R */ #define NV_CNVDEC_MV1_MVRCOLADDR_RCOL_ADDR 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVRCOLPARAM 0x000a2100 /* RW-4R */ #define NV_CNVDEC_MV1_MVRCOLPARAM_RCOL_LWIDTH 7:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVRCOLPARAM_RCOL_NLIN 8:8 /* RW-VF */ #define NV_CNVDEC_MV1_MVRCOLLINE 0x000a2200 /* RW-4R */ #define NV_CNVDEC_MV1_MVRCOLLINE_RCOL_LREM 7:0 /* RWXUF */ #define NV_CNVDEC_MV1_MVRCOLLINE_RCOL_LCNT 16:8 /* RWXUF */ #define NV_CNVDEC_MV1_MVRCOLOFFS 0x000a2300 /* RW-4R */ #define NV_CNVDEC_MV1_MVRCOLOFFS_RCOL_OFFS 11:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVRCOLOFFS_RCOL_LODD 12:12 /* RW-VF */ #define NV_CNVDEC_MV1_MVRCOLOFFS_4K_RCOL_OFFS 15:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVRCOLOFFS_4K_RCOL_LODD 16:16 /* RW-VF */ #define NV_CNVDEC_MV1_MVRCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_CNVDEC_MV1_MVWCOLADDR 0x000a2400 /* RW-4R */ #define NV_CNVDEC_MV1_MVWCOLADDR_WCOL_ADDR 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVWCOLPARAM 0x000a2500 /* RW-4R */ #define NV_CNVDEC_MV1_MVWCOLPARAM_WCOL_LWIDTH 7:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVWCOLPARAM_WCOL_MBAFF 8:8 /* RW-VF */ #define NV_CNVDEC_MV1_MVWCOLPARAM_WCOL_FIELD 9:9 /* RW-VF */ #define NV_CNVDEC_MV1_MVWCOLPARAM_4MV 10:10 /* RW-VF */ #define NV_CNVDEC_MV1_MVWCOLPARAM_4MV_DIS 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVWCOLPARAM_4MV_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_MV1_MVWCOLPARAM_WRITEENABLE 11:11 /* RW-VF */ #define NV_CNVDEC_MV1_MVWCOLPARAM_WRITEENABLE_DIS 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVWCOLPARAM_WRITEENABLE_EN 0x00000001 /* RW--V */ #define NV_CNVDEC_MV1_MVWCOLLINE 0x000a2600 /* RW-4R */ #define NV_CNVDEC_MV1_MVWCOLLINE_WCOL_LREM 7:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVWCOLLINE_WCOL_LCNT 16:8 /* RW-UF */ #define NV_CNVDEC_MV1_MVWCOLOFFS 0x000a2700 /* RW-4R */ #define NV_CNVDEC_MV1_MVWCOLOFFS_WCOL_OFFS 12:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVWCOLOFFS_WCOL_LODD 13:13 /* RW-VF */ #define NV_CNVDEC_MV1_MVWCOLOFFS_4K_WCOL_OFFS 15:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVWCOLOFFS_4K_WCOL_LODD 16:16 /* RW-VF */ #define NV_CNVDEC_MV1_MVWCOLOFFS_4K_EN 31:31 /* RW-VF */ #define NV_CNVDEC_MV1_MV_MB_COUNTER 0x000a3200 /* RW-4R */ #define NV_CNVDEC_MV1_MV_MB_COUNTER_INTRA 15:0 /* RW-VF */ #define NV_CNVDEC_MV1_MV_MB_COUNTER_INTRA_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MV_MB_COUNTER_SKIP 31:16 /* RW-VF */ #define NV_CNVDEC_MV1_MV_MB_COUNTER_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MV_MB_COUNTER1 0x000a3300 /* RW-4R */ #define NV_CNVDEC_MV1_MV_MB_COUNTER1_REG 16:0 /* RW-VF */ #define NV_CNVDEC_MV1_MV_MB_COUNTER1_REG_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVILPOFFSETMVX(i) (0x000a3680+(i)*4) /* RW-4A */ #define NV_CNVDEC_MV1_MVILPOFFSETMVX__SIZE_1 8 /* */ #define NV_CNVDEC_MV1_MVILPOFFSETMVX_DATA 27:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPOFFSETMVY(i) (0x000a36a0+(i)*4) /* RW-4A */ #define NV_CNVDEC_MV1_MVILPOFFSETMVY__SIZE_1 8 /* */ #define NV_CNVDEC_MV1_MVILPOFFSETMVY_DATA 25:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPDIM 0x000a3700 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPDIM_STRIDEM1 7:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPDIM_WIDTHM1 23:16 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPDIM_HEIGHTM1 31:24 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPMBCTL_REF 0x000a3800 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPMBCTL_REF_OFFS 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPMBCTL_CUR 0x000a3900 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPMBCTL_CUR_OFFS 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPSLICE_MODE_CUR 0x000a3a00 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPSLICE_MODE_CUR_OFFS 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL 0x000a3b00 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL_RD_ENABLE 0:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL_WR_ENABLE 1:1 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL_CROPCHANGE 2:2 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL_RESTRRESCHANGE 3:3 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL_DIR8X8INF 4:4 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL_REFCLAMP_ENABLE 15:15 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL_REFWIDTHM1 23:16 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPLAYER_CTL_REFHEIGHTM1 31:24 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL 0x000a3c00 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE 1:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE_P 0x00000000 /* RWX-V */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE_B 0x00000001 /* RWX-V */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_SLICETYPE_I 0x00000002 /* RWX-V */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_NOILP 2:2 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_NOILP_INIT 0x00000000 /* RWI-V */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_NUMENTRIES 7:4 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPSLICE_CTL_NUMENTRIES_INIT 0x00000008 /* RWI-V */ #define NV_CNVDEC_MV1_MVILPOFFSETX_LO 0x000a3e00 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPOFFSETX_LO_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPOFFSETY_LO 0x000a3f00 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPOFFSETY_LO_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPOFFSET_HI 0x000a4000 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPOFFSET_HI_X 1:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPOFFSET_HI_Y 17:16 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPSCALEX 0x000a4100 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPSCALEX_DATA 24:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPSCALEY 0x000a4200 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPSCALEY_DATA 24:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPREFIDXMAPL0_LO 0x000a4300 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPREFIDXMAPL0_LO_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPREFIDXMAPL0_HI 0x000a4400 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPREFIDXMAPL0_HI_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPREFIDXMAPL1_LO 0x000a4500 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPREFIDXMAPL1_LO_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVILPREFIDXMAPL1_HI 0x000a4600 /* RW-4R */ #define NV_CNVDEC_MV1_MVILPREFIDXMAPL1_HI_DATA 31:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVSFCLAYOUT 0x000a4700 /* RW-4R */ #define NV_CNVDEC_MV1_MVSFCLAYOUT_DATA 15:0 /* RW-UF */ #define NV_CNVDEC_MV1_MVSFCLAYOUT_DATA_INIT 0x0000ffff /* RWI-V */ #endif // __ga102_dev_nvdec_csb_h__