/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2003-2016 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

#ifndef __dev_nv_pcfg_xve_regmap_h__
#define __dev_nv_pcfg_xve_regmap_h__

/* This file is autogenerated. Do not edit */

#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000

/*
 * <prefix>_MAP   has 1 bit set for each dword register.
 * <prefix>_COUNT has total number of set bits in <prefix>_MAP.
 */
#define NV_PCFG_XVE_REGISTER_VALID_COUNT 472
#define NV_PCFG_XVE_REGISTER_VALID_MAP { \
    /* 0x00088000 */ 0xFFF1FFFF, 0x101FFF9F, \
    /* 0x00088100 */ 0x3FFA3C7F, 0x00000000, \
    /* 0x00088200 */ 0x03F00000, 0x00000000, \
    /* 0x00088300 */ 0x00000000, 0x00000000, \
    /* 0x00088400 */ 0x8007FFC0, 0x3F3F5807, \
    /* 0x00088500 */ 0x000000BF, 0x00000000, \
    /* 0x00088600 */ 0x0140AA1F, 0x00000000, \
    /* 0x00088700 */ 0x00013FFF, 0x00000000, \
    /* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \
    /* 0x00088900 */ 0xFFFFFFFF, 0x002FFFFF, \
    /* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \
    /* 0x00088B00 */ 0x00000000, 0xFFFFF000, \
    /* 0x00088C00 */ 0x0007BFE7, 0xFFC003FC, \
    /* 0x00088D00 */ 0xFFFFFFFF, 0x7C1F3FFF, \
    /* 0x00088E00 */ 0xFFFFFFFF, 0x00FFFFFF, \
    /* 0x00088F00 */ 0x00000000, 0xFE000000 }

#define NV_PCFG_XVE_REGISTER_WR_COUNT 350
#define NV_PCFG_XVE_REGISTER_WR_MAP { \
    /* 0x00088000 */ 0x3EF193FA, 0x1007C505, \
    /* 0x00088100 */ 0x3FFA0828, 0x00000000, \
    /* 0x00088200 */ 0x03200000, 0x00000000, \
    /* 0x00088300 */ 0x00000000, 0x00000000, \
    /* 0x00088400 */ 0x80007EC0, 0x3F075007, \
    /* 0x00088500 */ 0x000000BF, 0x00000000, \
    /* 0x00088600 */ 0x0140AA10, 0x00000000, \
    /* 0x00088700 */ 0x00013FFF, 0x00000000, \
    /* 0x00088800 */ 0x004C5FC3, 0x1C5AFFC0, \
    /* 0x00088900 */ 0xFFFC7804, 0x002FFFFF, \
    /* 0x00088A00 */ 0xFF7FFDFD, 0x00007FFF, \
    /* 0x00088B00 */ 0x00000000, 0xF8A54000, \
    /* 0x00088C00 */ 0x00003C01, 0x3FC003FC, \
    /* 0x00088D00 */ 0xFFFFFFFC, 0x701B2C3F, \
    /* 0x00088E00 */ 0xFFFFFFF8, 0x00FFBFFF, \
    /* 0x00088F00 */ 0x00000000, 0xFE000000 }

#endif // {__dev_nv_pcfg_xve_regmap_h__}